QorIQTM Multicore Processor Development P2020DS Integrated media and communications processor development system Overview The P2010E is a single-core The P2020/P2010 Development System version of the P2020E. The P2020E (P2020DS) is ideal for hardware and software processor also integrates an development for embedded applications. optional hardware encryption block It leverages Freescale's highly integrated that supports different algorithms QorIQTM P2020 processor and for high-performance data that leading-edge external components. is critical for supporting secure The high level of integration in the P2020E processor helps to lower system costs, improve performance and simplify board communications. Devices marked with an E include this security engine. design. The P2020E processor supports: A board support package (BSP) Dual e500 cores, built on Power Architecture(R) technology is pre-installed on the P2020DS. * 800-1200 MHz (u-boot) and a generic Power * 512 KB frontside L2 cache w/ECC, hardware cache coherent * 36-bit physical addressing, DP-FPU System Unit This BSP consists of a boot loader Architecture technology system based on the Linux(R) kernel. The u-boot binary and the Linux kernel reside in the on-board flash memory with a file system pre- * 64-/32-bit DDR2/DDR3 with ECC installed on the hard disk shipped * Integrated SEC 3.1 Security Engine in the P2020DS development * Open-PIC Interrupt controller, performance system. monitor, 2x I2C, timers, 16 GPIOs, DUART * 16-bit enhanced local bus supports booting from NAND flash memory * One USB 2.0 host controller with ULPI interface * SPI controller supports booting from SPI serial flash memory * SD/MMC card controller supports booting from flash cards * Three 10/100/1000 Ethernet controllers (eTSEC) w/ Jumbo Frame support, SGMII interface * Enhanced features: Parser/filer, QOS, IP-checksum offload, lossless flow control * IEEE(R) 1588 v2 support * Two Serial RapidIO(R) controllers with integrated message unit operating up to 3.125 GHz * Three PCI Express(R) 1.0a controllers The P2020DS BSP generation takes advantage of the Linux Target Image Builder (LTIB), a suite of tools that leverages existing open source configuration scripts and source code packages, packing them all into a single BSP generation bundle. The source code packages include boot loader and Linux kernel sources as well as many user-space source code packages to build a complete BSP. The LTIB also provides compiler Many third-party applications are available packages, required to build the BSP. Freescale for the P2020DS. They are typically developers use the LTIB to create BSPs for a built on top of the BSP delivered by multitude of Freescale development markets. Freescale and can be installed on the hard The LTIB leverages as many BSP elements as disk. To see demonstrations or to acquire possible for the Freescale markets supported, details of Freescale's third-party applications while offering the flexibility necessary to for this platform, please contact your local customize components that require platform- Freescale sales office. specific modifications. P2020DS Block Diagram Security Acceleration (optional) e500 Core 32 KB L1 I-Cache XOR USB Host 2x Ser 32 KB L1 D-Cache DDR2/DDR3 SDRAM Controller e500 Core 512 KB L2 Cache 32 KB L1 I-Cache PHY USB 2.0 Coherency Module BUF DUART System Bus 32 KB L1 D-Cache SPI DDR3 DIMM DDR Regulator MMCCard EEPROM JTAG GPIO Temp/Vmon eSDHC eTSEC1 3x Ethernet Quad RGMII PHY eTSEC2 eTSEC3 I2C On-Chip Network 3 x Gigabit Ethernet SD Card Slot PCI PCI PCI Serial Serial Express(R) Express Express RapidIO(R) RapidIO 4-ch. DMA 4-ch. DMA Enhanced Local Bus Controller (eLBC) Real-Time Clock NOR flash 4-lane SerDes PromJET Lanes 2 and 3 PCI Express Lanes 0 and 1 Multiplexers selected at boot-up SGMII 1x/2x Pixis FPGA VDD (VCore+ VPlat) VSerDes Clocks 1x PCI 5V PCI Express x1/x2 NVidia(R) M1575 PCI Express x2 3x SATA SGMII riser card slot 3x Audio P2020E Development System * Dual I2C * P2020E QorIQTM multicore communications processor, built on Power Architecture technology * SD/MMC card slot * Memory * SATA2 * DDR clock * USB Type A connector * UARTs: Two DB9 connectors * GPIO: 16 128 MB NOR flash memory * Three 10/100/1000 Ethernet connectors 16 MB SPI ROM * SGMII riser card slot 256B NVRAM * System logic (Pixis FPGA) Manages system reset sequencing * Ethernet Manages system bus and PCI clock speed selections eTSEC3: RGMII or SGMII * IEEE 1588 (R) Clock input from precision oscillator Accessible via test header Implements registers for system control and monitoring * Documentation Schematics Bill of materials Board errata Configuration guide * Software tools Linux 2.6.x kernel * System clock SYSCLK switch can be set to one of eight common settings in the interval 33 MHz-166 MHz Learn More: Freescale and the Freescale logo are trademarks or registered trademarks of Freescale Semiconductor, Inc. in the U.S. and other countries. All other product or service names are the property of their respective owners. The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and service marks licensed by Power.org. (c) Freescale Semiconductor, Inc. 2009. Document Number: P2020DSFS REV 0 Combined regulator for VDD and VDD_PLAT (nominally 1.05V) Reference manual * PCI Express: dual x2 slot eTSEC2: RGMII or SGMII DDRCLK switch can be set to one of eight common settings in the interval 33 MHz-166 MHz * Power supplies 2 GB DDR3 DIMM eTSEC1: RGMII 1x eSATA Cross compile and native GNU tool chain CodeWarriorTM USB TAP For current information about Freescale products and documentation, please visit www.freescale.com/QorIQ.