SII9022ACNU - LATTICE SEMICONDUCTOR

SiI9022A/SiI9024A HDMI Transmitter

Data Sheet

SiI-DS-1076-E.01

August 2016

SiI9022A/SiI9024A HDMI Transmitter

Data Sheet

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

2 SiI-DS-1076-E.01

Contents

1. General Description ...................................................................................................................................................... 7

Video Input ........................................................................................................................................................... 7

HDMI Output ........................................................................................................................................................ 7

Control Capability ................................................................................................................................................. 7

Digital Audio Interface .......................................................................................................................................... 7

Power Management ............................................................................................................................................. 7

Packaging .............................................................................................................................................................. 7

Comparison of the SiI9022A/SiI9024A Device with Other HDMI Transmitters .................................................... 8

2. Functional Description .................................................................................................................................................. 9

Video Data Input and Conversion ....................................................................................................................... 10

Input Clock Multiplier/Divider .................................................................................................................... 10

Video Data Capture ..................................................................................................................................... 10

Embedded Sync Decoding ........................................................................................................................... 10

Data Enable Generator ............................................................................................................................... 10

Color Space Converter ................................................................................................................................ 10

4:2:2 to 4:4:4 Upsampler ............................................................................................................................ 11

4:4:4 to 4:2:2 Downsampler ....................................................................................................................... 11

Dither 10 to 8 .............................................................................................................................................. 11

Audio Data Capture Logic ................................................................................................................................... 11

I2C Slave Interface ............................................................................................................................................... 11

Control and Configuration .................................................................................................................................. 11

DDC Master I2C Interface .................................................................................................................................... 11

Interrupt Logic .................................................................................................................................................... 11

Hot Plug Detection Logic ..................................................................................................................................... 12

HDCP Encryption Engine/XOR Mask (SiI9024A Device Only) .............................................................................. 12

HDCP Key ROM (SiI9024A Device Only) .............................................................................................................. 12

TMDS Digital Core ........................................................................................................................................... 12

CEC Interface ................................................................................................................................................... 12

3. Electrical Specifications .............................................................................................................................................. 13

Absolute Maximum Conditions .......................................................................................................................... 13

Normal Operating Conditions ............................................................................................................................. 13

IOVCC Supply Voltage Requirements .......................................................................................................... 13

DC Specifications ................................................................................................................................................. 14

Digital I/O Specifications ............................................................................................................................. 14

DC Power Supply Specifications .................................................................................................................. 16

AC Specifications ................................................................................................................................................. 17

TMDS AC Timing Specifications ................................................................................................................... 17

Audio AC Timing Specifications ................................................................................................................... 18

Video Input AC Timing Specifications ......................................................................................................... 18

Control Signal Timing Specifications ........................................................................................................... 20

4. Timing Diagrams ......................................................................................................................................................... 21

Input Timing Diagrams ........................................................................................................................................ 21

Audio Timing Diagrams ....................................................................................................................................... 23

Power Supply Sequencing ................................................................................................................................... 24

Output Timing Diagrams ............................................................................................................................. 24

Minimum Horizontal Blanking Specification ....................................................................................................... 25

5. Ball and Pin Diagrams and Descriptions ..................................................................................................................... 26

Ball and Pin Diagrams ......................................................................................................................................... 26

81-Ball VFBGA Package ............................................................................................................................... 26

49-Ball VFBGA Package ............................................................................................................................... 27

72-Pin QFN Package .................................................................................................................................... 28

Ball and Pin Descriptions ..................................................................................................................................... 29

SiI9022A/SiI9024A HDMI Transmitter

Data Sheet

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1076-E.01 3

Video Input ................................................................................................................................................. 29

Audio Input ................................................................................................................................................. 30

CEC .............................................................................................................................................................. 30

Configuration and Control .......................................................................................................................... 31

25BDDC Bus ...................................................................................................................................................... 32

Differential Data ......................................................................................................................................... 32

Power and Ground ...................................................................................................................................... 33

6. Feature Information ................................................................................................................................................... 34

RGB to YCbCr Color Space Converter.................................................................................................................. 34

YCbCr to RGB Color Space Converter.................................................................................................................. 34

3D Video Formats ............................................................................................................................................... 34

Limitations .................................................................................................................................................. 35

S/PDIF Audio Input .............................................................................................................................................. 35

I2S Audio Inputs ................................................................................................................................................... 35

Supported Audio Sampling Rates ....................................................................................................................... 36

I2C Register Information ..................................................................................................................................... 37

DDC Support ....................................................................................................................................................... 37

DDC Stall Support ........................................................................................................................................ 38

Power Saving Modes and Wakeup Feature ........................................................................................................ 38

Wakeup Support in D3 Cold and D3 Hot Modes ......................................................................................... 38

Common Video Input Formats........................................................................................................................ 39

Data Bus Mappings ......................................................................................................................................... 40

Data Mappings for 81-ball and 72-pin Package .......................................................................................... 42

Data Mappings for 49-Ball Package ............................................................................................................ 58

7. Design Recommendations .......................................................................................................................................... 67

Power Supplies Decoupling ................................................................................................................................ 67

High-Speed TMDS Signals ................................................................................................................................... 67

Source Termination .................................................................................................................................... 67

ESD Protection ............................................................................................................................................ 68

Transmitter Layout Guidelines.................................................................................................................... 68

Hot Plug Signal Conditioning............................................................................................................................... 68

EMI Considerations ............................................................................................................................................. 68

Typical Circuits .................................................................................................................................................... 69

Power Supply Decoupling ........................................................................................................................... 69

HDMI Port Connections .............................................................................................................................. 70

Control Signal Connections ......................................................................................................................... 71

77BDigital Video Input Connections ................................................................................................................. 72

8. Packaging .................................................................................................................................................................... 73

49-Ball Package Dimensions ............................................................................................................................... 73

36B81-Ball Package Dimensions ............................................................................................................................... 74

72-Pin Package Dimensions ................................................................................................................................ 75

Marking Specification ......................................................................................................................................... 76

Ordering Information .......................................................................................................................................... 77

References .......................................................................................................................................................................... 78

Standards Documents..................................................................................................................................................... 78

Standards Groups ........................................................................................................................................................... 78

Lattice Semiconductor Documents ................................................................................................................................. 78

Technical Support ........................................................................................................................................................... 78

Revision History .................................................................................................................................................................. 79

SiI9022A/SiI9024A HDMI Transmitter

Data Sheet

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

4 SiI-DS-1076-E.01

Figures

Figure 1.1. Typical Application (SiI9022A HDMI Transmitter Shown)................................................................................... 7

Figure 2.1. Functional Block Diagram ................................................................................................................................... 9

Figure 2.2. Transmitter Video Data Processing Path .......................................................................................................... 10

Figure 4.1. IDCK Clock Cycle/High/Low Times .................................................................................................................... 21

Figure 4.2. Control and Data Single-Edge Setup/Hold Times to IDCK ................................................................................. 21

Figure 4.3. Dual-Edge Setup/Hold Times to IDCK ............................................................................................................... 21

Figure 4.4. VSYNC and HSYNC Delay Times from/to DE ..................................................................................................... 22

Figure 4.5. DE High/Low Times ........................................................................................................................................... 22

Figure 4.6. Conditions for Use of RESET# ............................................................................................................................ 22

Figure 4.7. RESET# Minimum Timings................................................................................................................................. 22

Figure 4.8. I2S Input Timings ............................................................................................................................................... 23

Figure 4.9. S/PDIF Input Timings ......................................................................................................................................... 23

Figure 4.10. MCLK Timings .................................................................................................................................................. 23

Figure 4.11. Power Supply Sequencing ............................................................................................................................... 24

Figure 4.12. Differential Transition Times .......................................................................................................................... 24

Figure 4.13. I2C Data Valid Delay (Driving Read Cycle Data) ............................................................................................... 24

Figure 4.14. INT Output Signal Response to Interrupt Condition ....................................................................................... 24

Figure 5.1. 81-Ball Package Ball Diagram (Top View).......................................................................................................... 26

Figure 5.2. 49-Ball Package Ball Diagram (Top View).......................................................................................................... 27

Figure 5.3. 72-Pin Package Pin Diagram (Top View) ........................................................................................................... 28

Figure 6.1. Simplified Host I2C Interface using Master DDC Port ........................................................................................ 37

Figure 6.2. Master I2C Supported Transactions .................................................................................................................. 38

Figure 6.3. Parallel Input Video to HDMI Output Video Permutations ............................................................................... 41

Figure 6.4. RGB/YCbCr 4:4:4 Separate Sync Timing (81-Ball and 72-Pin Package) .............................................................. 42

Figure 6.5. 16-Bit YC 4:2:2 Separate Sync Timing (81-Ball and 72-Pin Package) ................................................................. 43

Figure 6.6. 20-Bit YC 4:2:2 Separate Sync Timing (81-Ball and 72-Pin Package) ................................................................. 44

Figure 6.7. 20-Bit YC 4:2:2 Separate Sync NB Mode Timing (81-Ball and 72-Pin Package) ................................................. 44

Figure 6.8. 24-Bit YC 4:2:2 Separate Sync Timing (81-Ball and 72-Pin Package) ................................................................. 45

Figure 6.9. 24-Bit YC 4:2:2 Separate Sync NB Mode Timing (81-Ball and 72-Pin Package) ................................................. 46

Figure 6.10. 16-Bit YC 4:2:2 Embedded Sync Timing (81-Ball and 72-Pin Package) ............................................................ 47

Figure 6.11. 20-Bit YC 4:2:2 Embedded Sync Timing (81-Ball and 72-Pin Package) ............................................................ 47

Figure 6.12. 20-Bit YC 4:2:2 Embedded Sync NB Mode Timing (81-Ball and 72-Pin Package)............................................ 47

Figure 6.13. 24-Bit YC 4:2:2 Embedded Sync Timing (81-Ball and 72-Pin Package) ............................................................ 48

Figure 6.14. 24-Bit YC 4:2:2 Embedded Sync NB Mode Timing (81-Ball and 72-Pin Package)............................................ 49

Figure 6.15. 8-Bit YC Mux 4:2:2 Separate Sync Timing (81-Ball and 72-Pin Package) ......................................................... 49

Figure 6.16. 10-Bit YC Mux 4:2:2 Separate Sync Timing (81-Ball and 72-Pin Package) ....................................................... 50

Figure 6.17. 12-Bit YC Mux 4:2:2 Separate Sync Timing (81-Ball and 72-Pin Package) ....................................................... 50

Figure 6.18. 8-Bit YC Mux 4:2:2 Embedded Sync Timing (81-Ball and 72-Pin Package)...................................................... 51

Figure 6.19. 10-Bit YC Mux 4:2:2 Embedded Sync Timing (81-Ball and 72-Pin Package).................................................... 51

Figure 6.20. 12-Bit YC Mux 4:2:2 Embedded Sync Timing (81-Ball and 72-Pin Package).................................................... 52

Figure 6.21. 12-Bit YC 4:2:2 Embedded Sync Dual Edge Timing (81-Ball and 72-Pin Package) ........................................... 53

Figure 6.22. 12-Bit RGB 4:4:4 Separate Sync Dual Edge Timing (81-Ball and 72-Pin Package) ........................................... 54

Figure 6.23. 8-Bit YC 4:2:2 Separate Sync Dual Edge Timing (81-b all and 72-p in Package) .............................................. 55

Figure 6.24. 10-Bit YC 4:2:2 Separate Sync Dual Edge Timing (81-Ball and 72-Pin Package) .............................................. 56

Figure 6.25. 12-Bit YC 4:2:2 Separate Sync Dual Edge Timing (81-Ball and 72-Pin Package) .............................................. 57

Figure 6.26. 12-Bit YC 4:2:2 Separate Sync NB Mode Dual Edge Timing (81-Ball and 72-Pin Package) .............................. 57

Figure 6.27. 16-bit YC 4:2:2 Separate Sync Timing (49-Ball Package) ................................................................................. 58

Figure 6.28. 16-Bit YC 4:2:2 Embedded Sync Timing (49-Ball Package) .............................................................................. 59

Figure 6.29. 8-Bit YC Mux 4:2:2 Separate Sync Timing (49-Ball Package) ........................................................................... 60

Figure 6.30. 8-Bit YC Mux 4:2:2 Embedded Sync Timing (49-Ball Package) ........................................................................ 61

Figure 6.31. 12-Bit YC 4:2:2 Embedded Sync Timing (49-Ball Package) .............................................................................. 62

Figure 6.32. 12-Bit RGB/YCbCr 4:4:4 Separate Sync Timing (49-Ball Package) ................................................................... 63

SiI9022A/SiI9024A HDMI Transmitter

Data Sheet

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1076-E.01 5

Figure 6.33. 8-Bit YC 4:2:2 Separate Sync Dual Edge Timing (49-Ball Package) .................................................................. 64

Figure 6.34. 10-Bit YC 4:2:2 Separate Sync Dual Edge Timing (49-Ball Package) ................................................................ 65

Figure 6.35. 12-Bit YC 4:2:2 Separate Sync Dual Edge Timing (49-Ball Package) ................................................................ 66

Figure 6.36. 12-Bit YC 4:2:2 Separate Sync NB Mode Dual Edge Timing (49-Ball Package) ................................................ 66

Figure 7.1. Decoupling and Bypass Schematic .................................................................................................................... 67

Figure 7.2. Decoupling and Bypass Capacitor Placement ................................................................................................... 67

Figure 7.3. Transmitter to HDMI Connector Routing – Top View ....................................................................................... 68

Figure 7.4. Power Supply Decoupling ................................................................................................................................. 69

Figure 7.5. HDMI Port Connection Schematic .................................................................................................................... 70

Figure 7.6. Controller Connections Schematic ................................................................................................................... 71

Figure 7.7. Digital Input Schematic ..................................................................................................................................... 72

Figure 8.1. 49-Ball VFBGA Package Diagram (SiI902nAYBT) ............................................................................................... 73

Figure 8.2. 81-Ball VFBGA Package Diagram (SiI902nARBT) ............................................................................................... 74

Figure 8.3. 72-Pin QFN Package Diagram (SiI902nACNU) ................................................................................................... 75

Figure 8.4. Marking Diagram (SiI902nARBT) ....................................................................................................................... 76

Figure 8.5. Marking Diagram (SiI902nAYBT) ....................................................................................................................... 76

Figure 8.6. Marking Diagram (SiI902nACNU) ...................................................................................................................... 77

SiI9022A/SiI9024A HDMI Transmitter

Data Sheet

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

6 SiI-DS-1076-E.01

Tables

Table 1.1. Summary of Features ........................................................................................................................................... 8

Table 3.1. Absolute Maximum Conditions .......................................................................................................................... 13

Table 3.2. Normal Operating Conditions ............................................................................................................................ 13

Table 3.3. DC Digital I/O Specifications: IOVCC = 1.8 V ....................................................................................................... 14

Table 3.4. DC Digital I/O Specifications: IOVCC = 3.3 V ....................................................................................................... 15

Table 3.5. TMDS I/O Specifications ..................................................................................................................................... 16

Table 3.6. Low Power Standby Mode Power Consumption ............................................................................................... 16

Table 3.7. Operating Mode Power Consumption ............................................................................................................... 16

Table 3.8. Power Operating Modes .................................................................................................................................... 17

Table 3.9. TMDS AC Specifications ...................................................................................................................................... 17

Table 3.10. I2S Input Port Timings ....................................................................................................................................... 18

Table 3.11. S/PDIF Input Port Timings ................................................................................................................................ 18

Table 3.12. Video Input AC Specifications: 1.8 V IOVCC ..................................................................................................... 18

Table 3.13. Video Input AC Specifications: 3.3 V IOVCC ..................................................................................................... 19

Table 3.14. Control Signal Timing Specifications ................................................................................................................ 20

Table 4.1. Minimum Horizontal Blanking Calculations ....................................................................................................... 25

Table 6.1. RGB to YCbCr Conversion Formulas ................................................................................................................... 34

Table 6.2. YCbCr-to-RGB Conversion Formulas .................................................................................................................. 34

Table 6.3. Supported 3D Video Formats ............................................................................................................................. 35

Table 6.4. Supported MCLK Frequencies ............................................................................................................................ 36

Table 6.5. S/PDIF Audio Formats Supported for each Video Format ................................................................................. 36

Table 6.6. I2S Audio Formats Supported for each Video Format ........................................................................................ 36

Table 6.7. Control of I2C Address with CI2CA Signal ........................................................................................................... 37

Table 6.8. D3 hot and D3 Cold Feature ............................................................................................................................... 38

Table 6.9. Video Input Formats........................................................................................................................................... 39

Table 6.10. Input Video Formats ........................................................................................................................................ 40

Table 6.11. RGB/YCbCr 4:4:4 Separate Sync Data Mapping (81-Ball and 72-Pin Package) ................................................. 42

Table 6.12. 16-Bit and 20-Bit YC 4:2:2 Separate Sync Data Mapping (81-Ball and 72-Pin Package) .................................. 43

Table 6.13. 24-Bit YC 4:2:2 Separate Sync Data Mapping (81-Ball and 72-Pin Package) .................................................... 45

Table 6.14. 16-Bit and 20-Bit YC 4:2:2 Embedded Sync Data Mapping (81-Ball and 72-Pin Package) ............................... 46

Table 6.15. 24-Bit YC 4:2:2 Embedded Sync Data Mapping (81-Ball and 72-Pin Package) ................................................. 48

Table 6.16. 8-, 10-, and 12-Bit YC Mux 4:2:2 Separate Sync Data Mapping (81-Ball and 72-Pin Package) ............................ 49

Table 6.17. 8-, 10-, and 12-Bit YC Mux 4:2:2 Embedded Sync Data Mapping (81-Ball and 72-Pin Package) ............................. 51

Table 6.18. 12-Bit YC 4:2:2 Embedded Sync Dual Edge Data Mapping (81-Ball and 72-Pin Package) ................................ 53

Table 6.19. 12-Bit RGB/YCbCr 4:4:4 Separate Sync Dual Edge Data Mapping (81-Ball and 72-Pin Package) ..................... 54

Table 6.20. 8-Bit YC 4:2:2 Separate Sync Dual Edge Data Mapping (81-Ball and 72-Pin Package) ..................................... 55

Table 6.21. 10-Bit YC 4:2:2 Separate Sync Dual Edge Data Mapping (81-Ball and 72-Pin Package) ................................... 56

Table 6.22. 12-Bit YC 4:2:2 Separate Sync Dual Edge Data Mapping (81-Ball and 72-Pin Package) ................................... 57

Table 6.23. 16-Bit YC 4:2:2 Separate Sync Data Mapping (49-Ball Package) ...................................................................... 58

Table 6.24. 16-Bit YC 4:2:2 Embedded Sync Data Mapping (49-Ball Package) ................................................................... 59

Table 6.25. 8-Bit YC Mux 4:2:2 Separate Sync Data Mapping (49-Ball Package) ................................................................ 60

Table 6.26. 8-Bit YC Mux 4:2:2 Embedded Sync Data Mapping (49-Ball Package) ............................................................. 61

Table 6.27. 12-Bit YC 4:2:2 Embedded Sync Dual Edge Data Mapping (49-Ball Package) .................................................. 62

Table 6.28. 12-Bit RGB/YCbCr 4:4:4 Separate Sync Dual Edge Data Mapping (49-Ball Package) ....................................... 63

Table 6.29. 8-Bit YC 4:2:2 Separate Sync Dual Edge Data Mapping (49-Ball Package) ....................................................... 64

Table 6.30. 10-Bit YC 4:2:2 Separate Sync Dual Edge Data Mapping (49-Ball Package) ..................................................... 65

Table 6.31. 12-Bit YC 4:2:2 Separate Sync Dual Edge Data Mapping (49-Ball Package) ..................................................... 66

SiI9022A/SiI9024A HDMI Transmitter

Data Sheet

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1076-E.01 7

1. General Description

The Lattice Semiconductor SiI9022A/SiI9024A HDMI®

transmitter supports the High Definition Multimedia

Interface (HDMI) Specification on a wide range of mobile

products. High definition camcorders, digital still

cameras, and personal mobile devices connect directly to

a large installed base of HDMI TVs and DVI PC monitors

by using the flexible audio and video interfaces provided

by this ultra-low-power solution. S/PDIF or I2S inputs

enable a pure digital audio connection to virtually any

system audio processor or codec. This transmitter is the

next generation of its family and is an enhanced

replacement for the SiI9022/SiI9024 device, with lower

power and enhanced features.

The SiI9024A transmitter is pre-programmed with HDCP

keys and has completely self-sequencing HDCP detection

and authentication, including SHA-1 for repeaters. The

device supports High-bandwidth Digital Content

Protection (HDCP) for devices that require secure

content delivery.

Video Input

 xvYCC metadata support

 BTA-T1004 video input format

 Integrated color space converter allows direct

connection to all major MPEG decoders, including

those that provide only an ITU-R.656 output

 Internal DE generator supports non-embedded sync

formats

HDMI Output

 HDMI, HDCP, and DVI compatible

 TMDS™ core runs at 165 MHz

 Video resolutions up to 1080p and UXGA (72-pin

QFN package supports 165 MHz dual-edge mode)

 3D-capable at 720p/60, 1080i/60, and

1080p/24 frame-pack, side-by-side, L + D, and

Top-and-Bottom modes

 HDMI Type A, Type-C, and micro-D connector

support

Control Capability

 Consumer Electronics Control (CEC) interface

incorporates an HDMI-compliant CEC I/O with

hardware protocol and arbitration logic, and

requires no external calibration

 Monitor detection is supported through both Hot

Plug and Receiver Sense circuits

 Single slave I2C from host, passing through to master

I2C interface for DDC connection, simplifies board

layout and lowers cost

 Defaults to SiI9020 transmitter register-compatible

mode for operation with existing legacy software

Digital Audio Interface

 Four I2S inputs for Dolby Digital, DTS, or MPEG2

audio with programmable channel mapping (49-ball

package supports one I2S input)

 DVD-Audio input (2 or up to 8 channels)

 MCLK is not required for I2S and S/PDIF

 S/PDIF input supports 2-channel PCM or compressed

Dolby Digital and DTS digital

 2:1 and 4:1 down-sampling to handle 96 kHz and

192 kHz audio streams

Power Management

 Flexible power management with hot-plug wakeup

 Ultra-low power requirement: less than 90 mW

active, 150 W standby

Packaging

 81-ball VFBGA (4.0 × 4.0 mm) package

 72-pin QFN (10 × 10 mm) package

 49-ball VFBGA (4.0 × 4.0 mm) package

 Standard part covers extended (–20 °C to +85 °C)

temperature range

Figure 1.1. Typical Application (SiI9022A HDMI Transmitter Shown)

SiI9022A/SiI9024A HDMI Transmitter

Data Sheet

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

8 SiI-DS-1076-E.01

Comparison of the SiI9022A/SiI9024A Device with Other HDMI Transmitters

Table 1.1 summarizes the differences among the previous Lattice Semiconductor HDMI transmitters and the

SiI9022A/SiI9024A HDMI transmitters.

Table 1.1. Summary of Features

HDMI Transmitter

SiI9030

SiI9020

SiI9022

SiI9022-6

SiI9024

SiI9024-6

SiI9022A

SiI9024A

SiI9022A

SiI9024A

VFBGA

QFN

Video Input

Clock duty cycle

60/40

70/30

Max frequency

150 MHz

84 MHz

82.5 MHz

165 MHz

82.5 MHz

165 MHz

165 MHz3

Input signal level2

3.3 V

3.3 V or

1.8 V

3.3 V or

1.8 V

3.3 V or

1.8 V

3.3 V or

1.8 V

3.3 V or

1.8 V

3.3 V or

1.8 V

3.3 V or

1.8 V

3.3 V or

1.8 V

Audio Input

Max S/PDIF

frequency

96 kHz

192 kHz

I2S MCLK required?

Yes

Optional

S/PDIF MCLK

required?

Yes

Optional

DDC I2C Bus

Voltage Tolerance1

5 V

HDCP

Encryption engine

Yes

Auto authentication

Yes

Other

Core power supply

1.8 V

1.2 V

I/O power supply2

3.3 V

3.3 V or

1.8 V

3.3 V or

1.8 V

3.3 V or

1.8 V

3.3 V or

1.8 V

3.3 V or

1.8V

3.3 V or

1.8 V

3.3 V or

1.8V4

3.3 V or

1.8 V4

Package

80-pin

TQFP

84-ball

TFBGA

84-ball

TFBGA or

81-ball

VFBGA

84-ball

TFBGA

84-ball

TFBGA or

81-ball

VFBGA

84-ball

TFBGA

81-ball

VFBGA or

49-ball

VFBGA

81-ball

VFBGA or

49-ball

VFBGA

72-pin

QFN

72-pin QFN

Notes:

1. The DDC pads of the SiI9022A/SiI9024A device are 5 V compliant with or without IOVCC power supply. For other devices listed

above, the DDC pads are 5 V tolerant only when chip IOVCC is applied

2. The SiI9022A/SiI9024A 81-ball and 72-pin package supports both 1.8 V and 3.3 V threshold-compliant operation. The 49-ball

package only supports 1.8 V compliant I/O. Both devices have 3.3 V tolerant I/O when IOVCC is 1.8 V.

3. Supports up to 165 MHz dual-edge and single-edge modes.

4. For dual-edge mode above 82.5 MHz, only 3.3 V ± 10% can be used for IOVCC.

SiI9022A/SiI9024A HDMI Transmitter

Data Sheet

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1076-E.01 9

2. Functional Description

The SiI9022A/SiI9024A HDMI transmitter provides a complete solution for transmitting HDMI-compliant digital audio

and video. Specialized audio and video processing is available within the transmitter to easily and cost-effectively add

HDMI capability to the consumer electronics devices. Figure 2.1 shows the functional block diagram of the chip. In the

49-ball package, DE and S/PDIF share the same pin.

TMDS

Digital

Core

Video Data

Input and

Conversion

I2C

Slave

Interface

CSCL

HSYNC

VSYNC

IDCK

EXT_SWING

TXC±

TX0±

TX1±

TX2±

RESET#

Audio Data

Capture

Logic

Block

SPDIF

MCLK

INT

HPD

Interrupt Logic

control signals

audio data

SCK

DSDA

DSCL

DDC

Master I2C

Interface

Control and

Configuration

Logic Block

CI2CA

Hot Plug

Detection Logic

CEC

Interface CEC

control signals

HDCP

Encryption

Engine/

XOR Mask

HDCP

Keys

SiI9024A

Transmitter only

(81-ball and 72-pin only)

CSDA

81-ball and 72-pin: D[23:0]

49-ball: D[15:0]

81-ball and 72-pin: SD[3:0]

49-ball: SD0

(81-ball and 72-pin only)

DE/SPDIF

(49-ball only)

Figure 2.1. Functional Block Diagram

SiI9022A/SiI9024A HDMI Transmitter

Data Sheet

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

10 SiI-DS-1076-E.01

Video Data Input and Conversion

Figure 2.2 shows the video data processing stages through the transmitter. Each of the processing blocks can be

bypassed by setting the appropriate register bits. The HSYNC and VSYNC input signals are required, except in

embedded sync modes. The DE input signal is optional, because it can be created with the DE generator using the

HSYNC and VSYNC signals.

Embedded

Sync

Decoding

Data Enable

Generator

4:2:2 to 4:4:4

Upsampler

YCbCr to RGB

Color Space

Converter

RGB to YCbCr

Color Space

Converter

Complete set of

signals required

for TMDS encoding.

HSYNC

VSYNC

IDCK

D[23:0] /

D[15:0]*

Dither 10 to 8

bypass CSC bypass CSC

Clock

HS,VS

bypass 422

Data

DE external DE

DE can be explicit input,

decoded from embedded

syncs, or generated from

Hsync and Vsync edges.

Video

Data

Capture

* For 49-ball VFBGA only bypass 444

4:4:4 to 4:2:2

Downsampler

bypass dither

To HDCP

or TMDS

Input

Clock

Multiplier/

Divider

Figure 2.2. Transmitter Video Data Processing Path

Input Clock Multiplier/Divider

The input pixel clock can be multiplied by 2 or 4, or divided by 2 (multiplied by 0.5). Video input formats which use a 2x

clock (such as YC Mux mode) can then be transmitted across the HDMI link with a 1x clock. Similarly, 1x-to-2x, 1x-to-4x,

and 2x-to-4x conversions are possible.

Video Data Capture

The video data capture block receives uncompressed digital video through an interface ranging from 8 to 16 bits in

width for the 49-ball package and from 8 to 24 bits in width for the 81-ball and 72-pin package. These interfaces have

two or three 8-bit data channels, which can be configured for the video formats shown in the RGB to YCbCr Color Space

Converter section on page 34. It provides a direct connection to major MPEG decoders. Registers set the bus width

(8/10/12/16/20/24-bit), format, and rising/falling edge latching according to the video format sent to the transmitter.

This information is passed over the HDMI link in the CEA-861D Auxiliary Video Information (AVI) InfoFrame packets.

Embedded Sync Decoding

The transmitter can create DE, HSYNC, and VSYNC signals using the start of active video (SAV) and end of active video

(EAV) codes within the ITU-R BT.656-format video stream.

Data Enable Generator

The transmitter includes logic to construct a Data Enable (DE) signal from the incoming HSYNC, VSYNC, and IDCK. This

signal is used to correct timing from sync extraction to conform to CEA-861D timing specifications. By programming

registers, the DE signal can define the size of the active display region. This feature is particularly useful when the

transmitter connects to MPEG decoders that do not provide a specific DE output signal.

Color Space Converter

Two color space converters (CSCs) (YCbCr to RGB and RGB to YCbCr) are available to interface to the many video

formats supplied by AV processors and to provide full DVI 1.0 backward compatibility. The CSC can be adjusted to

perform standard-definition conversions (ITU.601) or high-definition conversions (ITU.709) by setting the appropriate

SiI9022A/SiI9024A HDMI Transmitter

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SiI-DS-1076-E.01 11

registers. See the RGB to YCbCr Color Space Converter and YCbCr to RGB Color Space Converter sections starting on

page 34 for more information.

4:2:2 to 4:4:4 Upsampler

Chrominance upsampling and downsampling increase or decrease the number of chrominance samples in each line of

video. Upsampling doubles the number of chrominance samples in each line, converting 4:2:2 sampled video to 4:4:4

sampled video.

4:4:4 to 4:2:2 Downsampler

Downsampling reduces the number of chrominance samples in each line by half, converting 4:4:4 sampled video to

4:2:2 video.

Dither 10 to 8

The dither block takes the internally processed data and reduces it down to 8 bits for output.

Audio Data Capture Logic

The SiI9022A/SiI9024A device in the 81-ball and 72-pin packages have individual S/PDIF and I2S (SD[3:0]) inputs for

accepting digital audio input. The Feature Information section on page 34 provides more information about audio

formats and available sampling frequencies.

Due to the reduced lead count, the SiI9022A/SiI9024A transmitter in the 49-ball package has certain restrictions on the

audio because ball G6 is shared by both the S/PDIF and DE inputs. When the device is configured to use S/PDIF, the

video format must use either the DE generator mode or one of the YC 4:2:2 embedded sync formats.

I2C Slave Interface

The controller I2C interface on the transmitter (signals CSCL and CSDA) is a slave interface with an operating frequency

from 40 kHz to 400 kHz and with an input tolerance of up to 4.0 V when all chip operating voltages are present. The

host uses this interface to configure the transmitter by reading from and writing to appropriate registers.

Control and Configuration

The register/configuration logic block incorporates all the registers required for configuring and managing the

transmitter. A separate logic block handles the configuration and operation of the CEC subsystem.

DDC Master I2C Interface

The transmitter has a master I2C port for direct connection to the HDMI cable. DDC read and write operations are

executed by reading and writing registers in the transmitter. This feature simplifies the system design and helps to

lower its cost. See the DDC Support section on page 37 for more information.

Interrupt Logic

The INT signal interrupts the host processor when certain conditions arise inside the transmitter. The INT output is

programmable to be either active HIGH or active LOW; see the Configuration and Control Signals section. Conditions

which create an interrupt include:

 Monitor detect (either from the HPD input level, or from the Receiver Sense feature)

 VSYNC (useful for synchronizing a host processor to the vertical timing interval)

 HDCP event

 CEC event

 Audio interrupt.

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12 SiI-DS-1076-E.01

Hot Plug Detection Logic

The Hot Plug Detection Logic block determines if a receiver is connected to the SiI9022A/SiI9024A transmitter. When

HIGH, the HPD signal indicates to the transmitter that the EDID of the connected receiver is readable. A HIGH voltage is

at least 2.0 V, and a LOW voltage is less than 0.8 V.

HDCP Encryption Engine/XOR Mask (SiI9024A Device Only)

The HDCP encryption engine contains the logic necessary to encrypt the incoming audio and video data and includes

support for HDCP authentication and repeater checks. The system microcontroller or microprocessor controls the

encryption process by using a set sequence of register reads and writes. An algorithm uses HDCP keys and a Key

Selector Value (KSV) stored in the on-board ROM to calculate a number that is then applied to an XOR mask. This

process encrypts the audio and video data on a pixel-by-pixel basis during each clock cycle.

HDCP Key ROM (SiI9024A Device Only)

The SiI9024A transmitter comes pre-programmed with a set of production HDCP keys stored in an internal ROM.

System manufacturers do not need to purchase key sets from the Digital Content Protection LLC. Lattice Semiconductor

handles all purchasing, programming, and security for the HDCP keys. The pre-programmed HDCP keys provide the

highest level of security because there is no way to read the keys once the devices are programmed. Customers must

sign the HDCP license agreement (www.digital-cp.com) or be under a specific NDA with Lattice Semiconductor before

receiving samples of the transmitter.

TMDS Digital Core

The TMDS Digital Core performs 8-bit to 10-bit TMDS encoding on the audio, video, and auxiliary data received from

the Dither 10 to 8 block. This data is sent through three TMDS differential data lines along with a TMDS differential

clock. A resistor connected to the EXT_SWING signal controls the TMDS swing amplitude.

CEC Interface

The Consumer Electronics Control (CEC) Interface block provides CEC- compliant signals between CEC devices and a CEC

master. A CEC controller using the Lattice Semiconductor CEC Programming Interface (CPI) is included on the chip. This

controller has a high-level register interface accessible through the I2C interface and is used to send and receive CEC

commands. This controller makes CEC implementation very straightforward and removes the burden of managing bit

transitions on the CEC bus from the host CPU.

The SiI9022A/SiI9024A CEC logic is self-calibrating and does not require a calibration procedure as the previous

generation devices did.

SiI9022A/SiI9024A HDMI Transmitter

Data Sheet

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SiI-DS-1076-E.01 13

3. Electrical Specifications

Absolute Maximum Conditions

Table 3.1. Absolute Maximum Conditions

Symbol

Parameter

Min

Typ

Max

Units

Note

IOVCC

I/O supply voltage

–0.3

—

4.0

1, 2, 3

AVCC12

TMDS analog supply voltage

–0.3

—

1.5

1, 2

CVCC12

Digital core supply voltage

–0.3

—

1.5

1, 2, 431H3

Input voltage

–0.3

—

1, 2

Output voltage

–0.3

—

1, 2

VI5V

Input voltage, 5 volt tolerant I/O

–0.3

—

5.5

1, 2, 4

VO5V

Output voltage, 5 volt tolerant I/O

–0.3

—

5.5

1, 2, 4

Junction temperature

—

125

C

—

TSTG

Storage temperature

–65

—

150

C

—

Notes:

1. Permanent device damage can occur if absolute maximum conditions are exceeded.

2. Functional operation should be restricted to the conditions described under Normal Operating Conditions.

3. Voltage undershoot or overshoot cannot exceed absolute maximum conditions.

4. HPD (input), DSCL (output), DSDA (input/output).

Normal Operating Conditions

Table 3.2. Normal Operating Conditions

Symbol

Parameter

Min

Typ

Max

Units

Note

IOVCC

I/O supply voltage: 1.8 V host

1.62

1.8

1.98

I/O supply voltage: 3.3 V host

3.0

3.3

3.6

AVCC12

TMDS analog supply voltage

1.08

1.2

1.32

CVCC12

Digital core supply voltage

1.08

1.2

1.32

VCCN

Allowable noise on AVCC

—

mVP-P

—

Ambient temperature (with power applied)

–20

C

—

Θja

Ambient thermal resistance (Theta JA)

—

75.3

C/W

3, 6

—

86.5

C/W

4, 6

—

28.5

C/W

5, 6

Θjc

Ambient thermal resistance (Theta JC)

—

22.6

C/W

3, 6

—

22.7

C/W

4, 6

—

13.1

C/W

5, 6

Notes:

1. CVCC12 and AVCC12 can be derived from the same power source.

2. The 81-ball and 72-pin package supports 3.3 V or 1.8 V; the 49-ball package supports 1.8 V only.

3. 81-ball package

4. 49-ball package

5. 72-pin package

6. Values for Θja and Θjc are provided for a 4-layer PCB, Airflow at 0 m/s.

See page 69 for schematics showing decoupling and power supply regulation.

IOVCC Supply Voltage Requirements

The 72-pin or 81-ball package SiI9022A/SiI9024A transmitter IOVCC supply can operate at either 3.3 V or 1.8 V, depending on

the input level to the IO_SEL pin provided by the host. When IOVCC = 1.8 V, the I/O is 3.3 V tolerant. However, to ensure the

input/output thresholds are within specifications, the IOVCC on the SiI9022A/SiI9024A transmitter should be the same as the

SiI9022A/SiI9024A HDMI Transmitter

Data Sheet

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14 SiI-DS-1076-E.01

host IOVCC, and IO_SEL should be set to the correct value, as described for the signal in the Configuration and Control Signals

section.

The 49-ball package is hardwired to be used with IOVCC = 1.8 V only.

DC Specifications

Digital I/O Specifications

Under normal operating conditions unless otherwise specified.

Table 3.3. DC Digital I/O Specifications: IOVCC = 1.8 V

In the 81-ball and 72-pin package, IO_SEL is tied to 1.8 V.

Symbol

Parameter

Signal Type

Signal Name3

Conditions

Min

Typ

Max

Units

Notes

VIH

HIGH-level input voltage

LVTTL

CEC_D

CI2CA

IO_SEL

—

1.2

—

VIL

LOW-level input voltage

—

0.60

VTH-

HIGH to LOW threshold

Schmitt

IDCK

D[23:0]

—

0.68

—

VTH+

LOW to HIGH threshold

1.25

—

VTH-

HIGH to LOW threshold

Schmitt

MCLK

SCK

SD[3:0]

SPDIF

—

0.45

—

VTH+

LOW to HIGH threshold

1.20

—

VTH-

HIGH to LOW threshold

Schmitt

HPD

—

0.65

—

VTH+

LOW to HIGH threshold

1.9

—

VTH-

HIGH to LOW threshold

Schmitt

RESET#

—

0.50

—

VTH+

LOW to HIGH threshold

1.2

—

VTH-

HIGH to LOW threshold

Schmitt

CSCL

CSDA

—

0.50

—

VTH+

LOW to HIGH threshold

1.32

—

VTH-

HIGH to LOW threshold

Schmitt

DSCL

DSDA

—

1.5

—

VTH+

LOW to HIGH threshold

3.0

—

VTH-

HIGH to LOW threshold

Schmitt

CEC_A

—

0.51

—

VTH+

LOW to HIGH threshold

1.15

—

VOH

HIGH-level output voltage

LVTTL

INT

—

1.4

—

VOL

LOW-level output voltage

—

0.3

VOLOD

LOW-level output voltage

Open Drain

INT

—

0.3

VCINL

Input clamp voltage

—

ICL = –18 mA

—

GND – 0.8

2, 5

VCIPL

Input clamp voltage

—

ICL = 18 mA

—

VCC + 0.8

2, 5

IIL

Input leakage current

—

High impedance

–10

—

µA

2, 9

IOL

Output drive current

Open Drain

DSCL

DSDA

VOUT = 0.4 V

—

6, 8

IOL

Output drive current

Open Drain

CSCL

CSDA

VOUT = 0.4 V

—

6, 8

IOL

Output drive current

Open Drain

CEC_A

VOUT = 0.4 V

3.5

—

IOL

Output drive current

Open Drain

CEC_D

VOUT = 0.4 V

2.0

—

IOL

Output drive current

LVTTL

INT

VOUT = 0.4 V

—

IOH

Output drive current

LVTTL

INT

VOUT = 1.4 V

—

Note: See notes under Table 3.4.

SiI9022A/SiI9024A HDMI Transmitter

Data Sheet

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SiI-DS-1076-E.01 15

Table 3.4. DC Digital I/O Specifications: IOVCC = 3.3 V

In the 81-ball and 72-pin package, IO_SEL is connected to ground.

Symbol

Parameter

Signal Type

Signal Name3

Conditions

Min

Typ

Max

Units

Notes

VIH

HIGH-level input voltage

LVTTL

CEC_D

CI2CA

IO_SEL

—

2.0

—

VIL

LOW-level input voltage

—

0.80

VTH-

HIGH to LOW threshold

Schmitt

IDCK

D[23:0]

—

1.25

—

VTH+

LOW to HIGH threshold

2.1

—

VTH-

HIGH to LOW threshold

Schmitt

MCLK

SCK

SD[3:0]

SPDIF

—

0.75

—

VTH+

LOW to HIGH threshold

1.80

—

VTH-

HIGH to LOW threshold

Schmitt

HPD

—

0.80

—

VTH+

LOW to HIGH threshold

1.85

—

VTH-

HIGH to LOW threshold

Schmitt

RESET#

—

0.85

—

VTH+

LOW to HIGH threshold

1.75

—

VTH-

HIGH to LOW threshold

Schmitt

CSCL

CSDA

—

0.70

—

VTH+

LOW to HIGH threshold

1.77

—

VTH-

HIGH to LOW threshold

Schmitt

DSCL

DSDA

—

1.5

—

VTH+

LOW to HIGH threshold

3.0

—

VTH-

HIGH to LOW threshold

Schmitt

CEC_A

—

0.8

—

VTH+

LOW to HIGH threshold

1.83

—

VOH

HIGH-level output voltage

LVTTL

INT

—

2.4

—

VOL

LOW-level output voltage

—

0.4

VOLOD

LOW-level output voltage

Open Drain

INT

—

0.4

4, 8

VCINL

Input clamp voltage

—

ICL = –18 mA

—

GND – 0.8

2, 5

VCIPL

Input clamp voltage

—

ICL = 18 mA

—

VCC + 0.8

2, 5

IIL

Input leakage current

—

High impedance

–10

—

µA

2, 9

IOL

Output drive current

Open Drain

DSCL, DSDA

VOUT = 0.4 V

—

7, 8

IOL

Output drive current

Open Drain

CSCL, CSDA

VOUT = 0.4 V

—

7, 8

IOL

Output drive current

Open Drain

CEC_A

VOUT = 0.4 V

3.5

—

IOL

Output drive current

Open Drain

CEC_D

VOUT = 0.4 V

2.0

—

IOL

Output drive current

LVTTL

INT

VOUT = 0.4 V

—

IOH

Output drive current

LVTTL

INT

VOUT = 2.4 V

—

Notes to Table 3.3 and Table 3.4:

1. Guaranteed by characterization unless otherwise noted.

2. These limits are guaranteed by design.

3. See the Ball and Pin Diagrams and Descriptions starting on page 26 for signal type designations for all package signals.

4. INT can be programmed as push-pull or open-drain. As a push-pull output, it drives VOL and VOH as defined here.

5. Guaranteed by design. Voltage undershoot or overshoot cannot exceed absolute maximum conditions for a pulse of greater

than 3 ns or for more than one third of the clock cycle, whichever is less. Exceeding the clamp current ICL listed in the Conditions

column of the table can result in permanent damage to the chip.

6. Minimum output drive specified at ambient = 85 ºC and IOVCC = 1.7 V. Typical output drive specified at ambient = 25 ºC and

IOVCC = 1.8 V. Maximum output drive specified at ambient = 0 ºC and IOVCC = 1.9 V.

7. Minimum output drive specified at ambient = 85 ºC and IOVCC = 3.0 V. Typical output drive specified at ambient = 25 ºC and

IOVCC = 3.3 V. Maximum output drive specified at ambient = 0 ºC and IOVCC = 3.6 V.

8. Do not remove IOVCC from the SiI9022A/SiI9024A HDMI Transmitter unless the attached I2C bus is completely idle.

9. Current leakage for input pins including audio and video pins will not exceed this range.

SiI9022A/SiI9024A HDMI Transmitter

Data Sheet

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16 SiI-DS-1076-E.01

Table 3.5. TMDS I/O Specifications

Symbol

Parameter

Signal Type

Conditions

Min

Typ

Max

Units

Notes

VOD

Differential outputs

single-ended swing amplitude

TMDS

RLOAD = 50 Ω

400

500

600

1, 2

VDOH

Differential HIGH level output

voltage

TMDS

—

3.3

—

IDOS

Differential output short

circuit current

TMDS

VOUT = 0 V

—

μA

—

Note:

1. Limits are defined by the HDMI Specification.

2. REXT_SWING condition as defined in the Differential Data Signals section.

DC Power Supply Specifications

Table 3.6 and Table 3.7 list the power consumption in both power-down and active modes using different IOVCC

supplies. See Table 3.8 for an explanation of the power operating modes.

Table 3.6. Low Power Standby Mode Power Consumption

Symbol

Parameter

Mode

3.3 V IOVCC

1.8 V IOVCC

1.2 V AVCC

1.2 V CVCC

Units

Notes

Typ6

Max

Ty6p

Max

Typ6

Max

Typ6

Max

IPDQ

Complete power-down

current

D3 Cold

0.15

0.20

0.018

0.022

0.05

0.066

0.02

0.025

1, 5

IPDQ

Complete power-down

current

D3 Hot

1.00

1.65

0.550

0.670

0.75

0.830

3.50

4.50

1, 5

IPDQ

Quiet power-down current

1.10

1.90

0.580

0.700

0.82

1.15

4.20

5.20

1, 5

Table 3.7. Operating Mode Power Consumption

Symbol

Parameter

Mode

Frequency

3.3 V IOVCC

1.8 V IOVCC

1.2 V AVCC

1.2 V CVCC

Units

Notes

Typ6

Max

Typ6

Max

Typ6

Max

Typ6

Max

ICCT

Transmitter

supply

current

Single-

Edge

Mode

74.25 MHz

4.0

5.4

1.0

2.4

7.5

11.8

18.0

26.7

2, 3

148.5 MHz

5.3

8.9

1.7

3.4

15.4

19.9

32.0

43.4

2, 3

162 MHz

5.0

8.7

1.5

3.2

16.5

20.9

33.0

45.6

2, 3

D0 Dual-

Edge

Mode

74.25 MHz

4.2

5.4

1.3

2.4

9.5

11.8

20.0

26.7

2, 3

148.5 MHz

7.3

10.0

2.0

3.9

18.0

20.9

34.0

44.0

2, 3

162 MHz

7.0

9.6

1.8

3.8

18.2

22.8

36.0

46.4

2, 3

Notes:

1. These values reflect the static device current with no IDCK clock applied.

2. Power is related to input clock (IDCK) frequency.

3. Maximum power limits measured with all power supplies at maximum normal operating conditions, minimum normal

operating ambient temperature, REXT_SWING as defined in the Differential Data Signals section on page 32, and a video pattern of

single-pixel vertical lines.

4. Power consumption was measured across all power rails at +10% VCC: IOVCC = 1.98 V or 3.6 V, CVCC12 = 1.32 V, and AVCC12

= 1.32 V.

5. IOVCC, CVCC12, and AVCC12 should not be removed in the low-power modes because input states and leakage current cannot

be guaranteed without all power supplies present.

6. Typical power consumption is shown for reference and may vary based on typical pattern usage of system.

SiI9022A/SiI9024A HDMI Transmitter

Data Sheet

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SiI-DS-1076-E.01 17

Table 3.8 describes the chip conditions for the various power consuming modes. Refer to the Programmer’s Reference

for details about setting different power operating modes.

Table 3.8. Power Operating Modes

Mode

Core

Running

Outputs

Powered

Oscillator

Powered

Inputs

Switching

Description

Comment

D3 Cold1,

Complete

Power

Down

Absolute

Minimum power.

Can still wake up through HPD, but

RSEN wake-up is disabled. Local I2C

interface is disabled. Hardware reset

is required to re-enable.

D3 Hot1, 2

Complete

Power

Down

Yes

Minimum power.

Can still wake up through HPD and

RSEN. Local I2C interface is disabled.

Hardware reset is required to re-

enable.

Quiet

Power

Down

Yes

Slave I2C bus

available for

Monitor events while minimizing

transmitter power.

Full Power

Yes

Full function.

Functional mode.

Notes:

1. A full hardware reset is required to wake the system up from D3 Hot or D3 Cold mode.

2. HPD must be low or Cable must not be connected prior to entering D3 Hot/Cold mode for wake-up to be valid.

AC Specifications

TMDS AC Timing Specifications

Under normal operating conditions unless otherwise specified.

Table 3.9. TMDS AC Specifications

Symbol

Parameter

Conditions

Min

Typ

Max

Units

Figure

Note

TDDF

VSYNC and HSYNC delay from DE falling edge

—

TCIP

Figure 4.4

TDDR

VSYNC and HSYNC delay to DE rising edge

—

TCIP

Figure 4.4

THDE

DE HIGH time

—

8191

TCIP

Figure 4.5

TLDE

DE LOW time

138

—

TCIP

Figure 4.5

1, 3

SLHT

Differential swing LOW-to-HIGH transition Time

RLOAD

= 50 Ω

—

Figure 4.12

2, 4, 5

SHLT

Differential swing HIGH-to-LOW transition Time

—

Figure 4.12

2, 4, 5

Notes:

1. Guaranteed by design.

2. Guaranteed by characterization.

3. TLDE (DE LOW time) minimum is defined for HDMI mode carrying 480p video with 192 kHz audio, which requires at least 138

pixel clocks of blanking to carry the audio packets. The minimum DE LOW time is 12 clocks for TMDS. For more details, see the

Minimum Horizontal Blanking Specification section (page 25). Minimum vertical blanking time is three horizontal line times.

4. Limits are defined by the HDMI Specification.

5. With REXT_SWING condition as defined in the Differential Data Signals section on page 32.

SiI9022A/SiI9024A HDMI Transmitter

Data Sheet

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18 SiI-DS-1076-E.01

Audio AC Timing Specifications

See the notes below Table 3.11.

Table 3.10. I2S Input Port Timings

Symbol

Parameter

Conditions

Min

Typ

Max

Units

Figure

FS_I2S

Sample rate

—

192

kHz

—

TSCKCYC

I2S cycle time1

CL = 10 pF

360

400

440

Figure 4.8

TSCKHIGH

I2S clock HIGH1

CL = 10 pF

110

—

TSCKLOW

I2S Clock LOW1

CL = 10 pF

110

—

TI2SSU

I2S setup time1

CL = 10 pF

—

Figure 4.8

TI2SHD

I2S hold time1

CL = 10 pF

—

Figure 4.8

TMCLKCYC

MCLK cycle time

CL = 10 pF

13.3

—

Figure 4.10

FMCLK

MCLK frequency

CL = 10 pF

—

MHz

—

TMCLKDUTY

MCLK duty cycle

CL = 10 pF

40%

—

60%

TMCLKCYC

Figure 4.10

Table 3.11. S/PDIF Input Port Timings

Symbol

Parameter

Conditions

Min

Typ

Max

Units

Figure

FS_SPDIF

Sample rate

—

192

kHz

—

TSPCYC

S/PDIF cycle time1

CL = 10 pF

—

1.0

Figure 4.9

TSPDUTY

S/PDIF duty cycle1

CL = 10 pF

90%

—

110%

Figure 4.9

TAUDDLY

Audio pipeline delay3

—

μs

—

Notes:

1. Refer to the I2S or S/PDIF specifications based on 2.5 MHz for I2S receiver.

2. Setup and hold minimum times are based on 13.388 MHz sampling, from Figure 3 of Philips I2S Specification.

3. Audio pipeline delay is measured from transmitter input signals to TMDS output. The video path delay is insignificant.

4. I2S and S/PDIF input timing is guaranteed by design to meet the listed specifications at default settings.

Video Input AC Timing Specifications

Table 3.12 lists the video input AC timing specifications when IOVCC is 1.8 V, and covers both package types. Table 3.13 on

the next page lists the timing when IOVCC is 3.3 V, and applies only to the 81-ball and 72-pin package. Data for both tables

are given for normal operating conditions unless otherwise specified.

Table 3.12. Video Input AC Specifications: 1.8 V IOVCC

Symbol

Parameter

Conditions

Min

Typ

Max

Units

Figure

Note

TCIP

IDCK period, one pixel per clock

—

Figure 4.2

FCIP

IDCK frequency, one pixel per clock

—

165

MHz

—

TCIP12

IDCK period, dual-edge clock

—

Figure 9

FCIP12

IDCK frequency, dual-edge clock

—

82.5

MHz

—

TDUTY

IDCK duty cycle: 24-bit single-edge clocking

—

30%

—

70%

TCIP

Figure 4.1

—

IDCK duty cycle: 12-bit dual-edge clocking

—

40%

—

60%

—

TIJIT

Worst case IDCK clock jitter

—

2.0

—

3, 4

TSIDF

Setup time to IDCK falling edge

Single-edge

clocking mode

—

Figure 4.2

5, 6

THIDF

Hold time to IDCK falling edge

1.8

—

Figure 4.2

TSIDR

Setup time to IDCK rising edge

—

Figure 4.2

5, 7

THIDR

Hold time to IDCK rising edge

2.0

—

Figure 4.2

TSIDF

Setup time to IDCK falling edge

12-bit dual-

edge clocking

mode

—

Figure 9

THIDF

Hold time to IDCK falling edge

2.1

—

Figure 9

TSIDR

Setup time to IDCK rising edge

—

Figure 9

THIDR

Hold time to IDCK rising edge

2.5

—

Figure 9

Note: See notes for Table 3.13.

SiI9022A/SiI9024A HDMI Transmitter

Data Sheet

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1076-E.01 19

Table 3.13. Video Input AC Specifications: 3.3 V IOVCC

3.3 V IOVCC ± 10% unless otherwise noted.

Symbol

Parameter

Conditions

Min

Typ

Max

Units

Figure

Note

TCIP

IDCK period, one pixel per clock

—

Figure 4.2

FCIP

IDCK frequency, one pixel per clock

—

165

MHz

—

TCIP12

IDCK period, dual-edge clock

—

Figure 9

FCIP12

IDCK frequency, dual-edge clock

—

82.5

MHz

—

TCIP12A

IDCK period, dual-edge clock

—

Figure 9

FCIP12A

IDCK frequency, dual-edge clock

—

165

MHz

—

TDUTY

IDCK duty cycle: 24-bit single-edge clocking

—

30%

—

70%

TCIP

Figure 4.1

—

IDCK duty cycle: 12-bit dual-edge clocking

—

40%

—

60%

—

TCH

Clock HIGH time, dual-edge clocking

FCIP > 82.5 MHz

3.6

—

Figure 4.1

—

TCL

Clock LOW time, dual-edge clocking

2.4

—

TIJIT

Worst case IDCK clock jitter

—

2.0

—

3, 4

TSIDF

Setup time to IDCK falling edge

Single-edge

clocking mode

—

Figure 4.2

5, 6

THIDF

Hold time to IDCK falling edge

1.8

—

Figure 4.2

TSIDR

Setup time to IDCK rising edge

—

Figure 4.2

THIDR

Hold time to IDCK rising edge

2.0

—

Figure 4.2

TSIDF

Setup time to IDCK falling edge

12-bit dual-

edge clocking

mode

—

Figure 9

THIDF

Hold time to IDCK falling edge

1.9

—

Figure 9

TSIDR

Setup time to IDCK rising edge

—

Figure 9

THIDR

Hold time to IDCK rising edge

2.4

—

Figure 9

Notes:

1. TCIP and FCIP apply in single-edge clocking modes. TCIP is the inverse of FCIP and is not a controlling specification.

2. TCIP12, TCIP12A, FCIP12, and FCIP12A apply in dual-edge mode. TCIP12 and TCIP12A are not controlling specifications.

3. Input clock jitter is estimated by triggering a digital scope at the rising edge of input clock, and measuring peak-to-peak time

spread of the rising edge of the input clock 1 s after the triggering.

4. Actual jitter tolerance can be higher depending on the frequency of the jitter.

5. Setup and hold time specifications apply to D[23:0] (81-ball and 72-pin package) or D[15:0] (49-ball package), DE, VSYNC, and

HSYNC input signals, relative to IDCK input clock.

6. Edge Select bit = 0.

7. Edge Select bit = 1.

8. Setup and hold limits are not affected by the Edge Select bit setting for 12-bit dual-edge clocking mode. (See the Programmer’s

Reference for information about the Edge Select bit setting.)

SiI9022A/SiI9024A HDMI Transmitter

Data Sheet

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

20 SiI-DS-1076-E.01

Control Signal Timing Specifications

Under normal operating conditions unless otherwise specified.

Table 3.14. Control Signal Timing Specifications

Symbol

Parameter

Conditions

Min

Typ

Max

Units

Figure

Note

TRESET

RESET# signal LOW time required for reset

—

100

—

µs

Figure 4.6

Figure 4.7

TI2CDVD

SDA data valid delay from SCL falling edge on

READ command

CL = 400 pF

—

700

Figure 4.13

2, 4

THDDAT

I2C data hold time

40–400 kHz

2.0

—

3, 4

TINT

Response time for INT output signal from

change in input condition (HPD, Receiver

Sense, VSYNC change, etc.).

RESET# =

HIGH

—

100

µs

Figure 4.14

FDSCL

Frequency on master DDC SCL signal

—

100

kHz

—

FCSCL

Frequency on CSCL signal

—

400

kHz

—

Notes:

1. Reset on RESET# signal can be LOW as CVCC12 and IOVCC become stable, or be pulled LOW for at least TRESET.

2. All standard-mode (100 kHz) I2C timing requirements are guaranteed by design and comply with the I2C Specification. These

timings apply to the slave I2C port (signals CSDA and CSCL) and to the master I2C port (signals DSDA and DSCL) with I2C stall

disabled.

3. This minimum hold time is required by CSCL and CSDA signals as an I2C slave. The device does not include the 300 ns internal

delay required by the I2C Specification (Version 2.1, Table 5, note 2).

4. Operation of I2C signals above 100 kHz is defined by LVTTL levels VIH, VIL, VOH, and VOL described on page 14.

5. During RESET# = LOW, the INT output signal shows whether there is an attached and powered-on TMDS receiver. See the

description of the INT signal in the Configuration and Control Signals section on page 31.

6. The Master DDC block provides an SCL signal for the E-DDC bus. The HDMI Specification limits this to I2C Standard Mode, or

100 kHz. Use of the Master DDC block does not require an active IDCK.

SiI9022A/SiI9024A HDMI Transmitter

Data Sheet

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SiI-DS-1076-E.01 21

4. Timing Diagrams

Data signals D[23:0] shown are available on the 81-ball and 72-pin device. Substitute D[15:0] for the 49-ball device.

Input Timing Diagrams

20%

80%

TDUTY

TCH

IDCK

TCIP

TCIP12

TCIP12A TCL

Figure 4.1. IDCK Clock Cycle/High/Low Times

50 % 50 %

IDCK

EDGE=0

TSIDF THIDF

50 % 50 %

IDCK

EDGE=1

TSIDR THIDR

50 % 50 %

no change allowed

TCIP

D[23:0] or D[15:0],

DE, HSYNC,VSYNC

D[23:0] or D[15:0],

DE, HSYNC,VSYNC

Signals may change only in the unshaded portion of the waveform, to meet both the minimum setup and minimum hold time

specifications.

D[23:0] are used in the 81-ball and 72-pin package; D[15:0] are used in the 49-ball package.

Figure 4.2. Control and Data Single-Edge Setup/Hold Times to IDCK

D[11:0] or D[15:4],

DE, HSYNC, VSYNC 50 % 50 %

IDCK

TSIDF THIDF

50 % 50 %

TSIDR THIDR

50 %

no change

allowed no change

allowed

Signals may change only in the unshaded portion of the waveform, to meet both the minimum setup

and minimum hold time specifications.

D[11:0] are used in the 81-ball and 72-pin package; D[15:4] are used in the 49-ball package.

TCIP12

Figure 4.3. Dual-Edge Setup/Hold Times to IDCK

SiI9022A/SiI9024A HDMI Transmitter

Data Sheet

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22 SiI-DS-1076-E.01

VSYNC, HSYNC

50%

TDDF TDDR

50%

Figure 4.4. VSYNC and HSYNC Delay Times from/to DE

TLDE

THDE

VIH

VIL

Figure 4.5. DE High/Low Times

RESET#

VCCmin

VCCmax

TRESET

VCC

Figure 4.6. Conditions for Use of RESET#

Note: VCC must be stable between its limits for Normal Operating Conditions for TRESET before RESET# goes HIGH.

RESET#

TRESET

Figure 4.7. RESET# Minimum Timings

Note: RESET# must be pulled LOW for TRESET before accessing registers. This can be done by holding RESET# LOW until TRESET after

stable power (as shown in Figure 4.6), or by pulling RESET# LOW from a HIGH state (as shown in Figure 4.7) for at least TRESET.

SiI9022A/SiI9024A HDMI Transmitter

Data Sheet

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SiI-DS-1076-E.01 23

Audio Timing Diagrams

SD[3:0], WS

SCK 0.8 V

2.0 V

0.8 V

2.0 V

TI2SSU TI2SHD

TSCKCYC TSCKDUTY TSCKDUTY

Figure 4.8. I2S Input Timings

SPDIF

50%

10%

90%

TSPDUTY

TSPCYC

Figure 4.9. S/PDIF Input Timings

MCLK

TMCLKCYC

TMCLKDUTY

50%50%

Figure 4.10. MCLK Timings

SiI9022A/SiI9024A HDMI Transmitter

Data Sheet

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

24 SiI-DS-1076-E.01

Power Supply Sequencing

Power sequencing is not usually required. Lattice Semiconductor recommends that all individual power supplies reach

their nominal levels within 5 ms in normal operation. Once powered on, the IOVCC, CVCC, and AVCC power supplies

should not be removed during any power mode including D0, D2, D3 Hot and D3 Cold.

1.2 V

(CVCC,

AVCC)

1.8 V

(IOVCC)

5 V

(DDC)

3.3 V

(IOVCC, CEC)

nominal 5 V

nominal 3.3 V

nominal 1.8 V

nominal 1.2 V T < 5 ms

Figure 4.11. Power Supply Sequencing

Output Timing Diagrams

SLHT

20% VOD

80% VOD

SHLT

Figure 4.12. Differential Transition Times

CSCL, DSCL

TI2CDVD

CSDA, DSDA

Figure 4.13. I2C Data Valid Delay (Driving Read Cycle Data)

INT Output

Interrupt

Condition TINT

Figure 4.14. INT Output Signal Response to Interrupt Condition

SiI9022A/SiI9024A HDMI Transmitter

Data Sheet

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1076-E.01 25

Minimum Horizontal Blanking Specification

Several cases define the minimum blanking time requirements. Vertical blanking times are normally multiples of the

horizontal line times and do not place a constraint on performance. (HDMI requires at least two line times in each

vertical blanking interval.) The minimum horizontal blanking time depends on the mode. An HSYNC or VSYNC edge can

occur in any clock cycle except when active video data is being transmitted. When HDMI is active, this includes the two

clocks of leading guard band for the active video data.

Table 4.1. Minimum Horizontal Blanking Calculations

Mode

Information Type

Clock Count

DVI Only

Defined by transmitter data sheet.

Total minimum horizontal blanking time

HDMI with No Data Islands

Defined by HDMI Spec (Section 5.2.3.2, page 46; and

Figure 5-3).

Minimum control period

Leading guard band

Total minimum horizontal blanking time

HDMI with One Data Island

HDMI allows a minimum of one data island, which can contain

one data packet.

Minimum control period

Leading guard band

Packet

Trailing guard band

Minimum control period

Leading guard band

Total minimum horizontal blanking time

SiI9022A/SiI9024A HDMI Transmitter

Data Sheet

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26 SiI-DS-1076-E.01

5. Ball and Pin Diagrams and Descriptions

Ball and Pin Diagrams

81-Ball VFBGA Package

Figure 5.1 shows the ball diagram for the SiI9022A/SiI9024A transmitter in the 81-ball package. See the Ball and Pin

Descriptions beginning on page 29 for a description of the ball functions. Balls are shaded using the grouping shown in

Figure 5.3 on page 28.

CEC_A

RSVDHO

AGND

TX1+

TX0+

TXC+

TXC-

AGND

EXT_SWING

CI2CA

VDDQ

TX2+

TX2-

TX1-

TX0-

CEC_D

IO_SEL

RSVDL

CSDA

CSCL

RESET#

CVCC12

IOGND

AVCC12

DSDA

DSCL

CGND

CVCC12

IOGND

IOVCC

IOGND

CVCC12

HPD

INT

D23

D22

D21

D20

IOVCC

SD1

CVCC12

IOVCC

D19

D18

D17

D16

CVCC12

SD2

SCK

SD0

D15

D14

CGND

CVCC12

SPDIF

MCLK

SD3

D12

D11

IDCK

CGND

VSYNC

D13

D10

CGND

HSYNC

Figure 5.1. 81-Ball Package Ball Diagram (Top View)

SiI9022A/SiI9024A HDMI Transmitter

Data Sheet

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SiI-DS-1076-E.01 27

49-Ball VFBGA Package

Figure 5.2 shows the ball diagram for the SiI9022A/SiI9024A transmitter in the 49-ball package. See the Ball and Pin

Descriptions beginning on page 29 for a description of the ball functions. Balls are shaded using the grouping shown in

Figure 5.3 on the next page.

TX2+

TX1+

TX1-

TX0+

TX0-

TXC+

TXC-

CEC_A

TX2-

AGND

AVCC12

DSDA

RSVDL

EXT_SWING

CSDA

CSCL

VDDQ

CVCC12

RESET#

INT

DSCL

D15

D14

IOGND

CGND

HPD

SD0

D13

D12

IOVCC

SCK

MCLK

D11

D10

IDCK

VSYNC

DE/SPDIF

HSYNC

Figure 5.2. 49-Ball Package Ball Diagram (Top View)

SiI9022A/SiI9024A HDMI Transmitter

Data Sheet

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28 SiI-DS-1076-E.01

72-Pin QFN Package

Figure 5.3 shows the pin diagram for the SiI9022A/SiI9024A transmitter in the 72-pin package. See the Ball and Pin

Descriptions beginning on page 29 for a description of the pin functions.

SiI9022A

SiI9024A

Top View

HPD

CVCC12

INT

DSDA

RESET#

CEC_D

DSCL

D20 IOVCC

SCK

CGND

D19

SD0

SD1

SD2

CSDA

MCLK

SD3

CSCL

D23

D22

D21 CVCC12

CVCC12

D12

D11

D17

D18

D16

D15

D14

D13

IOVCC

CVCC12

TX1+

TX1-

CEC_A

CI2CA

IO_SEL

TX2-

AVCC12

EXT_SWING

RSVDL

TX0+

AGND

AVCC12

TXC+

TXC-

IOGND

VDDQ

TX0-

TX2+

CVCC12

D10

IDCK

VSYNC

SPDIF

HSYNC

IOVCC

Ground

Audio and video data input

TMDS output

Audio, video, and HDMI control I/O

Chip configuration and control

Power

Reserved and not connected

Figure 5.3. 72-Pin Package Pin Diagram (Top View)

SiI9022A/SiI9024A HDMI Transmitter

Data Sheet

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SiI-DS-1076-E.01 29

Ball and Pin Descriptions

Video Input

The digital video input signals all operate from the IOVCC power plane and are tolerant up to the voltage supplied to

that plane (1.8 V or 3.3 V). These balls or pins have internal weak pull-down resistors, and are high-impedance in D3

power-down mode.

Name

VFBGA

QFN

Type

Dir

Description

49-Ball

81-Ball

72-Pin

81-Ball / 72-Pin

49-Ball

Schmitt

Input

12-bit Input Pixel Data

Bus.

These pins or balls are

used in 12-bit dual-

edge mode and in

24-bit single-edge

mode.

16-bit Input Pixel Data

Bus.

D10

D11

D12

Schmitt

Input

12-bit Input Pixel Data

Bus.

These pins or balls are

used only in 24-bit

single-edge mode. In

12-bit dual-edge mode

these signals should be

left unconnected.

D13

D14

D15

D16

D17

D18

D19

D20

D21

D22

D23

IDCK

Schmitt

Input

Input Data Clock.

Schmitt

Input

Data Enable input control signal.

DE/SPDIF

Schmitt

Input

Input DE Control Signal or S/PDIF.

HSYNC

Schmitt

Input

Horizontal sync input control signal.

VSYNC

Schmitt

Input

Vertical sync input control signal.

Note: Any unused video or control balls or pins listed in this section should be left not connected to conserve power.

SiI9022A/SiI9024A HDMI Transmitter

Data Sheet

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30 SiI-DS-1076-E.01

Audio Input

The digital audio input signals all operate from the IOVCC power plane, and are tolerant up to the voltage supplied to

that plane (1.8 V or 3.3 V). These balls or pins have weak internal pull-up resistors, and are high-impedance in D3

power-down mode.

Name

VFBGA

QFN

Type

Dir

Description

49-Ball

81-Ball

72-Pin

SCK

Schmitt

Input

I2S Serial Clock.

Schmitt

Input

I2S Word Select.

SD0

Schmitt

Input

I2S Serial Data 0.

SD1

Schmitt

Input

I2S Serial Data 1.

SD2

Schmitt

Input

I2S Serial Data 2.

SD3

Schmitt

Input

I2S Serial Data 3.

MCLK

Schmitt

Input

Audio Input Master Clock.

SPDIF

Schmitt

Input

S/PDIF Audio Input.

DE/SPDIF

Schmitt

Input

S/PDIF audio or DE control input.

(Applies to 49-ball package only.)

Note: Any unused audio balls or pins listed in this section should be left not connected to conserve power. All data, clock, and

control inputs in this section have a weak internal pullup, which is switched off in D3 mode to reduce leakage current.

CEC

The CEC signals operate from an internally generated power plane, but are tolerant up to the 3.3 V power specified for

CEC.

Name

VFBGA

QFN

Type

Dir

Description

49-Ball

81-Ball

72-Pin

CEC_A

CEC-compliant

Input/

Output

HDMI compliant CEC I/O to interface to CEC

devices.

CEC electrically compliant I/O. This ball or pin

connects to the CEC signal of all HDMI

connectors in the system.

For IOVCC = 3.3 V:

No external pullup resistor is required.

For IOVCC = 1.8 V:

A 51 kΩ pullup resistor in series with a Schottky

diode to a 3.3 V source is required; see Figure 7.5

on page 70.

As an input, the pad acts as a LVTTL Schmitt

triggered input. As an output, the pad acts as an

NMOS driver.

CEC_D

LVTTL

Input/

Output

CEC interface to local system.

This is an LVTTL I/O with a weak pull-up resistor.

This ball or pin typically connects to the local

CPU.

The CEC_D output can be disabled with

programming to allow the internal CEC logic to

handle the CEC_A signal.

SiI9022A/SiI9024A HDMI Transmitter

Data Sheet

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SiI-DS-1076-E.01 31

Configuration and Control

The configuration and control input and output signals all operate from the IOVCC 1.8 V or 3.3 V power plane, and are

tolerant up to and drive to the voltage supplied to that plane.

The CSCL, CSDA, DSCL, and DSDA signals are not true open-drain buffers. When no VCC is applied to the chip, these

signals can continue to draw a small current, and prevent the master IC from communicating with other devices on the

I2C bus. Therefore, do not remove VCC from the SiI9022A/SiI9024A HDMI Transmitter unless the attached I2C bus is

completely idle. Note that the level on the CI2CA signal is not latched internally and should not be changed during any

active I2C operations.

Name

VFBGA

QFN

Type

Dir

Description

49-Ball

81-Ball

72-Pin

HPD

Schmitt

5 V tolerant

Input

Hot Plug Detect Input.

An external 10 kΩ pulldown resistor to GND on the

board is required.

INT

LVTTL

Output

Interrupt Output.

Configurable by a register setting to be either an

active-HIGH (push-pull) output or an active-LOW

(open-drain) output. In push-pull mode, the output

drives to the corresponding level for the IOVCC

power plane. In active-LOW (default) output, an

external pull-up to 3.3 V is required.

CI2CA

LVTTL

Input

I2C Device Address Select.

For 49-ball package:

Not available. Fixed LOW internally.

For 81-ball and 72-pin package:

A 4.7 kΩ external pull-down to GND or pull-up resistor to

IO_SEL voltage level MUST be connected to this signal for

proper operation.

See the Control and Configuration section on

page 11 for additional information

RESET#

Schmitt

Input

Reset signal (active LOW). When RESET# is LOW,

all input and output pins are not functional.

CSCL

Schmitt

Open-drain

Input/

Output

Local I2C Bus Clock.

This bus accesses the compatible mode registers, the

TPI registers, and the CPI registers. An external

4.7 kΩ pullup resistor on the board is required.

CSDA

Schmitt

Open-drain

Input/

Output

Local I2C Bus Data.

This accesses the compatible mode registers, the

TPI registers, and the CPI registers..

An external 4.7 kΩ pullup resistor on the board is

required.

IO_SEL

LVTTL

Input

I/O Select.

This input sets the I/O thresholds to the proper

level to match the I/O supply voltage.

LOW – Selects 3.3 V I/O thresholds.

HIGH – Selects 1.8 V I/O thresholds.

Connect IO_SEL to 1.8 V to select 1.8 V I/O

threshold and to ground to select 3.3 V I/O

threshold.

SiI9022A/SiI9024A HDMI Transmitter

Data Sheet

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32 SiI-DS-1076-E.01

25BDDC Bus

The DDC signals operate from an internally generated power plane, but are tolerant up to the 5 V power specified for

DDC.

Name

VFBGA

QFN

Type

Dir

Description

49-Ball

81-Ball

72-Pin

DSCL

Schmitt

Open-drain

5 V tolerant

Input/

Output

DDC I2C Bus Clock.

This bus accesses the EDID and HDCP data on an

attached sink device. The DSCL signal is bi-directional,

since the transmitter monitors the state of DSCL so that

it can accommodate I2C clock stretching by the slave

device.

An external pullup resistor between 1.8 kΩ and 2.2 kΩ

on the board is required.

DSDA

Schmitt

Open-drain

5 V tolerant

Input/

Output

DDC I2C Bus Data.

This bus accesses the EDID and HDCP data on an

attached sink device.

An external pullup resistor between 1.8 kΩ and 2.2 kΩ

on the board is required.

Differential Data

Name

VFBGA

QFN

Type

Dir

Description

49-Ball

81-Ball

72-Pin

TX0+

TMDS

Output

TMDS output data pairs.

TX0-

TMDS

Output

TX1+

TMDS

Output

TX1-

TMDS

Output

TX2+

TMDS

Output

TX2-

TMDS

Output

TXC+

TMDS

Output

TMDS output clock pair.

TXC-

TMDS

Output

EXT_SWING

Analog

Input

Voltage Swing Adjust.

A resistor (REXT_SWING ) is connected from this ball or pin

to GROUND. This resistor determines the amplitude of

the voltage swing. The recommended value is 4.3 kΩ

±1% with internal source termination enabled and 5.1

kΩ ±1% without internal source termination. The value

of this resistor can be adjusted to optimize the signal

swing in the specific design.

SiI9022A/SiI9024A HDMI Transmitter

Data Sheet

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1076-E.01 33

Power and Ground

Name

VFBGA

QFN

Type

Description

49-Ball

81-Ball

72-Pin

CVCC12

C4, D3, D7,

E7, F5, G6

5, 12, 26,

42, 47, 53

Power

Digital Core VCC.

Connect to 1.2 V supply.

CGND

D1, D2, G5,

H5, J5

Ground

Digital Core GND.

IOVCC

D5, E5, E8,

3, 21, 46

Power

I/O VCC.

Connect to either the 1.8 V or 3.3 V supply. This ball must be

connected to 1.8 V in the 49-ball package.

IOGND

C5, D4, D6

Ground

I/O GND.

AVCC12

C6, C7

60, 66

Power

Analog VCC.

Connect to 1.2 V supply.

AGND

A3, A8

Ground

Analog GND.

RSVDH0

No connect

Reserved.

This ball is not connected in the 81-ball package for downward

compatibility with the SiI9022A/SiI9024A transmitter. It can be left

open, or connected to ground or CVCC12 without adverse effect.

RSVDL

LVTTL Input

Reserved.

Must be tied LOW.

VDDQ

LVTTL Input

Reserved.

Must be tied LOW.

Note: The 72-pin QFN package has an e-Pad which must be connected to the ground plane of the board.

SiI9022A/SiI9024A HDMI Transmitter

Data Sheet

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

34 SiI-DS-1076-E.01

6. Feature Information

RGB to YCbCr Color Space Converter

The RGBYCbCr color space converter can convert from video data RGB to standard definition or to high definition

YCbCr formats. Table 6.1 lists the conversion formulas that are used. The HDMI AVI packet defines the color space of

the incoming video.

Table 6.1. RGB to YCbCr Conversion Formulas

Video Format

Conversion

Formulas

CE Mode 16-235 RGB

640 × 480

ITU-R BT.601

Y = 0.299R′ + 0.587G′ + 0.114B′

Cb = –0.172R′ – 0.339G′ + 0.511B′ + 128

Cr = 0.511R′ – 0.428G′ – 0.083B′ + 128

480i

ITU-R BT.601

576i

ITU-R BT.601

480p

ITU-R BT.601

576p

ITU-R BT.601

240p

ITU-R BT.601

288p

ITU-R BT.601

720p

ITU-R BT.709

Y = 0.213R′ + 0.715G′ + 0.072B′

Cb = –0.117R′ – 0.394G′ + 0.511B′ + 128

Cr = 0.511R′ – 0.464G′ – 0.047B′ + 128

1080i

ITU-R BT.709

1080p

ITU-R BT.709

YCbCr to RGB Color Space Converter

The YCbCrRGB color space converter allows MPEG decoders to interface with RGB-only inputs. The CSC can convert

from YCbCr in standard-definition (ITU.601) or high-definition (ITU.709) to RGB. Refer to the detailed formulas in

Table 6.2X. Note the difference between RGB range for CE modes and PC modes.

Table 6.2. YCbCr-to-RGB Conversion Formulas

Format change

Conversion

YCbCr Input Color Range

YCbCr 16-235 Input

RGB 16-235 Output

601*

R′ = Y + 1.371(Cr – 128)

G′ = Y – 0.698(Cr – 128) – 0.336(Cb – 128)

B′ = Y + 1.732(Cb – 128)

7091

R′ = Y + 1.540(Cr – 128)

G′ = Y – 0.459(Cr – 128) – 0.183(Cb – 128)

B′ = Y + 1.816(Cb – 128)

YCbCr 16-235 Input

RGB 0-255 Output

601

R′ = 1.164((Y-16) + 1.371(Cr – 128))

G′ = 1.164((Y-16) – 0.698(Cr – 128) – 0.336(Cb – 128))

B′ = 1.164((Y-16) + 1.732(Cb – 128))

709

R′ = 1.164((Y-16) + 1.540(Cr – 128))

G′ = 1.164((Y-16) – 0.459(Cr – 128) – 0.183(Cb – 128))

B′ = 1.164((Y-16) + 1.816(Cb – 128))

*Note: No clipping can be done.

3D Video Formats

The SiI9022A/SiI9024A transmitter supports the 3D video modes described in the HDMI 1.4a Specification. All modes

support RGB 4:4:4, YCbCr 4:2:2, and YCbCr 4:4:4 color formats and 8-bit color depth. External separate HSYNC, VSYNC,

and DE signals can be supplied, or these signals can be supplied as embedded EAV/SAV sequences in the video stream.

Table 6.3 lists only the maximum possible resolution with a given frame rate; for example, Side-by-Side mode is defined

for 1080p60, which implies that 720p60 and 480p60 are also supported. Furthermore, a frame rate of 24 Hz also means

SiI9022A/SiI9024A HDMI Transmitter

Data Sheet

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1076-E.01 35

that a frame rate of 23.98 Hz is supported and a frame rate of 60 Hz also means a frame rate of 59.94 Hz and its

associated pixel frequency is supported.

Limitations

Frame Packing format: The Frame packing format requires Vact_space which must have constant video data. Dithering

should be disabled when transmitting the frame packing format.

The 1080p 24 Hz video format has a total of 2250 lines. However, the VRES counter (TPI 0x6C, 0x6D) of the

SiI9022A/SiI9024A device is only 11 bits, which provides for a maximum of 2047 lines. In this case, the VRES counter

will overflow and show the value of 0. This does not affect the output of the transmitter.

The DE generator is supported for all formats except 1080p 24 Hz. DE_LIN (TPI 0x68, 0x69) is only 11 bits (maximum

2047) while this value for 1080p 24 Hz should be 2205 lines.

Side-by-Side format: L frame and R frame are concatenated without a border. Since 4:4:4 to 4:2:2 downsampling and

4:2:2 dithering and upsampling to 4:4:4 has a decimation filter and looks at some adjacent pixels, these three features

should be avoided to prevent possible visible artifacts.

L + Depth format: No video processing should be used.

Top-and-Bottom format: There are no limitations.

Table 6.3. Supported 3D Video Formats

3D Format

Extended Definition

Resolution

Frame Rate (Hz)

Input Pixel Clock (MHz)

Frame Packing

—

1080p

148.5

720p

50 / 60

interlaced

1080i

50 / 60

L + Depth

—

1080p

720p

50/60

Side-by-Side

Full

1080i

50/60

720p

50/60

Half

1080p

50/60

1080p

74.25

720p

50/60

1080i 50/60

Top-and-Bottom

—

1080p

720p

50/60

S/PDIF Audio Input

The S/PDIF stream carries 2-channel uncompressed PCM data (IEC 60958) or a compressed bit stream for multi-channel

(IEC 61937) formats. The audio data capture logic described in the Audio Data Capture Logic section packetizes the

audio data according to the HDMI specification. The S/PDIF input supports audio sampling rates from 32 to 192 kHz. No

clock input is required for S/PDIF since the chip logic extracts the clock from the incoming S/PDIF data stream.

Optionally, an external MCLK source can be used.

I2S Audio Inputs

The 81-ball and 72-pin packages support four I2S inputs, SD0 through SD3, which allow transmission of DVD-Audio and

decoded Dolby Digital/DTS bit stream to A/V receivers and high-end displays. This interface supports 2-channel to 8-

channel audio with up to 192 kHz sampling rate. The input clock SCK is used to latch the incoming data; data must meet

specified setup and hold time requirements with respect to SCK.

The 49-ball package has only one I2S input, SD0, which supports only 2-channel audio up to 192 kHz sampling rate.

A separate master clock signal that is coherent with the I2S inputs is required for HDMI time-stamping purposes.

Coherent means that this clock signal and the I2S inputs must have been created from the same clock source. This clock

SiI9022A/SiI9024A HDMI Transmitter

Data Sheet

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

36 SiI-DS-1076-E.01

can be generated internally, using a PLL. As an option, the original MCLK signal used to strobe the I2S signals out from

the sourcing chip can be used. If the internal PLL is used, then an external MCLK input is not required.

Supported Audio Sampling Rates

The audio data can be down-sampled by one-half or one-fourth with register control. This feature allows the

transmitter to share the audio bus with a high-sample-rate audio DAC, while down-sampling audio for an attached

display that supports only lower rates. The transmitter supports conversions from 192 to 48 kHz, 176.4 to 44.1 kHz, 96

to 48 kHz, and 88.2 to 44.1 kHz.

The appropriate registers must be configured to describe the format of audio provided to the transmitter. This

information is passed over the HDMI link in the CEA-861D Audio Info (AI) packets.

Table 6.4 lists the supported MCLK frequencies and audio sample rates.

Table 6.4. Supported MCLK Frequencies

Multiple

of Fs

Audio Sample Rate, Fs

32 kHz1, 2

44.1 kHz1, 2

48 kHz1, 2

88.2 kHz1, 2

96 kHz1, 2

176.4 kHz2

192 kHz2

128

4.096 MHz

5.645 MHz

6.144 MHz

11.290 MHz

12.288 MHz

22.579 MHz

24.576 MHz

192

6.144 MHz

8.467 MHz

9.216 MHz

16.934 MHz

18.432 MHz

33.869 MHz

36.864 MHz

256

8.192 MHz

11.290 MHz

12.288 MHz

22.579 MHz

24.576 MHz

45.158 MHz

49.152 MHz

384

12.288 MHz

16.934 MHz

18.432 MHz

33.869 MHz

36.864 MHz

67.738 MHz

73.728 MHz

512

16.384 MHz

22.579 MHz

24.576 MHz

45.158 MHz

49.152 MHz

768

24.576 MHz

33.869 MHz

36.864 MHz

67.738 MHz

73.728 MHz

1024

32.768 MHz

45.158 MHz

49.152 MHz

1152

36.864 MHz

50.803 MHz

55.296 MHz

Notes:

1. 2-channel S/PDIF supported rate.

2. 2-channel and 8-channel I2S supported rate.

Table 6.5. S/PDIF Audio Formats Supported for each Video Format

Video Format

32 kHz

44.1 kHz

48 kHz

96 kHz

96 kHz48 kHz

192 kHz

2-ch

5.1-ch

2-ch

VGA



480i



480p



576p



720p and above



Note:  = Supported, — = Not Supported

Table 6.6. I2S Audio Formats Supported for each Video Format

Video Format

I2S Format

2-Channel Audio

8-Channel Audio

(81-Ball and 72-Pin package only)

44.1

88.2

96→48

176.4

192

192→48

88.2

192

VGA



—

480i



—

480p



—

576p



—

480p 2x



—

720p and above



Note:  = Supported, — = Not Supported

SiI9022A/SiI9024A HDMI Transmitter

Data Sheet

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SiI-DS-1076-E.01 37

I2C Register Information

I2C registers monitor and control all functions of the transmitter. For devices in the 81-ball and 72-pin package, the

device I2C addresses can be altered setting the CI2CA signal LOW or HIGH as listed in Table 6.7. An external pull-up or

pull-down resistor (depending on the desired set of I2C addresses) is used to set the level on the CI2CA signal. Note that

the level on the CI2CA signal is not latched internally and should not be changed during any active I2C operations.

The CI2CA signal is not externally accessible on the 49-ball package and is internally connected to ground. As a result,

the device I2C addresses for devices in the 49-ball package cannot be changed and are fixed to the same addresses as

when the CI2CA signal is LOW.

Table 6.7. Control of I2C Address with CI2CA Signal

Internal Function

CI2CA = LOW

CI2CA = HIGH

49-Ball / 81-Ball / 72-Pin

81-Ball / 72-Pin

Transmitter Programming Interface (TPI) device address

0x72

0x76

CEC Programming Interface (CPI) device address

0xC0

0xC4

SiI9020-compatible internal registers: first device address

0x72

0x76

SiI9020-compatible internal registers: second device address

0x7A

0x7E

Two separate sets of registers are available for the transmitter subsystem.

 SiI9020-compatible registers are nearly identical to those used by previous generations of Lattice Semiconductor

parts. These registers can run under the direct control of existing code on a host processor and are used to

perform audio/video format processing, CEA-861D InfoFrame packet formatting, and power-down control. Refer

to the SiI9020 HDMI PanelLink Transmitter Programmer’s Reference (listed in References section) for information

about these registers.

 Transmitter Programming Interface (TPI) registers represent a higher-level interface. Lattice Semiconductor

recommends using the TPI registers instead of the SiI9020-compatible registers, because they automate in

hardware many functions such as audio N-value calculation, HDCP local link authentication and integrity checking,

and HDCP repeater authentication. The HDCP feature, which was not available on the SiI9020 transmitter, can only

be used through the TPI register interface of the SiI9024A device. Refer to the Programmer’s Reference (listed in

References section) for information on these registers.

For the CEC subsystem, a set of CEC Programming Interface registers fully automates CEC handling. Refer to the CEC

Programming Interface (CPI) Programmer’s Reference (listed in References section) for information on these registers.

DDC Support

The Master DDC block supports I2C transactions specified by VESA Enhanced Display Data Channel Standard (Section

3.1.2). The Master DDC block complies with the Standard Mode timing of the I2C specification, limited to 100 kHz by

Section 8.4.1 of the HDMI specification, and supports slave clock stretching as required by E-DDC. Figure 6.1 below and

Figure 7.6 on page 71 show the connection of the HDMI connector to the DDC ports of the transmitter. Figure 6.2 on the

next page shows the supported I2C transactions.

MPEG Chip

SiI9022A Transmitter

SiI9024A Transmitter

HDMI Connnector

Video

Audio

I2C

HDMI

DDC

CEC Programming

Interface registers

Transmitter

Programming

Interface registers

DDC Master access

Figure 6.1. Simplified Host I2C Interface using Master DDC Port

SiI9022A/SiI9024A HDMI Transmitter

Data Sheet

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

38 SiI-DS-1076-E.01

S slv addr + W device offset slv addr + R data 0 data n PAsAsAsAmAm

S = start

Sr = restart

As = slave acknowledge

Am = master acknowledge

N = no ack

P = stop

* Don't care for segment 0, ACK for segment 1 and above

Current Read

S slv addr + R data 0 data n PAsAmdata 1 AmAmN/As

Sequential Read

N/As

S slv addr + W device offset slv addr + R data 0 data n PAsAsAsAmAm

Enhanced DDC Read

N/As

0x60 segment

N/AsN/As*

S slv addr + W device offset data nAsdata 0 PAsAsAsN/As

Sequential Write

Figure 6.2. Master I2C Supported Transactions

DDC Stall Support

Stall feature is also supported on the SiI9022A/SiI9024A device. Stall can be enabled after ACK or on every cycle. This

feature can also reduce an incoming 400 kHz Local I2C speed to 100 kHz DDC. Lattice Semiconductor does not recommend

enabling this feature when the incoming local I2C speed and DDC speed is set to 100 kHz since additional I2C bus free time

is required. Additionally, if a sink device supports I2C speeds higher than 100 kHz, this feature should be disabled.

Power Saving Modes and Wakeup Feature

In addition to D2 mode, the SiI9022A/SiI9024A device supports 2 additional power saving modes which include the D3

Hot and D3 Cold mode. D3 Hot mode provides better power savings compared to D2 mode. D3 Cold mode offers the

best power savings compared to D2 and D3 Hot. Once in D3 Hot or Cold modes, the I2C registers are no longer

accessible, and to regain full access to the internal registers, the transmitter must be hardware reset.

The wakeup feature is an additional function to alert the host and re-enable the SiI9022A/SiI9024A device from D3 Cold

or D3 Hot mode. The wakeup feature works by sending an INT# signal to the host when an active display sink is

connected to the transmitter. The INT# signal is generated when either an active Receiver Sense or a Hotplug signal is

detected by the transmitter.

Wakeup Support in D3 Cold and D3 Hot Modes

To enable the wakeup feature in either D3 Hot or D3 Cold mode, adhere to the following sequences; refer to the

Programmer’s Reference for more details. Table 6.8 below summarizes the detection support of D3 Hot and Cold.

Table 6.8. D3 hot and D3 Cold Feature

Mode

RSEN

Detect

Hotplug

Detect

Minimum

Requirements

Condition

D3 Cold

Complete Power

Down

Yes

HPD low or Cable

Disconnected

HPD only. Cable must be disconnected

before entering D3 Cold.

D3 Hot

Complete Power

Down

Yes

RSEN disconnected

Can be used with Display Sinks with multi

input ports that disable input but keep HPD

high.

SiI9022A/SiI9024A HDMI Transmitter

Data Sheet

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SiI-DS-1076-E.01 39

6.9.1.1. D3 Cold Wakeup

The D3 Cold Wakeup feature sends an INT signal when connecting a cable produces a Hotplug signal. Lattice

Semiconductor recommends disconnecting the cable to theSiI9022A/SiI9024A transmitter before entering D3 Cold

mode.

1. 1. Disconnect the cable.

2. 2. Clear any pending interrupts.

3. 3. Perform a hardware reset of the transmitter.

4. 4. Program register 0xC7 to 0x00 to enter TPI mode.

5. 5. Set INT# source to Hotplug using register 0x3C.

6. 6. Clear any pending interrupts.

7. 7. Enter D3 Cold mode using register 0x1E.

6.9.1.2. D3 Hot Wakeup

Unlike the D3 Cold mode, the D3 Hot mode also supports using RSEN for a wakeup event. This allows the D3 Hot mode

to support a different usage model. In a situation where the sink may have additional input ports but may disable the

inputs while keeping the Hotplug active or vice versa, a change in either the RSEN or Hotplug signal prompts an INT#

signal from the transmitter. The INT# will trigger if there is any change in the HPD signal, such as a HIGH-to-LOW

change. Since this is not the intended wakeup event required, the host can choose to re-enter the D3 Hot mode.

8. 1. Cable can be disconnected or left connected.

9. 2. Set INT# source to either RSEN or HPD.

10. 3. Clear any pending interrupts.

11. 4. Enable D3 Hot mode via register 0x1E.

Common Video Input Formats

Table 6.9 lists the bus interface formats available to support common video input resolutions. The format number in

the left column of this table lists the input modes indicated in Table 6.10 on the next page that are required to support

each format. Additional discrete CEA and VESA resolutions meeting the requirements listed in Table 3.14 on page 20

and Table 4.1 on page 25 may also be supported.

Table 6.9. Video Input Formats

Format

Input Pixel Clock (MHz)

Notes

480i400H

1, 3

480p402H

XGA

720p

1080i

1080p24

1080p

UXGA

74.25

148.5

162

—

74.25

—

74.25

148.5

162

—

148.5

—

Notes:

1. 480i support also encompasses 576i support.

2. 480p support also encompasses 576p support.

3. 480i must be input at 27 MHz using pixel replication to be transmitted across the HDMI link.

4. BTA-T1004 format is defined for a single-channel (8/10/12-bit) bus.

SiI9022A/SiI9024A HDMI Transmitter

Data Sheet

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40 SiI-DS-1076-E.01

Data Bus Mappings

The transmitter supports multiple input data mappings. Some have explicit control signals, and some have embedded

control signals. The selection of data mapping mode should be consistent at the signals and in the corresponding

register settings. Refer to the Programmer’s Reference for more details. All versions of this transmitter support up to a

maximum of 8-bit color depth in any mode.

Table 6.10. Input Video Formats

Input Mode

Input

Format

Data Bus

Width

Clock

Mode11

Sync Signals

Page

Notes

81-Ball/72-Pin

49-Ball

RGB 4:4:4

Separate

—

6, 10

YCbCr 4:4:4

Separate

—

1, 6, 10

YC 4:2:2 Separate Syncs

16, 2010, 2410

Separate

YC 4:2:2 Embedded Syncs

16, 2010, 2410

Embedded

2, 4

YC MUX 4:2:2 Separate Syncs

8, 1010, 1210

Separate

2, 3, 4, 7

YC MUX 4:2:2 Embedded Syncs

8, 1010, 1210

Embedded

2, 3, 4, 5, 7

RGB 4:4:4

dual-edge

Separate

YCbCr 4:4:4

dual-edge

Separate

1, 8

YC 4:2:2 Separate Syncs

8, 10, 12

dual-edge

Separate

2, 4, 8

YC 4:2:2 Embedded Syncs

dual-edge

Embedded

2, 4, 8

Notes:

1. 4:4:4 data contains one Cr, one Cb, and one Y value for every pixel.

2. 4:2:2 data contains one Cr and one Cb value for every two pixels, and one Y value for every pixel.

3. In YC MUX mode, data is input on one or two 8-bit channels. A 2x pixel clock is required.

4. Y and CbCr data can be input on 12 bits (as part of a 24-bit mode or as a 12-bit mode), but the two least-significant bits will be

zero since the internal data path is 10 bits wide.

5. Embedded sync decoding extracts the syncs. A 2x pixel clock is required. Note that the DE generator may be needed to convert

extracted sync timings to CEA-861D-compliant timings.

6. A 2x pixel clock can also be sent with 4:4:4 data. This is necessary when the receiver is required to reformat such a stream into

4:2:2 data or into a multiplexed YC MUX output format.

7. When sending a 2x pixel clock, the HDMI source must also send AVI InfoFrames with an accurate pixel replication

field. Refer to the HDMI Specification, section 6.4.

8. Dual-edge clocking is allowed for these video mappings. Frequencies above 82.5 MHz dual-edge mode are only supported by

the 72-pin QFN package and with IOVCC supplied at 3.3 V ± 10%.

9. The HDMI and the EIA/CEA-861D specifications require virtually every HDMI source to transmit an accurate AVI InfoFrame.

Even in the rare cases where it is not absolutely required, Lattice Semiconductor strongly recommends that an AVI InfoFrame

be transmitted during every vertical blanking interval.

10. Supported only in the 81-ball and 72-pin package.

11. Latching edge is programmable in single-edge clocking.

The transmitter can provide video across the HDMI link in various formats. Figure 6.3 on the next page shows an

overview of the processing blocks needed for some of the available format transformations from video input to HDMI

output. The TMDS encoding step is not shown in this figure. See also Figure 2.1 on page 9.

The mapping tables and timing diagrams beginning on page 42 are divided into two sections. The first is for the 81-ball

and 72-pin package, and begins on page 42; the second is for the 49-ball package, and begins on page 58. In these

tables, the term Swap indicates that the Y and the Cb/Cr pin assignments are reversed, meaning the Y signals of the

Swap mapping appear on the Cb/Cr signals of the standard mapping. The term Non-broken (NB) indicates that the

signal assignments of Y, Cb, and Cr signals are contiguous. For example, signals Y0 through Y9 appear on consecutive

data pins D[2:11], whereas in the standard mapping they may be broken by NC or Cb/Cr signals.

In the timing diagrams which follow, data bits labeled val do not convey pixel information and will contain values

defined by the relevant specification. In the diagrams showing embedded sync, the SAV and EAV sequence FF, 00, 00,

XY is specified by ITU-R BT.656.

Unused inputs should be left unconnected.

SiI9022A/SiI9024A HDMI Transmitter

Data Sheet

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SiI-DS-1076-E.01 41

Generator

YCbCrToRGB

CSC

HSYNC

VSYNC

IDCK

D[23:0]

Clock

HS,VS bypass 422

DE external DE

bypass CSC

Generator

422to444

Upsampler YCbCrToRGB

CSC Dither10To8

IDCK

D[23:0] /

D[15:0]*

Clock

Data HS,VS

DE external DE

bypass CSC

Up-sample to 4:4:4 for link Convert to RGB or allow

YCbCr, depending on EDID

Generator

IDCK

D[23:0] /

D[15:0]* bypass dither

Clock

HS,VS

DE external DE

bypass CSC

Transmit 4:2:2 Transmit YCbCr

bypass 422

422to444

Upsampler YCbCrToRGB

CSC Dither10To8

bypass CSC

Embedded syncs

with no explicit DE

bypass dither

bypass 422 bypass CSC

Transmit

4:2:2

Transmit YCbCr

RGB or YCbCr 4:4:4YCbCr 4:2:2 with syncsYCbCr 4:2:2 with syncs

RGB or YCbCr 4:4:4RGB or YCbCr 4:4:4YCbCr 4:2:2

YCbCr 4:2:2 emb. syncs

YCbCr 4:2:2 RGB or YCbCr 4:4:4

YCbCr 4:2:2 emb. syncs

Up-sample to

4:4:4 for link Convert to RGB or allow

YCbCr, depending on EDID

All signals required

for TMDS formatting.

Data

DeMux656

IDCK

D[23:0] /

D[15:0]*

Clock

HS,VS

Data

DeMux656

IDCK

D[23:0] /

D[15:0]*

Clock

HS,VS

Data

HSYNC

VSYNC

HSYNC

VSYNC

Explicit syncs, with or without DE.

Explicit syncs, with

or without DE.

bypass dither

bypass 422 bypass CSC

Transmit

4:2:2

Transmit YCbCr

YCMux 4:2:2 with syncs

DeMux YC

2x IDCK

D[15:0] /

D[7:0]

Clock

HS,VS

Data

YCbCr 4:2:2

HSYNC

VSYNC

bypass dither

bypass 422 bypass CSC

YCMux 4:2:2 emb. syncs

DeMux YC

2x IDCK

D[15:0] /

D[7:0]*

Clock

YCbCr 4:2:2

DeMux656 HS,VS

Data

Embedded syncs

with no explicit DE

Dither10To8

Dithering is required whenever

processing pixels in 10-bit internal

path, and outputting 8-bit values.

All signals required

for TMDS formatting.

All signals required

for TMDS formatting.

All signals required

for TMDS formatting.

* 49-ball VFBGA only

Figure 6.3. Parallel Input Video to HDMI Output Video Permutations

SiI9022A/SiI9024A HDMI Transmitter

Data Sheet

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

42 SiI-DS-1076-E.01

Data Mappings for 81-ball and 72-pin Package

6.11.1.1. RGB and YCbCr 4:4:4 Separate Sync Formats

The pixel clock runs at the pixel rate and a complete definition of each pixel is received on each clock cycle. Each

column in Table 6.11 lists the first pixel of n + 1 pixels in the line of video. The figure below the table shows RGB and

YCbCr data; the YCbCr 4:4:4 data is given in braces {}.

Table 6.11. RGB/YCbCr 4:4:4 Separate Sync Data Mapping (81-Ball and 72-Pin Package)

Pin Name

24-bit Data Bus

RGB

YCbCr

B0[0]

Cb0[0]

B0[1]

Cb0[1]

B0[2]

Cb0[2]

B0[3]

Cb0[3]

B0[4]

Cb0[4]

B0[5]

Cb0[5]

B0[6]

Cb0[6]

B0[7]

Cb0[7]

G0[0]

Y0[0]

G0[1]

Y0[1]

D10

G0[2]

Y0[2]

D11

G0[3]

Y0[3]

D12

G0[4]

Y0[4]

D13

G0[5]

Y0[5]

D14

G0[6]

Y0[6]

D15

G0[7]

Y0[7]

D16

R0[0]

Cr0[0]

D17

R0[1]

Cr0[1]

D18

R0[2]

Cr0[2]

D19

R0[3]

Cr0[3]

D20

R0[4]

Cr0[4]

D21

R0[5]

Cr0[5]

D22

R0[6]

Cr0[6]

D23

R0[7]

Cr0[7]

HSYNC

VSYNC

D[23:16]

blank Pixel 0 Pixel 1 Pixel 2 Pixel 3

val R0[7:0]

{Cr0[7:0]} R1[7:0]

{Cr1[7:0]} R2[7:0]

{Cr2[7:0]} R3[7:0]

{Cr3[7:0]}

D[15:8] val G0[7:0]

{Y0[7:0]} G1[7:0]

{Y1[7:0]} G2[7:0]

{Y2[7:0]} G3[7:0]

{Y3[7:0]}

D[7:0] val B0[7:0]

{Cb0[7:0]} B1[7:0]

{Cb1[7:0]} B2[7:0]

{Cb2[7:0]} B3[7:0]

{Cb3[7:0]}

IDCK

HSYNC,

VSYNC

Pixeln - 1 blank blank blankPixel n

Rn-1[7:0]

{Crn-1[7:0]} val val val

Rn[7:0]

{Crn[7:0]}

Gn-1[7:0]

{Yn-1[7:0]} val val val

Gn[7:0]

{Yn[7:0]}

Bn-1[7:0]

{Cbn-1[7:0]} val val val

Bn[7:0]

{Cbn[7:0]}

Figure 6.4. RGB/YCbCr 4:4:4 Separate Sync Timing (81-Ball and 72-Pin Package)

SiI9022A/SiI9024A HDMI Transmitter

Data Sheet

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1076-E.01 43

6.11.1.2. YC 4:2:2 Separate Sync Formats

The YC 4:2:2 formats receive one pixel for every pixel clock period. A luma (Y) value is carried for every pixel, but the

chroma values (Cb and Cr) change only every second pixel. The data bus can be 16-bit, 20-bit, or 24-bit. HSYNC and

VSYNC are driven explicitly on their own pins. Each pair of columns in Table 6.12 and Table 6.13 list the first and second

pixel of n + 1 pixels in the line of video. In the figures of this section, values in braces {} show the Swap mode. The DE

HIGH time must contain an even number of pixel clocks.

Table 6.12. 16-Bit and 20-Bit YC 4:2:2 Separate Sync Data Mapping (81-Ball and 72-Pin Package)

Name

16-bit Data Bus

Swap

20-bit Data Bus

Swap

Pixel #0

Pixel #1

Pixel #0

Pixel #1

Pixel #0

Pixel #1

Pixel #0

Pixel #1

Pixel #0

Pixel #1

D[1:0]

Y0[0]

Y1[0]

Y0[0]

Y1[0]

Cb0[0]

Cr0[0]

Y0[1]

Y1[1]

Y0[1]

Y1[1]

Cb0[1]

Cr0[1]

Y0[2]

Y1[2]

Y0[3]

Y1[3]

Cb0[0]

Cr0[0]

Y0[4]

Y1[4]

Y0[0]

Y1[0]

Cb0[1]

Cr0[1]

Y0[5]

Y1[5]

Y0[1]

Y1[1]

Y0[0]

Y1[0]

Cb0[0]

Cr0[0]

Y0[2]

Y1[2]

Y0[6]

Y1[6]

Cb0[2]

Cr0[2]

Y0[1]

Y1[1]

Cb0[1]

Cr0[1]

Y0[3]

Y1[3]

Y0[7]

Y1[7]

Cb0[3]

Cr0[3]

D10

Y0[2]

Y1[2]

Cb0[2]

Cr0[2]

Y0[4]

Y1[4]

Y0[8]

Y1[8]

Cb0[4]

Cr0[4]

D11

Y0[3]

Y1[3]

Cb0[3]

Cr0[3]

Y0[5]

Y1[5]

Y0[9]

Y1[9]

Cb0[5]

Cr0[5]

D12

Y0[4]

Y1[4]

Cb0[4]

Cr0[4]

Y0[6]

Y1[6]

Cb0[6]

Cr0[6]

D13

Y0[5]

Y1[5]

Cb0[5]

Cr0[5]

Y0[7]

Y1[7]

Cb0[7]

Cr0[7]

D14

Y0[6]

Y1[6]

Cb0[6]

Cr0[6]

Y0[8]

Y1[8]

Cb0[0]

Cr0[0]

Cb0[8]

Cr0[8]

D15

Y0[7]

Y1[7]

Cb0[7]

Cr0[7]

Y0[9]

Y1[9]

Cb0[1]

Cr0[1]

Cb0[9]

Cr0[9]

D16

Cb0[0]

Cr0[0]

Y0[0]

Y1[0]

Cb0[2]

Cr0[2]

Cb0[2]

Cr0[2]

Y0[2]

Y1[2]

D17

Cb0[1]

Cr0[1]

Y0[1]

Y1[1]

Cb0[3]

Cr0[3]

Cb0[3]

Cr0[3]

Y0[3]

Y1[3]

D18

Cb0[2]

Cr0[2]

Y0[2]

Y1[2]

Cb0[4]

Cr0[4]

Cb0[4]

Cr0[4]

Y0[4]

Y1[4]

D19

Cb0[3]

Cr0[3]

Y0[3]

Y1[3]

Cb0[5]

Cr0[5]

Cb0[5]

Cr0[5]

Y0[5]

Y1[5]

D20

Cb0[4]

Cr0[4]

Y0[4]

Y1[4]

Cb0[6]

Cr0[6]

Cb0[6]

Cr0[6]

Y0[6]

Y1[6]

D21

Cb0[5]

Cr0[5]

Y0[5]

Y1[5]

Cb0[7]

Cr0[7]

Cb0[7]

Cr0[7]

Y0[7]

Y1[7]

D22

Cb0[6]

Cr0[6]

Y0[6]

Y1[6]

Cb0[8]

Cr0[8]

Cb0[8]

Cr0[8]

Y0[8]

Y1[8]

D23

Cb0[7]

Cr0[7]

Y0[7]

Y1[7]

Cb0[9]

Cr0[9]

Cb0[9]

Cr0[9]

Y0[9]

Y1[9]

HSYNC

VSYNC

D[23:16]

blank Pixel 0 Pixel 1 Pixel 2 Pixel 3

val Cb0[7:0] Cr0[7:0] Cb2[7:0] Cr2[7:0]

D[15:8] val Y0[7:0] Y1[7:0] Y2[7:0] Y3[7:0]

IDCK

HSYNC,

VSYNC

Pixeln - 1 blank blank blankPixel n

val val val

Yn-1[7:0] val val val

Yn[7:0]

Cbn-1[7:0] Crn-1[7:0]

{Cb0[7:0]} {Cr0[7:0]} {Cb2[7:0]} {Cr2[7:0]}

{Y0[7:0]} {Y1[7:0]} {Y2[7:0]} {Y3[7:0]} {Yn-1[7:0]} {Yn[7:0]}

{Cbn-1[7:0]} {Crn-1[7:0]}

Figure 6.5. 16-Bit YC 4:2:2 Separate Sync Timing (81-Ball and 72-Pin Package)

SiI9022A/SiI9024A HDMI Transmitter

Data Sheet

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

44 SiI-DS-1076-E.01

IDCK

HSYNC,

VSYNC

D[7:6] val val val val

D[3:2] val val val val

D[23:16] val

D[15:8] val

val val val

Y0[1:0] Y1[1:0] Y2[1:0] Y3[1:0] Yn-1[1:0] Yn[1:0]

Cb0[9:2] Cr0[9:2] Cb2[9:2] Cr2[9:2] Cbn-1[9:2] Crn-1[9:2]

Y0[9:2] Y1[9:2] Y2[9:2] Y3[9:2] Yn-1[9:2] Yn[9:2]

Cbn-1[1:0] Crn-1[1:0]

Cb0[1:0] Cr0[1:0] Cb2[1:0] Cr2[1:0]

{Cb0[9:2]} {Cr0[9:2]} {Cb2[9:2]} {Cr2[9:2]} {Cbn-1[9:2]} {Crn-1[9:2]}

{Y0[9:2]} {Y1[9:2]} {Y2[9:2]} {Y3[9:2]} {Y-1[9:2]} {Yn[9:2]}

{Y0[1:0]} {Y1[1:0]} {Y2[1:0]} {Y3[1:0]} {Yn-1[1:0]} {Yn[1:0]}

{Cbn-1[1:0]} {Crn-1[1:0]}

{Cb0[1:0]} {Cr0[1:0]} {Cb2[1:0]} {Cr2[1:0]}

blank Pixel 0 Pixel 1 Pixel 2 Pixel 3 Pixeln - 1 blank blank blankPixel n

Figure 6.6. 20-Bit YC 4:2:2 Separate Sync Timing (81-Ball and 72-Pin Package)

blank Pixel 0 Pixel 1 Pixel 2 Pixel 3 Pixeln - 1 blank blank blankPixel n

IDCK

HSYNC,

VSYNC

D[23:14] val

D[11:2] val

val val val

Cb0[9:0] Cr0[9:0] Cb2[9:0] Cr2[9:0]

Y0[9:0] Y1[9:0] Y2[9:0] Y3[9:0] Yn-1[9:0] Yn[9:0]

Cbn-1[9:0] Crn-1[9:0]

Figure 6.7. 20-Bit YC 4:2:2 Separate Sync NB Mode Timing (81-Ball and 72-Pin Package)

SiI9022A/SiI9024A HDMI Transmitter

Data Sheet

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1076-E.01 45

Table 6.13. 24-Bit YC 4:2:2 Separate Sync Data Mapping (81-Ball and 72-Pin Package)

Name

24-bit Data Bus

24-bit Data Bus NB

24-bit Data Bus Swap

Pixel #0

Pixel #1

Pixel #0

Pixel #1

Pixel #0

Pixel #1

Y0[0]

Y1[0]

Y0[0]

Y1[0]

Cb0[0]

Cr0[0]

Y0[1]

Y1[1]

Y0[1]

Y1[1]

Cb0[1]

Cr0[1]

Y0[2]

Y1[2]

Y0[2]

Y1[2]

Cb0[2]

Cr0[2]

Y0[3]

Y1[3]

Y0[3]

Y1[3]

Cb0[3]

Cr0[3]

Cb0[0]

Cr0[0]

Y0[4]

Y1[4]

Y0[0]

Y1[0]

Cb0[1]

Cr0[1]

Y0[5]

Y1[5]

Y0[1]

Y1[1]

Cb0[2]

Cr0[2]

Y0[6]

Y1[6]

Y0[2]

Y1[2]

Cb0[3]

Cr0[3]

Y0[7]

Y1[7]

Y0[3]

Y1[3]

Y0[4]

Y1[4]

Y0[8]

Y1[8]

Cb0[4]

Cr0[4]

Y0[5]

Y1[5]

Y0[9]

Y1[9]

Cb0[5]

Cr0[5]

D10

Y0[6]

Y1[6]

Y0[10]

Y1[10]

Cb0[6]

Cr0[6]

D11

Y0[7]

Y1[7]

Y0[11]

Y1[11]

Cb0[7]

Cr0[7]

D12

Y0[8]

Y1[8]

Cb0[0]

Cr0[0]

Cb0[8]

Cr0[8]

D13

Y0[9]

Y1[9]

Cb0[1]

Cr0[1]

Cb0[9]

Cr0[9]

D14

Y0[10]

Y1[10]

Cb0[2]

Cr0[2]

Cb0[10]

Cr0[10]

D15

Y0[11]

Y1[11]

Cb0[3]

Cr0[3]

Cb0[11]

Cr0[11]

D16

Cb0[4]

Cr0[4]

Cb0[4]

Cr0[4]

Y0[4]

Y1[4]

D17

Cb0[5]

Cr0[5]

Cb0[5]

Cr0[5]

Y0[5]

Y1[5]

D18

Cb0[6]

Cr0[6]

Cb0[6]

Cr0[6]

Y0[6]

Y1[6]

D19

Cb0[7]

Cr0[7]

Cb0[7]

Cr0[7]

Y0[7]

Y1[7]

D20

Cb0[8]

Cr0[8]

Cb0[8]

Cr0[8]

Y0[8]

Y1[8]

D21

Cb0[9]

Cr0[9]

Cb0[9]

Cr0[9]

Y0[9]

Y1[9]

D22

Cb0[10]

Cr0[10]

Cb0[10]

Cr0[10]

Y0[10]

Y1[10]

D23

Cb0[11]

Cr0[11]

Cb0[11]

Cr0[11]

Y0[11]

Y1[11]

HSYNC

VSYNC

Y0[11:4] Y1[11:4] Y2[11:4] Y3[11:4] Yn-1[11:4]

{Y0[3:0]} {Y1[3:0]} {Y2[3:0]} {Y3[3:0]}

Yn[11:4]

{Yn-1[3:0]} {Yn[3:0]}

Cb0[11:4] Cr0[11:4] Cb2[11:4] Cr2[11:4] Cbn-1[11:4] Crn-1[11:4]

{Y0[11:4]} {Y1[11:4]} {Y2[11:4]} {Y3[11:4]} {Yn-1[11:4]} {Yn[11:4]}

IDCK

HSYNC,

VSYNC

D[7:4] val val val val

D[3:0] val val val val

D[23:16] val

D[15:8] val

val val val

blank Pixel 0 Pixel 1 Pixel 2 Pixel 3 Pixeln - 1 blank blank blankPixel n

Cb0[3:0] Cr0[3:0] Cb2[3:0] Cr2[3:0] Cbn-1[3:0] Crn-1[3:0]

{Cb0[3:0]} {Cr0[3:0]} {Cb2[3:0]} {Cr2[3:0]} {Cbn-1[3:0]} {Crn-1[3:0]}

{Cb0[11:4]} {Cr0[11:4]} {Cb2[11:4]} {Cr2[11:4]} {Cbn-1[11:4]} {Crn-1[11:4]}

Y0[3:0] Y1[3:0] Y2[3:0] Y3[3:0] Yn-1[3:0] Yn[3:0]

Figure 6.8. 24-Bit YC 4:2:2 Separate Sync Timing (81-Ball and 72-Pin Package)

SiI9022A/SiI9024A HDMI Transmitter

Data Sheet

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

46 SiI-DS-1076-E.01

blank Pixel 0 Pixel 1 Pixel 2 Pixel 3 Pixeln - 1 blank blank blankPixel n

IDCK

HSYNC,

VSYNC

D[23:12] val

D[11:0] val

val val val

Cb0[11:0] Cr0[11:0] Cb2[11:0] Cr2[11:0]

Y0[11:0] Y1[11:0] Y2[11:0] Y3[11:0]

Cbn-1[11:0] Crn-1[11:0]

Yn-1[11:0] Yn[11:0]

Figure 6.9. 24-Bit YC 4:2:2 Separate Sync NB Mode Timing (81-Ball and 72-Pin Package)

6.11.1.3. YC 4:2:2 Embedded Sync Formats

The Embedded Sync format is identical to the YC 4:2:2 Formats with Separate Syncs format, except that the syncs are

embedded and not explicit. The data bus can be 16-bit, 20-bit, or 24-bit. Each pair of columns in Table 6.14 and Table

6.15 list the first and second pixel of n + 1 pixels in the line of video. In the figures of this section, values in braces {}

show the Swap mode.

Table 6.14. 16-Bit and 20-Bit YC 4:2:2 Embedded Sync Data Mapping (81-Ball and 72-Pin Package)

Name

16-bit Data Bus

Swap

20-bit Data Bus

Swap

20-bit Data Bus

Pixel #0

Pixel #1

Pixel #0

Pixel #1

Pixel #0

Pixel #1

Pixel #0

Pixel #1

Pixel #0

Pixel #1

D[1:0]

Y0[0]

Y1[0]

Cb0[0]

Cr0[0]

Y0[0]

Y1[0]

Y0[1]

Y1[1]

Cb0[1]

Cr0[1]

Y0[1]

Y1[1]

Y0[2]

Y1[2]

Y0[3]

Y1[3]

Cb0[0]

Cr0[0]

Y0[0]

Y1[0]

Y0[4]

Y1[4]

Cb0[1]

Cr0[1]

Y0[1]

Y1[1]

Y0[5]

Y1[5]

Y0[0]

Y1[0]

Cb0[0]

Cr0[0]

Y0[2]

Y1[2]

Cb0[2]

Cr0[2]

Y0[6]

Y1[6]

Y0[1]

Y1[1]

Cb0[1]

Cr0[1]

Y0[3]

Y1[3]

Cb0[3]

Cr0[3]

Y0[7]

Y1[7]

D10

Y0[2]

Y1[2]

Cb0[2]

Cr0[2]

Y0[4]

Y1[4]

Cb0[4]

Cr0[4]

Y0[8]

Y1[8]

D11

Y0[3]

Y1[3]

Cb0[3]

Cr0[3]

Y0[5]

Y1[5]

Cb0[5]

Cr0[5]

Y0[9]

Y1[9]

D12

Y0[4]

Y1[4]

Cb0[4]

Cr0[4]

Y0[6]

Y1[6]

Cb0[6]

Cr0[6]

D13

Y0[5]

Y1[5]

Cb0[5]

Cr0[5]

Y0[7]

Y1[7]

Cb0[7]

Cr0[7]

D14

Y0[6]

Y1[6]

Cb0[6]

Cr0[6]

Y0[8]

Y1[8]

Cb0[8]

Cr0[8]

Cb0[0]

Cr0[0]

D15

Y0[7]

Y1[7]

Cb0[7]

Cr0[7]

Y0[9]

Y1[9]

Cb0[9]

Cr0[9]

Cb0[1]

Cr0[1]

D16

Cb0[0]

Cr0[0]

Y0[0]

Y1[0]

Cb0[2]

Cr0[2]

Y0[2]

Y1[2]

Cb0[2]

Cr0[2]

D17

Cb0[1]

Cr0[1]

Y0[1]

Y1[1]

Cb0[3]

Cr0[3]

Y0[3]

Y1[3]

Cb0[3]

Cr0[3]

D18

Cb0[2]

Cr0[2]

Y0[2]

Y1[2]

Cb0[4]

Cr0[4]

Y0[4]

Y1[4]

Cb0[4]

Cr0[4]

D19

Cb0[3]

Cr0[3]

Y0[3]

Y1[3]

Cb0[5]

Cr0[5]

Y0[5]

Y1[5]

Cb0[5]

Cr0[5]

D20

Cb0[4]

Cr0[4]

Y0[4]

Y1[4]

Cb0[6]

Cr0[6]

Y0[6]

Y1[6]

Cb0[6]

Cr0[6]

D21

Cb0[5]

Cr0[5]

Y0[5]

Y1[5]

Cb0[7]

Cr0[7]

Y0[7]

Y1[7]

Cb0[7]

Cr0[7]

D22

Cb0[6]

Cr0[6]

Y0[6]

Y1[6]

Cb0[8]

Cr0[8]

Y0[8]

Y1[8]

Cb0[8]

Cr0[8]

D23

Cb0[7]

Cr0[7]

Y0[7]

Y1[7]

Cb0[9]

Cr0[9]

Y0[9]

Y1[9]

Cb0[9]

Cr0[9]

HSYNC

VSYNC

SiI9022A/SiI9024A HDMI Transmitter

Data Sheet

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1076-E.01 47

SAV Pixel 0 Pixel 1 Pixel 2 Pixel 3

D[23:16]

IDCK

Active

video

EAV

D[15:8]

Pixel n - 1 Pixel n

00FF

nc nc nc nc nc nc nc nc

Cb0[7:0] Cr0[7:0] Cb2[7:0] Cr2[7:0]

Y0[7:0] Y1[7:0] Y2[7:0] Y3[7:0]

{Cb0[7:0]} {Cr0[7:0]} {Cb2[7:0]} {Cr2[7:0]}

{Y0[7:0]} {Y1[7:0]} {Y2[7:0]} {Y3[7:0]}

Yn-1[7:0] Yn[7:0]

Cbn-1[7:0] Crn-1[7:0]

{Yn-1[7:0]} {Yn[7:0]}

{Cbn-1[7:0]} {Crn-1[7:0]}

Figure 6.10. 16-Bit YC 4:2:2 Embedded Sync Timing (81-Ball and 72-Pin Package)

Y0[1:0] Y1[1:0] Y2[1:0] Y3[1:0]

Cb0[9:2] Cr0[9:2] Cb2[9:2] Cr2[9:2]

Y0[9:2] Y1[9:2] Y2[9:2] Y3[9:2]

Cb0[1:0] Cr0[1:0] Cb2[1:0] Cr2[1:0]

{Cr0[9:2]} {Cb2[9:2]} {Cr2[9:2]}

{Y0[9:2]} {Y1[9:2]} {Y2[9:2]} {Y3[9:2]}

{Y0[1:0]} {Y1[1:0]} {Y2[1:0]} {Y3[1:0]}

{Cb0[1:0]} {Cr0[1:0]} {Cb2[1:0]} {Cr2[1:0]}

{Cb0[9:2]}

Yn-1[1:0] Yn[1:0]

Cbn-1[9:2] Crn-1[9:2]

Yn-1[9:2] Yn[9:2]

Cbn-1[1:0] Crn-1[1:0]

{Cbn-1[9:2]} {Crn-1[9:2]}

{Y-1[9:2]} {Yn[9:2]}

{Yn-1[1:0]} {Yn[1:0]}

{Cbn-1[1:0]} {Crn-1[1:0]}

D[23:16]

SAV Pixel 0 Pixel 1 Pixel 2 Pixel 3

D[15:8]

IDCK

Active

video

EAV

D[7:6]

D[3:2]

Pixel n - 1 Pixel n

00FF

nc nc nc nc nc nc nc nc

Figure 6.11. 20-Bit YC 4:2:2 Embedded Sync Timing (81-Ball and 72-Pin Package)

SAV Pixel 0 Pixel 1 Pixel 2 Pixel 3

D[23:14]

IDCK

Active

video

EAV

D[11:2]

Pixel n - 1 Pixel n

00FF

nc nc nc nc nc nc nc nc

Cb0[9:0] Cr0[9:0] Cb2[9:0] Cr2[9:0]

Y0[9:0] Y1[9:0] Y2[9:0] Y3[9:0] Yn-1[9:0] Yn[9:0]

Cbn-1[9:0] Crn-1[9:0]

Figure 6.12. 20-Bit YC 4:2:2 Embedded Sync NB Mode Timing (81-Ball and 72-Pin Package)

SiI9022A/SiI9024A HDMI Transmitter

Data Sheet

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

48 SiI-DS-1076-E.01

Table 6.15. 24-Bit YC 4:2:2 Embedded Sync Data Mapping (81-Ball and 72-Pin Package)

Name

24-bitData Bus

Swap

24-bitData Bus

Pixel #0

Pixel #1

Pixel #0

Pixel #1

Pixel #0

Pixel #1

Y0[0]

Y1[0]

Cb0[0]

Cr0[0]

Y0[0]

Y1[0]

Y0[1]

Y1[1]

Cb0[1]

Cr0[1]

Y0[1]

Y1[1]

Y0[2]

Y1[2]

Cb0[2]

Cr0[2]

Y0[2]

Y1[2]

Y0[3]

Y1[3]

Cb0[3]

Cr0[3]

Y0[3]

Y1[3]

Cb0[0]

Cr0[0]

Y0[0]

Y1[0]

Y0[4]

Y1[4]

Cb0[1]

Cr0[1]

Y0[1]

Y1[1]

Y0[5]

Y1[5]

Cb0[2]

Cr0[2]

Y0[2]

Y1[2]

Y0[6]

Y1[6]

Cb0[3]

Cr0[3]

Y0[3]

Y1[3]

Y0[7]

Y1[7]

Y0[4]

Y1[4]

Cb0[4]

Cr0[4]

Y0[8]

Y1[8]

Y0[5]

Y1[5]

Cb0[5]

Cr0[5]

Y0[9]

Y1[9]

D10

Y0[6]

Y1[6]

Cb0[6]

Cr0[6]

Y0[10]

Y1[10]

D11

Y0[7]

Y1[7]

Cb0[7]

Cr0[7]

Y0[11]

Y1[11]

D12

Y0[8]

Y1[8]

Cb0[8]

Cr0[8]

Cb0[0]

Cr0[0]

D13

Y0[9]

Y1[9]

Cb0[9]

Cr0[9]

Cb0[1]

Cr0[1]

D14

Y0[10]

Y1[10]

Cb0[10]

Cr0[10]

Cb0[2]

Cr0[2]

D15

Y0[11]

Y1[11]

Cb0[11]

Cr0[11]

Cb0[3]

Cr0[3]

D16

Cb0[4]

Cr0[4]

Y0[4]

Y1[4]

Cb0[4]

Cr0[4]

D17

Cb0[5]

Cr0[5]

Y0[5]

Y1[5]

Cb0[5]

Cr0[5]

D18

Cb0[6]

Cr0[6]

Y0[6]

Y1[6]

Cb0[6]

Cr0[6]

D19

Cb0[7]

Cr0[7]

Y0[7]

Y1[7]

Cb0[7]

Cr0[7]

D20

Cb0[8]

Cr0[8]

Y0[8]

Y1[8]

Cb0[8]

Cr0[8]

D21

Cb0[9]

Cr0[9]

Y0[9]

Y1[9]

Cb0[9]

Cr0[9]

D22

Cb0[10]

Cr0[10]

Y0[10]

Y1[10]

Cb0[10]

Cr0[10]

D23

Cb0[11]

Cr0[11]

Y0[11]

Y1[11]

Cb0[11]

Cr0[11]

HSYNC

VSYNC

D[23:16]

SAV Pixel 0 Pixel 1 Pixel 2 Pixel 3

D[15:8]

IDCK

Active

video

EAV

D[7:4]

D[3:0]

Pixel n - 1 Pixel n

00FF

nc nc nc nc nc nc nc nc

Y0[11:4] Y1[11:4] Y2[11:4] Y3[11:4]

{Y0[3:0]} {Y1[3:0]} {Y2[3:0]} {Y3[3:0]}

Cb0[11:4] Cr0[11:4] Cb2[11:4] Cr2[11:4]

{Y0[11:4]} {Y1[11:4]} {Y2[11:4]} {Y3[11:4]}

Cb0[3:0] Cr0[3:0] Cb2[3:0] Cr2[3:0]

{Cb0[3:0]} {Cr0[3:0]} {Cb2[3:0]} {Cr2[3:0]}

{Cb0[11:4]} {Cr0[11:4]} {Cb2[11:4]} {Cr2[11:4]}

Y0[3:0] Y1[3:0] Y2[3:0] Y3[3:0]

Yn-1[11:4] Yn[11:4]

{Yn-1[3:0]} {Yn[3:0]}

Cbn-1[11:4] Crn-1[11:4]

{Yn-1[11:4]} {Yn[11:4]}

Cbn-1[3:0] Crn-1[3:0]

{Cbn-1[3:0]} {Crn-1[3:0]}

n-1[11:4]} {Crn-1[11:4]}

Yn-1[3:0] Yn[3:0]

Figure 6.13. 24-Bit YC 4:2:2 Embedded Sync Timing (81-Ball and 72-Pin Package)

SiI9022A/SiI9024A HDMI Transmitter

Data Sheet

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1076-E.01 49

SAV Pixel 0 Pixel 1 Pixel 2 Pixel 3

D[23:12]

IDCK

Active

video

EAV

D[11:0]

Pixel n - 1 Pixel n

00FF

nc nc nc nc nc nc nc nc

Cb0[11:0] Cr0[11:0] Cb2[11:0] Cr2[11:0]

Y0[11:0] Y1[11:0] Y2[11:0] Y3[11:0]

Cbn-1[11:0] Crn-1[11:0]

Yn-1[11:0] Yn[11:0]

Figure 6.14. 24-Bit YC 4:2:2 Embedded Sync NB Mode Timing (81-Ball and 72-Pin Package)

6.11.1.4. YC Mux 4:2:2 Separate Sync Formats

The video data is multiplexed onto fewer pins than the mapping described in the YC 4:2:2 Separate Sync Formats on

page 43. The clock rate is doubled so a chroma value is sent for each pixel, followed by a corresponding luma value for

the same pixel. Thus, a luma (Y) value is provided for each pixel, while the Cb and Cr values alternate on successive

pixels. Each group of four columns in Table 6.16 lists the four clock cycles for the first two pixels of the line. Pixel values

for Cr0 and Y0 values are sent with the first pixel (first two clock cycles). Then the Cb0 and Y1 values are sent with the

second pixel (next two clock cycles). The figures below the table show how this pattern is extended for the rest of the

pixels in a video line of n + 1 pixels.

Table 6.16. 8-, 10-, and 12-Bit YC Mux 4:2:2 Separate Sync Data Mapping (81-Ball and 72-Pin Package)

Name

8-bit Data Bus

10-bit Data Bus

12-bit Data Bus

Clock cycle

First

Second

Third

Fourth

First

Second

Third

Fourth

First

Second

Third

Fourth

Cb0[0]

Y0[0]

Cr0[0]

Y1[0]

Cb0[1]

Y0[1]

Cr0[1]

Y1[1]

Cb0[0]

Y0[0]

Cr0[0]

Y1[0]

Cb0[2]

Y0[2]

Cr0[2]

Y1[2]

Cb0[1]

Y0[1]

Cr0[1]

Y1[1]

Cb0[3]

Y0[3]

Cr0[3]

Y1[3]

D[7:4]

Cb0[0]

Y0[0]

Cr0[0]

Y1[0]

Cb0[2]

Y0[2]

Cr0[2]

Y1[2]

Cb0[4]

Y0[4]

Cr0[4]

Y1[4]

Cb0[1]

Y0[1]

Cr0[1]

Y1[1]

Cb0[3]

Y0[3]

Cr0[3]

Y1[3]

Cb0[5]

Y0[5]

Cr0[5]

Y1[5]

D10

Cb0[2]

Y0[2]

Cr0[2]

Y1[2]

Cb0[4]

Y0[4]

Cr0[4]

Y1[4]

Cb0[6]

Y0[6]

Cr0[6]]

Y1[6]

D11

Cb0[3]

Y0[3]

Cr0[3]

Y1[3]

Cb0[5]

Y0[5]

Cr0[5]

Y1[5]

Cb0[7]

Y0[7]

Cr0[7]

Y1[7]

D12

Cb0[4]

Y0[4]

Cr0[4]

Y1[4]

Cb0[6]

Y0[6]

Cr0[6]]

Y1[6]

Cb0[8]

Y0[8]

Cr0[8]

Y1[8]

D13

Cb0[5]

Y0[5]

Cr0[5]

Y1[5]

Cb0[7]

Y0[7]

Cr0[7]

Y1[7]

Cb0[9]

Y0[9]

Cr0[9]

Y1[9]

D14

Cb0[6]

Y0[6]

Cr0[6]]

Y1[6]

Cb0[8]

Y0[8]

Cr0[8]

Y1[8]

Cb0[10]

Y0[10]

Cr0[10]

Y1[10]

D15

Cb0[7]

Y0[7]

Cr0[7]

Y1[7]

Cb0[9]

Y0[9]

Cr0[9]

Y1[9]

Cb0[11]

Y0[11]

Cr0[11]

Y1[11]

D[23:16]

HSYNC

VSYNC

D[15:8] Y1[7:0] Cb2[7:0] Y2[7:0] Cr2[7:0]

IDCK

Yn-1[7:0] Yn[7:0]

HSYNC

VSYNC

Cb0[7:0] Y0[7:0] Cr0[7:0] Y3[7:0] Cbn-1[7:0] Crn-1[7:0]

Pixel 0 Pixel 1 Pixel 2 Pixel 3 Pixel n - 1 Pixel n

val val

Figure 6.15. 8-Bit YC Mux 4:2:2 Separate Sync Timing (81-Ball and 72-Pin Package)

SiI9022A/SiI9024A HDMI Transmitter

Data Sheet

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

50 SiI-DS-1076-E.01

D[15:8] Y1[9:2] Cb2[9:2] Y2[9:2] Cr2[9:2]

IDCK

Yn-1[9:2] Yn[9:2]

HSYNC

VSYNC

Cb0[9:2] Y0[9:2] Cr0[9:2] Y3[9:2] Cbn-1[9:2] Crn-1[9:2]

Pixel 0 Pixel 1 Pixel 2 Pixel 3 Pixel n - 1 Pixel n

val val

D[3:2] Y1[1:0] Cb2[1:0] Y2[1:0] Cr2[1:0] Yn-1[1:0] Yn[1:0]

Cb0[1:0] Y0[1:0] Cr0[1:0] Y3[1:0] Cbn-1[1:0] Crn-1[1:0]

val val

Figure 6.16. 10-Bit YC Mux 4:2:2 Separate Sync Timing (81-Ball and 72-Pin Package)

D[15:8] Y1[11:4] Cb2[11:4] Y2[11:4] Cr2[11:4]

IDCK

Yn-1[11:4] Yn[11:4]

HSYNC

VSYNC

Cb0[11:4] Y0[11:4] Cr0[11:4] Y3[11:4] Cbn-1[11:4] Crn-1[11:4]

Pixel 0 Pixel 1 Pixel 2 Pixel 3 Pixel n - 1 Pixel n

val val

D[3:0] Y1[3:0] Cb2[3:0] Y2[3:0] Cr2[3:0] Yn-1[3:0] Yn[3:0]

Cb0[3:0] Y0[3:0] Cr0[3:0] Y3[3:0] Cbn-1[3:0] Crn-1[3:0]

val val

Figure 6.17. 12-Bit YC Mux 4:2:2 Separate Sync Timing (81-Ball and 72-Pin Package)

SiI9022A/SiI9024A HDMI Transmitter

Data Sheet

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1076-E.01 51

6.11.1.5. YC Mux 4:2:2 Embedded Sync Formats

This format is similar to the one described in the YC Mux 4:2:2 Separate Sync Formats section on page 49, except the

syncs are embedded. Normally this mode is used only for 480i, 480p, 576i and 576p modes. It is similar to SMTPE 293

in embedding the syncs. A luma (Y) value is provided for each pixel, while the Cb and Cr values alternate on successive

pixels. The input clock rate is twice the pixel clock rate. Each group of four columns in Table 6.17 lists the four clock

cycles for the first two pixels of the line. Pixel values for Cr0 and Y0 values are sent with the first pixel (first two clock

cycles). Then the Cb0 and Y1 values are sent with the second pixel (next two clock cycles). The figures following this

table show only the first two pixels and last pixel of the line to make room to show the SAV and EAV sequences, but the

remaining pixels are similar to those shown in the figures of the previous section. 480p, 54 MHz input can be achieved

if the input clock is 54 MHz. The DE generator may be needed to convert extracted sync timings to CEA-861D timings.

See the ITU-R BT.656 Specification.

Table 6.17. 8-, 10-, and 12-Bit YC Mux 4:2:2 Embedded Sync Data Mapping (81-Ball and 72-Pin Package)

Name

8-bit Data Bus

10-bit Data Bus

12-bit Data Bus

Clock cycle

First

Second

Third

Fourth

First

Second

Third

Fourth

First

Second

Third

Fourth

Cb0[0]

Y0[0]

Cr0[0]

Y1[0]

Cb0[1]

Y0[1]

Cr0[1]

Y1[1]

Cb0[0]

Y0[0]

Cr0[0]

Y1[0]

Cb0[2]

Y0[2]

Cr0[2]

Y1[2]

Cb0[1]

Y0[1]

Cr0[1]

Y1[1]

Cb0[3]

Y0[3]

Cr0[3]

Y1[3]

D[7:4]

Cb0[0]

Y0[0]

Cr0[0]

Y1[0]

Cb0[2]

Y0[2]

Cr0[2]

Y1[2]

Cb0[4]

Y0[4]

Cr0[4]

Y1[4]

Cb0[1]

Y0[1]

Cr0[1]

Y1[1]

Cb0[3]

Y0[3]

Cr0[3]

Y1[3]

Cb0[5]

Y0[5]

Cr0[5]

Y1[5]

D10

Cb0[2]

Y0[2]

Cr0[2]

Y1[2]

Cb0[4]

Y0[4]

Cr0[4]

Y1[4]

Cb0[6]

Y0[6]

Cr0[6]]

Y1[6]

D11

Cb0[3]

Y0[3]

Cr0[3]

Y1[3]

Cb0[5]

Y0[5]

Cr0[5]

Y1[5]

Cb0[7]

Y0[7]

Cr0[7]

Y1[7]

D12

Cb0[4]

Y0[4]

Cr0[4]

Y1[4]

Cb0[6]

Y0[6]

Cr0[6]]

Y1[6]

Cb0[8]

Y0[8]

Cr0[8]

Y1[8]

D13

Cb0[5]

Y0[5]

Cr0[5]

Y1[5]

Cb0[7]

Y0[7]

Cr0[7]

Y1[7]

Cb0[9]

Y0[9]

Cr0[9]

Y1[9]

D14

Cb0[6]

Y0[6]

Cr0[6]]

Y1[6]

Cb0[8]

Y0[8]

Cr0[8]

Y1[8]

Cb0[10]

Y0[10]

Cr0[10]

Y1[10]

D15

Cb0[7]

Y0[7]

Cr0[7]

Y1[7]

Cb0[9]

Y0[9]

Cr0[9]

Y1[9]

Cb0[11]

Y0[11]

Cr0[11]

Y1[11]

D[23:16]

HSYNC

VSYNC

SAV Pixel 0 Pixel 1

D[15:8] XY Cb0[7:0]

IDCK

Active

video

EAV

Pixel n

00FF Y0[7:0] Cr0[7:0] Y1[7:0] Crn-1[7:0] Yn[7:0] XY

00FF

Figure 6.18. 8-Bit YC Mux 4:2:2 Embedded Sync Timing (81-Ball and 72-Pin Package)

SAV Pixel 0 Pixel 1

D[15:8] Cb0[9:2]

IDCK

Active

video

EAV

Pixel n

D[3:2]

Y0[9:2] Cr0[9:2] Y1[9:2] Crn-1[9:2] Yn[9:2]

Crn-1[1:0] Yn[1:0]

Cb0[1:0] Y0[1:0] Cr0[1:0] Y1[1:0]

00FF XY

00FF

00FF XY

00FF

Figure 6.19. 10-Bit YC Mux 4:2:2 Embedded Sync Timing (81-Ball and 72-Pin Package)

SiI9022A/SiI9024A HDMI Transmitter

Data Sheet

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

52 SiI-DS-1076-E.01

SAV Pixel 0 Pixel 1

D[15:8] Cb0[11:4]

IDCK

Active

video

EAV

Pixel n

D[3:0]

Y0[11:4] Cr0[11:4] Y1[11:4] Crn-1[11:4] Yn[11:4]

Crn-1[3:0] Yn[3:0]

Cb0[3:0] Y0[3:0] Cr0[3:0] Y1[3:0]

00FF XY

00FF

00FF XY

00FF

Figure 6.20. 12-Bit YC Mux 4:2:2 Embedded Sync Timing (81-Ball and 72-Pin Package)

SiI9022A/SiI9024A HDMI Transmitter

Data Sheet

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1076-E.01 53

6.11.1.6. YC 4:2:2 Embedded Sync Dual Edge Format

The pixel clock runs at the pixel rate and a complete definition of each pixel is received on each clock. One clock edge

latches in half the pixel data on 12 pins. The opposite clock edge latches in the remaining half of the pixel data on the

same 12 pins. Data signals (Dx]) must change state to meet the setup and hold times, specified for the 12-bit dual edge

mode, with respect to the first edge of IDCK as defined by the setting of the Edge Select bit. See Table 3.12 on page 18

or Table 3.13 on page 19. The syncs are embedded and not explicit. Figure 6.21 lists IDCK latching input data when the

Edge Select bit is set to 1 (first edge is the rising edge).

Table 6.18. 12-Bit YC 4:2:2 Embedded Sync Dual Edge Data Mapping (81-Ball and 72-Pin Package)

Pin Name

12-bit Data Bus

Pixel #0

Pixel #1

First Edge

Second Edge

First Edge

Second Edge

Y0[0]

Y0[8]

Y1[0]

Y1[8]

Y0[1]

Y0[9]

Y1[1]

Y1[9]

Y0[2]

Y0[10]

Y1[2]

Y1[10]

Y0[3]

Y0[11]

Y13]

Y1[11]

Cb0[0]

Cb0[4]

Cr0[0]

Cr0[4]

Cb0[1]

Cb0[5]

Cr0[1]

Cr0[5]

Cb0[2]

Cb0[6]

Cr0[2]

Cr0[6]

Cb0[3]

Cb0[7]

Cr0[3]

Cr0[7]

Y0[4]

Cb0[8]

Y1[4]

Cr0[8]

Y0[5]

Cb0[9]

Y1[5]

Cr0[9]

D10

Y0[6]

Cb0[10]

Y1[6]

Cr0[10]

D11

Y0[7]

Cb0[11]

Y1[7]

Cr0[11]

D[23:12]

HSYNC

—

VSYNC

—

SAV Pixel 0 Pixel 1

D[11:8]

IDCK

Active

video

D[7:4]

D[3:0]

00FF

nc nc nc nc nc nc nc nc

nc Y0[3:0] Y0[11:8]

Cb0[3:0] Cb0[7:4]

Y0[7:4] Cb0[11:8]

Y1[3:0] Y1[11:8]

Cr0[3:0] Cr0[7:4]

Y1[7:4] Cr0[11:8]

EAV

D[11:8]

IDCK

D[7:4]

D[3:0]

nc nc nc nc

Pixel n - 1 Pixel n

nc nc nc nc

Yn-1[3:0] Yn-1[11:8]

Cbn-1[3:0] Cbn-1[7:4]

Yn-1[7:4] Cbn-1[11:8]

Yn[3:0] Yn[11:8]

Crn-1[3:0] Crn-1[7:4]

Yn[7:4] Crn-1[11:8]

Active

video

00FF

Figure 6.21. 12-Bit YC 4:2:2 Embedded Sync Dual Edge Timing (81-Ball and 72-Pin Package)

SiI9022A/SiI9024A HDMI Transmitter

Data Sheet

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

54 SiI-DS-1076-E.01

6.11.1.7. RGB and YCbCr 4:4:4 Dual Edge Formats

The pixel clock runs at the pixel rate and a complete definition of each pixel is received on each clock cycle. One clock

edge latches in half the pixel data. The opposite clock edge latches in the remaining half of the pixel data on the same

pins. The same timing format is used for RGB and YCbCr 4:4:4. Each pair of columns in Table 6.19 lists the first pixel of n

+ 1 pixels in the line of video. The figures below the table show RGB and YCbCr data; the YCbCr 4:4:4 data is given in

braces {}. Data and control signals (Dx, DE, HSYNC, and VSYNC) must change state to meet the setup and hold times

specified for the dual edge mode, with respect to the first edge of IDCK as defined by the setting of the Edge Select bit

(see the Programmer’s Reference). The figures show IDCK latching input data when the Edge Select bit is set to 1 (first

edge is the rising edge). See Table 3.12 on page 18 or Table 3.13 on page 19 for the required timing relationships.

Table 6.19. 12-Bit RGB/YCbCr 4:4:4 Separate Sync Dual Edge Data Mapping (81-Ball and 72-Pin Package)

Name

12-bit Data Bus

RGB

YCbCr

First Edge

Second Edge

First Edge

Second Edge

B0[0]

G0[4]

Cb0[0]

Y0[4]

B0[1]

G0[5]

Cb0[1]

Y0[5]

B0[2]

G0[6]

Cb0[2]

Y0[6]

B0[3]

G0[7]

Cb0[3]

Y0[7]

B0[4]

R0[0]

Cb0[4]

Cr0[0]

B0[5]

R0[1]

Cb0[5]

Cr0[1]

B0[6]

R0[2]

Cb0[6]

Cr0[2]

B0[7]

R0[3]

Cb0[7]

Cr0[3]

G0[0]

R0[4]

Y0[0]

Cr0[4]

G0[1]

R0[5]

Y0[1]

Cr0[5]

D10

G0[2]

R0[6]

Y0[2]

Cr0[6]

D11

G0[3]

R0[7]

Y0[3]

Cr0[7]

D[23:12]

HSYNC

—

HSYNC

—

VSYNC

—

VSYNC

—

Note: Unused inputs should be left not connected.

Figure 6.22 shows IDCK latching input data when the Edge Select bit is set to 1 (first edge is the rising edge).

Pixel n - 1

blank Pixel 0 Pixel 1 Pixel 2

val

D[7:4]

D[3:0]

IDCK

HSYNC,

VSYNC

val

D[11:8] val

val

blank blank

Pixel n

B0[7:4]

{Cb0[7:4]}

G0[3:0]

{Y0[3:0]}

B0[3:0]

{Cb0[3:0]}

R0[3:0]

{Cr0[3:0]}

R0[7:4]

{Cr0[7:4]}

G0[7:4]

{Y0[7:4]}

Bn-1[7:4]

{Cbn-1[7:4]}

Gn-1[3:0]

{Yn-1[3:0]}

Bn-1[3:0]

{Cbn-1[3:0]}

Rn-1[3:0]

{Crn-1[3:0]}

Rn-1[7:4]

{Crn-1[7:4]}

Gn-1[7:4]

{Yn-1[7:4]}

Bn[7:4]

{Cbn[7:4]}

Gn[3:0]

{Yn[3:0]}

Bn[3:0]

{Cbn[3:0}

Rn[3:0]

{Crn[3:0]}

Rn[7:4]

{Crn[7:4]}

Gn[7:4]

{Yn[7:4]}

B1[7:4]

{Cb1[7:4]}

G1[3:0]

{Y1[3:0]}

B1[3:0]

{Cb1[3:0]}

R1[3:0]

{Cr1[3:0]}

R1[7:4]

{Cr1[7:4]}

G1[7:4]

{Y1[7:4]}

B2[7:4]

{Cb2[7:4]}

G2[3:0]

{Y2[3:0]}

B2[3:0]

{Cb2[3:0]}

R0[3:0]

{Cr2[3:0]}

R2[7:4]

{Cr2[7:4]}

G0[7:4]

{Y2[7:4]}

Figure 6.22. 12-Bit RGB 4:4:4 Separate Sync Dual Edge Timing (81-Ball and 72-Pin Package)

SiI9022A/SiI9024A HDMI Transmitter

Data Sheet

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1076-E.01 55

6.11.1.8. YC 4:2:2 Separate Sync Dual Edge Formats

The pixel clock runs at the pixel rate and a complete definition of each pixel is received on each clock cycle. One clock

edge latches in half the pixel data. The opposite clock edge latches in the remaining half of the pixel data on the same

pins. Each group of 4 columns in the tables of this section lists the first two pixels of n + 1 pixels in the line of video. Data

and control signals (Dx, DE, HSYNC, and VSYNC) must change state to meet the setup and hold times specified for the

dual edge mode, with respect to the first edge of IDCK as defined by the setting of the Edge Select bit (see the

Programmer’s Reference). The figures show IDCK latching input data when the Edge Select bit is set to 1 (first edge is the

rising edge). See Table 3.12 on page 18 or Table 3.13 on page 19 for the required timing relationships. Pixel values

within braces {} in the figures show the values in Swap mode.

Table 6.20. 8-Bit YC 4:2:2 Separate Sync Dual Edge Data Mapping (81-Ball and 72-Pin Package)

Pin Name

8-bit Data Bus

8-bit Data Bus Swap

Pixel #0

Pixel #1

Pixel #0

Pixel #1

First Edge

Second Edge

First Edge

Second Edge

First Edge

Second

Edge

First Edge

Second

Edge

D[3:0]

Y0[0]

Cb0[0]

Y1[0]

Cr0[0]

Cb0[0]

Y0[0]

Cr0[0]

Y1[0]

Y0[1]

Cb0[1]

Y1[1]

Cr0[1]

Cb0[1]

Y0[1]

Cr0[1]

Y1[1]

Y0[2]

Cb0[2]

Y1[2]

Cr0[2]

Cb0[2]

Y0[2]

Cr0[2]

Y1[2]

Y0[3]

Cb0[3]

Y1[3]

Cr0[3]

Cb0[3]

Y0[3]

Cr0[3]

Y1[3]

Y0[4]

Cb0[4]

Y1[4]

Cr0[4]

Cb0[4]

Y0[4]

Cr0[4]

Y1[4]

Y0[5]

Cb0[5]

Y1[5]

Cr0[5]

Cb0[5]

Y0[5]

Cr0[5]

Y1[5]

D10

Y0[6]

Cb0[6]

Y1[6]

Cr0[6]

Cb0[6]

Y0[6]

Cr0[6]

Y1[6]

D11

Y0[7]

Cb0[7]

Y1[7]

Cr0[7]

Cb0[7]

Y0[7]

Cr0[7]

Y1[7]

D[23:12]

HSYNC

—

HSYNC

—

HSYNC

—

HSYNC

—

VSYNC

—

VSYNC

—

VSYNC

—

VSYNC

—

Pixel n - 1

blank Pixel 0 Pixel 1 Pixel 2

val

D[11:4]

IDCK

HSYNC,

VSYNC

val val val val

blank blank

Pixel n

Cbn-1[7:0]

Cb0[7:0]

{Y0[7:0]}

Y0[7:0]

{Cb0[7:0]} Cr0[7:0]

{Y1[7:0]}

Y1[7:0]

{Cr0[7:0]} Cb2[7:0]

{Y2[7:0]}

Y2[7:0]

{Cb2[7:0]} Crn-1[7:0]Yn-1[7:0] Yn[7:0]

{Cbn-1[7:0]} {Yn-1[7:0]} {Yn[7:0]}

{Crn-1[7:0]}

Figure 6.23. 8-Bit YC 4:2:2 Separate Sync Dual Edge Timing (81-b all and 72-p in Package)

SiI9022A/SiI9024A HDMI Transmitter

Data Sheet

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

56 SiI-DS-1076-E.01

Table 6.21. 10-Bit YC 4:2:2 Separate Sync Dual Edge Data Mapping (81-Ball and 72-Pin Package)

Pin Name

10-bit Data Bus

10-bit Data Bus Swap

Pixel #0

Pixel #1

Pixel #0

Pixel #1

First Edge

Second Edge

First Edge

Second Edge

First Edge

Second Edge

First Edge

Second Edge

D[1:0]

Y0[0]

Cb0[0]

Y1[0]

Cr0[0]

Cb0[0]

Y0[0]

Cr0[0]

Y1[0]

Y0[1]

Cb0[1]

Y1[1]

Cr0[1]

Cb0[1]

Y0[1]

Cr0[1]

Y1[1]

Y0[2]

Cb0[2]

Y1[2]

Cr0[2]

Cb0[2]

Y0[2]

Cr0[2]

Y1[2]

Y0[3]

Cb0[3]

Y1[3]

Cr0[3]

Cb0[3]

Y0[3]

Cr0[3]

Y1[3]

Y0[4]

Cb0[4]

Y1[4]

Cr0[4]

Cb0[4]

Y0[4]

Cr0[4]

Y1[4]

Y0[5]

Cb0[5]

Y1[5]

Cr0[5]

Cb0[5]

Y0[5]

Cr0[5]

Y1[5]

Y0[6]

Cb0[6]

Y1[6]

Cr0[6]

Cb0[6]

Y0[6]

Cr0[6]

Y1[6]

Y0[7]

Cb0[7]

Y1[7]

Cr0[7]

Cb0[7]

Y0[7]

Cr0[7]

Y1[7]

D10

Y0[8]

Cb0[8]

Y1[8]

Cr0[8]

Cb0[8]

Y0[8]

Cr0[8]

Y1[8]

D11

Y0[9]

Cb0[9]

Y1[9]

Cr0[9]

Cb0[9]

Y0[9]

Cr0[9]

Y1[9]

D[23:12]

HSYNC

—

HSYNC

—

HSYNC

—

HSYNC

—

VSYNC

—

VSYNC

—

VSYNC

—

VSYNC

—

Pixel n - 1

blank Pixel 0 Pixel 1 Pixel 2

val

D[11:2]

IDCK

HSYNC,

VSYNC

val val val val

blank blank

Pixel n

Cbn-1[9:0]

Cb0[9:0]

{Y0[9:0]}

Y0[9:0]

{Cb0[9:0]} Cr0[9:0]

{Y1[9:0]}

Y1[9:0]

{Cr0[9:0]} Cb2[9:0]

{Y2[9:0]}

Y2[9:0]

{Cb2[9:0]} Crn-1[9:0]Yn-1[9:0] Yn[9:0]

{Cbn-1[9:0]} {Yn-1[9:0]} {Yn[9:0]}

{Crn-1[9:0]}

Figure 6.24. 10-Bit YC 4:2:2 Separate Sync Dual Edge Timing (81-Ball and 72-Pin Package)

SiI9022A/SiI9024A HDMI Transmitter

Data Sheet

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1076-E.01 57

Table 6.22. 12-Bit YC 4:2:2 Separate Sync Dual Edge Data Mapping (81-Ball and 72-Pin Package)

Pin Name

12-bit Data Bus

12-bit Data Bus NB

12-bit Data Bus NB Swap

Pixel #0

Pixel #1

Pixel #0

Pixel #1

Pixel #0

Pixel #1

First

Edge

Second

Edge

First

Edge

Second

Edge

First

Edge

Second

Edge

First

Edge

Second

Edge

First

Edge

Second

Edge

First

Edge

Second

Edge

Y0[0]

Y0[8]

Y1[0]

Y1[8]

Y0[0]

Cb0[0]

Y1[0]

Cr0[0]

Cb0[0]

Y0[0]

Cr0[0]

Y1[0]

Y0[1]

Y0[9]

Y1[1]

Y1[9]

Y0[1]

Cb0[1]

Y1[1]

Cr0[1]

Cb0[1]

Y0[1]

Cr0[1]

Y1[1]

Y0[2]

Y0[10]

Y1[2]

Y1[10]

Y0[2]

Cb0[2]

Y1[2]

Cr0[2]

Cb0[2]

Y0[2]

Cr0[2]

Y1[2]

Y0[3]

Y0[11]

Y1[3]

Y1[11]

Y0[3]

Cb0[3]

Y1[3]

Cr0[3]

Cb0[3]

Y0[3]

Cr0[3]

Y1[3]

Cb0[0]

Cb0[4]

Cr0[0]

Cr0[4]

Y0[4]

Cb0[4]

Y1[4]

Cr0[4]

Cb0[4]

Y0[4]

Cr0[4]

Y1[4]

Cb0[1]

Cb0[5]

Cr0[1]

Cr0[5]

Y0[5]

Cb0[5]

Y1[5]

Cr0[5]

Cb0[5]

Y0[5]

Cr0[5]

Y1[5]

Cb0[2]

Cb0[6]

Cr0[2]

Cr0[6]

Y0[6]

Cb0[6]

Y1[6]

Cr0[6]

Cb0[6]

Y0[6]

Cr0[6]

Y1[6]

Cb0[3]

Cb0[7]

Cr0[3]

Cr0[7]

Y0[7]

Cb0[7]

Y1[7]

Cr0[7]

Cb0[7]

Y0[7]

Cr0[7]

Y1[7]

Y0[4]

Cb0[8]

Y1[4]

Cr0[8]

Y0[8]

Cb0[8]

Y1[8]

Cr0[8]

Cb0[8]

Y0[8]

Cr0[8]

Y1[8]

Y0[5]

Cb0[9]

Y1[5]

Cr0[9]

Y0[9]

Cb0[9]

Y1[9]

Cr0[9]

Cb0[9]

Y0[9]

Cr0[9]

Y1[9]

D10

Y0[6]

Cb0[10]

Y1[6]

Cr0[10]

Y0[10]

Cb0[10]

Y1[10]

Cr0[10]

Cb0[10]

Y0[10]

Cr0[10]

Y1[10]

D11

Y0[7]

Cb0[11]

Y1[7]

Cr0[11]

Y0[11]

Cb0[11]

Y1[11]

Cr0[11]

Cb0[11]

Y0[11]

Cr0[11]

Y1[11]

D[23:12]

HSYNC

—

HSYNC

—

HSYNC

—

HSYNC

—

HSYNC

—

HSYNC

—

VSYNC

—

VSYNC

—

VSYNC

—

VSYNC

—

VSYNC

—

VSYNC

—

Pixel n - 1

blank Pixel 0 Pixel 1 Pixel 2

val

D[7:4]

D[3:0]

IDCK

HSYNC,

VSYNC

val

D[11:8] val

val

blank blank

Pixel n

Y0[3:0] Y0[11:8]

Cb0[3:0] Cb0[7:4]

Y0[7:4] Cb0[11:8]

Y1[3:0] Y1[11:8]

Cr0[3:0] Cr0[7:4]

Y1[7:4] Cr0[11:8]

Y2[3:0] Y2[11:8]

Cb2[3:0] Cb2[7:4]

Y2[7:4] Cb2[11:8] Yn-1[7:4] Cbn-1[11:8] Yn[7:4] Crn-1[11:8]

Yn-1[3:0] Yn-1[11:8 Yn[3:0] Yn[11:8

Cbn-1[3:0] Cbn-1[7:4] Crn-1[3:0] Crn-1[7:4]

Figure 6.25. 12-Bit YC 4:2:2 Separate Sync Dual Edge Timing (81-Ball and 72-Pin Package)

Pixel n - 1

blank Pixel 0 Pixel 1 Pixel 2

val

D[11:0]

IDCK

HSYNC,

VSYNC

val val val val

blank blank

Pixel n

Cbn-1[11:0]

Cb0[11:0]

{Y0[11:0]}

Y0[11:0]

{Cb0[11:0]} Cr0[11:0]

{Y1[11:0]}

Y1[11:0]

{Cr0[11:0]} Cb2[11:0]

{Y2[11:0]}

Y2[11:0]

{Cb2[11:0]} Crn-1[11:0]Yn-1[11:0] Yn[11:0]

{Cbn-1[11:0]} {Yn-1[11:0]} {Yn[11:0]}

{Crn-1[11:0]}

Figure 6.26. 12-Bit YC 4:2:2 Separate Sync NB Mode Dual Edge Timing (81-Ball and 72-Pin Package)

SiI9022A/SiI9024A HDMI Transmitter

Data Sheet

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

58 SiI-DS-1076-E.01

Data Mappings for 49-Ball Package

6.11.2.1. YC 4:2:2 Separate Sync Formats

The YC 4:2:2 format receives one pixel for every pixel clock period. A luma (Y) value is carried for every pixel, but the

chroma values (Cb and Cr) change only every second pixel. The data bus can only be 16-bits. HSYNC and VSYNC are

driven explicitly on their own pins. Each pair of columns in Table 6.23 lists the first and second pixel of n + 1 pixels in

the line of video. Pixel values within braces {} in the figures show the values in Swap mode. The DE HIGH time must

contain an even number of pixel clocks.

Table 6.23. 16-Bit YC 4:2:2 Separate Sync Data Mapping (49-Ball Package)

Name

16-bit Data Bus

16-bit Data Bus Swap

Pixel #0

Pixel #1

Pixel #0

Pixel #1

Y0[0]

Y1[0]

Cb0[0]

Cr0[0]

Y0[1]

Y1[1]

Cb0[1]

Cr0[1]

Y0[2]

Y1[2]

Cb0[2]

Cr0[2]

Y0[3]

Y1[3]

Cb0[3]

Cr0[3]

Y0[4]

Y1[4]

Cb0[4]

Cr0[4]

Y0[5]

Y1[5]

Cb0[5]

Cr0[5]

Y0[6]

Y1[6]

Cb0[6]

Cr0[6]

Y0[7]

Y1[7]

Cb0[7]

Cr0[7]

Cb0[0]

Cr0[0]

Y0[0]

Y1[0]

Cb0[1]

Cr0[1]

Y0[1]

Y1[1]

D10

Cb0[2]

Cr0[2]

Y0[2]

Y1[2]

D11

Cb0[3]

Cr0[3]

Y0[3]

Y1[3]

D12

Cb0[4]

Cr0[4]

Y0[4]

Y1[4]

D13

Cb0[5]

Cr0[5]

Y0[5]

Y1[5]

D14

Cb0[6]

Cr0[6]

Y0[6]

Y1[6]

D15

Cb0[7]

Cr0[7]

Y0[7]

Y1[7]

HSYNC

VSYNC

D[15:8]

blank Pixel 0 Pixel 1 Pixel 2 Pixel 3

val Cb0[7:0] Cr0[7:0] Cb2[7:0] Cr2[7:0]

D[7:0] val Y0[7:0] Y1[7:0] Y2[7:0] Y3[7:0]

IDCK

HSYNC,

VSYNC

Pixeln - 1 blank blank blankPixel n

val val val

Yn-1[7:0] val val val

Yn[7:0]

Cbn-1[7:0] Crn-1[7:0]

{Cb0[7:0]} {Cr0[7:0]} {Cb2[7:0]} {Cr2[7:0]}

{Y0[7:0]} {Y1[7:0]} {Y2[7:0]} {Y3[7:0]} {Yn-1[7:0]} {Yn[7:0]}

{Cbn-1[7:0]} {Crn-1[7:0]}

Figure 6.27. 16-bit YC 4:2:2 Separate Sync Timing (49-Ball Package)

SiI9022A/SiI9024A HDMI Transmitter

Data Sheet

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1076-E.01 59

6.11.2.2. YC 4:2:2 Embedded Sync Format

The Embedded Sync format is identical to the YC 4:2:2 Format with Separate Syncs, except that the syncs are

embedded and not explicit. The data bus can be 16-bit, 20-bit, or 24-bit. Each pair of columns in Table 6.24 lists the first

and second pixel of n + 1 pixels in the line of video.

Table 6.24. 16-Bit YC 4:2:2 Embedded Sync Data Mapping (49-Ball Package)

Name

16-bit Data Bus

Pixel #0

Pixel #1

Y0[0]

Y1[0]

Y0[1]

Y1[1]

Y0[2]

Y1[2]

Y0[3]

Y1[3]

Y0[4]

Y1[4]

Y0[5]

Y1[5]

Y0[6]

Y1[6]

Y0[7]

Y1[7]

Cb0[0]

Cr0[0]

Cb0[1]

Cr0[1]

D10

Cb0[2]

Cr0[2]

D11

Cb0[3]

Cr0[3]

D12

Cb0[4]

Cr0[4]

D13

Cb0[5]

Cr0[5]

D14

Cb0[6]

Cr0[6]

D15

Cb0[7]

Cr0[7]

HSYNC

VSYNC

SAV Pixel 0 Pixel 1 Pixel 2 Pixel 3

D[15:8]

IDCK

Active

video

EAV

D[7:0]

Pixel n - 1 Pixel n

00FF

nc nc nc nc nc nc nc nc

Cb0[7:0] Cr0[7:0] Cb2[7:0] Cr2[7:0]

Y0[7:0] Y1[7:0] Y2[7:0] Y3[7:0] Yn-1[7:0] Yn[7:0]

Cbn-1[7:0] Crn-1[7:0]

Figure 6.28. 16-Bit YC 4:2:2 Embedded Sync Timing (49-Ball Package)

SiI9022A/SiI9024A HDMI Transmitter

Data Sheet

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

60 SiI-DS-1076-E.01

6.11.2.3. YC Mux 4:2:2 Separate Sync Format

The video data is multiplexed onto fewer pins than the mapping described in the YC 4:2:2 Separate Sync Formats on

page 58. The clock rate is doubled so a chroma value is sent for each pixel, followed by a corresponding luma value for

the same pixel. Thus, a luma (Y) value is provided for each pixel, while the Cb and Cr values alternate on successive

pixels. Each group of four columns in Table 6.25 lists the four clock cycles for the first two pixels of the line. Pixel values

for Cr0 and Y0 values are sent with the first pixel (first two clock cycles). Then the Cb0 and Y1 values are sent with the

second pixel (next two clock cycles). The figure below the table shows how this pattern is extended for the rest of the

pixels in a video line of n + 1 pixels.

Table 6.25. 8-Bit YC Mux 4:2:2 Separate Sync Data Mapping (49-Ball Package)

Name

8-bit Data Bus

Clock cycle

First

Second

Third

Fourth

Cb0[0]

Y0[0]

Cr0[0]

Y1[0]

Cb0[1]

Y0[1]

Cr0[1]

Y1[1]

Cb0[2]

Y0[2]

Cr0[2]

Y1[2]

Cb0[3]

Y0[3]

Cr0[3]

Y1[3]

Cb0[4]

Y0[4]

Cr0[4]

Y1[4]

Cb0[5]

Y0[5]

Cr0[5]

Y1[5]

Cb0[6]

Y0[6]

Cr0[6]

Y1[6]

Cb0[7]

Y0[7]

Cr0[7]

Y1[7]

D[15:8]

HSYNC

VSYNC

D[7:0] Y1[7:0] Cb2[7:0] Y2[7:0] Cr2[7:0]

IDCK

Yn-1[7:0] Yn[7:0]

HSYNC

VSYNC

Cb0[7:0] Y0[7:0] Cr0[7:0] Y3[7:0] Cbn-1[7:0] Crn-1[7:0]

Pixel 0 Pixel 1 Pixel 2 Pixel 3 Pixel n - 1 Pixel n

val val

Figure 6.29. 8-Bit YC Mux 4:2:2 Separate Sync Timing (49-Ball Package)

SiI9022A/SiI9024A HDMI Transmitter

Data Sheet

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1076-E.01 61

6.11.2.4. YC Mux 4:2:2 Embedded Sync Format

This format is similar to the one described in the YC Mux 4:2:2 Separate Sync Format section on page 60, except the

syncs are embedded. Normally this mode is used only for 480i, 480p, 576i and 576p modes. It is similar to SMTPE 293

in embedding the syncs. A luma (Y) value is provided for each pixel, while the Cb and Cr values alternate on successive

pixels. The input clock rate is twice the pixel clock rate. Each group of four columns in Table 6.17 lists the four clock

cycles for the first two pixels of the line. Pixel values for Cr0 and Y0 values are sent with the first pixel (first two clock

cycles). Then the Cb0 and Y1 values are sent with the second pixel (next two clock cycles). The figure following this

table shows only the first two pixels and last pixel of the line to make room to show the SAV and EAV sequences, but

the remaining pixels are similar to those shown in the figure of the previous section. 480p, 54 MHz input can be

achieved if the input clock is 54 MHz. The DE generator may be needed to convert extracted sync timings to CEA-861D

timings. See the ITU-R BT.656 Specification.

Table 6.26. 8-Bit YC Mux 4:2:2 Embedded Sync Data Mapping (49-Ball Package)

Name

8-bit Data Bus

Clock cycle

First

Second

Third

Fourth

Cb0[0]

Y0[0]

Cr0[0]

Y1[0]

Cb0[1]

Y0[1]

Cr0[1]

Y1[1]

Cb0[2]

Y0[2]

Cr0[2]

Y1[2]

Cb0[3]

Y0[3]

Cr0[3]

Y1[3]

Cb0[4]

Y0[4]

Cr0[4]

Y1[4]

Cb0[5]

Y0[5]

Cr0[5]

Y1[5]

Cb0[6]

Y0[6]

Cr0[6]

Y1[6]

Cb0[7]

Y0[7]

Cr0[7]

Y1[7]

D[15:8]

HSYNC

VSYNC

SAV Pixel 0 Pixel 1

D[7:0] XY Cb0[7:0]

IDCK

Active

video

EAV

Pixel n

00FF Y0[7:0] Cr0[7:0] Y1[7:0] Crn-1[7:0] Yn[7:0] XY

00FF

Figure 6.30. 8-Bit YC Mux 4:2:2 Embedded Sync Timing (49-Ball Package)

SiI9022A/SiI9024A HDMI Transmitter

Data Sheet

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

62 SiI-DS-1076-E.01

6.11.2.5. YC 4:2:2 Embedded Sync Dual Edge Format

The pixel clock runs at the pixel rate and a complete definition of each pixel is received on each clock. One clock edge

latches in half the pixel data on 12 pins. The opposite clock edge latches in the remaining half of the pixel data on the

same 12 pins. Data signals (Dx) must change state to meet the setup and hold times, specified for the 12-bit dual edge

mode, with respect to the first edge of IDCK as defined by the setting of the Edge Select bit. See Table 3.12 on page 18.

The syncs are embedded and not explicit. Figure 6.31 shows IDCK latching input data when the Edge Select bit is set to

1 (first edge is the rising edge).

Table 6.27. 12-Bit YC 4:2:2 Embedded Sync Dual Edge Data Mapping (49-Ball Package)

Pin Name

12-bit Data Bus

Pixel #0

Pixel #1

First Edge

Second Edge

First Edge

Second Edge

D[3:0]

Y0[0]

Y0[8]

Y1[0]

Y1[8]

Y0[1]

Y0[9]

Y1[1]

Y1[9]

Y0[2]

Y0[10]

Y1[2]

Y1[10]

Y0[3]

Y0[11]

Y1[3]

Y1[11]

Cb0[0]

Cb0[4]

Cr0[0]

Cr0[4]

Cb0[1]

Cb0[5]

Cr0[1]

Cr0[5]

D10

Cb0[2]

Cb0[6]

Cr0[2]

Cr0[6]

D11

Cb0[3]

Cb0[7]

Cr0[3]

Cr0[7]

D12

Y0[4]

Cb0[8]

Y1[4]

Cr0[8]

D13

Y0[5]

Cb0[9]

Y1[5]

Cr0[9]

D14

Y0[6]

Cb0[10]

Y1[6]

Cr0[10]

D15

Y0[7]

Cb0[11]

Y1[7]

Cr0[11]

HSYNC

—

VSYNC

—

SAV Pixel 0 Pixel 1

D[15:12]

IDCK

Active

video

D[11:8]

D[7:4]

00FF

nc nc nc nc nc nc nc nc

nc Y0[3:0] Y0[11:8]

Cb0[3:0] Cb0[7:4]

Y0[7:4] Cb0[11:8]

Y1[3:0] Y1[11:8]

Cr0[3:0] Cr0[7:4]

Y1[7:4] Cr0[11:8]

EAV

D[15:12]

IDCK

D[11:8]

D[7:4]

nc nc nc nc

Pixel n - 1 Pixel n

nc nc nc nc

Yn-1[3:0] Yn-1[11:8]

Cbn-1[3:0] Cbn-1[7:4]

Yn-1[7:4] Cbn-1[11:8]

Yn[3:0] Yn[11:8]

Crn-1[3:0] Crn-1[7:4]

Yn[7:4] Crn-1[11:8]

Active

video

00FF

Figure 6.31. 12-Bit YC 4:2:2 Embedded Sync Timing (49-Ball Package)

SiI9022A/SiI9024A HDMI Transmitter

Data Sheet

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1076-E.01 63

6.11.2.6. RGB and YCbCr 4:4:4 Dual Edge Formats

The pixel clock runs at the pixel rate and a complete definition of each pixel is received on each clock cycle. One clock

edge latches in half the pixel data. The opposite clock edge latches in the remaining half of the pixel data on the same

pins. The same timing format is used for RGB and YCbCr 4:4:4. Each pair of columns in Table 6.28 lists the first pixel of n

+ 1 pixels in the line of video. The figures below the table show RGB and YCbCr data; the YCbCr 4:4:4 data is given in

braces {}. Data and control signals (Dx, DE, HSYNC, and VSYNC) must change state to meet the setup and hold times

specified for the dual edge mode, with respect to the first edge of IDCK as defined by the setting of the Edge Select bit

(see the Programmer’s Reference). The figures show IDCK latching input data when the Edge Select bit is set to 1 (first

edge is the rising edge). See Table 3.12 on page 18 for the required timing relationships.

Table 6.28. 12-Bit RGB/YCbCr 4:4:4 Separate Sync Dual Edge Data Mapping (49-Ball Package)

Name

12-bit Data Bus

RGB

YCbCr

First Edge

Second Edge

First Edge

Second Edge

D[3-0]

B0[0]

G0[4]

Cb0[0]

Y0[4]

B0[1]

G0[5]

Cb0[1]

Y0[5]

B0[2]

G0[6]

Cb0[2]

Y0[6]

B0[3]

G0[7]

Cb0[3]

Y0[7]

B0[4]

R0[0]

Cb0[4]

Cr0[0]

B0[5]

R0[1]

Cb0[5]

Cr0[1]

D10

B0[6]

R0[2]

Cb0[6]

Cr0[2]

D11

B0[7]

R0[3]

Cb0[7]

Cr0[3]

D12

G0[0]

R0[4]

Y0[0]

Cr0[4]

D13

G0[1]

R0[5]

Y0[1]

Cr0[5]

D14

G0[2]

R0[6]

Y0[2]

Cr0[6]

D15

G0[3]

R0[7]

Y0[3]

Cr0[7]

HSYNC

—

HSYNC

—

VSYNC

—

VSYNC

—

Pixel n - 1

blank Pixel 0 Pixel 1 Pixel 2

val

D[11:8]

D[7:4]

IDCK

HSYNC,

VSYNC

val

D[15:12] val

val

blank blank

Pixel n

B0[7:4]

{Cb0[7:4]}

G0[3:0]

{Y0[3:0]}

B0[3:0]

{Cb0[3:0]}

R0[3:0]

{Cr0[3:0]}

R0[7:4]

{Cr0[7:4]}

G0[7:4]

{Y0[7:4]}

Bn-1[7:4]

{Cbn-1[7:4]}

Gn-1[3:0]

{Yn-1[3:0]}

Bn-1[3:0]

{Cbn-1[3:0]}

Rn-1[3:0]

{Crn-1[3:0]}

Rn-1[7:4]

{Crn-1[7:4]}

Gn-1[7:4]

{Yn-1[7:4]}

Bn[7:4]

{Cbn[7:4]}

Gn[3:0]

{Yn[3:0]}

Bn[3:0]

{Cbn[3:0}

Rn[3:0]

{Crn[3:0]}

Rn[7:4]

{Crn[7:4]}

Gn[7:4]

{Yn[7:4]}

B1[7:4]

{Cb1[7:4]}

G1[3:0]

{Y1[3:0]}

B1[3:0]

{Cb1[3:0]}

R1[3:0]

{Cr1[3:0]}

R1[7:4]

{Cr1[7:4]}

G1[7:4]

{Y1[7:4]}

B2[7:4]

{Cb2[7:4]}

G2[3:0]

{Y2[3:0]}

B2[3:0]

{Cb2[3:0]}

R0[3:0]

{Cr2[3:0]}

R2[7:4]

{Cr2[7:4]}

G0[7:4]

{Y2[7:4]}

Figure 6.32. 12-Bit RGB/YCbCr 4:4:4 Separate Sync Timing (49-Ball Package)

SiI9022A/SiI9024A HDMI Transmitter

Data Sheet

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

64 SiI-DS-1076-E.01

6.11.2.7. YC 4:2:2 Separate Sync Dual Edge Formats

The pixel clock runs at the pixel rate and a complete definition of each pixel is received on each clock cycle. One clock

edge latches in half the pixel data. The opposite clock edge latches in the remaining half of the pixel data on the same

pins. Each group of 4 columns in the tables of this section lists the first two pixels of n + 1 pixels in the line of video. Data

and control signals (Dx, DE, HSYNC, and VSYNC) must change state to meet the setup and hold times specified for the

dual edge mode, with respect to the first edge of IDCK as defined by the setting of the Edge Select bit (see the

Programmer’s Reference). The figures show IDCK latching input data when the Edge Select bit is set to 1 (first edge is the

rising edge). See Table 3.12 on page 18 for the required timing relationships. Pixel values within braces {} in the figures

show the values in Swap mode.

Table 6.29. 8-Bit YC 4:2:2 Separate Sync Dual Edge Data Mapping (49-Ball Package)

Pin Name

8-bit Data Bus

8-bit Data Bus Swap

Pixel #0

Pixel #1

Pixel #0

Pixel #1

First Edge

Second Edge

First Edge

Second Edge

First Edge

Second Edge

First Edge

Second Edge

D[7:0]

Y0[0]

Cb0[0]

Y1[0]

Cr0[0]

Cb0[0]

Y0[0]

Cr0[0]

Y1[0]

Y0[1]

Cb0[1]

Y1[1]

Cr0[1]

Cb0[1]

Y0[1]

Cr0[1]

Y1[1]

D10

Y0[2]

Cb0[2]

Y1[2]

Cr0[2]

Cb0[2]

Y0[2]

Cr0[2]

Y1[2]

D11

Y0[3]

Cb0[3]

Y1[3]

Cr0[3]

Cb0[3]

Y0[3]

Cr0[3]

Y1[3]

D12

Y0[4]

Cb0[4]

Y1[4]

Cr0[4]

Cb0[4]

Y0[4]

Cr0[4]

Y1[4]

D13

Y0[5]

Cb0[5]

Y1[5]

Cr0[5]

Cb0[5]

Y0[5]

Cr0[5]

Y1[5]

D14

Y0[6]

Cb0[6]

Y1[6]

Cr0[6]

Cb0[6]

Y0[6]

Cr0[6]

Y1[6]

D15

Y0[7]

Cb0[7]

Y1[7]

Cr0[7]

Cb0[7]

Y0[7]

Cr0[7]

Y1[7]

HSYNC

—

HSYNC

—

HSYNC

—

HSYNC

—

VSYNC

—

VSYNC

—

VSYNC

—

VSYNC

—

Pixel n - 1

blank Pixel 0 Pixel 1 Pixel 2

val

D[15:8]

IDCK

HSYNC,

VSYNC

val val val val

blank blank

Pixel n

Cbn-1[7:0]

Cb0[7:0]

{Y0[7:0]}

Y0[7:0]

{Cb0[7:0]} Cr0[7:0]

{Y1[7:0]}

Y1[7:0]

{Cr0[7:0]} Cb2[7:0]

{Y2[7:0]}

Y2[7:0]

{Cb2[7:0]} Crn-1[7:0]Yn-1[7:0] Yn[7:0]

{Cbn-1[7:0]} {Yn-1[7:0]} {Yn[7:0]}

{Crn-1[7:0]}

Figure 6.33. 8-Bit YC 4:2:2 Separate Sync Dual Edge Timing (49-Ball Package)

SiI9022A/SiI9024A HDMI Transmitter

Data Sheet

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1076-E.01 65

Table 6.30. 10-Bit YC 4:2:2 Separate Sync Dual Edge Data Mapping (49-Ball Package)

Pin Name

10-bit Data Bus

10-bit Data Bus Swap

Pixel #0

Pixel #1

Pixel #0

Pixel #1

First Edge

Second Edge

First Edge

Second Edge

First Edge

Second Edge

First Edge

Second Edge

D[5:0]

Y0[0]

Cb0[0]

Y1[0]

Cr0[0]

Cb0[0]

Y0[0]

Cr0[0]

Y1[0]

Y0[1]

Cb0[1]

Y1[1]

Cr0[1]

Cb0[1]

Y0[1]

Cr0[1]

Y1[1]

Y0[2]

Cb0[2]

Y1[2]

Cr0[2]

Cb0[2]

Y0[2]

Cr0[2]

Y1[2]

Y0[3]

Cb0[3]

Y1[3]

Cr0[3]

Cb0[3]

Y0[3]

Cr0[3]

Y1[3]

D10

Y0[4]

Cb0[4]

Y1[4]

Cr0[4]

Cb0[4]

Y0[4]

Cr0[4]

Y1[4]

D11

Y0[5]

Cb0[5]

Y1[5]

Cr0[5]

Cb0[5]

Y0[5]

Cr0[5]

Y1[5]

D12

Y0[6]

Cb0[6]

Y1[6]

Cr0[6]

Cb0[6]

Y0[6]

Cr0[6]

Y1[6]

D13

Y0[7]

Cb0[7]

Y1[7]

Cr0[7]

Cb0[7]

Y0[7]

Cr0[7]

Y1[7]

D14

Y0[8]

Cb0[8]

Y1[8]

Cr0[8]

Cb0[8]

Y0[8]

Cr0[8]

Y1[8]

D15

Y0[9]

Cb0[9]

Y1[9]

Cr0[9]

Cb0[9]

Y0[9]

Cr0[9]

Y1[9]

HSYNC

—

HSYNC

—

HSYNC

—

HSYNC

—

VSYNC

—

VSYNC

—

VSYNC

—

VSYNC

—

Pixel n - 1

blank Pixel 0 Pixel 1 Pixel 2

val

D[15:6]

IDCK

HSYNC,

VSYNC

val val val val

blank blank

Pixel n

Cbn-1[9:0]

Cb0[9:0]

{Y0[9:0]}

Y0[9:0]

{Cb0[9:0]} Cr0[9:0]

{Y1[9:0]}

Y1[9:0]

{Cr0[9:0]} Cb2[9:0]

{Y2[9:0]}

Y2[9:0]

{Cb2[9:0]} Crn-1[9:0]Yn-1[9:0] Yn[9:0]

{Cbn-1[9:0]} {Yn-1[9:0]} {Yn[9:0]}

{Crn-1[9:0]}

Figure 6.34. 10-Bit YC 4:2:2 Separate Sync Dual Edge Timing (49-Ball Package)

SiI9022A/SiI9024A HDMI Transmitter

Data Sheet

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

66 SiI-DS-1076-E.01

Table 6.31. 12-Bit YC 4:2:2 Separate Sync Dual Edge Data Mapping (49-Ball Package)

Pin Name

12-bit Data Bus

NB Swap

Pixel #0

Pixel #1

Pixel #0

Pixel #1

Pixel #0

Pixel #1

First

Edge

Second

Edge

First

Edge

Second

Edge

First

Edge

Second

Edge

First

Edge

Second

Edge

First

Edge

Second

Edge

First

Edge

Second

Edge

D[3:0]

Y0[0]

Y0[8]

Y1[0]

Y1[8]

Y0[0]

Cb0[0]

Y1[0]

Cr0[0]

Cb0[0]

Y0[0]

Cr0[0]

Y1[0]

Y0[1]

Y0[9]

Y1[1]

Y1[9]

Y0[1]

Cb0[1]

Y1[1]

Cr0[1]

Cb0[1]

Y0[1]

Cr0[1]

Y1[1]

Y0[2]

Y0[10]

Y1[2]

Y1[10]

Y0[2]

Cb0[2]

Y1[2]

Cr0[2]

Cb0[2]

Y0[2]

Cr0[2]

Y1[2]

Y0[3]

Y0[11]

Y1[3]

Y1[11]

Y0[3]

Cb0[3]

Y1[3]

Cr0[3]

Cb0[3]

Y0[3]

Cr0[3]

Y1[3]

Cb0[0]

Cb0[4]

Cr0[0]

Cr0[4]

Y0[4]

Cb0[4]

Y1[4]

Cr0[4]

Cb0[4]

Y0[4]

Cr0[4]

Y1[4]

Cb0[1]

Cb0[5]

Cr0[1]

Cr0[5]

Y0[5]

Cb0[5]

Y1[5]

Cr0[5]

Cb0[5]

Y0[5]

Cr0[5]

Y1[5]

D10

Cb0[2]

Cb0[6]

Cr0[2]

Cr0[6]

Y0[6]

Cb0[6]

Y1[6]

Cr0[6]

Cb0[6]

Y0[6]

Cr0[6]

Y1[6]

D11

Cb0[3]

Cb0[7]

Cr0[3]

Cr0[7]

Y0[7]

Cb0[7]

Y1[7]

Cr0[7]

Cb0[7]

Y0[7]

Cr0[7]

Y1[7]

D12

Y0[4]

Cb0[8]

Y1[4]

Cr0[8]

Y0[8]

Cb0[8]

Y1[8]

Cr0[8]

Cb0[8]

Y0[8]

Cr0[8]

Y1[8]

D13

Y0[5]

Cb0[9]

Y1[5]

Cr0[9]

Y0[9]

Cb0[9]

Y1[9]

Cr0[9]

Cb0[9]

Y0[9]

Cr0[9]

Y1[9]

D14

Y0[6]

Cb0[10]

Y1[6]

Cr0[10]

Y0[10]

Cb0[10]

Y1[10]

Cr0[10]

Cb0[10]

Y0[10]

Cr0[10]

Y1[10]

D15

Y0[7]

Cb0[11]

Y1[7]

Cr0[11]

Y0[11]

Cb0[11]

Y1[11]

Cr0[11]

Cb0[11]

Y0[11]

Cr0[11]

Y1[11]

HSYNC

—

HSYNC

—

HSYNC

—

HSYNC

—

HSYNC

—

HSYNC

—

VSYNC

—

VSYNC

—

VSYNC

—

VSYNC

—

VSYNC

—

VSYNC

—

Pixel n - 1

blank Pixel 0 Pixel 1 Pixel 2

val

D[11:8]

D[7:4]

IDCK

HSYNC,

VSYNC

val

D[15:12] val

val

blank blank

Pixel n

Y0[3:0] Y0[11:8]

Cb0[3:0] Cb0[7:4]

Y0[7:4] Cb0[11:8]

Y1[3:0] Y1[11:8]

Cr0[3:0] Cr0[7:4]

Y1[7:4] Cr0[11:8]

Y2[3:0] Y2[11:8]

Cb2[3:0] Cb2[7:4]

Y2[7:4] Cb2[11:8] Yn-1[7:4] Cbn-1[11:8] Yn[7:4] Crn-1[11:8]

Yn-1[3:0] Yn-1[11:8 Yn[3:0] Yn[11:8

Cbn-1[3:0] Cbn-1[7:4] Crn-1[3:0] Crn-1[7:4]

Figure 6.35. 12-Bit YC 4:2:2 Separate Sync Dual Edge Timing (49-Ball Package)

Pixel n - 1

blank Pixel 0 Pixel 1 Pixel 2

val

D[15:4]

IDCK

HSYNC,

VSYNC

val val val val

blank blank

Pixel n

Cbn-1[11:0]

Cb0[11:0]

{Y0[11:0]}

Y0[11:0]

{Cb0[11:0]} Cr0[11:0]

{Y1[11:0]}

Y1[11:0]

{Cr0[11:0]} Cb2[11:0]

{Y2[11:0]}

Y2[11:0]

{Cb2[11:0]} Crn-1[11:0]Yn-1[11:0] Yn[11:0]

{Cbn-1[11:0]} {Yn-1[11:0]} {Yn[11:0]}

{Crn-1[11:0]}

Figure 6.36. 12-Bit YC 4:2:2 Separate Sync NB Mode Dual Edge Timing (49-Ball Package)

SiI9022A/SiI9024A HDMI Transmitter

Data Sheet

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1076-E.01 67

7. Design Recommendations

Power Supplies Decoupling

Designers should include adequate decoupling capacitors and a ferrite for each power supply, and an additional

capacitor at each power ball or pin in the layout. These are shown schematically in Figure 7.1. Place these components

as close as possible to the transmitter device balls or pins, and avoid routing through vias if possible, as shown in

Figure 7.2, which represents a typical power connection on the transmitter. Connections in one group (such as AVCC12)

can share C2, the ferrite, and C3, with each ball or pin having a separate C1 placed as close to the package as possible.

Figure 7.2 shows one of the VFBGA packages; the same information applies to the 72-pin package.

Because of the low noise requirements of AVCC12, particular care must be taken to ensure the noise at the pin is less

than 50 mV.

C2C1

VCC Ball

GND

+1.2 V

Figure 7.1. Decoupling and Bypass Schematic

VCC

GND

VCC

Ferrite

Via to GND

Figure 7.2. Decoupling and Bypass Capacitor Placement

High-Speed TMDS Signals

Source Termination

Source termination suppresses signal reflection and overshoot, and at the same time allows the transmitter to provide

strong drive to support longer cables. The SiI9022A/SiI9024A transmitter supports internal source termination, which is

disabled by default and can be enabled by programming. Lattice Semiconductor strongly recommends the use of

internal source termination for applications running over 100 MHz.

SiI9022A/SiI9024A HDMI Transmitter

Data Sheet

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

68 SiI-DS-1076-E.01

ESD Protection

The transmitter chip is designed to withstand electrostatic discharge during manufacturing handling. In applications

where higher protection levels are required in the finished product, ESD-limiting components should be placed on all of

the device pins connecting to an external interface. Special care should be taken on the TMDS signals to use low-

capacitance ESD devices to minimize signal degradation. In no case should the capacitance value exceed 3 pF.

Transmitter Layout Guidelines

Place the transmitter chip as closely as possible to the output connector that carries the TMDS signals, and place the

ESD diodes as close as possible to the HDMI connector. Route the differential signal lines together and as directly as

possible from transmitter to connector. Lattice Semiconductor TMDS devices are tolerant of skews between

differential pairs, so spiral skew compensation for path length differences is not required. Avoid passing the TMDS lines

through vias unless absolutely necessary when using the HDMI Type-D micro connector. The distance separating the

two traces of the differential pair should be designed for 100- differential impedance. An example of routing for the

49-ball package is shown in Figure 7.3. For additional ball grid array layout guidelines, refer to Designing with BGA

Packages (listed in References section).

HDMI

Connector

ESD

Diodes

TX2+

TX2-

TX1+

TX1-

TX0+

TX0-

TXC+

TXC-

SiI9022A/

9024A

Figure 7.3. Transmitter to HDMI Connector Routing – Top View

Hot Plug Signal Conditioning

The HDMI interface provides a hot plug signal back to the host side from the display. This signal is generated by routing

a 5 V source, in the host, through the cable to the display and back. The specification defines the minimum HIGH level

for the hot plug as 2.0 V at the connector pin. The HPD signal is 5 V tolerant and can be connected to the HPD signal

directly. However, an external pull down resistor of 10 k is required, as shown in the circuit in Figure 7.5 on page 70,

to guarantee that this CMOS input is not floating.

EMI Considerations

Electromagnetic interference is a function of board layout, shielding, receiver component operating voltage, frequency

of operation, and additional factors. To control emissions, it is important not to place any passive components on the

differential signal lines, except for the essential ESD protection described earlier. The differential signaling used in

HDMI is inherently low in EMI, as long as the routing recommendations noted in the Transmitter Layout Guidelines

section are followed.

The PCB ground plane should extend unbroken under as much of the transmitter chip and associated circuitry as

possible, with all ground signals of the chip using a common ground.

SiI9022A/SiI9024A HDMI Transmitter

Data Sheet

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1076-E.01 69

Typical Circuits

Representative circuits for using the transmitter chip are shown in Figure 7.4 through Figure 7.7. For a detailed review

of your intended circuit implementation, contact your Lattice Semiconductor representative.

Power Supply Decoupling

Excessive noise on AVCC12 can cause improper PLL operation as the PLL tries to stay locked to the incoming video

clock. Keep AVCC12 noise below the maximum allowable value VCCN as specified in Table 3.2. If the ripple is higher than

allowed for in the specifications, Lattice Semiconductor recommends using a separate power source to supply the

AVCC12 inputs. The other power planes are relatively insensitive to ripple. Lattice Semiconductor recommends using

low ESR capacitors. The 72-pin QFN package has an e-Pad which must be connected to the ground plane of the board.

AVCC12

AGND

Place a 0.1 F ceramic capacitor

close to each VCC pin

IOVCC

IOGND

CVCC12

CGND

Ferrite

+1.2 V

+1.8 V or

+3.3 V

+1.2 V

10 F0.1 F

(81-ball: C6, C7)

(49-ball: B4)

(72-pin: 60, 66)

0.1 F

0.1 F0.1 F0.1 F

10 F

0.1 F0.1 F0.1 F0.1 F0.1 F

10 F

F

Provide a minimum of one 0.1 F

decoupling capacitor for each

VCC connection in the 81-ball

and 72-pin package.

(81-ball: CA3, A8)

(49-ball: B3)

(72-pin: 63)

(81-ball: D5, E5, E8, E9)

(49-ball: E3)

(72-pin: 3, 21, 46)

(81-ball: C5, D4, D6)

(49-ball: D3)

(72-pin: 57)

(81-ball: C4, D3, D7, E7, F5, G6)

(49-ball: C4)

(72-pin: 5, 12, 26, 42, 47, 53)

(81-ball: D1, D2, G5, H5, J5)

(49-ball: D4)

(72-pin: 43)

Ferrite

Figure 7.4. Power Supply Decoupling

Note: The 72-pin QFN package has an e-Pad which must be connected to the ground plane of the board.

SiI9022A/SiI9024A HDMI Transmitter

Data Sheet

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

70 SiI-DS-1076-E.01

HDMI Port Connections

The suggested value for REXT_SWING is specified in the Differential Data Signals section on page 32. The Hot Plug Detect

signal (HPD) is 5 V tolerant, so it is connected directly to the HDMI connector with a 10 kΩ pull-down resistor. No level-

shifting circuit is needed for HPD.

SiI9022A

SiI9024A

HDMI

Connector

+5 V

ESD Clamps

EXT_SWING

DSCL

HPD

DSDA

CEC_A

TX2-

TX2+

TX1-

TX1+

TX0-

TX0+

TXC+

TXC-

TX1-

TX1+

TX0-

TX0+

TXC+

TXC-

DDC SCL

HTPG

DDC SDA

CEC

TX2-

TX2+

2.2 k

(typ)

Voltage swing

adjust resistor

4.3 k or

5.1 k

10 k

RClamp0514M or equivalent

3.3 V

51 k

Pullup resistor and diode

required only if IOVCC =

1.8 V.

2.2 k

(typ)

Figure 7.5. HDMI Port Connection Schematic

SiI9022A/SiI9024A HDMI Transmitter

Data Sheet

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1076-E.01 71

Control Signal Connections

The general bus interconnection between the host processor and the transmitter is shown in Figure 7.6. The INT output

can be connected as an interrupt to the processor, or the processor can poll a register to determine if any of the

enabled interrupts have occurred.

INT

RESET#

CSDA

CSCL

C_SCL

CI2CA

Stuff only one of two 4.7 kresistors

to set chip I2C address (Required for

81-ball VFBGA and 72-pin QFN)

RSVDL

CEC_D

MPEG Chip

Host processor

IOVCC IOVCC

IOVCC =

1.8 V or 3.3 V

4.7 k4.7 k

4.7 k

C_SDA

GPIO

C_CEC

GPIO

SiI9022A/9024A

Transmitter

(For 81-ball and 72-pin packages only)

1.8 V

IO_SEL

Connect IO_SEL to 1.8 V for

1.8-volt IOVCC. Connect to

ground for 3.3-volt IOVCC.

(Required for 81-ball VFBGA

and 72-pin QFN)

(For 81-ball and 72-pin packages only)

Figure 7.6. Controller Connections Schematic

SiI9022A/SiI9024A HDMI Transmitter

Data Sheet

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

72 SiI-DS-1076-E.01

77BDigital Video Input Connections

HSYNC

VSYNC

IDCK

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D20

D21

D22

D23

MCLK

SPDIF

SCK

SD0

SD1

SD2

SD3

(For 49-ball package

only)

(For 81-ball and 72-pin

packages only)

(For 81-ball and 72-pin

packages only)

Note: Some system designs

may require series resistors

to reduce reflections on the

parallel input bus.

Figure 7.7. Digital Input Schematic

SiI9022A/SiI9024A HDMI Transmitter

Data Sheet

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1076-E.01 73

8. Packaging

49-Ball Package Dimensions

These drawings are not to scale.

Top View Bottom View

Detail B Detail A

0.10

0.15

0.05

0.08C

0.10C

JEDEC Package Code MO-225

Item

Description

Min

Typ

Max

Thickness

—

0.80

Stand-off

0.13

0.18

0.23

Substrate thickness +

Mold thickness

0.446

0.508

0.560

Body size

3.90

4.00

4.10

Body size

3.90

4.00

4.10

Footprint

—

3.00

—

Footprint

—

3.00

—

Ball width

0.20

0.25

0.30

Ball pitch

—

0.50

—

All dimensions are in millimeters.

Figure 8.1. 49-Ball VFBGA Package Diagram (SiI902nAYBT)

SiI9022A/SiI9024A HDMI Transmitter

Data Sheet

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

74 SiI-DS-1076-E.01

36B81-Ball Package Dimensions

These drawings are not to scale.

8 9

Top View Bottom View

Detail B Detail A

0.15

0.05

0.10

0.08C

0.10C

JEDEC Package Code MO-225

Item

Description

Min

Typ

Max

Thickness

—

0.80

Stand-off

0.13

0.18

0.23

Substrate thickness +

Mold thickness

0.446

0.508

0.560

Body size

3.90

4.00

4.10

Body size

3.90

4.00

4.10

Footprint

—

3.20

—

Footprint

—

3.20

—

Ball width

0.20

0.25

0.30

Ball pitch

—

0.40

—

All dimensions are in millimeters.

Figure 8.2. 81-Ball VFBGA Package Diagram (SiI902nARBT)

SiI9022A/SiI9024A HDMI Transmitter

Data Sheet

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1076-E.01 75

72-Pin Package Dimensions

These drawings are not to scale.

0.6 max

0.10 C

0.05 C

0.6 max

Seating Plane



0.08C

EE1

0.15C

BD2

Top View

Side View

Bottom View

Detail A

0.10C

0.10 C

MA B

0.10 C

MA B

JEDEC Package Code MO-220

Item

Description

Min

Typ

Max

Item

Description

Min

Typ

Max

Thickness

0.80

0.85

0.90

ePad size

4.55

4.70

4.85

Stand-off

0.00

0.02

0.05

ePad size

4.55

4.70

4.85

Body thickness

0.60

0.65

0.70

Plated lead width

0.18

0.23

0.28

0.20 REF

Lead pitch

0.50 BSC

Footprint

10.00 BSC

ePad-to-pin clearance

0.20

—

Footprint

10.00 BSC

Lead foot length

0.30

0.40

0.50

Body size

9.75 BSC

Lead radius

0.09

—

Body size

9.75 BSC



Lead foot angle

0°

—

14°

All dimensions are in millimeters.

Figure 8.3. 72-Pin QFN Package Diagram (SiI902nACNU)

SiI9022A/SiI9024A HDMI Transmitter

Data Sheet

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

76 SiI-DS-1076-E.01

Marking Specification

Marking drawings are not to scale.

902nARBT

LLLLL.LL-L

XXXXXYWW

Logo

Silicon Image Part Number

Lot # (= Job#)

Trace code and Date code

Ball A1 location

Figure 8.4. Marking Diagram (SiI902nARBT)

902nAYBT

LLLLL.LL-L

XXXXXYWW

Logo

Silicon Image Part Number

Lot # (= Job#)

Trace code and Date code

Ball A1 location

Figure 8.5. Marking Diagram (SiI902nAYBT)

SiI9022A/SiI9024A HDMI Transmitter

Data Sheet

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1076-E.01 77

LLLLLL.LL-L

YYWW

XXXXXXX

Logo

Silicon Image Part Number

Lot # (= Job#)

Date code

Trace code

Pin 1 location

Product

Designation

SiInnnnrppp

Package Type

Revision

SiI902nACNU

Figure 8.6. Marking Diagram (SiI902nACNU)

Ordering Information

Part Numbers

Package Type

Pixel Clock Range

Security

Temperature Grade

SiI9022ARBT

81-ball 4 × 4 mm VFBGA

25 MHz –165 MHz

—

Extended (–20 °C to +85 °C)

SiI9022AYBT

49-ball 4 × 4 mm VFBGA

25 MHz –165 MHz

—

Extended (–20 °C to +85 °C)

SiI9022ACNU

72-pin 10 × 10 mm QFN

25 MHz –165 MHz

—

Extended (–20 °C to +85 °C)

SiI9024ARBT

81-ball 4 × 4 mm VFBGA

25 MHz –165 MHz

HDCP

Extended (–20 °C to +85 °C)

SiI9024AYBT

49-ball 4 × 4 mm VFBGA

25 MHz –165 MHz

HDCP

Extended (–20 °C to +85 °C)

SiI9024ACNU

72-pin 10 × 10 mm QFN

25 MHz –165 MHz

HDCP

Extended (–20 °C to +85 °C)

The universal package can be used in both lead-free and ordinary process lines.

SiI9022A/SiI9024A HDMI Transmitter

Data Sheet

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

78 SiI-DS-1076-E.01

References

Standards Documents

This is a list of the standards abbreviations appearing in this document.

Abbreviation

Standards publication, organization, and date

HDMI

High Definition Multimedia Interface, Revision 1.4a, HDMI Consortium; March 2010

HCTS

HDMI Compliance Test Specification, Revision 1.4a, HDMI Consortium; March 2010

HDCP

High-bandwidth Digital Content Protection, Revision 1.3, Digital Content Protection, LLC; December 2006

E-EDID

Enhanced Extended Display Identification Data Standard, Release A Revision 1, VESA; Feb. 2000

E-EDID IG

VESA EDID Implementation Guide, Version 1.0, VESA; June 2001

CEA-861-E

A DTV Profile for Uncompressed High Speed Digital Interfaces, EIA/CEA; March 2008

EDDC

Enhanced Display Data Channel Standard, Version 1.1, VESA; March 2004

Standards Groups

For information on the specifications that apply to this document, contact the responsible standards groups appearing

on this list.

Standards Group

Web URL

ANSI/EIA/CEA

http://global.ihs.com

VESA

http://www.vesa.org

DVI

http://www.ddwg.org

HDCP

http://www.digital-cp.com

HDMI

http://www.hdmi.org

Lattice Semiconductor Documents

This is a list of the related documents that are available from your Lattice Semiconductor sales representative.

The Programmer’s Reference requires an NDA with Lattice Semiconductor.

Document

Title

SiI-PR-1032

Transmitter Programming Interface (TPI) Programmer’s Reference

SiI-PR-0020

SiI9020 HDMI PanelLink Transmitter Programmer’s Reference

SiI-PR-0041

CEC Programming Interface (CPI) Programmer’s Reference

SiI-AN-1016

Designing with BGA Packages

SiI-AN-1029

Layout Guidelines and Results for Using HDMI Type-D Micro-Connector with SiI902nA Devices

SiI-UG-1043

CP9022AR/CP9024AR/CP9022AY/CP9024AY HDMI Transmitter Starter Kit User Guide

Technical Support

For assistance, submit a technical support case at www.latticesemi.com/techsupport.

SiI9022A/SiI9024A HDMI Transmitter

Data Sheet

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1076-E.01 79

Revision History

Revision E.01, August 2016

Formatted to latest template. No content has been changed.

Revision E, October 2015

Updated description of CSCL item in the Configuration and Control Signals section. Updated copyright information and

legal disclaimers.

Revision D.01, January 2011

Updated Table 3.3. DC Digital I/O Specifications: IOVCC = 1.8 V, Table 3.4. DC Digital I/O Specifications: IOVCC = 3.3 V,

Table 3.10. I2S Input Port Timings; corrected 1080p 24 Hz 3D lines.

Revision C.01, September 2010

Removed Patent information from DB, rolled the revision for DS.

Revision C, July 2010

Added information about L + D, and Top-and-Bottom modes; added Limitations section.

Revision B.01, April 2010

Update with new features; minor corrections and changes.

Revision B, December 2009

Updated to add 81-ball and 72-pin information; added Pixel Number to Data Mapping tables.

Revision A.01, November 2009

Update specification tables; minor corrections throughout.

Revision A, November 2009

First production release.

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Portland, OR 97204, USA

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