1
File Number 2863.5
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 |Copyright © Intersil Corporation 2000
ICL8013
1MHz, Four Quadrant Analog Multiplier
The ICL8013 is a four quadrant analog multiplier whose
output is proportional to the algebraic product of two input
signals. Feedback around an internal op amp provides level
shifting and can be used to generate division and square
root functions. A simple arrangement of potentiometers may
be used to trim gain accuracy, offset voltage and
feedthrough performance. The high accuracy, wide
bandwidth, and increased versatility of the ICL8013 make it
ideal for all multiplier applications in control and
instrumentation systems. Applications include RMS
measuring equipment, frequency doublers, balanced
modulators and demodulators, function generators, and
voltage controlled amplifiers.
Features
• Accuracy. . . . . . . . . . . . . . . . . . . . . . . . ±1% (“B” Version)
• Input Voltage Range. . . . . . . . . . . . . . . . . . . . . . . . . ±10V
• Bandwidth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1MHz
• Uses Standard ±15V Supplies
• Built-In Op Amp Provides Level Shifting, Division and
Square Root Functions
Pinout ICL8013
(METAL CAN)
TOP VIEW
Functional Diagram
Part Number Information
PART
NUMBER
MULTIPLI-
CATION
ERROR
(MAX) TEMP.
RANGE (oC) PKG PKG.
NO.
ICL8013BCTX ±1% 0 to 70 10 Pin
Metal Can T10.B
ICL8013CCTX ±2% 0 to 70 10 Pin
Metal Can T10.B
YOS
GND
V-
OUTPUT
V+ 2
5
1
3
10
4
8
9
7
6
ZOS
XOS
XIN
ZIN
YIN
VOLTAGE TO CURRENT
CONVERTER AND
SIGNAL COMPRESSION
BALANCED
VARIABLE GAIN
AMPLIFIER
OP
AMP OUT
VOLTAGE TO CURRENT
CONVERTER
ZOS
ZIN
YOS
YIN
XIN
XOS
ZIN
Data Sheet November 2000
[ /Title
(ICL80
13)
/Sub-
ject (
1MHz,
Four
Quad-
rant
Ana-
log
Multi-
plier
)
/Autho
r ()
/Key-
words
(Inter-
sil
Corpo-
ration,
semi-
con-
ductor,
analog
multi-
plier,
four
quad-
rant,
high
accu-
racy,
low
power,
modu-
lator,
FOR A POSSIBLE SUBSTITUTE PRODUCT
call Central Applications 1-888-INTERSIL
or email: centapp@intersil.com
OBSOLETE PRODUCT
2
Absolute Maximum Ratings Thermal Information
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18
Input Voltages (XIN, YIN, ZIN, XOS, YOS, ZOS) . . . . . . . . . VSUPPLY
Operating Conditions
Temperature Range
ICL8013XC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC
Thermal Resistance (Typical, Note 1) θJA (oC/W) θJC (oC/W)
Metal Can Package . . . . . . . . . . . . . . . 160 75
Maximum Junction Temperature (Metal Can Package) . . . . . . .175oC
Maximum Storage Temperature Range. . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications TA= 25oC, VSUPPLY = ±15V, Gain and Offset Potentiometers Externally Trimmed, Unless Otherwise
Specified
PARAMETER TEST
CONDITIONS
ICL8013B ICL8013C
UNITSMIN TYP MAX MIN TYP MAX
Multiplier Function - XY
10 --XY
10 -
Multiplication Error -10 < X < 10
-10 < Y < 10 - - 1.0 - - 2.0 % Full Scale
Divider Function - 10Z
X- - 10Z
X-
Division Error X = -10 - 0.3 - - 0.3 - % Full Scale
X = -1 - 1.5 - - 1.5 - % Full Scale
Feedthrough X = 0, Y = ±10V - - 100 - - 200 mV
Y = 0, X = ±10V - - 100 - - 150 mV
Non-Linearity
X Input X = 20VP-P
Y= ±10VDC -±0.5 - - ±0.8 - %
Y Input Y = 20VP-P
X = ±10VDC -±0.2 - - ±0.3 - %
Frequency Response Small Signal
Bandwidth (-3dB) - 1.0 - - 1.0 - MHz
Full Power Bandwidth - 750 - - 750 - kHz
Slew Rate - 45 - - 45 - V/µs
1% Amplitude Error - 75 - - 75 - kHz
1% Vector Error (0.5o Phase Shift) - 5 - - 5 - kHz
Settling Time (to ±2% of Final Value) VlN = ±10V - 1 - - 1 - µs
Overload Recovery (to ±2% of Final Value) VlN = ±10V - 1 - - 1 - µs
Output Noise 5Hz to 10kHz - 0.6 - - 0.6 - mVRMS
5Hz to 5MHz - 3 - - 3 - mVRMS
Input Resistance VlN = 0V
X lnput - 10 - - 10 - MΩ
Y lnput - 6 - - 6 - MΩ
Z lnput - 36 - - 36 - kΩ
Input Bias Current VlN = 0V
X or Y Input - - 7.5 - - 10 µA
Z Input - 25 - - 25 - µA
ICL8013
3
Schematic Diagram
Power Supply Variation
Multiplication Error - 0.2 - - 0.2 - %/%
Output Offset - - 75 - - 100 mV/V
Scale Factor - 0.1 - - 0.1 - %/%
Quiescent Current - 3.5 6.0 - 3.5 6.0 mA
THE FOLLOWING SPECIFICATIONS APPLY OVER THE OPERATING TEMPERATURE RANGES
Multiplication Error -10V < XIN < 10V,
-10V < YIN < 10V - 2 - - 3 - % Full Scale
Average Temp. Coefficients
Accuracy - 0.06 - - 0.06 - %/oC
Output Offset - 0.2 - - 0.2 - mV/oC
Scale Factor - 0.04 - - 0.04 - %/oC
Input Bias Current VIN = 0V
X or Y Input - - 5 - - 10 µA
Z Input - - 25 - - 35 µA
Input Voltage (X, Y, or Z) - - ±10 - - ±10 V
Output Voltage Swing RL≥ 2kΩ
CL < 1000pF -±10 - - ±10 - V
Electrical Specifications TA=25
oC, VSUPPLY =±15V, Gain and Offset Potentiometers Externally Trimmed, Unless Otherwise Specified
(Continued)
PARAMETER TEST
CONDITIONS
ICL8013B ICL8013C
UNITSMIN TYP MAX MIN TYP MAX
Q1Q2
Q3Q4
R3
R1
COMMON
YIN
XIN
V+
V-
Q5Q6
R4R5
Q28
Q7Q8Q14 Q15
Q10
R13
Q9
R9
R6R7
R10
Q11 Q12
Q13
R12 R15
R11 R19
R18
R17
YOS
XOS
R20 R22
R16
R2R8R23
R24 R25 R26
R21
Q19
Q18
Q20
Q16
Q24
Q23
Q22
Q26
C1Q21
R27
Q25
R31 R30
R28
R29
Q27
R33
OUTPUT
ZIN
Q17
R32
ZOS
ICL8013
4
Application Information
Detailed Circuit Description
The fundamental element of the ICL8013 multiplier is the
bipolar differential amplifier of Figure 1.
The small signal differential voltage gain of this circuit is
given by:
The output voltage is thus proportional to the product of the
input voltage VlN and the emitter current IE. In the simple
transconductance multiplier of Figure 2, a current source
comprising Q3, D1, and RY is used. If VY is large compared
with the drop across D1, then
There are several difficulties with this simple modulator:
1. VY must be positive and greater than VD.
2. Some portion of the signal at VXwill appear at the output
unless IE = 0.
3. VXmust be a small signal for the differential pair to be
linear.
4. The output voltage is not centered around ground.
The first problem relates to the method of converting the VY
voltage to a current to vary the gain of the VXdifferential pair.
A better method, Figure 3, uses another differential pair but
with considerable emitter degeneration. In this circuit the
differential input voltage appears across the common emitter
resistor, producing a current which adds or subtracts from
the quiescent current in either collector. This type of voltage
to current converter handles signals from 0V to ±10V with
excellent linearity.
The second problem is called feedthrough; i.e., the product
of zero and some finite Input signal does not produce zero
output voltage. The circuit whose operation is illustrated by
Figures 4A, 4B, and 4C overcomes this problem and forms
the heart of many multiplier circuits in use today.
This circuit is basically two matched differential pairs with
cross coupled collectors. Consider the case shown in Figure
4A of exactly equal current sources basing the two pairs.
With a small positive signal at VlN, the collector current of Q1
and Q4 will increase but the collector currents of Q2 and Q3
will decrease by the same amount. Since the collectors are
cross coupled the current through the load resistors remains
unchanged and independent of the VlN input voltage.
In Figure 4B, notice that with VIN = 0 any variation in the ratio
of biasing current sources will produce a common mode
voltage across the load resistors. The differential output
voltage will remain zero. In Figure 4C we apply a differential
input voltage with unbalanced current sources. If IE1 is twice
IE2 the gain of differential pair Q1and Q2is twice the gain of
pair Q3 and Q4. Therefore, the change in cross coupled
collector currents will be unequal and a differential output
voltage will result. By replacing the separate biasing current
sources with the voltage to current converter of Figure 3 we
hav e a balanced m ultiplier circuit capab le of f our quadr ant
operation (Figure 5).
2IE
RL
RL
VIN
VOUT
V+
V-
FIGURE 1. DIFFERENTIAL AMPLIFIER
AVVOUT
VIN
----------------RL
rE
-------==
Substituting rE1
gM
------- kT
qIE
---------==
VOUT VIN RL
rE
-------
VIN qIERL
kT
-------------------
×==
IDVY
RY
--------
≈2IEand=
VOUT qRL
kTRY
--------------- VXVY
×()=
2IE
RL
RL
VIN
VOUT
V+
V-
Q3
RY
VY
ID
VDD1
qRL
kTRY(VX x VY)
VOUT = K (VX x VY) =
-
+
FIGURE 2. TRANSCONDUCTANCE MULTIPLIER
IE + ∆I
IE
IE - ∆I
VIN
∆VOUT
V+
V-
IE
∆I = VIN
RE
FIGURE 3. VOLTAGE TO CURRENT CONVERTER
ICL8013
5
This circuit of Figure 5 still has the problem that the input
voltage VIN must be small to keep the differential amplifier in
the linear region. To be able to handle large signals, we need
an amplitude compression circuit.
Figure 2 showed a current source formed by relying on the
matching characteristics of a diode and the emitter base
junction of a transistor. Extension of this idea to a differential
circuit is shown in Figure 6A. In a differential pair, the input
voltage splits the biasing current in a logarithmic ratio. (The
usual assumption of linearity is useful only for small signals.)
Since the input to the differential pair in Figure 6A is the
difference in voltage across the two diodes, which in turn is
proportional to the log of the ratio of drive currents, it follows
that the ratio of diode currents and the ratio of collector
currents are linearly related and independent of amplitude. If
we combine this circuit with the voltage to current converter
of Figure 3, we have Figure 6B. The output of the differential
amplifier is now proportional to the input voltage over a large
dynamic range, thereby improving linearity while minimizing
drift and noise factors.
The complete schematic is shown after the Electrical
Specifications Table. The differential pair Q3 and Q4 form a
voltage to current converter whose output is compressed in
collector diodes Q1 and Q2. These diodes drive the
balanced cross-coupled differential amplifier Q7/Q8Q14/Q15.
The gain of these amplifiers is modulated by the voltage to
current converter Q9 and Q10. Transistors Q5, Q6, Q11, and
Q12 are constant current sources which bias the voltage to
current converter. The output amplifier comprises transistors
Q16 through Q27.
IE
RL
VIN
∆VOUT = 0
V+
IE
V-
1/2 IE + ∆
+
-
1/2 IE - ∆
RL
Q1Q2Q3Q4
1/2 IE - ∆
1/2 IE + ∆
IEIE
FIGURE 4A. INPUT SIGNAL WITH BALANCED CURRENT
SOURCES ∆VOUT = 0V
IE
RL
VIN = 0
∆VOUT = 0
V+
2IE
V-
1/2 IE
+
-
1/2 IE
RL
Q1Q2Q3Q4
IE
IE
FIGURE 4B. NO INPUT SIGNAL WITH UNBALANCED
CURRENT SOURCES ∆VOUT = 0V
IE
RL
VIN
∆VOUT = 0
V+
2IE
V-
1/2 IE + ∆
+
-
1/2 IE - ∆
RL
Q1Q2Q3Q4
1/2 IE -2∆
IE + 2∆
3/2I + ∆3/2I - ∆
FIGURE 4C. INPUT SIGNAL WITH UNBALANCED CURRENT
SOURCES, DIFFERENTIAL OUTPUT VOLTAGE
IE
RL
VIN
∆V = K • (VX • VY)
V+
IE
V-
+
-
R
Q1Q2Q3Q4
RE
VIN
FIGURE 5. TYPICAL FOUR QUADRANT MULTIPLIER-
MODULATOR
X x IDX x IE(I - X) IE(I - X) ID
2 IE
FIGURE 6A. CURRENT GAIN CELL
ICL8013
6
Definition of Terms
Multiplication/Division Error: This is the basic accuracy
specification. It includes terms due to linearity, gain, and
offset errors, and is expressed as a percentage of the full
scale output.
Feedthrough: With either input at zero, the output of an
ideal multiplier should be zero regardless of the signal
applied to the other input. The output seen in a non-ideal
multiplier is known as the feedthrough.
Nonlinearity: The maximum deviation from the best
straight line constructed through the output data, expressed
as a percentage of full scale. One input is held constant and
the other swept through it nominal range. The nonlinearity is
the component of the total multiplication/division error which
cannot be trimmed out.
Typical Applications
Multiplication
In the standard multiplier connection, the Z terminal is
connected to the op amp output. All of the modulator output
current thus flows through the feedback resistor R27 and
produces a proportional output voltage.
MULTIPLIER TRIMMING PROCEDURE
1. Set XIN = YIN = 0V and adjust ZOS for zero Output.
2. Apply a ±10V low frequency (≤100Hz) sweep (sine or trian-
gle) to YIN with XIN = 0V, and adjust XOS f or minimum out-
put.
3. Applythe sweepsignalofStep 2 to XIN withYIN = 0V and
adjust YOS for minimum Output.
4. Readjust ZOS as in Step 1, if necessary.
5. WithXIN=10.0VDCandthesweepsignalofStep2applied
to YIN, adjust the Gain potentiometer f or Output = YIN.
This is easily accomplished with a diff erential scope plug-
in (A+B) by inverting one signal and adjusting Gain control
f or (Output - YIN) = Zero.
Division
If the Z terminal is used as an input, and the output of the op
amp connected to the Y input, the device functions as a
divider. Since the input to the op amp is at virtual ground,
and requires negligible bias current, the overall feedback
forces the modulator output current to equal the current
produced by Z.
Note that when connected as a divider, the X input must be a
negative voltage to maintain overall negative feedback.
DIVIDER TRIMMING PROCEDURE
1. Set trimming potentiometers at mid-scale by adjusting
voltage on pins 7, 9 and 10 (XOS, YOS, ZOS) for 0V.
2. With ZIN = 0V, trim ZOS to hold the Output constant, as
XIN is varied from -10V through -1V.
3. With ZIN = 0V and XIN = -10.0V adjust YOS for zero Out-
put voltage.
4. With ZIN = XIN (and/or ZIN = -XIN) adjust XOS for mini-
mumworst casevariationof Output, as XIN is variedfrom
-10V to -1V.
5. Repeat Steps 2 and 3 if Step 4 required a large initial ad-
justment.
6. With ZIN =X
IN (and/or ZIN =-X
IN) adjust the gain control
until the output is the closest average around +10.0V
(-10V for ZIN = -XIN) as XIN is varied from -10V to -3V.
VIN
V+
VOUT
V-
V-
FIGURE 6B. VOLTAGE GAIN WITH SIGNAL COMPRESSION
OP AMP
MODULATOR
XIN
YIN
ZIN
IO = XIN • YIN
R =
VOUT =
1
10 XIN YIN
10
FIGURE 7A. MULTIPLIER BLOCK DIAGRAM
ICL8013
ZIN
XIN
YIN
5K
7.5K
710 9
XOS YOS ZOS
4
3
6
1
OUTPUT = XIN YIN
10
FIGURE 7B. MULTIPLIER CIRCUIT CONNECTION
Therefore IOXIN YIN
•ZIN
R
----------10ZIN
===
Since YIN VOUT VOUT
,10ZIN
XIN
-----------------==
ICL8013
7
Squaring
The squaring function is achieved by simply multiplying with
the two inputs tied together. The squaring circuit may also be
used as the basis for a frequency doubler since cos2ωt=1/2
(cos 2ωt + 1).
Square Root
Tying the X and Y inputs together and using overall feedback
from the op amp results in the square root function. The
output of the modulator is again forced to equal the current
produced by the Z input.
The output is a negative voltage which maintains overall
negative feedback. A diode in series with the op amp output
prevents the latchup that would otherwise occur for negative
input voltages.
SQUARE ROOT TRIMMING PROCEDURE
1. Connect the ICL8013 in the Divider configuration.
2. Adjust ZOS,Y
OS,X
OS, and Gain using Steps 1 through 6
of Divider Trimming Procedure.
3. Convert to the Square Root configuration by connecting
XIN tothe output andinserting a diodebetweenPin 4and
the output node.
4. With ZIN = 0V adjust ZOS for zero output voltage.
Variable Gain Amplifier
Most applications for the ICL8013 are straight forward
variations of the simple arithmetic functions described
above. Although the circuit description frequently disguises
the fact, it has already been shown that the frequency
doubIer is nothing more than a squaring circuit. Similarly the
variable gain amplifier is nothing more than a multiplier, with
the input signal applied at the X input and the control voltage
applied at the Y input.
OP AMP
MODULATOR
XIN
YIN
ZIN
IZR =
VOUT =
1
10 10ZIN
XIN
IO
FIGURE 8A. DIVISION BLOCK DIAGRAM
ICL8013
ZIN
XIN
YIN 5K
7.5K
710 9
XOS YOS ZOS
4
6
3
1
OUTPUT = 10ZIN
XIN
GAIN
(0 TO -10V)
FIGURE 8B. DIVISION CIRCUIT CONNECTION
OP AMP
XIN
YIN
ZIN
IO = XIN • YIN
R =
VOUT =
1
10
XIN2
10
X
FIGURE 9A. SQUARER BLOCK DIAGRAM
ICL8013
XIN
7.5kΩ710 9
XOS YOS ZOS
4
3
6
1
OUTPUT = XIN2
10
5kΩ
SCALE
FACTOR
ADJUST
FIGURE 9B. SQUARER CIRCUIT CONNECTION
IOXIN YIN
×VOUT
–()
210ZIN
== =
VOUT 10ZIN
–=
OP AMP
MODULATOR
XIN
YIN
Z
IZR =
VOUT = -√10ZIN
1
10
IO = VO2
FIGURE 10A. SQUARE ROOT BLOCK DIAGRAM
ICL8013
ZIN
XIN
YIN
5K
7.5K
710 9
XOS YOS ZOS
4
6
3
1
OUTPUT = -√10ZIN
GAIN
(0V T O + 10V) 1N4148
FIGURE 10B. ACTUAL CIRCUIT CONNECTION
ICL8013
8
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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
ICL8013
Z
INPUT
GAIN
5K
7.5K
710 9
XOS YOS ZOS
4
3
6
1
OUTPUT = XY
10
CONTROL
VOLTAGE
FIGURE 11. VARIABLE GAIN AMPLIFIER
XOS YOS ZOS
V+
V-
20K
20K20K
FIGURE12. POTENTIOMETERSFORTRIMMINGOFFSETAND
FEEDTHROUGH
Typical Performance Curves
FIGURE 13. FREQUENCY RESPONSE FIGURE 14. NONLINEARITY vs FREQUENCY
FIGURE 15. FEEDTHROUGH vs FREQUENCY
AMPLITUDE (dB)
FREQUENCY (Hz)
PHASE (DEGREES)
PHASE
AMPLITUDE
1K 10K 100K 1M 10M
25
0
5
10
15
20
-50
0
-10
-20
-30
-40
FREQUENCY (Hz)
1K 10K 100K100
100
10
1
0.1
0.01
NONLINEARITY (% OF FULL SCALE)
Y-INPUT
X-INPUT
FREQUENCY (Hz)
1K 10K 100K 1M 10M
FEEDTHROUGH (dB)
-10
-20
-30
-40
-50
-60
-70
X = 0, Y = 20VP-P
Y = 0, X = 20VP-P
ICL8013
