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May 31, 2016
3-PHASE BRIDGE DRIVER
Package Options
Features
Floating channel designed for bootstrap operation
Tolerant to negative transient voltage – dV/dt immune
Gate drive supply range from 11.5 V to 20 V
Undervoltage lockout for all channels
Over-current shutdown turns off all six drivers
Independent 3 half-bridge drivers
Matched propagation delay for all channels
Cross-conduction prevention logic
Low side and High side outputs in phase with inputs.
3.3 V logic compatible
Lower di/dt gate drive for better noise immunity
Externally programmable delay for automatic fault clear
RoHS Compliant
Typical Applications
Motor Control
Air Conditioners/ Washing Machines
General Purpose Inverters
Micro/Mini Inverter Drives
IR21364(S&J)PBF
Product Summary
Topology
3 phase bridge
driver
VOFFSET
≤ 600 V
VOUT
11.5 V – 20V
IO+ & IO-
(typical)
200 mA & 350 mA
tON & tOFF
(typical)
500 ns & 530 ns
28-Lead SOIC 44-Lead PLCC
w/o 12 Leads
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May 31, 2016
IR21364(S&J)PBF
Description
The IR21364(S&J)PBF is a high voltage, high speed power MOSFET and IGBT drivers with three independent high and low side
referenced output channels for 3-phase applications. Proprietary HVIC technology enables ruggedized monolithic construction.
Logic inputs are compatible with CMOS or LSTTL outputs, down to 3.3V logic. A current trip function which terminates all six
outputs can be derived from an external current sense resistor. An enable function is available to terminate all six outputs
simultaneously. An open-drain FAULT signal is provided to indicate that an overcurrent or undervoltage shutdown has occurred.
Overcurrent fault conditions are cleared automatically after a delay programmed externally via an RC network connected to the
RCIN input. The output drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction.
Propagation delays are matched to simplify use in high frequency applications. The floating channel can be used to drive N-
channel power MOSFETs or IGBTs in the high side configuration which operates up to 600 V.
Qualification Information†
Qualification Level
Industrial††
Comments: This family of ICs has passed JEDEC’s
Industrial qualification. IR’s Consumer qualification level is
granted by extension of the higher Industrial level.
Moisture Sensitivity Level
SOIC28W
MSL3†††, 260C
(per IPC/JEDEC J-STD-020)
PLCC44
MSL3†††, 245C
(per IPC/JEDEC J-STD-020)
ESD
Human Body Model
Class 2
(per JEDEC standard JESD22-A114)
Machine Model
Class B
(per EIA/JEDEC standard EIA/JESD22-A115)
IC Latch-Up Test
Class I, Level A
(per JESD78)
RoHS Compliant
Yes
†
Qualification standards can be found at International Rectifier’s web site http://www.irf.com/
††
Higher qualification ratings may be available should the user have such requirements. Please contact your
International Rectifier sales representative for further information.
†††
Higher MSL ratings may be available for the specific package types listed here. Please contact your
International Rectifier sales representative for further information.
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May 31, 2016
IR21364(S&J)PBF
Absolute Maximum Ratings
Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage
parameters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are
measured under board mounted and still air conditions.
Recommended Operating Conditions
The input/output logic timing diagram is shown in Fig. 1. For proper operation the device should be used within the
recommended conditions. All voltage parameters are absolute referenced to COM. The VS & VSS offset rating are
tested with all supplies biased at a 15 V differential.
Symbol
Definition
Min.
Max.
Units
VB1,2,3
High side floating supply voltage
IR21364
VS1,2,3 +11.5
VS1,2,3 + 20
V
VS 1,2,3
High side floating supply voltage
Note 1
600
VCC
Low side supply voltage
IR21364
11.5
20
VHO 1,2,3
High side output voltage
VS1,2,3
VB1,2,3
VLO1,2,3
Low side output voltage
0
VCC
VSS
Logic ground
-5
5
VFLT
FAULT output voltage
VSS
VCC
VRCIN
RCIN input voltage
VSS
VCC
VITRIP
ITRIP input voltage
VSS
VSS + 5
VIN
Logic input voltage LIN, HIN, EN
VSS
VSS + 5
TA
Ambient temperature
-40
125
°C
Note 1: Logic operational for VS of COM -5 V to COM + 600 V. Logic state held for VS of COM -5 to COM – VBS.
(Please refer to the Design Tip DT97 -3 for more details).
Symbol
Definition
Min
Max
Units
VS
High side offset voltage
VB 1,2,3 - 25
VB 1,2,3 + 0.3
V
VB
High side floating supply voltage
-0.3
625
VHO
High side floating output voltage
VS1,2,3 - 0.3
VB 1,2,3 + 0.3
VCC
Low side and logic fixed supply voltage
-0.3
25
VSS
Logic ground
VCC - 25
VCC + 0.3
VLO1,2,3
Low side output voltage
-0.3
VCC + 0.3
VIN
Input voltage LIN, HIN, ITRIP, EN, RCIN
VSS -0.3
lower of
VCC + 0.3 or
Vss+15
VFLT
FAULT output voltage
VSS -0.3
VCC + 0.3
dV/dt
Allowable offset voltage slew rate
—
50
V/ns
PD
Package power dissipation
@ TA ≤ +25 °C
(28 lead SOIC)
—
1.6
W
(44 lead PLCC)
—
2.0
RthJA
Thermal resistance, junction to
ambient
(28 lead SOIC)
—
78
°C/W
(44 lead PLCC)
—
63
TJ
Junction temperature
—
150
°C
TS
Storage temperature
-55
150
TL
Lead temperature (soldering, 10 seconds)
—
300
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May 31, 2016
IR21364(S&J)PBF
Static Electrical Characteristics
VBIAS (VCC, VBS 1,2,3) = 15 V, TA = 25°C unless otherwise specified. The VIN, VTH and IIN parameters are referenced to
VSS and are applicable to all six channels (HIN1,2,3 and LIN1,2,3). The VO and IO parameters are referenced to COM
and VS1,2,3 and are applicable to the respective output leads: HO1,2,3 and LO1,2,3.
Symbol
Definition
Min
Typ
Max
Units
Test
Conditions
VIH
Logic “0” input voltage
—
—
0.8
V
VIL
Logic “1” input voltage
2.5
—
—
VEN,TH+
Enable positive going threshold
—
—
2.5
VEN,TH-
Enable negative going threshold
0.8
—
—
VIT,TH+
ITRIP positive going threshold
0.37
0.46
0.55
VIT,HYS
ITRIP hysteresis
—
0.07
—
VRCIN, TH+
RCIN positive going threshold
—
8
—
VRCIN, HYS
RCIN hysteresis
—
3
—
VOH
High level output voltage, VBIAS - VO
—
0.9
1.4
Io = 20 mA
VOL
Low level output voltage, VO
—
0.4
0.6
VCCUV+
VCC supply undervoltage positive going
threshold
IR21364
9.6
10.4
11.2
VCCUV-
VCC supply undervoltage negative going
threshold
IR21364
8.6
9.4
10.2
VCCUVHY
VCC supply undervoltage hysteresis
IR21364
—
1
—
VBSUV+
VBS supply undervoltage positive going
threshold
IR21364
9.6
10.4
11.2
VBSUV-
VBS supply undervoltage negative going
threshold
IR21364
8.6
9.4
10.2
VBSUVHY
VBS supply undervoltage
hysteresis
IR21364
—
1
—
llk
Offset supply leakage current
—
—
50
µA
VB = VS = 600 V
IQBS
Quiescent VBS supply current
—
70
120
VB1,2,3 = VS1,2,3 =
600 V
IQCC
Quiescent VCC supply current
—
0.6
1.3
mA
VIN = 0 V or 5 V
ILIN+
Input bias current (LOUT = HI)
—
100
195
µA
VLIN = 3.3 V
ILIN-
Input bias current (LOUT = LO)
-1
—
—
VLIN = 0 V
IHIN+
Input bias current (HOUT = HI)
—
100
195
VHIN = 3.3 V
IHIN-
Input bias current (HOUT = LO)
-1
—
—
VHIN = 0 V
IITRIP+
“High” ITRIP input bias current
—
3.3
6
VITRIP = 3.3 V
IITRIP-
“Low” ITRIP input bias current
-1
—
—
VITRIP = 0 V
IEN+
“High” ENABLE input bias current
—
100
—
VEN = 3.3 V
IEN-
“Low” ENABLE input bias current
-1
—
—
VEN = 0 V
IRCIN
RCIN input bias current
—
—
1
Vrcin = 0 V or 15
V
Io+
Output high short circuit pulsed current
120
200
—
mA
Vo = 0 V,
PW ≤ 10 µs
Io-
Output low short circuit pulsed current
250
350
—
Vo = 15 V,
PW ≤ 10 µs
Ron_RCIN
RCIN low on resistance
—
50
100
Ω
I = 1.5 mA
Ron_FAULT
FAULT low on resistance
—
50
100
5
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May 31, 2016
IR21364(S&J)PBF
Dynamic Electrical Characteristics
Dynamic Electrical Characteristics VCC = VBS = VBIAS = 15 V, VS1,2,3 = VSS = COM, TA = 25°C and CL = 1000 pF
unless otherwise specified.
Symbol
Definition
Min
Typ
Max
Units
Test Conditions
ton
Turn-on propagation delay
350
500
650
ns
VIN = 0 V & 5 V
toff
Turn-off propagation delay
375
530
685
tr
Turn-on rise time
—
125
190
tf
Turn-off fall time
—
50
75
tEN
ENABLE low to output shutdown propagation
delay
300
450
600
VIN, VEN = 0 V or 5 V
tITRIP
ITRIP to output shutdown propagation delay
500
750
1000
VITRIP = 5 V
tbl
ITRIP blanking time
100
150
—
VIN = 0 V or 5 V
VITRIP = 5 V
tFLT
ITRIP to FAULT propagation delay
400
600
800
tFILIN
Input filter time (HIN, LIN)
100
200
—
VIN = 0 V & 5 V
tfilterEn
Enable input filter time
100
200
—
DT
Deadtime
220
290
360
MT
Ton, off matching time (on all six channels)
—
—
75
External dead time
>450 nsec
MDT
DT matching (Hi->Lo & Lo->Hi on all channels)
—
—
70
PM
pulse width distortion (pwin-pwout)
—
—
75
PW input =10 µs
tFLTCLR
FAULT clear time RCIN: R = 2 MΩ, C = 1 nF
1.3
1.65
2
ms
VIN = 0 V or 5 V
VITRIP = 0 V
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May 31, 2016
IR21364(S&J)PBF
Fig. 1. Input/Output Timing Diagram
Fig. 2. Switching Time Waveforms
Fig. 3. Output Enable Timing Waveform
EN
ITRIP
FAULT
HIN1,2,3
LIN1,2,3
RCIN
HO1,2,3
LO1,2,3
90%
ten
EN
50%
LIN1,2,3
HIN1,2,
3
50%
50%
PW
IN
t
r
10%
HO1,2,3
LO1,2,3
90%
t
f
ton
tof
f
90%
10%
HO1,2,3
LO1,2,3
PW
50
%
OUT
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May 31, 2016
IR21364(S&J)PBF
RCIN
ITRIP
FAULT
Any
Ouput
titrip
50%
50%
90%
tflt 50%
tfltclr
50%
Fig. 5. ITRIP/RCIN Timing Waveforms
Fig. 6. Input Filter Function
Fig. 4. Internal Deadtime Timing Waveforms
on
off
on
HIN/LI
N
t
in,fi
l
lo
w
t
in,fi
l
on
off
off
high
LO1,2,3
HO1,2,3
50%
50%
DT 50%
HIN1,2,3
LIN1,2,3 50% 50%
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May 31, 2016
IR21364(S&J)PBF
Lead Definitions
Symbol
Description
VCC
Low side supply voltage
VSS
Logic ground
HIN1,2,3
Logic inputs for high side gate driver outputs (HO1,2,3), in phase
LIN1,2,3
Logic input for low side gate driver outputs (LO1,2,3), in phase
FAULT
Indicates over-current (ITRIP) or low-side undervoltage lockout has occurred. Negative logic, open-drain
output
EN
Logic input to enable I/O functionality. Positive logic, i.e. I/O logic functions When ENABLE is high. No
effect on FAULT and not latched
ITRIP
Analog input for overcurrent shutdown. When active, ITRIP shuts down outputs and activates FAULT and
RCIN low. When ITRIP becomes inactive, FAULT stays active low for an externally set time TFLTCLR, then
automatically becomes inactive (open-drain high impedance).
RCIN
External RC network input used to define FAULT CLEAR delay, TFLTCLR, approximately equal to R*C.
When RCIN > 8 V, the FAULT pin goes back into open-drain high-impedance
COM
Low side gate drivers return
VB1,2,3
High side floating supply
HO1,2,3
High side gate driver outputs
VS1,2,3
High voltage floating supply return
LO1,2,3
Low side gate driver outputs
28 Lead SOIC (wide body)
IR21364J
IR21364S
VCC
FAULT
LIN3
LIN2
LIN1
HO3
VB3
HO2
VB2
VB1
VS1
HO1HIN1
1
2
3
4
5
6
7
8
9
10
11
12
13
14 15
17
16
19
18
26
27
28
24
25
23
22
21
20
HIN2
HIN3
VS2
ITRIP
EN
RCIN
VSS
COM
LO3
LO1
LO2
VS3
44 Lead PLCC w/o 12 leads
7
8
9
10
11
12
13
14
15
16
17
5 34 4142
43
6
18 19 20 21 22 23 24 25
LIN2
LIN3
FAULT
LIN1
ITRIP
EN
RCIN
HIN3
HIN2
HIN1
VCC
VB1
HO1
VS1
VSS
COM
LO3
LO2
LO1
29
30
31
35
36
37
VS3
HO3
VB3
VS2
HO2
VB2
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May 31, 2016
IR21364(S&J)PBF
Functional Block Diagram
VCC
VBS
ITRIP
ENAB LE
FAULT
LO1,2,3
HO1,2,3
<UVCC
X
X
X
0 (note 1)
0
0
15 V
<UVBS
0 V
5 V
high imp
LIN1,2,3
0
15 V
15 V
0 V
5 V
high imp
LIN1,2,3
HIN1,2,3
15 V
15 V
>VITRIP
5 V
0 (note 2)
0
0
15 V
15 V
0 V
0 V
high imp
0
0
Note 1: A shoot-through prevention logic prevents LO1,2,3 and HO1,2,3 for each channel from turning on simultaneously.
Note 2: UVCC is not latched, when VCC > UVCC, FAULT return to high impedance.
Note 3: When ITRIP <VITRIP, FAULT returns to high-impedance after RCIN pin becomes greater than 8 V (@ VCC = 15 V)
INPUT
NOISE
FILTER
HIN1
LIN1
HIN2
LIN2
HIN3
LIN3
VSS
EN
FAULT
COM
VB1
DEADTIME &
SHOOT- THROUGH
PREVENTION
UV
DETECT
LATCH
UV
DETECT
HV
LEVEL
SHIFTER RESET
SET DRIVER
LATCH
UV
DETECT
VSS/COM
LEVEL
SHIFTER
HV
LEVEL
SHIFTER RESET
SET DRIVER
LATCH
UV
DETECT
RESET
SET DRIVER
LO1
LO2
LO3
HO2
HO3
HO1
ITRIP
RCIN S
R SET
DOMINANT
LATCH Q
DELAY DRIVER
DELAY DRIVER
DELAY DRIVER
0.5 V
VCC
VB2
VS1
VS3
VB3
VS2
IR21364
DEADTIME &
SHOOT- THROUGH
PREVENTION
DEADTIME &
SHOOT- THROUGH
PREVENTION
INPUT
NOISE
FILTER
INPUT
NOISE
FILTER
INPUT
NOISE
FILTER
INPUT
NOISE
FILTER
INPUT
NOISE
FILTER
INPUT
NOISE
FILTER
INPUT
NOISE
FILTER
VSS/COM
LEVEL
SHIFTER
VSS/COM
LEVEL
SHIFTER
VSS/COM
LEVEL
SHIFTER
VSS/COM
LEVEL
SHIFTER
VSS/COM
LEVEL
SHIFTER
HV
LEVEL
SHIFTER
10
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IR21364(S&J)PBF
Parameter Temperature Trends
Figures 7-39 provide information on the experimental performance of the IR21364 HVIC. The line plotted
in each figure is generated from actual lab data. A small number of individual samples were tested at
three temperatures (-40 ºC, 25 ºC, and 125 ºC) in order to generate the experimental (Exp.) curve. The
line labeled Exp. consist of three data points (one data point at each of the tested temperatures) that have
been connected together to illustrate the understood temperature trend. The individual data points on the
curve were determined by calculating the averaged experimental value of the parameter (for a given
temperature).
Fig. 7. (Ton_Ls1 ) Turn-on Propagation Delay
vs. Temperature
0
100
200
300
400
500
600
700
800
-50 -25 0 25 50 75 100 125
Temperature (oC)
tON (ns)
Exp.
0
200
400
600
800
1000
-50 -25 0 25 50 75 100 125
Temperature (oC)
tOFF (ns)
Exp.
Fig. 8. (Toff_Ls1) Turn-off Propagation Delay
vs. Temperature
0
100
200
300
400
500
600
700
800
-50 -25 0 25 50 75 100 125
Temperature (oC)
tON (ns)
Exp.
Fig. 9. (Ton_Hs11) Turn-on Propagation Delay
vs. Temperature
0
100
200
300
400
500
600
700
800
-50 -25 0 25 50 75 100 125
Temperature (oC)
tOFF (ns)
Exp.
Fig. 10. (Toff_Hs21) Turn-off Propagation
Delay vs. Temperature
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May 31, 2016
IR21364(S&J)PBF
0
50
100
150
200
250
-50 -25 0 25 50 75 100 125
Temperature (oC)
tR (ns)
Exp.
Fig. 11. Turn-on Rise Time vs. Temperature
0
20
40
60
80
100
120
-50 -25 0 25 50 75 100 125
Temperature (oC)
tF (ns)
Exp.
Fig. 12. Turn-off Fall Time vs. Temperature
0
200
400
600
800
1000
-50 -25 0 25 50 75 100 125
Temperature (oC)
tITRIP (ns)
Exp.
Fig. 16. ITRIP to Output Shutdown Propagation
Delay vs. Temperature
0
20
40
60
80
100
-50 -25 0 25 50 75 100 125
Temperature (oC)
MT (ns)
Exp.
Fig. 13. Ton, off matching time vs.
Temperature
0
20
40
60
80
100
-50 -25 0 25 50 75 100 125
Temperature (oC)
MDT (ns)
Exp.
Fig. 14. DT matching time vs. Temperature
0
20
40
60
80
100
-50 -25 0 25 50 75 100 125
Temperature (oC)
PM (ns)
Exp.
Fig. 15. Pulse Width Distortion vs.
Temperature
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May 31, 2016
IR21364(S&J)PBF
0
200
400
600
800
1000
-50 -25 0 25 50 75 100 125
Temperature (oC)
TEN (nS)
Exp.
Figure 18. EN to Output Shutdown Time vs.
Temperature
0
100
200
300
400
500
600
700
800
900
1000
-50 -25 0 25 50 75 100 125
Temperature (oC)
tFLT (ns)
Exp.
Fig. 19. ITRIP to FAULT Indication Delay vs.
Temperature
0.0
1.0
2.0
3.0
4.0
5.0
-50 -25 0 25 50 75 100 125
Temperature (oC)
TFLTCLR (mS)
Exp.
Fig. 20. FAULT Clear Time vs. Temperature
0
200
400
600
800
1000
1200
-50 -25 0 25 50 75 100 125
Temperature (oC)
DLTon1 (ns)
Exp.
Fig. 17. Dead Time vs. Temperature
0.0
1.5
3.0
4.5
6.0
-50 -25 0 25 50 75 100 125
Temperature (oC)
LIN1_VTH+ (V)
Exp.
Fig. 21. Input Positive Going Threshold vs.
Temperature
0.0
0.5
1.0
1.5
2.0
2.5
-50 -25 0 25 50 75 100 125
Temperature (oC)
LIN1_VTH- (V)
Exp.
Fig. 22. Input Negative Going Threshold vs.
Temperature
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May 31, 2016
IR21364(S&J)PBF
0
100
200
300
400
500
600
700
800
-50 -25 0 25 50 75 100 125
Temperature (oC)
VIT,TH+ (mV)
EXP.
p.
Fig. 23. ITRIP Input Positive Going Threshold
vs. Temperature
0
100
200
300
400
500
600
700
800
-50 -25 0 25 50 75 100 125
Temperature (oC)
VIT,TH-
(mV)
Exp.
Fig. 24. ITRIP Input Negative Going Threshold
vs. Temperature
0
100
200
300
400
500
600
-50 -25 0 25 50 75 100 125
Temperature (oC)
VOL_LO1 (mV)
Exp.
Fig. 25. Low Level Output Voltage vs.
Temperature
0
400
800
1200
1600
-50 -25 0 25 50 75 100 125
Temperature (oC)
VOH_LO1 (mV)
Exp.
Fig. 26. High Level Output Voltage vs.
Temperature
0.0
0.5
1.0
1.5
2.0
2.5
-50 -25 0 25 50 75 100 125
Temperature (oC)
ileak1 (µA)
Exp.
Fig. 28. Offset Supply Leakage Current vs.
Temperature
0
20
40
60
80
100
120
-50 -25 0 25 50 75 100 125
Temperature (oC)
RON,FLT (Ω)
Exp.
Fig. 27. FAULT Low On-Resistance vs.
Temperature
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May 31, 2016
IR21364(S&J)PBF
0.0
0.5
1.0
1.5
2.0
-50 -25 0 25 50 75 100 125
Temperature (oC)
IQCC1 (mA)
Exp.
Fig. 29. Quiescent VCC Supply Current vs.
Temperature
0.0
0.5
1.0
1.5
2.0
-50 -25 0 25 50 75 100 125
Temperature (oC)
IQCC0 (mA)
Exp.
Fig. 30. Quiescent VCC Supply Current vs.
Temperature
0
10
20
30
40
50
60
70
80
-50 -25 0 25 50 75 100 125
Temperature (oC)
IQBS10 (μA)
Exp.
Fig. 31. Quiescent VBS Supply Current vs.
Temperature
0
20
40
60
80
100
120
140
-50 -25 0 25 50 75 100 125
Temperature (oC)
IQBS11 (μA)
Exp.
Fig. 32. Quiescent VBS Supply Current vs.
Temperature
0.0
3.0
6.0
9.0
12.0
15.0
-50 -25 0 25 50 75 100 125
Temperature (oC)
VCCUV- (V)
Exp.
Fig. 33. VCC Supply Undervoltage Negative
Going Threshold vs. Temperature
0.0
3.0
6.0
9.0
12.0
15.0
18.0
-50 -25 0 25 50 75 100 125
Temperature (oC)
VCCUV+ (V)
Exp.
Fig. 34. VCC Supply Undervoltage Positive
Going Threshold vs. Temperature
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May 31, 2016
IR21364(S&J)PBF
0.0
3.0
6.0
9.0
12.0
15.0
-50 -25 0 25 50 75 100 125
Temperature (oC)
VBSUV- (V)
Exp.
Fig. 35. VBS Supply Undervoltage Negative
Going Threshold vs. Temperature
0.0
3.0
6.0
9.0
12.0
15.0
-50 -25 0 25 50 75 100 125
Temperature (oC)
VBSUV+ (V)
Exp.
Fig. 36. VBS Supply Undervoltage Positive
Going Threshold vs. Temperature
-0.5
-0.4
-0.3
-0.2
-0.1
0.0-50 -25 0 25 50 75 100 125
Temperature (oC)
IO+ (mA)
Exp.
p.
Fig. 37. Output High Short Circuit Pulsed
Current vs. Temperature
0.0
0.1
0.2
0.3
0.4
0.5
-50 -25 0 25 50 75 100 125
Temperature (oC)
IO- (mA)
Exp.
Fig. 38. Output Low Short Circuit Pulsed Current
vs. Temperature
-14
-12
-10
-8
-6
-4
-2
0-50 -25 0 25 50 75 100 125
Temperature (oC)
Vs1_RST_domin (V)
Exp.
Fig. 39. Max -VS vs. Temperature
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IR21364(S&J)PBF
Case Outlines
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IR21364(S&J)PBF
CARRIER TAPE DIMENSION FOR 28SOICW
Code Min Max Min Max
A11.90 12.10 0.468 0.476
B 3.90 4.10 0.153 0.161
C23.70 24.30 0.933 0.956
D11.40 11.60 0.448 0.456
E10.80 11.00 0.425 0.433
F18.20 18.40 0.716 0.724
G1.50 n/a 0.059 n/a
H1.50 1.60 0.059 0.062
Metric
Imperial
REEL DIMENSIONS FOR 28SOICW
Code Min Max Min Max
A329.60 330.25 12.976 13.001
B20.95 21.45 0.824 0.844
C12.80 13.20 0.503 0.519
D1.95 2.45 0.767 0.096
E98.00 102.00 3.858 4.015
Fn/a 30.40 n/a 1.196
G26.50 29.10 1.04 1.145
H24.40 26.40 0.96 1.039
Metric
Imperial
E
F
A
C
D
G
A
B
H
NOTE : CONTROLLING
DIMENSION IN MM
LOADED TAPE FEED DIRECTION
A
H
F
E
G
D
B
C
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May 31, 2016
IR21364(S&J)PBF
CARRIER TAPE DIMENSION FOR 44PLCC
Code Min Max Min Max
A23.90 24.10 0.94 0.948
B 3.90 4.10 0.153 0.161
C31.70 32.30 1.248 1.271
D14.10 14.30 0.555 0.562
E17.90 18.10 0.704 0.712
F17.90 18.10 0.704 0.712
G2.00 n/a 0.078 n/a
H1.50 1.60 0.059 0.062
Metric
Imperial
REEL DIMENSIONS FOR 44PLCC
Code Min Max Min Max
A329.60 330.25 12.976 13.001
B20.95 21.45 0.824 0.844
C12.80 13.20 0.503 0.519
D1.95 2.45 0.767 0.096
E98.00 102.00 3.858 4.015
Fn/a 38.4 n/a 1.511
G34.7 35.8 1.366 1.409
H32.6 33.1 1.283 1.303
Metric
Imperial
E
F
A
C
D
G
A
B
H
NOTE : CONTROLLING
DIMENSION IN MM
LOADED TAPE FEED DIRECTION
A
H
F
E
G
D
B
C
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May 31, 2016
IR21364(S&J)PBF
The information provided in this document is believed to be accurate and reliable. However, International Rectifier assumes no responsibility
for the consequences of the use of this information. International Rectifier assumes no responsibility for any infringement of patents or of other
rights of third parties which may result from the use of this information. No license is granted by implication or otherwise under any patent or
patent rights of International Rectifier. The specifications mentioned in this document are subject to change without notice. This document
supersedes and replaces all information previously supplied.
For technical support, please contact IR’s Technical Assistance Center
http://www.irf.com/technical-info/
WORLD HEADQUARTERS:
233 Kansas St., El Segundo, California 90245
Tel: (310) 252-7105
ORDER INFORMATION
28-Lead SOIC IR21364SPbF
44-Lead PLCC IR21364JPbF
IRSxxxxx
IR logo
YWW?
Part number
Date code
Pin 1
Identifier Lot Code
(Prod mode – 4 digit SPN code)
Assembly site code
Per SCOP 200-002
LEAD-FREE PART MARKING INFORMATION
MARKING CODE
Lead Free Released
Non-Lead Free
Relased
?XXXX
?
P
28-Lead SOIC Tape & Reel IR21364STRPbF
44-Lead PLCC Tape & Reel IR21364JTRPbF
20
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May 31, 2016
IR21364(S&J)PBF
Change History
Revision
Date
Change comments
1.0
04/03/08
Included Qual Info, Replaced “Also available LEAD-FREE”
statement in the front page with “RoHS Compliant”, removed typical
spec limit for MT, MDT, & PM, added Tri-temp plots, and added
disclaimer at end of the datasheet.
2.0
5/3/2016
in package drawing
