PHP/PHB/PHD63NQ03LT
TrenchMOS™ logic level FET
Rev. 01 — 14 June 2002 Product data
1. Product profile
1.1 Description
N-channel enhancement mode field-effect transistor in a plastic package using
TrenchMOS™ technology.
Product availability:
PHP63NQ03LT in SOT78 (TO-220AB)
PHB63NQ03LT in SOT404 (D2-PAK)
PHD63NQ03LT in SOT428 (D-PAK).
1.2 Features
1.3 Applications
1.4 Quick reference data
2. Pinning information
[1] It is not possible to make connection to pin 2 of the SOT404 or SOT428 packages.
■Logic level compatible ■Low gate charge
■DC to DC converters ■Switched mode power supplies
■VDS =30V ■ID= 68.9 A
■Ptot = 111 W ■RDSon ≤13 mΩ
Table 1: Pinning - SOT78, SOT404, SOT428 simplified outline and symbol
Pin Description Simplified outline Symbol
1 gate (g)
SOT78 (TO-220) SOT404 (D2-PAK) SOT428 (D-PAK)
2 drain (d) [1]
3 source (s)
mb mounting base,
connected to drain (d)
MBK106
12
mb
3
13
2
MBK116
mb
MBK091
Top view
13
mb
2s
d
g
MBB076
Philips Semiconductors PHP/PHB/PHD63NQ03LT
TrenchMOS™ logic level FET
Product data Rev. 01 — 14 June 2002 2 of 14
9397 750 09822 © Koninklijke Philips Electronics N.V. 2002. All rights reserved.
3. Limiting values
Table 2: Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VDS drain-source voltage (DC) 25 °C≤Tj≤ 175 °C - 30 V
VDGR drain-gate voltage (DC) 25 °C≤Tj≤ 175 °C; RGS =20kΩ-30V
VGS gate-source voltage (DC) - ±20 V
VGSM peak gate-source voltage tp≤50 µs; pulsed; duty cycle = 25 % - ±25 V
IDdrain current (DC) Tmb =25°C; VGS =10V;Figure 2 and 3- 68.9 A
Tmb = 100 °C; VGS =10V;Figure 2 - 48.7 A
IDM peak drain current Tmb =25°C; pulsed; tp≤10 µs; Figure 3 - 240 A
Ptot total power dissipation Tmb =25°C; Figure 1 - 111 W
Tstg storage temperature −55 +175 °C
Tjjunction temperature −55 +175 °C
Source-drain diode
ISsource (diode forward) current (DC) Tmb =25°C - 68.9 A
ISM peak source (diode forward) current Tmb =25°C; pulsed; tp≤10 µs - 48.7 A
Philips Semiconductors PHP/PHB/PHD63NQ03LT
TrenchMOS™ logic level FET
Product data Rev. 01 — 14 June 2002 3 of 14
9397 750 09822 © Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Fig 1. Normalized total power dissipation as a
function of mounting base temperature. Fig 2. Normalized continuous drain current as a
function of mounting base temperature.
Tmb =25°C; IDM is single pulse; VGS = 10V.
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage.
03aa16
0
40
80
120
0 50 100 150 200
Tmb (°C)
Pder
(%)
03aa24
0
40
80
120
0 50 100 150 200
Tmb (°C)
Ider
(%)
Pder Ptot
Ptot 25 C
°
()
----------------------- 100%×=Ider ID
ID25C
°
()
------------------- 100%×=
03ai84
1
10
102
103
1 10 10
VDS (V)
ID
(A)
DC
Limit RDSon = VDS / ID
1 ms
tp = 10 µs
100 µs
Philips Semiconductors PHP/PHB/PHD63NQ03LT
TrenchMOS™ logic level FET
Product data Rev. 01 — 14 June 2002 4 of 14
9397 750 09822 © Koninklijke Philips Electronics N.V. 2002. All rights reserved.
4. Thermal characteristics
4.1 Transient thermal impedance
Table 3: Thermal characteristics
Symbol Parameter Conditions Min Typ Max Unit
Rth(j-mb) thermal resistance from junction to mounting base Figure 4 - - 1.35 K/W
Rth(j-a) thermal resistance from junction to ambient
SOT78 vertical in still air - 60 - K/W
SOT428 SOT428 minimum footprint;
mounted on a PCB - 75 - K/W
SOT404 and SOT428 SOT404 minimum footprint;
mounted on a PCB - 50 - K/W
Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration.
03ai83
10-2
10-1
1
10
10-5 10-4 10-3 10-2 10-1
tp (s)
Zth(j-mb)
(K/W)
single pulse
δ = 0.5
0.2
0.1
0.05
0.02
tp
tp
T
P
t
T
δ =
Philips Semiconductors PHP/PHB/PHD63NQ03LT
TrenchMOS™ logic level FET
Product data Rev. 01 — 14 June 2002 5 of 14
9397 750 09822 © Koninklijke Philips Electronics N.V. 2002. All rights reserved.
5. Characteristics
Table 4: Characteristics
T
j
=25
°
C unless otherwise specified
Symbol Parameter Conditions Min Typ Max Unit
Static characteristics
V(BR)DSS drain-source breakdown voltage ID= 250 µA; VGS =0V
Tj=25°C 30--V
Tj=−55 °C 27--V
VGS(th) gate-source threshold voltage ID= 1 mA; VDS =V
GS;Figure 9 V
Tj=25°C 1 1.9 2.5 V
Tj= 175 °C 0.6 - - V
Tj=−55 °C - - 2.9 V
IDSS drain-source leakage current VDS =30V; V
GS =0V
Tj=25°C - 0.05 1 µA
Tj= 175 °C - - 500 µA
IGSS gate-source leakage current VGS =±20 V; VDS = 0 V - 10 100 nA
RDSon drain-source on-state resistance VGS =5V; I
D=25A;Figure 7 and 8
Tj=25°C - 15 17.7 mΩ
Tj= 175 °C - 24 28.3 mΩ
VGS = 10 V; ID=25A;Figure 7 and 8- 1113mΩ
Dynamic characteristics
Qg(tot) total gate charge ID= 50 A; VDD =15V; V
GS =5V;Figure 13 - 9.6 - nC
Qgs gate-source charge - 4 - nC
Qgd gate-drain (Miller) charge - 3.2 - nC
Ciss input capacitance VGS =0V; V
DS = 25 V; f = 1 MHz; Figure 11 - 920 - pF
Coss output capacitance - 275 - pF
Crss reverse transfer capacitance - 110 - pF
td(on) turn-on delay time VDD =15V; I
D= 25 A; VGS = 4.5 V; RG= 5.6 Ω-12-ns
trrise time - 140 - ns
td(off) turn-off delay time - 10.5 - ns
tffall time -14-ns
Source-drain diode
VSD source-drain (diode forward) voltage IS= 25 A; VGS =0V;Figure 12 - 0.95 1.2 V
trr reverse recovery time IS= 10 A; dIS/dt = −100 A/µs; VGS =0V - 23 - ns
Qrrecovered charge - 12 - nC
Philips Semiconductors PHP/PHB/PHD63NQ03LT
TrenchMOS™ logic level FET
Product data Rev. 01 — 14 June 2002 6 of 14
9397 750 09822 © Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Tj=25°CT
j=25°C and 175 °C; VDS >IDxR
DSon
Fig 5. Output characteristics: drain current as a
function of drain-source voltage; typical values. Fig 6. Transfer characteristics: drain current as a
function of gate-source voltage; typical values.
Tj=25°C
Fig 7. Drain-source on-state resistance as a function
of drain current; typical values. Fig 8. Normalized drain-source on-state resistance
factor as a function of junction temperature.
03ai85
0
20
40
60
80
0 0.4 0.8 1.2 1.6
VDS (V)
ID
(A) 5 V
Tj = 25 °C
VGS = 3 V
10 V
4.5 V
5.5 V
3.5 V
4 V
6 V
03ai87
0
20
40
60
80
0246
VGS (V)
ID
(A) VDS > ID x RDSon
Tj = 25 °C175 °C
03ai86
0
10
20
30
0 20406080
ID (A)
RDSon
(mΩ)
5 V
VGS = 4. 5 VTj = 25 °C
5.5V
10 V
6 V
03af18
0
0.5
1
1.5
2
-60 0 60 120 180
Tj (°C)
a
aRDSon
RDSon 25 C
°
()
-----------------------------
=
Philips Semiconductors PHP/PHB/PHD63NQ03LT
TrenchMOS™ logic level FET
Product data Rev. 01 — 14 June 2002 7 of 14
9397 750 09822 © Koninklijke Philips Electronics N.V. 2002. All rights reserved.
ID= 1 mA; VDS =V
GS Tj=25°C; VDS =5V
Fig 9. Gate-source threshold voltage as a function of
junction temperature. Fig 10. Sub-threshold drain current as a function of
gate-source voltage.
VGS =0V;f=1MHz
Fig 11. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values.
03ai29
0
0.8
1.6
2.4
3.2
-60 0 60 120 180
Tj (°C)
VGS(th)
(V)
min
typ
max
03ai28
10-6
10-5
10-4
10-3
10-2
10-1
0 0.8 1.6 2.4 3.2
VGS(V)
ID
(A)
typ maxmin
03ai89
10
102
103
104
10-1 1 10 102
VDS (V)
C
(pF)
Ciss
Coss
Crss
Philips Semiconductors PHP/PHB/PHD63NQ03LT
TrenchMOS™ logic level FET
Product data Rev. 01 — 14 June 2002 8 of 14
9397 750 09822 © Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Tj=25°C and 175 °C; VGS =0V I
D= 50 A; VDD =15V
Fig 12. Source (diode forward) current as a function of
source-drain (diode forward) voltage; typical
values.
Fig 13. Gate-source voltage as a function of gate
charge; typical values.
03ai88
0
20
40
60
80
0 0.4 0.8 1.2 1.6
VSD (V)
IS
(A)
Tj = 25 °C175 °C
VGS = 0 V
03ai90
0
2
4
6
8
10
0 5 10 15 20
QG (nC)
VGS
(V) ID = 50 A
Tj = 25 ˚ C
VDD = 15 V
Philips Semiconductors PHP/PHB/PHD63NQ03LT
TrenchMOS™ logic level FET
Product data Rev. 01 — 14 June 2002 9 of 14
9397 750 09822 © Koninklijke Philips Electronics N.V. 2002. All rights reserved.
6. Package outline
Fig 14. SOT78 (TO-220AB).
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC EIAJ
SOT78 SC-463-lead TO-220AB
D
D1
q
p
L
123
L1(1)
b1
ee
b
0 5 10 mm
scale
Plastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead TO-220AB SOT78
DIMENSIONS (mm are the original dimensions)
AE
A1
c
Note
1. Terminals in this zone are not tinned.
Q
L2
UNIT A1b1D1ep
mm 2.54
qQ
AbD
cL2
max.
3.0 3.8
3.6
15.0
13.5 3.30
2.79 3.0
2.7 2.6
2.2
0.7
0.4 15.8
15.2
0.9
0.7 1.3
1.0
4.5
4.1 1.39
1.27 6.4
5.9 10.3
9.7
L1(1)
EL
00-09-07
01-02-16
mounting
base
Philips Semiconductors PHP/PHB/PHD63NQ03LT
TrenchMOS™ logic level FET
Product data Rev. 01 — 14 June 2002 10 of 14
9397 750 09822 © Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Fig 15. SOT404 (D2-PAK)
UNIT A
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC EIAJ
mm
A1D1
D
max. EeL
pHDQc
2.54 2.60
2.20
15.80
14.80
2.90
2.10
11 1.60
1.20 10.30
9.70
4.50
4.10 1.40
1.27 0.85
0.60 0.64
0.46
b
DIMENSIONS (mm are the original dimensions)
SOT404
0 2.5 5 mm
scale
Plastic single-ended surface mounted package (Philips version of D2-PAK); 3 leads
(one lead cropped) SOT404
e e
E
b
D1
HD
D
Q
Lp
c
A1
A
13
2
mounting
base
99-06-25
01-02-12
Philips Semiconductors PHP/PHB/PHD63NQ03LT
TrenchMOS™ logic level FET
Product data Rev. 01 — 14 June 2002 11 of 14
9397 750 09822 © Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Fig 16. SOT428 (D-PAK)
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
SOT428 TO-252 SC-63 99-09-13
01-12-11
0 10 20 mm
scale
Plastic single-ended surface mounted package (Philips version of D-PAK); 3 leads
(one lead cropped) SOT428
E
b2E1
wAM
bc
b1
L1
L
13
2
D
D1
HE
L2
Note
1. Measured from heatsink back to lead.
e1
e
AA2
A
A1
y
seating plane
mounting
base
A1(1) D
bE1
EH
Ewy
max.
A2b2
b1cD1
min. ee
1L1
min. L2
L
A
UNIT
DIMENSIONS (mm are the original dimensions)
0.2 0.2
mm 2.38
2.22 0.65
0.45 0.93
0.73 0.89
0.71 1.1
0.9 5.46
5.26 0.4
0.2 6.22
5.98 4.81
4.45 2.285 4.57 10.4
9.6 0.5 0.9
0.5
6.73
6.47
4.0 2.95
2.55
Philips Semiconductors PHP/PHB/PHD63NQ03LT
TrenchMOS™ logic level FET
Product data Rev. 01 — 14 June 2002 12 of 14
9397 750 09822 © Koninklijke Philips Electronics N.V. 2002. All rights reserved.
7. Revision history
Table 5: Revision history
Rev Date CPCN Description
01 20020614 - Product data; initial version
9397 750 09822
Philips Semiconductors PHP/PHB/PHD63NQ03LT
TrenchMOS™ logic level FET
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data Rev. 01 — 14 June 2002 13 of 14
9397 750 09822
Philips Semiconductors PHP/PHB/PHD63NQ03LT
TrenchMOS™ logic level FET
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data Rev. 01 — 14 June 2002 13 of 14
Contact information
For additional information, please visit http://www.semiconductors.philips.com.
For sales office addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com.Fax: +31 40 27 24825
8. Data sheet status
[1] Please consult the most recently issued data sheet before initiating or completing a design.
[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.
9. Definitions
Short-form specification — The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.
Application information — Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.
10. Disclaimers
Life support — These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to
make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve
design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
licence or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.
11. Trademarks
TrenchMOS — is a trademark of Koninklijke Philips Electronics N.V.
Data sheet status[1] Product status[2] Definition
Objective data Development This datasheet contains data from theobjectivespecification forproduct development.Philips Semiconductors
reserves the right to change the specification in any manner without notice.
Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a
later date. Philips Semiconductors reserves the right to change the specification without notice, in order to
improve the design and supply the best possible product.
Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to
make changes at any time in order to improve the design, manufacturing and supply. Changes will be
communicated according to the Customer Product/Process Change Notification (CPCN) procedure
SNW-SQ-650A.
© Koninklijke Philips Electronics N.V. 2002.
Printed in The Netherlands
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner.
The information presented in this document does not form part of any quotation or
contract, is believed to be accurate and reliable and may be changed without notice. No
liability will be accepted by the publisher for any consequence of its use. Publication
thereof does not convey nor imply any license under patent- or other industrial or
intellectual property rights.
Date of release: 14 June 2002 Document order number: 9397 750 09822
Contents
Philips Semiconductors PHP/PHB/PHD63NQ03LT
TrenchMOS™ logic level FET
1 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.4 Quick reference data. . . . . . . . . . . . . . . . . . . . . 1
2 Pinning information. . . . . . . . . . . . . . . . . . . . . . 1
3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2
4 Thermal characteristics. . . . . . . . . . . . . . . . . . . 4
4.1 Transient thermal impedance . . . . . . . . . . . . . . 4
5 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 5
6 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9
7 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 12
8 Data sheet status. . . . . . . . . . . . . . . . . . . . . . . 13
9 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
10 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
11 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
