ICS954206B Advance Information Integrated Circuit Systems, Inc. Programmable Timing Control HubTM for Mobile P4TM Systems Recommended Application: CK410M Compliant Main Clock Output Features: * 2 - 0.7V current-mode differential CPU pairs * 4 - 0.7V current-mode differential PCI Express*pairs * 1 - 0.7V current-mode differential CPU/PCI Express selectable pair * 1 - 0.7V current-mode differential SATA pair * 1 - 0.7V current-mode differential LCDCLK/PCI Express selectable pair * 4 - PCI (33MHz) * 2 - PCICLK_F, (33MHz) free-running * 1 - USB, 48MHz * 1 - DOT, 96MHz, 0.7V current differential pair * 2 - REF, 14.318MHz VDDPCI GND PCICLK3 PCICLK4 PCICLK5 GND VDDPCI ITP_EN/PCICLK_F0 *SELPCIEX_LCDCLK#/PCICLK_F1 Vtt_PwrGd#/PD VDD48 FSLA/USB_48MHz GND DOTT_96MHz DOTC_96MHz FSLB/TEST_MODE LCDCLK_SS/PCIEX0T LCDCLK_SS/PCIEX0C PCIEXT1 PCIEXC1 VDDPCIEX PCIEXT2 PCIEXC2 PCIEXT3 PCIEXC3 SATACLKT SATACLKC VDDPCIEX 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 ICS954206B Pin Configuration 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 Key Specifications: * CPU outputs cycle-cycle jitter < 85ps * PCI Express outputs cycle-cycle jitter < 125ps * SATA outputs cycle-cycle jitter < 125ps * PCI outputs cycle-cycle jitter < 500ps * +/- 300ppm frequency accuracy on CPU, PCI Express and SATA clocks * +/- 100ppm frequency accuracy on USB clocks Features/Benefits: * Supports tight ppm accuracy clocks for Serial-ATA and PCI Express * Supports programmable spread percentage and frequency * Uses external 14.318MHz crystal, external crystal load caps are required for frequency tuning * Supports undriven differential CPU, PCI Express pair in PD for power management. * PEREQ# pins to support PCI Express and SATA power management. PCICLK2/REQ_SEL** PCI/SRC_STOP# CPU_STOP# REF1/FSLC/TEST_SEL REF0 GND X1 X2 VDDREF SDATA SCLK GND CPUCLKT0 CPUCLKC0 VDDCPU CPUCLKT1 CPUCLKC1 IREF GNDA VDDA CPUCLKT2_ITP/PCIEXT6 CPUCLKC2_ITP/PCIEXC6 VDDPCIEX PEREQ1#*/PCIEXT5 PEREQ2#*/PCIEXC5 PCIEXT4 PCIEXC4 GND 56-pin SSOP & TSSOP * Internal Pull-Up Resistor ** Internal Pull-Down Resistor Table 1: Frequency Selection Table FS LC B6b2 FS LB B6b1 FS LA B6b0 0 0 0 0 1 1 1 1 0940--06/23/05 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 CPU MHz 266.66 133.33 200.00 166.66 333.33 100.00 400.00 200.00 PCIEX MHz 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 PCI MHz 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 REF MHz 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 USB MHz 48.00 48.00 48.00 48.00 48.00 48.00 48.00 48.00 DOT MHz 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 Spread % 0.5% Down 0.5% Down 0.5% Down 0.5% Down 0.5% Down 0.5% Down 0.5% Down 0.5% Down *Other names and brands may be claimed as the property of others. ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals. ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners. ICS954206B Advance Information Integrated Circuit Systems, Inc. Pin Description PIN # PIN NAME TYPE DESCRIPTION PWR PWR OUT OUT OUT PWR PWR Power supply for PCI clocks, nominal 3.3V Ground pin. PCI clock output. PCI clock output. PCI clock output. Ground pin. Power supply for PCI clocks, nominal 3.3V Free running PCI clock not affected by PCI_STOP# through I2C . ITP_EN: latched input to select pin functionality 1 = CPU_2_ITP pair 0 = PCIEX_6 pair Latched select input for LCDCLK/PCIEX output 0 = LCDCLK, 1 = PCIEX / Free running 3.3V PCI clock output. Vtt_PwrGd# is an active low input used to determine when latched inputs are ready to be sampled. PD is an asynchronous active high input pin used to put the device into a low power state. The internal clocks, PLLs and the crystal oscillator are stopped. Power pin for the 48MHz output.3.3V 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values. / Fixed 48MHz USB clock output. 3.3V. Ground pin. True clock of differential pair for 96.00MHz DOT clock. Complement clock of differential pair for 96.00MHz DOT clock. 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values. TEST_MODE is a real time input to select between Hi-Z and REF/N divider mode while in test mode. Refer to Test Clarification Table. True clock of LCDCLK_SS output / True clock of PCI Express differential pair. Selected by SELPCIEX_LCDCLK# Complementary clock of LCDCLK_SS output / Complementary clock of PCI Express differential pair. Selected by SELPCIEX_LCDCLK# True clock of differential PCI_Express pair. Complement clock of differential PCI_Express pair. Power supply for PCI Express clocks, nominal 3.3V True clock of differential PCI_Express pair. Complement clock of differential PCI_Express pair. True clock of differential PCI_Express pair. Complement clock of differential PCI_Express pair. True clock of differential SATA pair. Complement clock of differential SATA pair. Power supply for PCI Express clocks, nominal 3.3V 1 2 3 4 5 6 7 VDDPCI GND PCICLK3 PCICLK4 PCICLK5 GND VDDPCI 8 ITP_EN/PCICLK_F0 I/O 9 *SELPCIEX_LCDCLK#/PCI CLK_F1 I/O 10 Vtt_PwrGd#/PD IN 11 VDD48 12 FSLA/USB_48MHz 13 14 15 GND DOTT_96MHz DOTC_96MHz 16 FSLB/TEST_MODE 17 LCDCLK_SS/PCIEX0T OUT 18 LCDCLK_SS/PCIEX0C OUT 19 20 21 22 23 24 25 26 27 28 PCIEXT1 PCIEXC1 VDDPCIEX PCIEXT2 PCIEXC2 PCIEXT3 PCIEXC3 SATACLKT SATACLKC VDDPCIEX OUT OUT PWR OUT OUT OUT OUT OUT OUT PWR PWR I/O PWR OUT OUT IN 0940--06/23/05 2 ICS954206B Advance Information Integrated Circuit Systems, Inc. Pin Description (Continued) PIN # PIN NAME TYPE 29 30 31 GND PCIEXC4 PCIEXT4 PWR OUT OUT 32 PEREQ2#*/PCIEXC5 I/O 33 PEREQ1#*/PCIEXT5 I/O 34 VDDPCIEX PWR 35 CPUCLKC2_ITP/PCIEXC6 OUT 36 CPUCLKT2_ITP/PCIEXT6 OUT 37 38 VDDA GNDA PWR PWR 39 IREF OUT 40 CPUCLKC1 OUT 41 CPUCLKT1 OUT 42 VDDCPU PWR 43 CPUCLKC0 OUT 44 CPUCLKT0 OUT 45 46 47 48 49 50 51 52 GND SCLK SDATA VDDREF X2 X1 GND REF0 PWR IN I/O PWR OUT IN PWR OUT 53 REF1/FSLC/TEST_SEL I/O 54 CPU_STOP# IN 55 PCI/SRC_STOP# IN 56 PCICLK2/REQ_SEL** I/O DESCRIPTION Ground pin. Complement clock of differential PCI_Express pair. True clock of differential PCI_Express pair. Real-time input pin that controls SATACLK and PCIEXCLK outputs that are selected through the I2c. 1 = disabled, 0 = enabled. / Complement clock of differential PCI Express output. Real-time input pin that controls SATACLK and PCIEXCLK outputs that are selected through the I2c. 1 = disabled, 0 = enabled. / True clock of differential PCI Express output. Power supply for PCI Express clocks, nominal 3.3V Complimentary clock of CPU_ITP/PCIEX differential pair CPU_ITP/PCIEX output. These are current mode outputs. External resistors are required for voltage bias. Selected by ITP_EN input. True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. / True clock of differential PCIEX pair 3.3V power for the PLL core. Ground pin for the PLL core. This pin establishes the reference current for the differential current-mode output pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. Complimentary clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. Supply for CPU clocks, 3.3V nominal Complimentary clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. Ground pin. Clock pin of SMBus circuitry, 5V tolerant. Data pin for SMBus circuitry, 5V tolerant. Ref, XTAL power supply, nominal 3.3V Crystal output, Nominally 14.318MHz Crystal input, Nominally 14.318MHz. Ground pin. 14.318 MHz reference clock. 14.318 MHz reference clock./ 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values. /TEST_Sel: 3-level latched input to enable test mode. Refer to Test Clarification Table Stops all CPUCLK, except those set to be free running clocks Stops all PCICLKs and SRCCLKs besides the free-running clocks at logic 0 level, when input low 3.3V PCI clock output / Latch select input pin. 0 = PCIEXCLK5 1 = PEREQ 0940--06/23/05 3 ICS954206B Advance Information Integrated Circuit Systems, Inc. General Description ICS954206B is a CK410M Compliant clock synthesizer. ICS954206B provides a single-chip solution for mobile systems built with Intel P4-M processors and Intel mobile chipsets. ICS954206B is driven with a 14.318MHz crystal and generates CPU outputs up to 400MHz. It provides the tight ppm accuracy required by Serial ATA and PCI Express. Block Diagram REF(1:0) USB_48MHz X1 X2 XTAL OSC. FIXED PLL DIVIDER DOT_96MHz PCICLK(5:2) PCICLK_F(1:0) PROG. SPREAD MAIN PLL PCI/SRC_STOP# CPU_STOP# FSL(C:A) ITP_EN TEST_MODE TEST_SEL VTT_PWRGD#/PD PEREQ#(2:1) SDATA SCLK SELPCIEX_LCDCLK# REQ_SEL PCIEX(5:1) PROG. DIVIDERS CPUCLK2/PCIEX6 CPUCLK(1:0) LCDCLK_SS/PCIEX0 CONTROL LOGIC SATACLK IREF 0940--06/23/05 4 ICS954206B Advance Information Integrated Circuit Systems, Inc. General SMBus serial interface information for the ICS954206B How to Write: How to Read: Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 (see Note 2) * ICS clock will acknowledge each byte one at a time * Controller (host) sends a Stop bit * * * * * * * * * * * * * * * * * * * * * * Controller (host) will send start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit Index Block Read Operation Index Block Write Operation Controller (Host) starT bit T Slave Address D2(H) WR WRite Controller (Host) T starT bit Slave Address D2(H) WR WRite ICS (Slave/Receiver) ICS (Slave/Receiver) ACK ACK Beginning Byte = N Beginning Byte = N ACK ACK RT Repeat starT Slave Address D3(H) RD ReaD Data Byte Count = X ACK Beginning Byte N ACK X Byte ACK Data Byte Count = X ACK Beginning Byte N Byte N + X - 1 ACK X Byte ACK P stoP bit Byte N + X - 1 N P 0940--06/23/05 5 Not acknowledge stoP bit ICS954206B Advance Information Integrated Circuit Systems, Inc. Table2: LCDCLK Spread and Frequency Selection Table Pin 17/18 Byte 6b7 Byte 6b6 Byte 6b5 Byte 6b4 Byte 6b3 0 0 0 0 0 MHz 96.00 0 0 0 0 1 96.00 0 0 0 1 0 96.00 0 0 0 1 1 96.00 0 0 1 0 0 96.00 0 0 1 0 1 96.00 0 0 1 1 0 96.00 0 0 1 1 1 96.00 0 1 0 0 0 96.00 0 1 0 0 1 96.00 0 1 0 1 0 96.00 0 1 0 1 1 96.00 0 1 1 0 0 96.00 0 1 1 0 1 96.00 0 1 1 1 0 96.00 0 1 1 1 1 96.00 1 0 0 0 0 100.00 1 0 0 0 1 100.00 1 0 0 1 0 100.00 1 0 0 1 1 100.00 1 0 1 0 0 100.00 1 0 1 0 1 100.00 1 0 1 1 0 100.00 1 0 1 1 1 100.00 1 1 0 0 0 100.00 1 1 0 0 1 100.00 1 1 0 1 0 100.00 1 1 0 1 1 100.00 1 1 1 0 0 100.00 1 1 1 0 1 100.00 1 1 1 1 1 1 1 1 0 1 100.00 100.00 0940--06/23/05 6 Spread % 0.8 Down 1 Down 1.25 Down 1.5 Down 1.75 Down 2 Down 2.5 Down 3 Down +/-0.3 Center +/-0.4 Center +/-0.5 Center +/-0.6 Center +/-0.8 Center +/-1.0 Center +/-1.25 Center +/-1.5 Center 0.8 Down 1 Down 1.25 Down 1.5 Down 1.75 Down 2 Down 2.5 Down 3 Down +/-0.3 Center +/-0.4 Center +/-0.5 Center +/-0.6 Center +/-0.8 Center +/-1.0 Center +/-1.25 Center +/-1.5 Center ICS954206B Advance Information Integrated Circuit Systems, Inc. Absolute Maximum Rating PARAMETER SYMBOL MIN VDD_A CONDITIONS - 3.3V Core Supply Voltage 3.3V Logic Input Supply Voltage Storage Temperature Ambient Operating Temp Case Temperature Tcase - Input ESD protection HBM ESD prot - TYP MAX UNITS VDD + 0.5V V Notes 1 VDD_In - GND - 0.5 V 1 Ts - -65 150 Tambient - 0 70 1 VDD + 0.5V 115 2000 C C 1 C 1 V 1 UNITS Notes 1 Guaranteed by design and characterization, not 100% tested in production. Electrical Characteristics - Input/Supply/Common Output Parameters PARAMETER SYMBOL CONDITIONS* Input High Voltage VIH 3.3 V +/-5% 2 VDD + 0.3 V 1 Input Low Voltage VIL 3.3 V +/-5% VSS - 0.3 0.8 V 1 Input High Current IIH VIN = VDD -5 5 uA 1 -5 uA 1 -200 uA 1 IIL1 Input Low Current IIL2 Low Threshold InputHigh Voltage Low Threshold InputLow Voltage VIN = 0 V; Inputs with no pull-up resistors VIN = 0 V; Inputs with pull-up resistors MIN TYP MAX VIH_FS 3.3 V +/-5% 0.7 VDD + 0.3 V 1 VIL_FS 3.3 V +/-5% VSS - 0.3 0.35 V 1 Operating Supply Current IDD3.3OP Full Active, CL = Full load; 350 mA 1 Operating Current IDD3.3OP all outputs driven 400 mA 1 all diff pairs driven 70 mA 1 Powerdown Current IDD3.3PD Input Frequency Fi Pin Inductance Lpin all differential pairs tri-stated 12 VDD = 3.3 V 14.31818 mA 1 MHz 2 1 7 nH CIN Logic Inputs 5 pF 1 COUT Output pin capacitance 6 pF 1 CINX 5 pF 1 1.8 ms 1 33 kHz 1 300 us 1 Tfall_PD X1 & X2 pins From VDD Power-Up or deassertion of PD to 1st clock Triangular Modulation CPU output enable after PD de-assertion PD fall time of 5 ns 1 Trise_PD PD rise time of 5 ns 1 5.5 V 1 0.4 V 1 mA 1 1000 ns 1 300 ns 1 Input Capacitance Clk Stabilization TSTAB Modulation Frequency Tdrive_PD SMBus Voltage VDD Low-level Output Voltage Current sinking at VOL = 0.4 V VOL 30 2.7 @ IPULLUP IPULLUP 4 SCLK/SDATA (Max VIL - 0.15) to TRI2C Clock/Data Rise Time (Min VIH + 0.15) SCLK/SDATA (Min VIH + 0.15) to T FI2C Clock/Data Fall Time (Max VIL - 0.15) *TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5% 1 Guaranteed by design and characterization, not 100% tested in production. 2 Input frequency should be measured at the REF pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL outputs. 0940--06/23/05 7 ICS954206B Advance Information Integrated Circuit Systems, Inc. Electrical Characteristics - CPU 0.7V Current Mode Differential Pair PARAMETER SYMBOL CONDITIONS* MIN Current Source Output Impedance Zo VO = Vx 3000 Voltage High VHigh Voltage Low VLow Statistical measurement on single ended signal 660 Max Voltage Vovs Min Voltage Vuds Crossing Voltage (abs) Vx(abs) Crossing Voltage (var) d-Vx Long Accuracy ppm Average period Absolute min period Tperiod Tabsmin Measurement on single ended signal using absolute value. -150 MAX UNITS 1 850 mV 1,3 150 mV 1,3 1150 mV 1 mV 1 550 mV 1 140 mV 1 -300 250 NOTES Variation of crossing over all edges see Tperiod min-max values -300 300 ppm 1,2 400MHz nominal 2.4993 2.5008 ns 2 400MHz spread 2.4993 2.5133 ns 2 333.33MHz nominal 2.9991 3.0009 ns 2 333.33MHz spread 2.9991 3.016 ns 2 266.66MHz nominal 3.7489 3.7511 ns 2 266.66MHz spread 3.7489 3.77 ns 2 200MHz nominal 4.9985 5.0015 ns 2 200MHz spread 4.9985 5.0266 ns 2 166.66MHz nominal 5.9982 6.0018 ns 2 166.66MHz spread 5.9982 6.0320 ns 2 133.33MHz nominal 7.4978 7.5023 ns 2 133.33MHz spread 7.4978 7.5400 ns 2 100.00MHz nominal 9.9970 10.0030 ns 2 10.0533 100.00MHz spread 9.9970 ns 2 400MHz nominal/spread 2.4143 ns 1,2 333.33MHz nominal/spread 2.9141 ns 1,2 266.66MHz nominal/spread 3.6639 ns 1,2 200MHz nominal/spread 4.8735 ns 1,2 166.66MHz nominal/spread 5.8732 ns 1,2 133.33MHz nominal/spread 7.3728 ns 1,2 100.00MHz nominal/spread 9.8720 ns 1,2 1 Rise Time tr VOL = 0.175V, VOH = 0.525V 175 700 ps Fall Time tf VOH = 0.525V VOL = 0.175V 175 700 ps 1 Rise Time Variation d-tr VOL = 0.175V, VOH = 0.525V 125 ps 1 Fall Time Variation d-tf 125 ps 1 Duty Cycle dt3 55 % 1 Skew tsk3 VOH = 0.525V VOL = 0.175V Measurement from differential wavefrom CPU(1:0), VT = 50% 100 ps 1 150 ps 1 125 ps 1 85 ps 1 45 CPU(1:0) to CPU2_ITP, tsk4 Skew VT = 50% Measurement from differential t Jitter, Cycle to cycle jcyc-cyc wavefrom (CPU2_ITP) Measurement from differential tjcyc-cyc Jitter, Cycle to cycle wavefrom, (CPU(1:0)) *TA = 0 - 70C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2, RP=49.9, REF = 475 1 TYP Guaranteed by design and characterization, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz 3 IREF = VDD/(3xRR). For RR = 475 (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50. 0940--06/23/05 8 ICS954206B Advance Information Integrated Circuit Systems, Inc. Electrical Characteristics - SRC/SATA/PCIEX 0.7V Current Mode Differential Pair PARAMETER SYMBOL CONDITIONS* MIN Current Source Output Impedance Zo VO = Vx 3000 Voltage High VHigh Voltage Low VLow Statistical measurement on single ended signal 660 Max Voltage Vovs Min Voltage Vuds Crossing Voltage (abs) Vx(abs) Crossing Voltage (var) d-Vx Long Accuracy ppm Measurement on single ended signal using absolute value. -150 MAX UNITS 1 850 mV 1,3 150 mV 1,3 1150 mV 1 mV 1 550 mV 1 140 mV 1 -300 250 Notes Variation of crossing over all edges see Tperiod min-max values -300 300 ppm 1,2 9.9970 10.0030 ns 2 10.0533 ns 2 ns 1,2 1 Average period Tperiod 100.00MHz nominal 100.00MHz spread 9.9970 Absolute min period Tabsmin 100.00MHz nominal/spread 9.8720 Rise Time tr VOL = 0.175V, VOH = 0.525V 175 700 ps Fall Time tf VOH = 0.525V VOL = 0.175V 175 700 ps 1 Rise Time Variation d-tr VOL = 0.175V, VOH = 0.525V 125 ps 1 125 ps 1 55 % 1 250 ps 1 125 ps 1 MAX UNITS NOTES 55 1 VOH = 0.525V VOL = 0.175V Measurement from differential dt3 Duty Cycle wavefrom tsk3 VT = 50% Skew Measurement from differential tjcyc-cyc Jitter, Cycle to cycle wavefrom *TA = 0 - 70C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2, RP=49.9, REF = 475 Fall Time Variation 1 TYP d-tf 45 Guaranteed by design and characterization, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz 3 IREF = VDD/(3xRR). For RR = 475 (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50. Electrical Characteristics - PCICLK/PCICLK_F SYMBOL RDSP CONDITIONS* VO = VDD*(0.5) MIN Output Impedance PARAMETER Output High Voltage VOH IOH = -1 mA 2.4 Output Low Voltage VOL IOL = 1 mA Output High Current IOH TYP 12 0.55 V OH @MIN = 1.0 V -33 VOH@MAX = 3.135 V VOL @ MIN = 1.95 V -33 30 V 1 V 1 mA 1 mA 1 mA 1 Output Low Current IOL 38 mA 1 Edge Rate tslewr/f Rising/Falling edge rate 1 4 V/ns 1 Rise Time tr VOL = 0.4 V, VOH = 2.4 V 0.5 2 ns 1 Fall Time tf VOH = 2.4 V, VOL = 0.4 V 0.5 2 ns 1 Duty Cycle dt1 VT = 1.5 V 45 55 % 1 Group Skew tskew VT = 1.5 V 250 ps 1 Jitter, Cycle to cycle tjcyc-cyc VT = 1.5 V 500 ps 1 VOL @ MAX = 0.4 V *TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, CL = 20 pF with Rs = 7 (unless otherwise specified) 1 Guaranteed by design and characterization, not 100% tested in production. 3 Spread Spectrum is off 0940--06/23/05 9 ICS954206B Advance Information Integrated Circuit Systems, Inc. Electrical Characteristics - 48MHz/USB48MHz/24_48MHz PARAMETER SYMBOL CONDITIONS* MIN MAX UNITS NOTES Long Accuracy ppm see Tperiod min-max values -100 100 ppm 1,2 Clock period Tperiod 48.00MHz output nominal 20.8313 20.8354 ns 2 Output Impedance RDSP VO = VDD*(0.5) 12 55 1 Output High Voltage VOH IOH = -1 mA 2.4 V 1 Output Low Voltage VOL IOL = 1 mA V 1 mA 1 Output High Current IOH TYP 0.55 V OH @MIN = 1.0 V -33 VOH@MAX = 3.135 V VOL @ MIN = 1.95 V -33 30 mA 1 mA 1 Output Low Current IOL 38 mA 1 Edge Rate tslewr/f Rising/Falling edge rate 1 4 V/ns 1 Edge Rate tslewr/f_USB USB48 Rising/Falling edge rate 1 2 V/ns 1 Rise Time tr VOL = 0.4 V, VOH = 2.4 V 0.5 2 ns 1 Fall Time tf VOH = 2.4 V, VOL = 0.4 V 0.5 2 ns 1 Rise Time tr_USB VOL = 0.4 V, VOH = 2.4 V 1 2 ns 1 Fall Time tf_USB VOH = 2.4 V, VOL = 0.4 V 1 2 ns 1 Duty Cycle dt1 VT = 1.5 V 45 55 % 1 Group Skew tskew VT = 1.5 V 250 ps 1 Jitter, Cycle to cycle tjcyc-cyc VT = 1.5 V 500 ps 1 UNITS Notes 1 VOL @ MAX = 0.4 V *TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, CL = 20 pF with Rs = 7 (Rs is used in USB48MHz test only) 1 Guaranteed by design and characterization, not 100% tested in production. Electrical Characteristics - DOT_96MHz 0.7V Current Mode Differential Pair PARAMETER SYMBOL CONDITIONS* MIN Current Source Output Impedance Zo VO = Vx 3000 Voltage High VHigh 850 mV 1,3 VLow Statistical measurement on single ended signal 660 Voltage Low -150 150 mV 1,3 Max Voltage Vovs 1150 mV 1 Min Voltage Vuds mV 1 Crossing Voltage (abs) Vx(abs) 550 mV 1 140 mV 1 1,2 Measurement on single ended signal using absolute value. MAX -300 250 Long Accuracy ppm Variation of crossing over all edges see Tperiod min-max values -100 100 ppm Average period Tperiod 96.00MHz nominal 10.4135 10.4198 ns 2 Absolute min period Tabsmin 96.00MHz nominal 10.1635 ns 1,2 Rise Time tr VOL = 0.175V, VOH = 0.525V 175 700 ps 1 Fall Time tf VOH = 0.525V VOL = 0.175V 175 700 ps 1 Rise Time Variation d-tr VOL = 0.175V, VOH = 0.525V 125 ps 1 125 ps 1 55 % 1 250 ps 1 Crossing Voltage (var) d-Vcross VOH = 0.525V VOL = 0.175V Measurement from differential dt3 Duty Cycle wavefrom Measurement from differential tjcyc-cyc Jitter, Cycle to cycle wavefrom *TA = 0 - 70C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2, RP=49.9, REF = 475 Fall Time Variation 1 TYP d-tf 45 Guaranteed by design and characterization, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz 3 IREF = VDD/(3xRR). For RR = 475 (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50. 0940--06/23/05 10 ICS954206B Advance Information Integrated Circuit Systems, Inc. Electrical Characteristics - REF-14.318MHz PARAMETER SYMBOL CONDITIONS MIN MAX UNITS Notes Long Accuracy ppm see Tperiod min-max values -300 300 ppm 1,2 Clock period Tperiod 14.318MHz output nominal 69.8270 69.8550 ns 2 Output High Voltage VOH IOH = -1 mA 2.4 V 1 Output Low Voltage VOL IOL = 1 mA 0.4 V 1 Output High Current IOH VOH @MIN = 1.0 V, VOH@MAX = 3.135 V -29 -23 mA 1 Output Low Current IOL 29 27 mA 1 Edge Rate tslewr/f Rising/Falling edge rate 1 4 V/ns 1 Rise Time tr1 VOL = 0.4 V, VOH = 2.4 V 1 2 ns 1 Fall Time tf1 VOH = 2.4 V, VOL = 0.4 V 1 2 ns 1 Skew tsk1 VT = 1.5 V 500 ps 1 Duty Cycle dt1 VT = 1.5 V 55 % 1 Jitter tjcyc-cyc VT = 1.5 V 1000 ps 1 VOL @MIN = 1.95 V, @MAX = 0.4 V VOL TYP 45 *TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, CL = 20 pF with Rs = 7 (Rs is used in USB48MHz test only) 1 Guaranteed by design and characterization, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz 0940--06/23/05 11 ICS954206B Advance Information Integrated Circuit Systems, Inc. I2C Table: Output Control Register Byte 0 Pin # Name Control Function Type 0 1 PWD Bit 7 - CPUCLK2_ITP/PCIEX6 Enable Output Enable RW Disable Enable 1 Bit 6 - PCIEX5 Enable Output Enable RW Disable Enable 1 Bit 5 - PCIEX4 Enable Output Enable RW Disable Enable 1 Bit 4 - SATACLK Enable Output Enable RW Disable Enable 1 Bit 3 - PCIEX3 Enable Output Enable RW Disable Enable 1 Bit 2 - PCIEX2 Enable Output Enable RW Disable Enable 1 Bit 1 Bit 0 - PCIEX1 Enable Output Enable RW Output Enable RW Enable Enable 1 LCDCLK/PCIEX0 Enable Disable Disable Type 0 1 PWD 0 1 I2C Table: Spread and Output Control Register Bit 7 - Test Clock Mode Entry Control Function Test Mode RW Disable Enable Bit 6 - DOT_96MHz Enable Output Enable RW Disable Enable 1 Bit 5 - USB_48MHz Enable Output Enable RW Disable Enable 1 Bit 4 - RW Disable Enable 1 Bit 3 Spread Control RW OFF ON 1 Bit 2 - RW RW Enable - Output Enable Output Enable Disable Bit 1 REF_0 Enable LCDCLK/PCIEX0 Spectrum Mode CPUCLK1 CPUCLK0 Output Enable - Disable Enable 1 1 Bit 0 - Spread Spectrum Mode Spread Control for PLL1 RW OFF ON 0 Type 0 1 PWD RW RW RW RW RW Disable Disable Disable Disable Hi-Z Enable Enable Enable Enable REF/N 1 1 1 1 0 RW Enable Disable 1 RW RW Disable Disable Enable Enable 1 1 Type 0 1 PWD RW Free Running Stoppable 0 RW Free Running Stoppable 0 RW Free Running Stoppable 0 RW Free Running Stoppable 0 RW Free Running Stoppable 0 RW Free Running Stoppable 1 Byte 1 Pin # Name I2C Table: Output Control Register Byte 2 Pin # Name 7 6 5 4 3 - Bit 2 - PCI_STOP Bit 1 Bit 0 - PCI_F0 Enable PCI_F1 Enable Bit Bit Bit Bit Bit PCICLK5 PCICLK4 PCICLK3 PCICLK2 Test Mode Selection Control Function Output Enable Output Enable Output Enable Output Enable Test Mode Selection Stop all PCI, PCIEX and SATA clocks Output Enable Output Enable I2C Table: Output Control Register Byte 3 Pin # Name Control Function Bit 7 - PCIEX6 Bit 6 - PCIEX5 Bit 5 - PCIEX4 Bit 4 - SATACLK Bit 3 - PCIEX3 Bit 2 - PCIEX2 Bit 1 - PCIEX1 RW Free Running Stoppable 1 Bit 0 - PCIEX0 RW Free Running Stoppable 1 Allow assertion of PCI_STOP# or setting of PCI_STOP control bit in SMBus register to stop PCIEX clocks 0940--06/23/05 12 ICS954206B Advance Information Integrated Circuit Systems, Inc. I2C Table:Output Control Register Bit 7 Bit 6 - REF_1 Enable 96MHz Control Function Output Enable Driven in PD Bit 5 - REF_0 STRENGTH Strength Programming RW 1X 2X 1 Bit 4 Bit 3 Bit 2 - PCI_F1 PCI_F0 CPUCLK2_ITP Allow assertion of PCI_STOP# or setting of RW RW RW Free Running Free Running Free Running Stoppable Stoppable Stoppable 1 1 1 Bit 1 - CPUCLK1 RW Free Running Stoppable 1 Bit 0 - CPUCLK0 RW Free Running Stoppable 1 Byte 4 Pin # Name Allow assertion of CPU_STOP# to stop CPUCLK outputs Type 0 1 PWD RW RW Disable Driven Enable Hi-Z 1 1 I2C Table:Output Control Register Byte 5 Pin # Bit 7 - Bit 6 - Bit 5 - Bit 4 - Bit 3 - Bit 2 - Bit 1 - Bit 0 - Name PCI_STOP Drive Mode CPUCLK2_ITP_STOP Drive Mode CPUCLK1_STOP Drive Mode CPUCLK0_STOP Drive Mode Control Function Driven in PCI_STOP# Driven in CPU_STOP# PCIEX (6:0) Drive Mode CPUCLK2_ITP_PD Drive Mode CPUCLK[1:0] PD Drive Mode Driven in Pow erdow n (PD) ITP_EN PCIEX/CPU_ITP select Type 0 1 PWD RW Driven Hi-Z 0 RW Driven Hi-Z 0 RW Driven Hi-Z 0 RW Driven Hi-Z 0 RW Driven Hi-Z 0 RW Driven Hi-Z 0 RW Driven Hi-Z 0 RW PCIEX CPU_ITP latch Type 0 1 PWD RW 96Mhz 100Mhz 0 I2C Table: Output Control Register Byte 6 Pin # Name SS4 - Bit 7 Control Function LCDCLK Spread Prog Bit 4 Bit 6 - SS3 LCDCLK Spread Prog Bit 3 Bit 5 - SS2 LCDCLK Spread Prog Bit 2 RW RW 1 0 See Table 2: LCDCLK Freq Sel FSLC LCDCLK Spread Prog Bit 1 LCDCLK Spread Prog Bit 0 Freq Select Bit 2 RW FSLB Freq Select Bit 1 RW FSLA Freq Select Bit 0 RW Control Function Type 0 1 PWD R R R R R R R R - - x x x x 0 0 0 1 Bit 4 - SS1 Bit 3 - SS0 Bit 2 - Bit 1 - Bit 0 - RW 0 RW 0 See Table 1: PLL1 Frequency Selection Table Latched Latched Latched I2C Table: Vendor & Revision ID Register Byte 7 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 Pin # - Name RID3 RID2 RID1 RID0 VID3 VID2 VID1 VID0 REVISION ID VENDOR ID 0940--06/23/05 13 ICS954206B Advance Information Integrated Circuit Systems, Inc. I2C Table: Byte Count Register Pin # Byte 8 Bit Bit Bit Bit Bit Bit Bit Bit - 7 6 5 4 3 2 1 0 Control Function Type Byte Count Programming b(7:0) RW RW RW RW RW RW RW RW Name BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0 0 1 Writing to this register will configure how many bytes will be read back, default is 0F = 15 bytes. PWD 0 0 0 0 1 1 1 1 I2C Table: Watchdog Timer Register Byte 9 Bit 7 Pin # - Name WDH_EN Bit 6 - WDS_EN Bit 5 Bit 4 - WD Hard Status WD Soft Status Bit 3 - WDTCtrl Bit 2 Bit 1 Bit 0 - WD2 WD1 WD0 Control Function Watchdog Hard Alarm Enable Watchdog Soft Alarm Enable WD Hard Alarm Status WD Soft Alarm Status Watch Dog Time base Control WD Timer Bit 2 WD Timer Bit 1 WD Timer Bit 0 Type 0 1 PWD RW Disable Enable 0 RW Disable Enable 0 R R Normal Normal Alarm Alarm X X RW 290ms Base 1160ms Base 0 RW RW RW These bits represent X*290ms (or 1.16S) the watchdog timer waits before it goes to alarm mode. Default is 7 X 290ms = 2s. 1 1 1 I2C Table: VCO Control Select Bit & WD Timer Control Register Byte 10 Pin # Name Control Function PLLM/N Programming Enable Type 0 1 PWD RW Disable Enable 0 Bit 7 - M/N_EN Bit 6 - LCDCLK/PCIEX0 SEL SELPCIEX0/LCDCLK# RW LCDCLK PCIEX0 latch Bit 5 - REQ_SEL REQ_SEL RW PCIEX5 PEREQ latch Bit 4 - LCDCLK/PCIEX0 Driven in PD RW Driven Hi-Z 0 RW Latch Inputs/Byte6[2:0] B10b(2:0) Bit 3 - WD Safe Freq Source Bit 2 - WD SFC Bit 1 - WD SFB Bit 0 - WD SFA WD Safe Freq Source Watch Dog Safe Freq Programming bits RW RW Writing to these bit will configure the safe frequency as Byte0 bit (4:0). RW 0 0 0 0 I2C Table: VCO Frequency Control Register Bit 7 - N Div8 Control Function N Divider Prog bit 8 Bit 6 - N Div 9 N Divider Prog bit 9 Byte 11 Pin # Name Type 0 1 RW PWD X RW X The decimal representation of M and N Divier in Byte 11 and 12 will configure the VCO frequency. Default at power up = latch-in or Byte 0 Rom table. VCO Frequency = 14.318 x [NDiv(9:0)+8] / [MDiv(5:0)+2] Bit 5 - M Div5 Bit 4 - M Div4 Bit 3 - M Div3 Bit 2 - M Div2 Bit 1 - M Div1 RW X Bit 0 - M Div0 RW X RW RW M Divider Programming bits 0940--06/23/05 14 RW RW X X X X ICS954206B Advance Information Integrated Circuit Systems, Inc. I2C Table: VCO Frequency Control Register Byte 12 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 Pin # - Name N Div7 N Div6 N Div5 N Div4 N Div3 N Div2 N Div1 Control Function N Divider Programming b(8:0) N Div0 Type RW RW RW RW RW RW RW 0 1 The decimal representation of M and N Divier in Byte 11 and 12 will configure the VCO frequency. Default at power up = latch-in or Byte 0 Rom table. VCO Frequency = 14.318 x [NDiv(9:0)+8] / [MDiv(5:0)+2] RW PWD X X X X X X X X I2C Table: Spread Spectrum Control Register Byte 13 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 Pin # - Name SSP7 SSP6 SSP5 SSP4 SSP3 SSP2 SSP1 SSP0 Control Function Type Spread Spectrum Programming b(7:0) RW RW RW RW RW RW RW RW 0 1 These Spread Spectrum bits in Byte 13 and 14 will program the spread pecentage. It is recommended to use ICS Spread % table for spread programming. PWD X X X X X X X X I2C Table: Spread Spectrum Control Register Byte 14 Pin # Name Control Function Reserved Type 0 1 PWD R - - 0 Bit 7 - Reserved Bit 6 - SSP14 Bit 5 - SSP13 Bit 4 - SSP12 Bit 3 - SSP11 Bit 2 - SSP10 RW Bit 1 - SSP9 RW X Bit 0 - SSP8 RW X RW RW Spread Spectrum Programming b(14:8) RW RW X These Spread Spectrum bits in Byte 13 and 14 will program the spread pecentage. It is recommended to use ICS Spread % table for spread programming. X X X X I2C Table: Output Divider Control Register Pin # Byte 15 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 - Name PCIEX Div3 PCIEX Div2 PCIEX Div1 PCIEX Div0 CPU Div3 CPU Div2 CPU Div1 CPU Div0 Control Function PCIEX Divider Ratio Programming Bits CPUDivider Ratio Programming Bits 0940--06/23/05 15 Type RW RW RW RW RW RW RW RW 0 1 0000:/2 0100:/4 1000:/8 1100:/16 0001:/3 0101:/6 1001:/12 1101:/24 0010:/5 0110:/10 1010:/20 1110:/40 0011:/15 0111:/30 1011:/60 1111:/120 0000:/2 0100:/4 1000:/8 1100:/16 0001:/3 0101:/6 1001:/12 1101:/24 0010:/5 0110:/10 1010:/20 1110:/40 0011:/15 0111:/30 1011:/60 1111:/120 PWD X X X X X X X X ICS954206B Advance Information Integrated Circuit Systems, Inc. I2C Table: PEREQ# Control Register Control Byte 16 Pin # Name Function Type 0 1 PWD Bit 7 - Reserved Reserved RW - - 0 Bit 6 - SATACLK is controlled RW Not Controlled Controlled 1 Bit 5 - PCIEX3 is controlled RW Not Controlled Controlled 0 Bit 4 - PEREQ2# controls selected outputs. Outputs controlled by this pin will be Hi-Z when PEREQ2# is high. PCIEX1 is controlled RW Not Controlled Controlled 0 Bit 3 - Reserved Reserved RW - - 0 Bit 2 - PCIEX4 is controlled RW Not Controlled Controlled 1 Bit 1 - PCIEX2 is controlled RW Not Controlled Controlled 0 Bit 0 - PEREQ1# controls selected outputs. Outputs controlled by this pin will be Hi-Z when PEREQ1# is high. PCIEX0 is controlled RW Not Controlled Controlled 0 Type 0 1 PWD I2C Table: PLL 2 VCO Frequency Control Register Byte 17 Pin # Name Control Function N Divider Prog bit 8 N Divider Prog bit 9 Bit 7 Bit 6 - N Div8 N Div9 Bit 5 - M Div5 Bit 4 - M Div4 Bit 3 - M Div3 Bit 2 - M Div2 Bit 1 - M Div1 RW X Bit 0 - M Div0 RW X RW RW RW RW M Divider Programming bits RW RW X X The decimal representation of M and N Divier in Byte 17 and 18 will configure the VCO frequency. Default at power up = Byte 0 Rom table. VCO Frequency = 14.318 x [NDiv(9:0)+8] / [MDiv(5:0)+2] X X X X I2C Table: PLL 2 VCO Frequency Control Register Byte 18 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 Pin # - Name N Div7 N Div6 N Div5 N Div4 N Div3 N Div2 N Div1 N Div0 Control Function Type N Divider Programming b(8:0) RW RW RW RW RW RW RW RW Control Function Type 0 1 The decimal representation of M and N Divier in Byte 17 and 18 will configure the VCO frequency. Default at power up = Byte 0 Rom table. VCO Frequency = 14.318 x [NDiv(9:0)+8] / [MDiv(5:0)+2] PWD X X X X X X X X I2C Table: PLL 2 Spread Spectrum Control Register Byte 19 Pin # Name Bit 7 - SSP7 RW Bit Bit Bit Bit 6 5 4 3 - SSP6 SSP5 SSP4 SSP3 RW RW RW RW Bit 2 Bit 1 Bit 0 - SSP2 SSP1 SSP0 Spread Spectrum Programming b(7:0) RW RW RW 0940--06/23/05 16 0 1 PWD X These Spread Spectrum bits in Byte 19 and 20 will program the spread pecentage. It is recommended to use ICS Spread % table for spread programming. X X X X X X X ICS954206B Advance Information Integrated Circuit Systems, Inc. I2C Table: PLL2 Spread Spectrum Control Register Byte 20 Pin # Control Function Reserved Name Type 0 1 R - - Bit 7 - Reserved Bit 6 Bit 5 Bit 4 - SSP14 SSP13 SSP12 Bit 3 - SSP11 Bit 2 - SSP10 Bit 1 - SSP9 RW Bit 0 - SSP8 RW RW RW RW Spread Spectrum Programming b(14:8) RW RW PWD 0 These Spread Spectrum bits in Byte 19 and 20 will program the spread pecentage. It is recommended to use ICS Spread % table for spread programming. HW SW T_SEL T_MODE HW PIN 0 1 1 1 HW PIN X 0 0 1 TEST ENTRY BIT W1b7 0 X X X 1 1 X 1 REF/N 0 X 1 0 HI-Z 0 X 1 1 REF/N FSLC/TES FSLB/TES Power-up w/ TEST_SEL = 1 to enter test mode Cycle power to disable test mode FSLC./TEST_SEL -->3-level latched input If power-up w/ V>2.0V (-0.3V) then use TEST_SEL If power-up w/ V<2.0V (-0.3V) then use FSLC FSLB/TEST_MODE -->low Vth input TEST_MODE is a If TEST_SEL HW pin is 0 during power-up, test mode can be invoked through W1b7. If test mode is invoked by W1b7, only W2b3 is used to select HI-Z or REF/N FSLB/TEST_Mode pin is not used. Cycle power to disable test mode, one shot control W1b7: 1= ENTER TEST MODE, Default = 0 (NORMAL OPERATION) W2b3: 1= REF/N, Default = 0 (HI-Z) 0940--06/23/05 17 X X X X Test Clarification Table Comments X X X REF/N or HI-Z W2b3 OUTPUT X NORMAL 0 HI-Z 1 REF/N 0 REF/N ICS954206B Advance Information Integrated Circuit Systems, Inc. c N L E1 INDEX AREA E 1 2 a D A A2 A1 56-Lead 6.10 mm. Body, 0.50 mm. Pitch TSSOP (240 mil) (20 mil) In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A -1.20 -.047 A1 0.05 0.15 .002 .006 A2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 D SEE VARIATIONS SEE VARIATIONS E 8.10 BASIC 0.319 BASIC E1 6.00 6.20 .236 .244 e 0.50 BASIC 0.020 BASIC L 0.45 0.75 .018 .030 N SEE VARIATIONS SEE VARIATIONS 0 8 0 8 aaa -0.10 -.004 -Ce SEATING PLANE b VARIATIONS N aaa C 56 D mm. MIN MAX 13.90 14.10 Reference Doc.: JEDEC Publication 95, M O-153 10-0039 Ordering Information ICS954206BGLFT Example: ICS XXXX B G LF T Designation for tape and reel packaging RoHS Compliant (Optional) Package Type G = TSSOP Revision Designator Device Type (consists of 3 to 7 digit numbers) 0940--06/23/05 Prefix ICS, AV = Standard Device 18 D (inch) MIN .547 MAX .555 ICS954206B Advance Information Integrated Circuit Systems, Inc. 56-Lead, 300 mil Body, 25 mil, SSOP SYMBOL A A1 b c D E E1 e h L N In Millimeters COMMON DIMENSIONS MIN MAX 2.41 2.80 0.20 0.40 0.20 0.34 0.13 0.25 SEE VARIATIONS 10.03 10.68 7.40 7.60 0.635 BASIC 0.38 0.64 0.50 1.02 SEE VARIATIONS 0 8 In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0 8 VARIATIONS N 56 D mm. MIN 18.31 D (inch) MAX 18.55 Reference Doc.: JEDEC Publication 95, MO-118 10-0034 Ordering Information ICS954206BFLFT Example: ICS XXXX B F LF T Designation for tape and reel packaging RoHS Compliant (Optional) Package Type F = SSOP Revision Designator Device Type (consists of 3 to 7 digit numbers) 0940--06/23/05 Prefix ICS, AV = Standard Device 19 MIN .720 MAX .730 ICS954206B Advance Information Integrated Circuit Systems, Inc. Revision History Rev. N/A 0.1 0.2 Issue Date 12/9/2004 6/22/2005 6/23/2005 Description Added SSOP ordering information Updated Ordering Information. Updated Test Clarification Table 0940--06/23/05 20 Page # 19 18-19 17