NP8P128A13B1760E - Micron Technology, Inc.

Products and specifications discussed herein are subject to change by Micron without notice.

128Mb: P8P Parallel PCM

Features

PDF: 09005aef8447d46d/Source: 09005aef845b5c96 Micron Technology, Inc., reserves the right to change products or specifica tions without notice.

P8P Parallel Phase Change

Memory (PCM)

Features

•High-performance READ

–115ns initial READ access

–135ns initial READ access

–25ns, 8-word asynchronous-page READ

•Architecture

–Asymmetrically blocked architecture

–Four 32KB parameter blocks with top or bottom

configuration

–128KB main blocks

–Serial peripheral interface (SPI) to en able lower

pin count on-board programming

• Phase change memory (PCM)

–Chalcogenide phase change storage element

–Bit-alterable WRITE operation

•Voltage and power

–VCC (core) voltage: 2.7–3.6V

–VCCQ (I/O) voltage: 1.7–3.6V

–Standby current: 80µA (TYP)

• Quality and reliability

–More than 1,000,000 WRITE cycles

–90nm PCM technology

•Temperature

–Commercial: 0°C to +70°C (115ns initial READ

access)

–Industrial: –40°C to +85°C (135ns initial READ

access)

• Simpli fied software management

–No block erase or cleanup required

–Bit twiddle in either direction (1:0, 0:1)

–35µs (TYP) PROGRAM SUSPEND

–35µs (TYP) ERASE SUSPEND

–Flash data integrator optimized

–Scalable command set and extended command set

compatible

–Common Flash interface capable

•Density and packaging

–128Mb density

–56-lead TSOP package

–64-ball easy BGA package

•Security

–One-time programmable registers

64 unique factory device identifier bits

2112 user-programmable OTP bits

–Selectable OTP space in main array

–Three adjacent main blocks available for boot code

or other secure information

–Absolute WRITE protection: VPP = VSS

–Power transition ERASE/PROGRAM lockout

–Individual zero-latency block locking

–Individual block l oc k-d own

PDF: 09005aef8447d46d/Source: 09005aef845b5c96 Micron Technology, Inc., reserves the right to change products or specifica tions without notice.

128Mb: P8P Parallel PCM

Table of Contents

Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Product Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Memory Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

TSOP Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

64-Ball Easy BGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Pinouts and Ballouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Signal Names and Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

READ Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

WRITE Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

OUTPUT DISABLE Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

STANDBY Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

RESET Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Command Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Device Command Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Device Command Bus Cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

READ Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

READ ARRAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

READ IDENTIFIER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

READ QUERY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

PROGRAM Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

WORD PROGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

BIT-ALTERABLE WORD WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

BUFFERED PROGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

BIT-ALTERABLE BUFFER WRITE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

BIT-ALTERABLE BUFFER PROGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

PROGRAM SUSPEND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

PROGRAM RESUME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

PROGRAM PROTECTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

ERASE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

BLOCK ERASE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

ERASE SUSPEND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

ERASE RESUME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Security Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Block Locking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Zero Latency Block Locking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Lock Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Unlock Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Lock Down Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

WP# Lock Down Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Block Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Locking Operations During ERASE SUSPEND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Permanent OTP Block Locking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

WP# Lock Down Control for Selectable OTP Lock Blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Selectable OTP Locking Implementation Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Read Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

CLEAR STATUS REGISTER Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

System Protection Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

PDF: 09005aef8447d46d/Source: 09005aef845b5c96 Micron Technology, Inc., reserves the right to change products or specifica tions without notice.

128Mb: P8P Parallel PCM

Table of Contents

Read Protection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Program Protection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Lock Protection Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

OTP Protection Register Addressing Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Serial Peripheral Interface (SPI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

SPI Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

SPI Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

SPI Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

SPI Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

WRITE ENABLE (WREN). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

WRITE DISABLE (WRDI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

READ IDENTIFICATION (RDID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

WIP Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

WEL Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

BP3, BP2, BP1, BP0 Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

Top/Bottom Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

SRWD Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

WRITE STATUS REGISTER (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Read Data Bytes (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

Read Data Bytes at Higher Speed (FAST_READ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

PAGE PROGRAM (PP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

SECTOR ERASE (SE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

Power and Reset Specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

Power-Up and Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

Reset Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

Power Supply Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

Maximum Ratings and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Endurance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

DC Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

DC Voltage Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

AC Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

AC Read Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

AC Write Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

SPI AC Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

Program and Erase Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

Supplemental Reference Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

Flowcharts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

Write State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74

Common Flash Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

Query Structure Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78

CFI Query Identification String. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78

Extended Query Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82

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128Mb: P8P Parallel PCM

List of Figur es

List of Figures

Figure 1: 56-Lead TSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Figure 2: 64-Ball Easy BGA Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Figure 3: 56-Lead TSOP Pinout (128Mb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Figure 4: 64-Ball Easy BGA Ballout (128Mb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Figure 5: Example VPP Power Supply Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Figure 6: Block Locking State Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Figure 7: Selectable OTP Locking Illustration (Bottom Parameter Device Example). . . . . . . . . . . . . . . . . . . . . .33

Figure 8: Protection Register Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Figure 9: WRITE ENABLE (WREN) Instruction Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

Figure 10: WRITE DISABLE (WRDI) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

Figure 11: READ IDENTIFICATION (RDID) Instruction Sequence and Data-Out Sequence. . . . . . . . . . . . . . . .41

Figure 12: READ STATUS REGISTER (RDSR) Instruction Sequence and Data-Out Sequence. . . . . . . . . . . . . . .43

Figure 13: WRITE STATUS REGISTER (WRSR) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

Figure 14: Read Data Bytes (READ) Instruction Sequ ence and Data -Out Sequence . . . . . . . . . . . . . . . . . . . . . . .45

Figure 15: FAST_READ Instruction Sequence and Data-Out Seque n ce . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

Figure 16: PAGE PROGRAM (PP) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

Figure 17: SECTOR ERASE (SE) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

Figure 18: Reset Operation Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

Figure 19: AC Input/Output Reference Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

Figure 20: Transient Equivalent Testing Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

Figure 21: Asynchronous Single-W ord Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

Figure 22: Asynchronous Page Mode Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

Figure 23: Write-to-Write Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

Figure 24: Asynchronous Read to Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

Figure 25: Write to Asynchronous Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

Figure 26: Serial Input Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

Figure 27: Write Protect Setup and Hold Timing during WRSR when SRWD = 1 . . . . . . . . . . . . . . . . . . . . . . . . . .58

Figure 28: Hold Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

Figure 29: Output Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

Figure 30: WOR D PROGR AM or BIT -ALT ERA BL E WORD WRITE Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

Figure 31: Full WRITE STATUS CHECK Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

Figure 32: WRITE SUSPEND/RESUME Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

Figure 33: BUFFER PROGRAM or Bit-Alterable BUFFER WRITE Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

Figure 34: BLOCK ERASE Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

Figure 35: BLOCK ERASE FULL ERASE STATUS CHECK Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

Figure 36: ERASE SUSPEND/RESUME Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

Figure 37: LOCKING OPERATIONS Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

Figure 38: PROGRAM PROTECTION REGISTER Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

Figure 39: FULL STATUS CHECK Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

Figure 40: Write State Machine — Next State Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74

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128Mb: P8P Parallel PCM

List of Tables

Table 1: Top Parameter Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Table 2: Bottom Parameter Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Table 3: TSOP Package Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Table 4: Easy BGA Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Table 5: Ball/Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Table 6: Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Table 7: Command Codes and Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Table 8: Command Sequences in x16 Bus Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Table 9: Read Identifier Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Table 10: Device Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Table 11: Buffered Programming and Bit-Alterable Buffer Write Timing Requirements. . . . . . . . . . . . . . . . . . .25

Table 12: Bit Alterability vs. Flash Bit-Masking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Table 13: Block Locking Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Table 14: Block Locking State Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Table 15: Selectable OTP Block Locking Feature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Table 16: Selectable OTP Block Locking Programming of PR-LOCK0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Table 17: Status Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Table 18: Protection Register Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Table 19: 2K OTP Space Addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Table 20: Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Table 21: Instruction Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Table 22: Status Register Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

Table 23: Protected Area Sizes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

Table 24: Power and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

Table 25: Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Table 26: Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Table 27: Endurance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

Table 28: DC Current Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

Table 29: DC Voltage Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

Table 30: Test Configuration Component Value for Worst-Case Speed Conditions. . . . . . . . . . . . . . . . . . . . . . .53

Table 31: Capacitance: TA = 25°C, f = 1 MHz1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

Table 32: AC Read Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

Table 33: AC Write Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

Table 34: SPI AC Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

Table 35: Program and Erase Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

Table 36: Active Line Item Order ing Tab le (0°C to 70°C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

Table 37: Active Line Item Ordering Table (–40°C to 85°C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

Table 38: WORD PROGRAM or BIT-ALTERABLE WORD WRITE Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

Table 39: Full WRITE STATUS CHECK Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

Table 40: WRITE SUSPEND/RESUME Procedure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

Table 41: BUFFER PROGRAM OR BIT-ALTERABLE BUFFER WRITE Procedure. . . . . . . . . . . . . . . . . . . . . . . . . .66

Table 42: BLOCK ERASE Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

Table 43: BLOCK ERASE FULL ERASE STATUS CHECK Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

Table 44: ERASE SUSPEND/RESUME Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

Table 45: LOCKING OPERATIONS Procedure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

Table 46: PROGRAM PROTECTION REGISTER Procedure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

Table 47: FULL STATUS CHECK Procedure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

Table 48: Summary of Query Structure Output as a Function of Device and Model . . . . . . . . . . . . . . . . . . . . . .77

Table 49: Example of Query Structure Output of x16 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78

Table 50: Query Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78

Table 51: Block Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

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128Mb: P8P Parallel PCM

List of Tables

Table 52: CFI Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

Table 53: System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

Table 54: Device Geometry Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

Table 55: Bit Field Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81

Table 56: Hex Code and Values for Device Geometry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81

Table 57: Primary Vendor-Specific Extended Query . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82

Table 58: Protection Register Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82

Table 59: Read Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83

Table 60: Partition and Erase Block Region Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83

Table 61: Hex Code and Values for Partition and Erase Block Regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85

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128Mb: P8P Parallel PCM

Functional Description

P8P parallel phase change memory (PCM) is nonvolatile memory that stores informa-

tion through a reversible structural phase change in a chalcogenide material. The mate-

rial exhibits a change in material proper ties, both electrical and optical, when changed

from the amorphous (disordered) to the polycrystalline (regularly ordered) state. In the

case of PCM, information is stored via the change in resistance that the chalcogenide

material experiences when undergoing a phase change. The material also changes

optical properties after experiencing a phase change, a characteristic that has been

successfully mastered for use in current rewritable optical storage devices, such as

rewritable CDs and DVDs.

The P8P parallel PCM storage element consists of a thin film of chalcogenide contacted

by a resistive heating element. In PCM, the phase change is induced in the memory cell

b y highly localized Joule heating caused by an induced current at the material junction.

During a WRITE operation, a small volume of the chalcogenide material is made to

change phase. The phase change is a reversible process and is modulated by the magni-

tude of injected current, the applied voltage, and the duration of the heating pulse.

Unlike other proposed alternative memories, P8P parallel PCM technology uses a

conventional CMOS process with the addition of a few additional layers to form the

memory storage element. Overall, the basic memory manufacturing process used to

make PCM is less complex than that of NAND, NOR or DRAM.

P8P parallel PCM combines the benefits of traditional floating gate Flash, both NOR-

type and NAND-type, with some of the key attributes of RAM and EEPROM. Like NOR

Flash and RAM technology, PCM offers fast random access times . Like NAND flash, PCM

has the ability to write moderately fast, and like RAM and EEPROM, PCM supports bit

alterable WRITEs (over write). Unlike Flash, no separate erase step is required to change

information from 0 to 1 and 1 to 0. Unlike RAM, however, the technology is nonvolatile

with data retention compared with NOR Flash.

Product Featur esP8P parallel PCM devices provide the convenience and ease of NOR flash emulation

while providing a set of super set features that exploit the inherent capabilities of PCM

technology. The device emulates most of the features of Micron embedded memory

(P33). This is intended to ease the evaluation and design of P8P parallel PCM into

existing har dwar e and softwar e dev elopment pl atforms . This basi c featur es set i s supple-

mented by the super set features, which are intended to enable the designer to exploit

the inherent capabilities of phase change memory technology and to enable the even-

tual simplification of hardware and software in the design.

The P8P parallel PCM pr oduct family supports 128Mb density and are available in 64-

ball easy BGA and 56-lead TSOP packages. These are the same pinouts and packages as

the existing P33 NOR Flash devices. Designed for low -oltage systems, P8P parallel PCM

supports READ, WRITE, and ERASE operations at a core supply of 2.7V VCC. P8P parallel

PCM offers additional power savings through standby mode, which is initiated when the

system deselects the device by driving CE inactive.

P8P parallel PCM provides a set of commands that are compatible with industry-stan-

dard command sequences used by NOR-type Flash. An internal write state machine

(WSM) automatically executes the algorithms and timings necessary for BLOCK ERASE

and WRITE. Each emulated BLOCK ERASE operation results in the contents of the

addre ssed block being written to all 1s . Data can be pr ogramme d in wor d or buffer i ncr e-

ments. Erase suspend enables system software to pause an ERASE command so it can

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128Mb: P8P Parallel PCM

Memory Maps

read or program data in another block. P ROGRAM SUSPEND enables system softwar e to

pause programming so it can read from other locations within the device. The status

A 64-byte, 32 word write buffer is also included to enable optimum write performance.

Using th e w rite buffer, data is overwritten or programmed in buffer increments. This

feature improves system program performance more than 20 times over independent

byte writes.

Similar to floating gate Flash, a command user interface (CUI) serves as the interface

between the system processor and internal operation of the device. A valid command

sequence written to the CUI initiates device automation. In addition to the CUI, a Flash-

compatible common Flash interface (CFI) permits software algorithms to be used for

entire families of devices. This enables device-independent, JEDEC ID-independent,

and forward- and backward -compatible software support for the specified Flash device

families.

The serial peripheral interface (SPI) enables in-system programming through minimal

pin count interface. This interface is provided in addition to a traditional parallel system

interface. This featur e has been added to facilitate the on-board, in-system program-

ming of code into the P8P parallel PCM device afte r it has been soldered to a circuit

board. Preprogramming code prior to high temperatur e board attach is not recom-

mended with a P8P parallel PCM device . Although device r eliabil ity across the oper ating

temperature range is typically superior to that of floating gate Flash, the P8P parallel

PCM device may be subject to thermally-activated disturbs at higher temperatures;

however, no permanent device damage occurs eith er du ring leaded or lead -free board

attach.

P8P parallel PCM block locking enables zero-latency block locking/unlocking and

permanent locking. Permanent block locking provides enhanced security for boot code .

The combination of these two locking features provides complete locking solution for

code and data.

PCM technology also supports the ability to change each memory bit independently

from 0 to 1 or 1 to 0 without an intervening BLOCK ERASE operation. Bi t alterability

enables software to write to the nonvolatile memory in a similar manner as writing to

RAM or EEPROM without the overhead of erasing blocks prior to write. Bit Alterable

writes use similar command seq u ences as word programming and Buffer Programming.

Memory Maps

Table 1: Top Parameter Memory Map

Programming Region Number Size (KW) Block 128Mb

7 16 130 7FC000-7FFFFF

16 129 7F8000-7FBFFF

16 128 7F4000-7F7FFF

16 127 7F0000-7F3FFF

64 126 7E0000-7EFFFF

…

64 112 700000-70FFFF

6 64 111 6F0000-6FFFFF

…

64 96 600000-60FFFF

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128Mb: P8P Parallel PCM

Memory Maps

5 64 95 5F0000-5FFFFF

…

64 80 500000-50FFFF

4 64 79 4F0000-4FFFFF

…

64 64 400000-40FFFF

3 64 63 3F0000-3FFFFF

…

64 48 300000-30FFFF

2 64 47 2F0000-2FFFFF

…

64 32 200000-20FFFF

1 64 31 1F0000-1FFFFF

…

64 16 100000-10FFFF

0 64 15 0F0000-0FFFFF

…

64 0 000000-00FFFF

Table 2: Bottom Parameter Memory Map

Programming Region Number Size (KW) Block 128Mb

7 64 130 7F0000-7FFFFF

…

64 115 700000-70FFFF

6 64 114 6F0000-6FFFFF

…

64 99 600000-60FFFF

5 64 98 5F0000-5FFFFF

…

64 83 500000-50FFFF

4 64 82 4F0000-4FFFFF

…

64 67 400000-40FFFF

3 64 66 3F0000-3FFFFF

…

64 51 300000-30FFFF

2 64 50 2F0000-2FFFFF

…

64 35 200000-20FFFF

Table 1: Top Parameter Memory Map (Continued)

Programming Region Number Size (KW) Block 128Mb

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128Mb: P8P Parallel PCM

Memory Maps

1 64 34 1F0000-1FFFFF

…

64 19 100000-10FFFF

0 64 18 0F0000-0FFFFF

…

64 4 010000-01FFFF

16 3 00C000-00FFFF

16 2 008000-00BFFF

16 1 004000-007FFF

16 0 000000-003FFF

Ta ble 2: Bottom Parameter Memory Map (Continued)

Programming Region Number Size (KW) Block 128Mb

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128Mb: P8P Parallel PCM

Package Dimensions

TSOP Mechanical Specifications

Figure 1: 56-Lead TSOP

Notes: 1. One dimple on package denotes pin 1.

2. If two dimples exis t, then the larger dimple denotes pin 1.

3. Pin 1 will always be in the upper left corner of the package, in reference to the product

mark.

Table 3: TSOP Package Dimensions

Parameter Symbol

Millimeters Inches

Min Nom Max Min Nom Max

Package he ig ht A – – 1.200 – – 0.047

Standoff A10.050 – – 0.002 – –

Package body thickne ss A20.965 0.995 1.025 0.038 0.039 0.040

Lead width b 0.100 0.150 0.200 0.004 0.006 0.008

Lead thickness c 0.100 0.150 0.200 0.004 0.006 0.008

Package body leng th D118.200 18.400 18.600 0.717 0.724 0.732

Package bo dy wid th E 13.800 14.000 14.200 0.543 0.551 0.559

Lead pitch e – 0.500 – – 0.0197 –

Terminal dimension D 19.800 20.00 20.200 0.780 0.787 0.795

See Detail A

0.5 TYP

14.00 ±0.2

0.25 ±0.1

1.20 MAX

18.4 ±0.2 0.995 ±0.03

20 ±0.2

0.15 ±0.05

Detail A0.60 ±0.10

0.05 MIN

0.10

Seating

plane

Pin #1 index

See notes 2

and 4

See note 3 See note 3

See note 3

0.15 ±0.05

3° +2°

-3°

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128Mb: P8P Parallel PCM

Package Dimensions

Lead tip length L 0.500 0.600 0.700 0.020 0.024 0.028

Lead count N – 56 – – 56 –

Lead tip angle q 0°3°5°0°3°5°

Seating plane coplan ari ty Y – – 0.100 – – 0.004

Lead to package offset Z 0.150 0.250 0.350 0.006 0.010 0.014

Table 3: TSOP Package Dimensions (Continued)

Parameter Symbol

Millimeters Inches

Min Nom Max Min Nom Max

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128Mb: P8P Parallel PCM

Package Dimensions

64-Ball Easy BGA Package

Figure 2: 64-Ball Easy BGA Package

Table 4: Easy BGA Package Dimensions

Parameter Symbol

Millimeters

Min Nom Max

Package height (128Mb) A––1.20

Ball heig ht A1 0.25 – –

Package body thickness (128Mb) A2 – 0.78 –

Ball (lLead) width b 0.33 0.43 0.53

Package bo dy wid th D 9.90 10.00 10.10

Package body leng th E 7.90 8.00 8.10

Pitch e – 1.00 –

Ball (lead) count N–64–

Seating plane coplan ari ty Y––0.10

Corner to ball A1 distance along D S1 1.40 1.50 1.60

Corner to ball A1 distance along E S2 0.49 0.50 0.51

Ball A1 ID

0.78 TYP

Seating

plane

0.1

1.20 MAX

1.00 TYP

8 7 6 5 4 3 2 1

0.5 ±0.1

10 ±0.1

64X Ø0.43 ±0.1

1.00 TYP

8 ±0.1

1.5 ±0.1 Ball A1 ID

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128Mb: P8P Parallel PCM

Pinouts and Ballouts

Figure 3: 56-Lead TSOP Pinout (128Mb)

Notes: 1. A1 is the least significant address bit to be compatible with x8 addressing systems even

though P8P parallel PCM is a 16-bit data bus.

A16

A15

A14

A13

A12

A11

A10

A23

A22

A21

VSS

VCC

WE#

WP#

A20

A19

A18

SERIAL

VSS

A17

DQ15

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

RST#

VPP

DQ11

DQ3

DQ10

DQ2

VCCQ

DQ9

DQ1

DQ8

DQ0

VCC

OE#/HOLD#

VSS

CE#/S#

Top View

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128Mb: P8P Parallel PCM

Pinouts and Ballouts

Figure 4: 64-Ball Easy BGA Ballout (128Mb)

Notes: 1. A1 is the least significant address bit to be compatible with x8 addressing systems even

though P8P parallel PCM is a 16-bit data bus.

SERIAL

A23

RFU

SERIAL

A23

RFU

A22

RFU

A21

A17

RFU

OE#/

HOLD#

WE#

RFU

A22

RFU

A21

A17

RFU

OE#/

HOLD#

WE#

RFU

A10

A11

D10

VCC

A10

A11

D10

VCC

VPP

CE#/SE#

A12

RST#

D11

VCCQ

VSS

VPP

CE#/SE#

A12

RST#

D11

VCCQ

VSS

A13

A14

A15

VCCQ

D12

D13

A13

A14

A15

VCCQ

D12

D13

VCC

RFU

WP#

VCCQ

VSSQ

VCC

RFU

WP#

VCCQ

VSSQ

A18

A19

A20

A16

D15

D14

A18

A19

A20

A16

D15

D14

Easy BGA

Top view-ball side down Easy BGA

Top view-ball side up

VSS

RFU

VSSQ

VSS

RFU

VSSQ

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128Mb: P8P Parallel PCM

Signal Names and Descriptions

Table 5: Ball/Pin Descriptions

Symbol Type Desctiption

A[MAX:1] Input Address inputs: Device address inputs. 128Mb: A[23 :1]. The address bus for TSOP and easy BGA

starts at A1. P8P parallel PCM uses x16 addressing. The P8P parallel PCM package is x8 addressing

and is compatible with J3 or P30 products.

DQ[15:0] Input/

Output Data input/outputs: Inputs data and commands during WRITEs (internally latched). Outputs data

during READ operations. Data signals float when CE# or OE# are VIH or RST# is VIL.

CE# or S# Input Chip enable: CE# LOW activates internal control logic, I/O buffers, decoders, and sense amps. CE#

HIGH deselects the device, places it in standby state, and places data outputs at High-Z.

SPI SPI select: S# LOW activates WRITE commands to the SPI interface. Raising S# to VIH completes (or

terminates) the SPI command cycle; it also sets Q to High-Z.

OE# or

HOLD# Input Output enable: Active LOW OE# enables the device’s output data buffers during a READ cycle.

With OE# at VIH, device data outputs are placed in High-Z state.

SPI SPI HOLD#: When asserted, suspends the current cycle and sets Q to High-Z until de-asserted.

RST# Input Reset chip: When LOW, RST# resets internal automation and inhi bits WRITE operat ions. This

provides data protection during power transitions. RST# HIGH enables normal operation. The device

is in 8-word page mode array read after reset exits.

WE# Input Write enable: controls command user interface (CUI) and array WRITEs. Its rising edge latches

addresses and data.

WP# Input Write protect: Disables/en ables the lock-down function. When WP# is VIL, the lo ck-down

mechanism is enabled and software cannot unlock blocks marked lock-down. When WP# is VIH, the

lock-down mechanism is disabled and blocks previously locked-down are now locked; software can

unlock and lock them. After WP# goes LOW, blocks previously marked lock-down revert to that

state.

CSPI

SPI clock: Synchronization clock for input and output data

DSPI

SPI data input: Serial data input for op codes, address, and program data bytes. Input data is

clocked in on the rising edge of C, starting with the MSB.

QSPI

SPI data output: Serial data output for read data. Output data is clocked out, triggered by the

falling edge of C, starting with the MSB.

SERIAL SPI SPI enable: SERIAL is a port select switching between the normal parallel or serial interface. When

VSS, the normal (non-SPI) P8P parallel PCM interface, is enabled, all other SPI inputs are “Don't

Care,” and Q is at High-Z. When VCC SPI mode is enabled, all non-SPI inputs are “Don't Care,” and all

outputs are at High-Z. This pin has an internal weak pull-down resistor to select the normal parallel

interface when users leave the pin floating. A CAM can be used to permanently disable this feature.

VPP Pwr Erase and write power: A valid VPP voltage enables erase or programming. Memory contents

can’t be altered when VPP  VPPLK.Set VPP = VCC for in-system PROGRAM and ERASE operations. To

accommodate resistor or diode drops from the system supply, the VIH level of VPP can be as low as

VPPL,min. Program/erase voltage is normally 1.7–3.6V.

VCC Pwr Device power supply: WRITEs are inhibited at VCC  VLKO. Device operations at invalid VCC

voltages should not be attempted.

VCCQ Pwr Output power supply: Enables all outputs to be driven at VCCQ. This input may be tied directly to

VCC if VCCQ is to function within the VCC range.

VSS Pwr Ground: Connects device circuitry to system ground.

VSSQ Pwr I/O ground: Tie to GND.

NC No connect: No internal connection; can be driven or floated.

DU Don’t use: Don’t connect to power supply or other signals.

RFU Reserved for future use: Don’t connect to other signals.

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128Mb: P8P Parallel PCM

Bus Operations

Bus Operations CE# at VIL and RST# at VIH enables device READ operations. Assume addresses are

always valid. OE# LOW activates the outputs and gates selected data onto the I/O bus.

WE# LOW enables device WRITE operations. When the VPP voltage  VPPLK (lock-out

voltage), only READ operations are enabled.

Notes: 1. See Table 8 on page 16 for valid DIN during a WRITE op er a tion.

2. X = “Don’t Care) (L or H).

3. OE# and WE# should never be asserted simultaneously. If this occurs, OE# overrides WE#.

READ Operations

To perform a READ operation, RST# and WE# must be de-asserted while CE# and OE#

are asserted. CE# is the device select control. When asserted, it enables the Flash

memory device. OE# is the data output control. When asserted, th e add ressed Flash

memory data is driven onto the I/O bus.

WRITE Operations

To perform a WRITE operation, both CE# and WE# are asserted while RST# and OE# are

de-asserted. During a WRITE operation, address and data are latched on the rising edge

of WE# or CE#, whichever occurs first. Table 7 on page 14 describes the bus cycle

sequence for each of the supported device commands , and Table 8 on page 16 describe s

each command . See “AC Characteristics” on page 48 for signal timing details.

Notes: 1. WRITE operations with invalid VCC and/or VPP voltages can produce spurious results

and should not be attempted.

OUTPUT DISABLE Operations

When OE# is de-asserted, device outputs DQ[15:0] are disabled and placed in High-Z;

WAIT is also placed in High-Z.

STANDBY Operations

When CE# is de-asserted, the device is deselected and placed in standby, substantially

reduc ing power consumption. In standby, the data outputs are placed in Hig h -Z, inde-

pendent of the level placed on OE#. Standby current, ICCS, is the average current

measured over any 5ms time interval, 5µs after CE# is de-asserted. During standby,

average current is measured over the same time interval 5µs after CE# is de-asserted.

When the device is deselected (while CE# is de-asserted) during a PROGRAM or ERASE

operation, it continues to consume active power until the PROGRAM or ERASE opera-

tion is completed.

Ta ble 6: Bus Operations

State RST# CE# OE# WE# DQ[15:0] Notes

READ (main array) VIH VIL VIL VIH DOUT

READ (status, query, identifier) VIH VIL VIL VIH DOUT

OUTPUT DISABLE VIH VIL VIH VIH High-Z

STANDBY VIH VIH XXHigh-Z2

RESET VIL XXXHigh-Z2

WRITE VIH VIL VIH VIL DIN 1

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128Mb: P8P Parallel PCM

Command Set

RESET Operations

As with any automated devic e, it is important to assert RST# when the system is reset.

When the system comes out of r eset, the system processor attempts to read from the

Flash memory if it is the system boot device. If a CPU reset occurs with no Flash memory

reset, improper CPU initialization may occur because the Flash memory may be

providing status information rather than array data. Micron Flash memory devices

enable proper CPU initialization following a system re set using the RST# input. RST#

should be controlled by the same low true RESET signal that resets the system CPU.

After initial power -up or re set, the device defaults to asynchronous read arr ay mode, and

the status register is set to 0x80. Asserting RST# de-energizes all internal circuits and

places the output drivers in High-Z. When RST# is asserted, the device shuts down the

operation in progre ss, a process that takes a minimum amount of time to complete.

When RST# has been de-asserted, the device is reset to asynchronous read array state.

Note: If RST# is asserted during a PROGRAM or ERASE operation, the operation is termi-

nated, and the memory contents at the aborted location (for a PROGRAM) or block

(for an ERASE) are no longer valid because the data may have been only partially writ-

ten or erased.

When returning from a reset (RST# de-asserted), a minimum wait is required before the

initial read access outputs valid data. Also, a minimum delay is required after a reset

before a WRITE cycle can be initia te d. Afte r th is wak e-up interval passes, normal opera-

tion is restored. See “AC Characteristics” on page48 for details about signal timing.

Command Set

Device Command Codes

The system CPU provides control of all in-system R E AD, WRITE, and ERASE operations

of the device via the system bus. The on-chip write state machine (WSM) manages all

block erase and word program algorithms .

Device commands are written to the command user interface (CUI) to control all Flash

memory device operations . The CUI does not occupy an addressa ble memory location;

it is the mechanism through which the Flash device is controlled.

Ta ble 7: Command Codes and Descriptions

Mode Code Command Description

Read FFh RE AD AR RA Y Places device in read array mode so that data signals output array data on DQ[15:0].

70h READ STATUS

device automatically enters this mode after a PROGRAM or ERASE command is

issued to it.

90h READ ID CODE Puts the device in read identifier mode. Device reads from the addresses output

manufacturer/device codes, block lock status, or protection register data on

DQ[15:0].

98h READ QUERY Puts the device in read query mode. Device reads from the address given

outputting the common Flash interface information on DQ[7:0].

50h CLEAR STATUS

erase (SR5) status bits to 1, but cannot clear them. Device reset or the CLEAR

STATUS REGISTER command at any device address clears those bits to 0.

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128Mb: P8P Parallel PCM

Command Set

Notes: 1. Do not use unassigned (reserved) commands.

Program 40h PROGRAM

SET-UP This prefe r re d program command’s first cycle prepares the CUI for a PROGRAM

operation. The second cycle latches address and data and executes the WSM

program algorithm at this location. Status register updates occur when CE# or OE#

is toggled. A READ ARRAY command is required to read array data after

programming.

10h ALT SET-UP Equivalent to a PROGRAM SET-UP command (40h).

42h BIT-ALTERABLE

WRITE The command sequence is the same as WORD PROGRAM (40h). The difference is

that the state of the PCM memory cell can change from a 0 to 1 or 1 to 0, unlike a

Flash memory cell, which can only change from 1 to 0 during programming.

E8h BUFFERED

PROGRAM This command loads a variable number of bytes up to the buf fer size 32 wo rds onto

the program buffer.

EAh BIT-ALTERABLE

BUFFERED

WRITE

This command sequence is the similar to BUFFERED PROGRAM, but the BUF FER

WRITE command is bit alterabl e or overwrite operation. The command sequence is

the same as E8h.

DEh BUFFER

PROGRAM ON

ALL 1s

This command is the same as BUFFERED PROGRAM, but the user indicates that the

page is already set to all 1s. The command sequence is the same as E8h

D0h BUFFERED

WRITE

CONFIRM

The confirm command is issued after the data streaming for writing into the buffer

is done. This initiates the WSM to carry out the buffered programing algorithm.

Erase 20h BLOCK ERASE

SET-UP Prepares the CUI for block erase. The device emulates erasure of the block

addressed by the ERASE CONFIRM command by writing all 1s. If the next command

is not ERASE CONFIRM:

The CUI sets status register bits SR4 and SR5 to 1.

The CUI places the device in the read status register mode.

The CUI waits for another command.

D0h ERASE

CONFIRM If the first command was ERASE SET-UP (20h), the CUI latches address and data, and

then emulates erasure of the block indicated by the ERASE CONFIRM cycle address.

Suspend B0h WRITE

SUSPEND or

ERASE

SUSPEND

This command issued at any device address initiates suspension of the currently

executi ng P ROG RAM/ERAS E op eration. Th e status register, invoked by a READ

STATUS REGISTER command, indicates successful SUSPEND operation by setting

status bits SR2 (write suspend) or SR6 (erase suspend) and SR7. The WSM remains in

suspend mode regardless of the control signal states, except RST# = VIL.

D0h SUSPEND

RESUME This command issued at any device address resumes suspended PROGRAM or ERASE

operation.

Block

Locking 60h LOCK SET-UP Prepares the CUI for lock configuration. If the next com mand is not BLOCK LOCK,

UNLOCK, or LOCK-DOWN the CUI sets SR4 and SR5 to indicate command sequence

error.

01h LOCK BLOCK If the previous command was LOCK SET-UP (60h), the CUI locks the addressed block.

D0h UNLOCK

BLOCK After a LOCK SET-UP (60h) command, the CUI latches the address and unlocks the

addressed block.

2Fh LOCK-DOWN After a LOCK SET-UP (60h) command, the CUI latches the address and locks down

the addressed bl ock.

Protection C0h PROTECTION

PROGRAM

SET-UP

Prepares the CUI for a protection register program operation. The second cycle

latches address and data and starts the WSM’s protection register program or lock

algorithm. Toggling CE# or OE# updates the PCM status register data. To read array

data after programming, issue a READ ARRAY command.

Ta ble 7: Command Codes and Descriptions (Co n tinued)

Mode Code Command Description

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128Mb: P8P Parallel PCM

Device Command Bus Cycles

Device operations are initiated by writing speci fi c de vic e commands to the CUI. Several

commands, including WORD PROGRAM and BLOCK ERASE, are used to modify array

data commands. Wr it ing eit her command to the CUI initiates a sequence of internally

timed functions that culminate in the completion of the requested task. However, the

operation can be aborted either by asserting RST# or by issuing an appropriate

SUSPEND command.

Notes: 1. First command cycle address should be the same as the operation’s target address.

X = Any valid address within the device

IA = Identification code address

BA = Address within the block

LPA = Lock prote ction addre ss (from the CFI); P8P parallel PCM LPA is at 0080h

PA = 4-word protection address in the user-programmable area of device identification

plane

DnA = Address within the device

DBA = Device base address: (A[MAX:1] = 0h)

PRA = Program region

QA = Query code address

WA = Word address of memory location to be writt en

2. SRD = Data read from the status register

WD = Data to be written at location WA

ID = Identifier code data

PD = User-programmable protecti on data

QD = Query code data on DQ[7:0]

N = Data count to be loaded into the device to indicate how many words would be written

Table 8: Command Sequences in x16 Bus Mode

Mode Command Bus

Cycles

First Bus Cycle Second Bus Cycle

Oper Addr1Data2Oper Addr1Data2

Read READ ARRAY/RESET 1 WRITE DnA FFh – – –

READ DEVICE IDENTIFIERS  2 WRITE DnA 90h READ DBA+IA ID

READ QUERY  2 WRITE DnA 98h READ DBA+QA QD

READ STATUS REGISTER 2 WRITE BA 70h READ BA SRD

CLEAR STATUS REGISTER 1WRITEX 50h – – –

Program PROGRAM 2 WRITE WA 40h or

10h WRITE WA WD

BIT-ALTERABLE PROGRAM 2 WRITE WA 42h WRITE PA PD

BUFFERED PROGRAM3 2 WRITE WA E8h WRITE WA N-1

BIT-ALTERABLE BUFFERED

PROGRAM3> 2 WRITE WA EAh WRITE WA N-1

BUFFERED PROGRAM ON ALL1s > 2 WRITE WA DEh WRITE WA N-1

Erase BLOCK ERASE 2 WRITE BA 20h WRITE BA D0h

Suspend PROGRAM/ERASE SUSPEND 1WRITEX B0h – – –

PROGRAM/ERASE RESUME 1 WRITE X D0h – – –

Block

Lock LOCK BLOCK 2 WRITE BA 60h WRITE BA 01h

UNLOCK BLOCK 2 WRITE BA 60h WRITE BA D0h

LOCK-DOWN BLOCK 2 WRITE BA 60h WRITE BA 2Fh

Protection PROTECTION PROGRAM 2 WRITE PA C0h WRITE PA PD

LOCK PROTECTION PROGRAM 2 WRITE LPA C0h WRITE LPA FFFDh

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128Mb: P8P Parallel PCM

READ Operations

into the buffer; because the internal registers count from 0, the user writes N - 1 to load N

words.

3. The second cycle of the BUFFERED PROGRAM command, which is the count bein g loaded

into the buffer, is followed by data streaming up to 32 words, and then a CONFIRM com-

mand is issued that triggers the programming operation. Refer to “Figure 33 on page 61.”

READ Operations

P8P parallel PCM has several read modes:

•Read array mode returns PCM array data from the addressed locations.

•Read identifier mode returns manufacturer device identifi er dat a, block lock status,

and protection register data.

•Read query mode returns device CFI (or query) data.

•Read S tatus R egister mode r eturns the device status register data. A system processor

can check the status register to determine the device’s state or to monitor program or

erase progress.

READ ARRAY

The READ ARR AY command places (or resets) the device to read array mode. Upon

initial device power-up or after reset (RST# transitions from VIL to VIH), the device

defaults to read array mode. If an ERASE or PROGRAM S USPEND command suspends

the WSM, a subsequent READ ARRAY command will place the device in read array

mode. The READ ARRAY command functions independently of VPP voltage.

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128Mb: P8P Parallel PCM

READ Operations

READ IDENTIFIER

The read id entifier mode is used to access the manufactur er/device identifi er, block lock

status, and protection register codes. The identifier space occupies the address range

supplied by the READ IDENTIFIER command (90h) address.

Notes: 1. DBA = Device base address: (A[MAX:18] = DBA). Micron reserves other configuration

address locations.

2. BBA = Block base address.

READ QUERY

The query space comes to the foreground and occupies the device address range

supplied by the READ QUERY command address. The mode outputs CFI dat a when the

device addresses are read. “Common Flash Interface” on page73 describes the query

mode information and addresses. Write the READ ARRAY command to return to read

array mode . The read performance of this CFI data follows the same timings as the main

array.

In addition to other ID mode data, the protection registers (such as block locking infor-

mation and the device JEDEC ID) may be accessed as long as there are no ongoing

WRITE or ERASE operations.

Table 9: Read Identifier Table

Parameter Address1, 2 Data

Manufacturer code DBA + 000000h 0089h

Device code DBA + 000001h ID (see Table 10 on page 18)

Block lock configu ratio n BBA + 000002h Lock

Block Is unlocked DQ0 = 0

Block Is locked DQ0 = 1

Block Is not locked down DQ1 = 0

Block Is locked down DQ1 = 1

Reserved for future use DQ[7:2]

Lock protection register 0 DBA + 000080h PR-LK0

64-bit factory-programmable

protection register DBA + 000081h–000084h Protection register data

64-bit user-programmable protection

Lock protection register 1 DBA + 000089h PR-LK1

16 x 128-bit user-programmable

protection registers DBA + 00008Ah–0000109h Protection register data

Ta ble 10: Device Codes

Device

Device Code (Byte/Word)

ModeHex

Binary

High Byte Low Byte

128Mb 881E 10001000 00011110 Top boot

128Mb 8821 10001000 00100001 Bottom boot

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128Mb: P8P Parallel PCM

PROGRAM Operations

Query (CFI) data is read b y sending the READ QUERY command to the device. Re ading

the query data is subject to the same restrictions as reading the protection registers.

PROGRAM Op erations

Five WRITE operations are available in P8P parallel PCM.

• WORD PROGRAM (40h, or 10h)

• BIT-ALTERABLE WOR D WRITE (42h)

•BUFFERED PROGRAM (E8h)

• BIT-ALTERABLE BUFFERED WRITE (EAh)

• BUFFERED PROGRAM ON ALL 1s (DEh)

Writing a PROGRAM command to the device initiates internally timed sequences that

write the requested word. The WSM executes a sequence of internally timed events to

write desired bits at the addressed location and to verify that the bits are sufficiently

written. For word programming, the memory changes specifically addressed bits to 0; 1

bits do not change the memory cell contents. This enables individual data bits to be

programmed (0) while 1 bits serve as data masks. For BIT-ALTERABLE WORD WRITE,

the memory cell can change from 0 to 1 or 1 to a 0.

The status reg ister can be examined for write progr ess and errors b y r eading any address

within the device during a WRITE operation. Issuing a READ STATUS REGISTER

command brings the status register to the foreground enabling write progress to be

monitored or detected at other device addresses. Status register bit SR7 indicates device

write status while the write sequence executes. CE# or OE# toggle (during polling)

updates the status register. Valid commands that can be issued to the writing device

during write include READ STATUS REGISTER, WRITE SUSPEND, READ IDENTIFIER,

READ Q UERY, and READ ARRAY; ho wev er, R EAD ARRAY will return unkno wn data whi le

the device is busy.

When writing completes, status register bit SR4 indicates write suc ce s s if zero (0) or

failure if set (1). If SR3 is set (1), the WSM couldn’t execute the WRITE command because

VPP was outside acceptable limits. If SR1 is set (1), the WRITE operation targeted a

locked block and was aborted. Atte mpting to write in an erase suspended block will

result in failure, and SR4 will be set (1).

After examining the status register, clear it by issuing the CLEAR STATUS R EGISTER

command before issuing a new command. The device remains in status register mode

until another command is written to that device. Any command can follow after writing

completes.

WORD PROGRAM

The system processor writes the WORD P ROGRAM SETUP command (40h/10h) to the

device followed by a second WRITE that specifies the address and data to be

programm ed. The device accessed during bo th of the command cycles automatical ly

outputs status re gister data when the device address is read. The device accessed during

the second cycle (the data cycle) of the program comman d se que n c e w il l be wh ere the

data is programmed. See Figure 33 on page 61.

When VPP is greate r than V PPLK, program and erase currents are drawn through the VCC

input. If VPP is driven by a logic signal, VPP must remain above VPP,min to perform in-

system PCM mod ifi cations. Figure 5 on page 22 shows PCM power supply usage in

variou s co nfiguration s.

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128Mb: P8P Parallel PCM

PROGRAM Operations

BIT-ALTERABLE WORD WRITE

The BIT-ALTERABLE WORD WRITE command executes just like the WORD PROGRAM

command (40h/10h), using a two-write command sequence. The BIT-ALTERABLE

WRITE SETUP command (42h) is written to the CUI, followe d by the specific address

and data to be written. The WSM will start executing the programming algorithm, but

the data written to the CUI will be directly overwritten into the PCM memory. This is

unlike Flash memory, which can only be written from 1 to 0 without a prior erase of the

entire block. See Table 12 on page 21. This overwrite function eliminates Flash bit

masking, which means that the softw are cannot use a 1 in a data mask to produce no

change of the memory cell, as might occur with floating gate Flash.

BUFFERED PROGRAM

A BUFFERED PROGRAM command sequence initiates the loading of a variable number

of words , up to the buffer size (32 words), into the program buffer and then into the PCM

device. F irst, the BUFFERED PROGRAM SETUP command is issue d along with the

BLOCK ADDRESS (Figure 33 on page 61). When status register bit SR7 is set to 1, the

buffer is ready for loading. Now a word count is given to the part with the block address.

On the next write, a device starting address is given along with the program buffer data.

Subsequent writes provide addition al de vic e addresses and dat a, de pe ndi n g on the

count. All subsequent addresses must lie within the starting address plus the buffer size.

Maximum programming performance and lower power are obtained by aligning the

starting address at the beginning of a 32-wor d boundary. A misaligned starting addr ess is

not allowed and results in invalid data. After the final buffer data is given, a PROGRAM

BUFFER CONFIRM command is issued. This initiates the WSM to begin copying the

buffer data to the PCM array.

If a command other than BUFFERED PROGRAM CONFIRM command (D0h) is written

to the device, an inv al id command/sequence erro r will be gener ated, and status register

bits SR5 and SR4 will be set to a 1. For additional buffer writes, issue another PROGRAM

BUFFER SETUP command and check SR7. If an error occurs while writing, the device

will stop writing, and status register bit SR4 will be set to a 1 to indicate a program

failure. The internal WSM verify only de tects errors for 1s that do not successfully

program to 0s.

If a program error is detected, the status re gister should be cleared by the user before

issuing the next PROGRAM command. A dditionally, if the user attempts to program past

the block boundary with a PROGRAM BUFFER command, the device will abort the

PROGRAM BUFFER operation. This will generate an invalid command/sequence error

and status register bits SR5 and SR4 will be set to a 1. All bus cycles in the buffered

programming sequence should be addressed to the same block. If a buffered program-

ming is attempted whil e the VPP  VPPLK, status register bits SR4 and SR3 will be set to 1.

Buffered write attempts with invalid VCC and VPP voltages produc e spurious results and

should not be attempted. Buffered progra m operations with VIH < RST# < VHH may

produce spurious results and should not be attempted.

S uccessful progr amming r equires that the addres sed block’s locking status to be cleared.

If the block is locked down, then the WP# pin must be raised HIGH, and then the block

could be unlocked to execute a PROGRAM operation. An attempt to program a locked

block results in se tting of SR4 and SR1 to a 1 (for example, error in programming).

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128Mb: P8P Parallel PCM

PROGRAM Operations

BIT-ALTERABLE BUFFER WRITE

The BIT-ALTERA BLE BUFFER WRITE command sequence is the same as for BUFFER

PROGRAM. For command sequence, see “BUFFERED PROGRAM” on page 20. The

primary difference between the two buffer com mands is when the WSM st arts

executing, the data written to the buffer will be directly ov erwritten into the PCM

memory, unlike Flash Memory, which can only go from 1 to 0 before an erase of the

entire block. See Table 12 on page 21. This overwrite function eliminates Flash bit

masking, which means software cannot use a 1 in a data mask for no change of the

memory cell, as might occur with floating gate Flash.

The advantage of bit alterability is that no block erase is needed prior to writing a block,

which minimizes system overhead for software management of data and ultimately

improves latency and determinism and reduces power consumption because of reduc-

tion of system overhead. Storing counter variables can easily be handled using PCM

memory because a 0 can change to a 1 or a 1 can change to a 0.

BIT-ALTERABLE BUFFER PROGRAM

This mode is sometimes referred to as PRESET BUFFERED PROGRAM.

PROGRAM ON ALL 1s is similar to program mode (1s treated as masks; 0s written to

cells) with the assumption that all the locations in the addressed page have previ ously

been set (1s). Performance of BUFFER PROGRAM ON ALL 1s expected to be better than

buffered program mode because the preread step before programming is eliminated.

The command sequence for BUFFERED PROGRAM ON ALL 1s is the same as BUFF-

ERED PROGRAM command (E8h).

PROGRAM SUSPEND

Issuing the P R OGRAM SUSPEND command while programm ing s uspends the program-

ming operation. This enables data to be accessed from the device other than the one

being programmed. The PROGRAM SUSPEND command can be issued to any device

address . A PROGRAM operation can be suspended to perform reads only. Additionally, a

PROGRAM operation that is running during an ERASE SUSPEND can be suspended to

perform a READ operation.

Table 11: Buffered Programming and Bit-Alterable Buffer Write Timing Requirements

Alignment Programming Time Example

32-word/64-byte aligned tPROG/PB Start address = 1FFF10h; end address = 1FFF2Fh

Ta ble 12: Bit Alterability vs. Flash Bit-Masking

Programming

Function Command

Issued Memory Cell

Current State Data From

User Memory Cell

After Programming

Flash bit mas king 40h or E 8h 0 0 0

40h or E8h 0 1 0

40h or E8h 1 0 0

40h or E8h 1 1 1

Bit alterability 42h or EAh 0 0 0

42h or EAh 0 1 1

42h or EAh 1 0 0

42h or EAh 1 1 1

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128Mb: P8P Parallel PCM

ERASE

When a programming operation is executing, issuing the PROGRAM SUSPEND

command requests the WSM to suspend the programming algorithm at predetermined

points. The device continues to output status register data after the PROGRAM

SUSPEND command is issued. Programming is suspended when status register bits

SR[7,2] are set.

To read data from the device, the READ ARRAY command must be issued. READ ARRAY,

READ STA TUS REGISTER, READ DEVICE IDEN TIFIER, READ CFI , and PR OGRAM

RESUME are valid commands during a PROGRAM SUSPEND.

During a PR OGRAM SUSPEND, de-assertin g CE# places the device in standby, reducing

active current. VPP must remain at it s programming level, and WP# must remain

unchanged while in PROGRAM SUSPEND. If RST# is asserted, the device is reset.

PROGRAM RESUME

The RESUME command instructs the device to continue programming, and automati-

cally clears S tatus Register bits SR[7,2]. This command can be written to any address. If

error bits are set, the Status Regi ster should be cle a red before issuing the next instruc-

tion. RST# must remain de- a sserted.

PROGRAM PROTECTION

Holding the VPP input at VIL provides absolute hardware write protection for all PCM

device blocks. If VPP is below VPPLK, WR ITE or ERASE operations halt and an error is

posted in status register bit SR3. The block lock registers are not affected by the VPP level;

they may be modified and read even if VPP is below VPPLK.

Figure 5: Example VPP Power Supply Configuration

ERASE U nlike floating g ate Flash, PCM does not r equir e a high-voltage BLOCK ER ASE operation

to change all the bits in a block to 1. As a bit-alterable technology, each bit is capable of

independently being changed from a 0 to a 1 and from a 1 to a 0. With floating gate Flash,

a high voltage potenti a l must be placed in parallel upon a group of bits called an erase

block. Each bit within the block may be changed independently from 1 to a 0, but only

System supply System supply

System supply

PROT# (logic signal)

System supply

• V

supply during factory programming

• Complete write/erase protection: V

≤ V

PPLK

• Low-Voltage programming

• Absolute write protection via logic signal

• Low-voltage and V

factory programming

• Low-Voltage programming

≤10kΩ

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128Mb: P8P Parallel PCM

ERASE

may be changed from a 1 to a 0 through a grouped ERASE operation. To maintain

compatibility with legacy Flash system softwar e, P8P parallel PCM mimics or emulates a

Flash erase b y writi ng each bit within a block to 1, emulating Flash-style erase.

BLOCK ERASE

The system processor writes the ERASE S ETUP command (20h) to the device follow ed by

a second CONFIRM (D0h) command write that specifies the address of the block to be

erased. During both of the command cycles, the device automatically outputs status

After writing the command, the device automatically enters read status mode. The

device status register bit SR7 will be se t (1) when the erase completes. If the erase fails,

status re gister bit SR5 will be set (1). SR3 = 1 indicates an invalid VPP voltage. SR1 = 1

indicates an ERASE operation was attempted on a locked block. CE# or OE# toggle

(during polling) updates the status register.

If an error bit is set, the status register can be cleared by issuing the CLEAR STATUS

status re gister mode until anothe r command is written to the device. Any command can

follow after ERASE completes. Only one block can be in erase mode at a time.

ERASE SUSPEND

The WRITE/ERASE SUSPEND command halts an in-progress WRITE or ERASE opera-

tion. The command can be issued at any device address. The SUSPEND command

enables data to be ac ce ss e d from mem o ry locat ions othe r than the o ne bl oc k be ing

written or the block being erased.

A WRITE operation can be suspended to perform reads at any location except the

address being progr ammed. An ERASE operation can be suspended to perform either a

WRITE or a READ operation within any block ex cept the block that is er ase suspended. A

WRITE command nested within a suspended ERASE can subsequently be suspended to

read yet another location. After the WRITE/ERASE process starts, the SUSPEND

command requests that the WSM suspend the WRITE/ERASE sequence at predeter-

mined points in the algorithm. An operation is suspended when status bits SR7 and SR6

and/or SR2 display 1. tSUSP/P/tSUSP/E specifies suspend latency.

To read data from other blocks within the device (other than an erase suspended block),

a READ ARRAY command can be written. During ERASE S USPEND, a WRITE command

can be issued to a block other than the erase suspended block. Block erase cannot

resume until WRITE oper ations initiated during ERASE SUSPEND complete. READ

ARRAY, READ STATUS REGISTER, READ IDENTIFIER (ID), READ QUERY, and WRITE

RESUME are valid commands during WRITE or ERASE SUSPEND. Additionally, CLEAR

STATUS REGISTER, PROGRAM, WRITE SUSPEND, ERASE RESUME, LOCK BLOCK,

UNLOCK BLOCK, and LOCK-DOWN BLOCK are valid commands during ERASE

SUSPEND.

During a suspend, CE# = VIH places the device in stand by state, which reduces supply

current. VPP must remain at its program lev el and WP# must r emain unchanged while i n

suspend mode.

The RESUME (D0h) command inst ructs the WSM to continue writing/erasing and auto-

matically clears status register bits SR2 (or SR6) and SR7. If status register error bits are

set, the status register can be cleared before issuing the next instruction. RST# must

re main at V IH. See F igure31 on page 58 and Figure33 on page 61.

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128Mb: P8P Parallel PCM

Security Mode

If software compatibility with the P33 device is desired, a minimum tERS/SUSP time (See

“Program and Erase Characteristics” on page 55) should elapse between an ERASE

command and a subsequent ERASE SUSPEND command to ensure that the device

achieves sufficient cumulative erase time. Occasional ERASE to SUSPEND interrupts do

not cause problems, but out-of-spec ERASE to SUSPEND commands issued too

freque ntly to a P33 device may produce uncertain results. However, this specification is

not required for this PCM device.

ERASE RESUME

The ERASE RESUME command instructs the device to continue erasing and automati-

cally clears status register bits SR[7,6]. This command can be wr itten to any address. If

status re gister error bits are set, the status register should be clear ed before issuing the

next instruction. RST # mus t remain de -asserted.

Security Mode The device features security mode s used to protect the infor m ation st ored in the Flash

memory array.

Block Locking

Two types of block locking are available on P8P parallel PCM: zero latency block loc king

and selectable OTP block locking. This type of locking enables permanent locking of the

parameter blocks and three main blocks .

Zero Latency Block Locking

Individual instant block locking protects code and data. It enables software to control

block locking or it can require hardwar e interaction before locking can be changed. Any

block can be locked or unlocked with no latency. Locked blocks cannot be written or

erased; they can only be read. WRITE or ERASE operations to a locked block returns a

status regi ster bit SR1 error. State (WP#, LAT1, LAT0) specifies lock states (WP# = WP#

state, LAT1 = internal bock lock down latch status, LAT0 = internal block lock latch

status). Figure 6 on page27 defines possible locking states. The following summarizes

the locking functionality.

• All blocks power-up in the locked state. Then UNLOCK and LOCK commands can

unlock or lock them.

• The LOCK DOWN command locks and prevents a block from being unlocked when

WP# = VIL.

•WP#=V

IH overrides LOCK DOWN so commands can unlock/lock blocks.

• If a pr evious ly locked down block is given a LOC K/UNLOCK/LOCK DO WN command

and WP# returns to VIL, then those blocks will return to lock down.

• LOCK DOWN is cleared only when the device is reset or pow ered down.

• The block lock r egisters are not affected by the VPP level; they may be modified an d

read even if VPP is below VPPLK.

Lock Block

All blocks default po wer -up or r eset state is locked (states [001] or [101]) to fully protect it

from alteration. WRITE or ERASE operations to a locked block return a status register bit

SR1 error. The LOCK BLOCK command sequence can lock an unlocked block.

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128Mb: P8P Parallel PCM

Security Mode

Unlock Block

The UN LOCK BLOCK command unlocks locked bloc ks (if block isn’t locked down) so

they can be programmed or erased. Unlocked blocks return to the locked state at device

reset or power-down.

Lock Down Block

Locked down blocks (state 3 or [011]) are protected from WRITE and ERASE operations

(just like locked bloc ks), but software commands cannot change their protection stat e.

When WP# is VIH, the lock down function is disabled (state 7 or [111]), and an UNLOCK

command (60h/D0h) must be issued to unlocked locked down block (state 6 or [110]),

prior to modifying data in these blocks. To return an unlocked block to locked down

state, a LOCK command (60h/01h) must be issued pr ior to changing WP# to VIL (state 7

or [111] and then state 3 or [011]). A locked or unlocked block can be locked down by

writing the LOCK DOWN B LOCK command sequence. Locked do wn blocks revert to the

locked state at device reset or power-down.

WP# Lock Down Control

WP# = VIH overrides the block lock down. See Table 13 on page 25. The WP# signal

controls the lock down function. WP# = 0 protects lock down blocks [011] from write,

erase, and lock status changes. When WP#= 1, the lock down function is disa bled [111]

and a software command can individually unlock locked down blocks [110] so they can

be erased and written. When the lock down function is disabled, locked down blocks

remain locked and must first be unlocked by writing the UNLOCK command prior to

modifying data in these blocks. These blocks can then be relocked [111] and unlocked

[110] while WP# remains HIGH.

When WP# goes LOW, blocks in relocked state [111] returns to locked down state [011].

However, WP# going LOW changes blocks at unlocked state [110] to [010] or virtual lock

down state. When the lock status of a virtual lock down blocks is read, it appears to be a

locked down state to user when WP# is VIL. Blocks in virtual lock down will be immedi-

ately unlocked when WP# is VIH. Therefore, to avoid virtual lock down, a LOCK

command must be issued to an unlocked block prior to WP# going LOW. Device reset or

power-down resets all blocks to the locked state[101] or [001], including locked down

blocks.

Ta ble 13: Block Locking Truth Table

VPP WP# RST# Block Write Protection Block Lock Bits

XXV

IL All blocks write/erase

protected Block lo ck bits may not be changed

VPPLK VIL VIH All blocks write/erase

protected Lock down block states may not be

changed

VPPLK VIH VIH All blocks write/erase

protected All Lock down block states may be

changed

VPPLK VIL VIH All lock down and locked

blocks write/erase protected Lock down block states may not be

changed

VPPLK VIH VIH All lock down and locked

blocks write/erase protected All Lock down block states may be

changed

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128Mb: P8P Parallel PCM

Security Mode

Block Lock Status

Every block’s lock status can be re ad in the device’s read identi fier mode. To enter this

mode, write 90h to the device. Subsequent reads at block base address + 00002h output

that block’s lock status. Data bits DQ0 and DQ1 represent the lock status. DQ0 indicates

the block lock/unlock state as set by the LOCK command and cleared by the UNLOCK

command. It is also automatically set when entering lock down. DQ 1 indicates lock

down state as set by the LOCK DOWN command. It cannot be cleared by software; it can

only be cleared by device reset or power-down. See Table 14 on page26.

Locking Operations During ERASE SUSPEND

Block lock configurations can be performed during an ERASE SUSPEND using the stan-

dard locking command sequences to unlock, lock, or lock down a block. This is useful

when another block needs to be updated while an ERASE oper ation is sus pen ded.

To change block locking during an ERASE operation, first write the ERASE SUSPEND

command, and then check the status register until it indicates that the ERASE operation

has suspended. Next write the desired LOCK command sequenc e to a block; the lock

state will be changed. After completing LOCK, READ, or PR OGRAM operations, resume

the ERASE operation with the ERASE RESUME command (D0h).

If a block is locked or locked down during a suspended ERASE of the same block, the

locking status bits will change immediately. But, when resumed, the ERASE operation

will complete. Locking operations cannot occur during WRITE SUSPEND. “Write State

Machine” on page 70 describes valid commands during ERASE SUSPEND.

Nested LOCK or WRITE commands during ERASE SUSPEND can return ambiguous

status register results. 60h followed by 01h commands lock a block. A CONFIGURATION

SETUP command (60h) followed by an invalid command produces a lock command

status regi ster error (SR4 and SR5 = 1). If this error occurs during ERASE SUSPEND, SR4

and SR5 remain at 1 after the erase r esumes . When erase completes, the previous locking

command error hides the status register’s erase err o rs. A similar situation occurs if a

WRITE operation error is nested within an ERASE SUSPEND.

Notes: 1. Additional illegal states are shown, but are not recommended for normal, non-erroneous

operational modes.

2. This column shows whether a block’s current locking state allows ERASE or WRITE.

Table 14: Block Locking State Transitions

Current State

ERASE/WRITE

Allowed?1

Lock Command Input

Result (Next State)5WP#

Toggle

Result

(Next

State)

Locking

Status

Readout

WP# LAT1 LAT0 Name UnLock Lock Lock-

Down D1 D0

0 0 0 Unlocked Yes 000 001 011 100 0 0

0 0 1 Locked (default)1No 000 001 011 101 0 1

0 1 0 Virtual lock down4No 011 011 011 110 1 1

0 1 1 Locked down No 011 011 011 111 1 1

1 0 0 Unlocked Yes 100 101 111 000 0 0

1 0 1 Locked No 100 101 111 001 0 1

1 1 0 Lock down disabled Yes 110 111 111 01 0 1 0

1 1 1 Lock down disabled No 110 111 111 011 1 1

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128Mb: P8P Parallel PCM

Security Mode

3. At power-up or device reset, blocks default to locked state [001 ] if WP# = 0, the recom-

mended default.

4. Blocks in virtual lock down appear to be in locked down state when WP# = VIL. WP# = 1

changes [010] to unlocked state [110].

5. This column shows the results of writing the four locking commands via WP# toggle from

the current locking state.

Figure 6: Block Locking State Diagram

Notes: 1. [a, b, c] represent [WP#, DQ1, DQ0]. X = “Don’t Care.”

2. DQ1 indicates block lock down status. DQ1 = 0; lock down has not been issued to this block.

DQ1 = 1; lock down has been issued to this block.

3. DQ0 indicates block lock status. DQ0 = 0; block is unlocked. DQ0 = 1, block is locked.

4. Lock down = hardware and software locked.

5. [011] states should be tracked by system software to determine differences between hard-

ware locked and locked down states.

Permanent OTP Block Locking

The parameter blocks and first three main blocks for a bottom parameter device (or if

device configured as a top parameter device, this would be the last three main blocks

and the parameter blocks) can be made O TP. As a result, further WRITE and ERASE oper-

ations to these blocks are disallowed, effectively permanently programming the blocks.

This is achieved by programming bits 2, 3, 4, and 5 in the PR-L OCK0 register at offset

0x80 in ID space. The OTP locking bit mapping may be seen in Table 15 on page 28.

Bit 6 in the PR-LOCK0 register at offset 0x80 in ID spac e is de fine d as the configuration

lock bit. When bit 6 is cleared (at zero), the device shall disable further programming of

the OTP Lock bits, thereby effectively fr eezing their state. Putting bit 6 at zero shall not

affect the ability to wri te any othe r bits in the non-OTP regions or in the system protec-

tion registers. Reference Table 16 on page 28 for configuration lock bit (Bit 6 in PR -

LOCK0) contr o l of allowed states when other bits of the register are programmed.

The READ operations of these permanently locked blocks are supporte d regardless of

the state of their corr espond ing pe rmanent lock bits . Zero latency block locking must be

used until the block is permanen tly locked with the OTP block locking. PROGRAM and

ERASE operations for these blocks remain fully supported until that block’s permanent

lock bit is cleared.

Locked

[X01]

Unlocked

[X00]

Locked

down4, 5

[011]

Software

locked

[111]

Hardware

locked5

[011]

Unlocked

[110]

Power-Up/Reset

Software block lock-down (0x60/0x2F)

Software block lock (0x60/0x01) or software block unlock (0x60/0xD0)

Hardware control (WP#)

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128Mb: P8P Parallel PCM

Security Mode

PROGRAM or ERASE operations to a permanently locked block returns a status register

bit SR1 error.

Programming of the permanent O TP block locking bits is not all owed during ER ASE

SUSPEND of a permanent lockable block.

Note: The selectable block locking will not be indicated in the zer o latency block lock status .

See “Block Lock Status” on page 26 for more information. Read PR-LOC K0 register to

determine block lock status for these blocks.

Table 15: Selectable OTP Block Locking Feature

Bit Number @ Offset

0x80 in CFI Space Function When Set (‘1b) Function When Cleared (‘0b)

2 Blocks not permanently locked WRITE/ERASE disabled for all parameter blocks

Bottom boot - Blocks 0–3

Top boot 128M - Blocks 127–130

3 Block not permanently locked WRITE/ERASE disabled for first Main Block

Bottom Boot - Block 4

Top Boot 128M - Block 126

4 Block not permanently locked WR ITE/ERASE disabled for second Main Block

Bottom Boot - Block 5

Top Boot 128M - Block 125

5 Block not permanently locke d WRITE/ERASE disabled for third Main Block

Bottom Boot - Block 6

Top Boot 128M - Block 124

6 Able to change PR-LOCK0[5:2] bits Program disabled for PR-LOCK0[5:2]

Table 16: Selectable OTP Block Locking Programming of PR-LOCK0

Bit 6 Program to

[5:2] Program to

[1:0] Status Register Abort

Program Status of Data in 80H OTP

Space

Unlocked Don’t Care Don’t Care No fail bits set No Changed

Locked Yes Yes Program fail/lock fail Yes No change

Locked Yes No Program fail/lock fail Yes No change

Locked No Yes No fail bits set No Changed

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128Mb: P8P Parallel PCM

Registers

Figure 7: Selectable OTP Locking Illustration (Bottom Parameter Device Example)

WP# Lock Down Control for Selectable OTP Lock Blocks

Once the block has been permanently locked with OTP bit, WP# at VIH does not o verride

the lock down of the blocks those bits control.

Selectable OTP Locking Implementation Details

Clearing (write to 0) any of the four permanent lock bits shall effectivel y cause the

following commands to fail with a block locking error when issued to their corre-

sponding blocks: B UFFER PROGRAM, BIT-ALTERA BLE BUFFER WRITE, WORD

PROGRAM, BIT-ALTERABLE WORD WRITE, and ERASE. No other commands shall be

affected.

Programming the permanent lock bits or the configuration lock bit shall be done using

the protection register programming command. As with all bits in the CFI/OTP space,

after the permanent lock or the configuration bits are programmed , they may not be

erased (set) again.

Registers

Read Status Register

The device’s status register displays PROGRAM and ERASE operation status. A device’s

status can be read after writing the READ STATUS REGISTER command. The status

sequence. Subsequent single reads from the device outputs its status until another valid

command is written.

The last of OE# or CE# falling edge latches and updates the status register content.

DQ[7:0] output is the satus register bits; DQ[15:8] output 00h. See Table 17 on page30.

Main Array Block 4

Main Array Block 5

Parameter Blocks: Blocks 0–3

0x80 (OTP array)

0x000000 (Parameter array)

0x010000 (Main array)

0x020000 (Main array)

0x030000 (Main array)

PR-LOCK0

Main Array Block 6

65 4 3 2

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128Mb: P8P Parallel PCM

System Pr otection Registers

Iss u ing a READ STATUS, BLOCK LOCK, PROGRAM, or ERASE command to the device

places it in the read status mode. Status register bit SR7 (DW S — device write status)

provides program/erase status of the device . Status register bits SR1–SR6 present infor-

mation about the WSM’s program, erase, suspend, VPP

, and block lock status mode.

CLEAR STATUS REGISTER Command

The CLEAR STATUS REGISTER command clears the status register. The command func-

tions independently of the applied VPP voltage. The WSM can set (1) status register bits

SR[7:0] and clear (0) bits 2, 6, and 7. Because bits 1, 3, 4, and 5 indicate various error

conditions, they can only be cleared by the Cclear status register command. By allowing

system software to reset these bits, several operations (such as cumulatively program-

ming several addresses or erasing multiple blocks in sequence) may be performed

before reading the status register to determine err o r occurrence. The status register

should be cleared before beginning another command or sequence. Device reset (RST#

= VIL) also clears the status register.

System Protection Registers

The device contains two 64-bit, and sixteen 128-bit individually lockable prote ct ion

registers that can increase system se curity or hinder device substitution by containing

values that mate the PCM component to the system’s CPU or ASIC.

Ta ble 17: Status Register Definitions

DRS ESS ES PS VPPS PSS DPS PRW

SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0

Status Register Bits Notes

SR7 = Device write/erase status (DWS)

0 = Device WSM is busy

1 = Device WSM is ready

SR7 indicates erase or program completion in the device. SR1–6 are invalid

while SR7 = 0

SR6 = Erase suspend status (ESS)

0 = Erase in progress/completed

1 = Erase suspended

After issuing an ERASE SUSPEND command, the WSM halts and sets (1) SR7

and SR6. SR6 remains set until the device receives an ERASE RESUME

command.

SR5 = Erase status (ES)

0 = Successful erase

1 = Erase error

SR5 is set (1) if an attempted erase failed.

A command sequence error is indicated when SR4, SR5, and SR7 are set.

SR4 = Program status (PS)

0 = Successful write

1 = Write error

SR4 is set (1) if the WSM failed to program.

A command sequence error is indicated when SR4, SR5, and SR7 are set.

SR3 = VPP status (VPPS)

0 = VPP OK

1 = VPP low detect, operation aborted

The WSM indicates the VPP level after program or erase starts. SR3 does not

provide continuous VPP feedbac k and isn’t guaranteed when VPP VPPLK

SR2 = Program suspend status (PSS)

0 = Write in progress/completed

1 = Write suspended

After receiving a WRITE SUSPEND command, the WSM halts execution and

sets (1) SR7 and SR2, which remains set until a RESUME command is

received.

SR1 = Device protect status (DPS)

0 = Unlocked

1 = Aborted erase/program at tempt on

locked bloc k

If an ERASE or PROGRAM operation is attempted to a locked block (if WP#

= VIL), the WSM sets (1) SR1 and aborts the operation.

SR0 Super Page write status (PRW)

0 = Reserved

1 = Reserved

Reserved

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128Mb: P8P Parallel PCM

System Pr otection Registers

One 64-bit protection register is programmed at the Micron factory with an non-

changeable unique 64-bit number. The other 64-bit and sixteen 128-bit protection regis-

ters are blank so customers can program them as de s ired. Once programmed, ea ch

customer segment can be locked to pr event further reprogramming.

Read Protection Register

The READ IDENTIFIER command allows protection register data to be read 16 bits at a

time from addresses shown in Table 9 on page 18. To read the protection register, first

issue the READ DEVICE IDENTIFIER command at device base address to place the

device in the r ead device identifier mode. N ext, perform a R EAD operation at the device’s

base address plus the address offset correspond ing to the register to be read. Table 9 on

page 18 shows the address offsets of the protection registers and lock registers. Register

data is read 16 bits at a time. Refer Table 18 on page 32.

Program Protection Register

The PROTECTION PROGRAM command should be issued followed by the data to be

programed at the specified location. It programs the 64 user protection r egister 16 bits at

a time. Table 9 on page18 and in Table 18 on page 32 show allo wab le addresses. S ee als o

Figur e 38 on page 68. Ad dress es A[MAX:11] ar e ignor ed when pr ogramming the O TP, and

OTP program will succeed if A[10:1] are within the prescribed pr otection addressing

range; otherw is e an error is indi cated by SR4 = 1.

Lock Protection Register

Each of the protection r egisters are l ockable b y progr amming their r espective lock bits in

the PR-LOCK0 or PR-LOCK1 registers. Bit 0 of the lock register -0 is programmed by

Micron to lock-in the unique device number. The physical address of the PR-LOCK0

programm ed by the user to lock the upper 64-bit portion. (Refer Table 18 on page 32.).

The bits in both PR -LOCK r egister s are made of PCM cells that may only be progr ammed

to 0 and may not be altered.

Note: Bit0 of the lock register, PR-LOCK0, is a “Don’t Care,” so users must mask out this bit

when readi ng PR LOCK0 register. This number is guaranteed to persist thr ough board

attach.

For the 2K OTP space, there exists an additional 16-bit lock register called PR_LOCK1.

Each bit in the PR_LOCK1 register locks a 128-bit segment of the 2K OTP space. There-

fore, the 16 128-bit segments of the 2K O TP space can be locked indivi dually. Hence, any

128-bit segment can be first programmed and then locked using the PROTECTION

PROGRAM command followed by protection register data. The PR-L OCK1 r egister is

physically located at the address 89h as shown in the F igure 8 on page 32.

After PR-LOCK register bits have been programmed, no further changes can be made to

the protection registers' stored v alues . PR OTECTION P ROGR AM commands written to a

locked section result in a status reg ister error (program error bit SR4 and lock error bit

SR1 are set to 1). Once locked, protection register states are not reversible.

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128Mb: P8P Parallel PCM

System Pr otection Registers

Figure 8: Protection Register Memory Map

OTP Protection Register Addressing Details

Notes: 1. Addresses A[23:9] should be set to zero.

Notes: 1. DBA - Device base address. Typically this woul d start from address 0.

Table 18: Protection Register Addressing

Word Use ID Offset A8 A7 A6 A5 A4 A3 A2 A1

LOCK Both DBA + 000080h 10000000

0 Micron DBA + 000081h 10000001

1 Micron DBA + 000082h 10000010

2 Micron DBA + 000083h 10000011

3 Micron DBA + 000084h 10000100

4 Customer DBA + 000085h 10000101

5 Customer DBA + 000086h 10000110

6 Customer DBA + 000087h 10000111

7 Customer DBA + 000088h 10001000

Table 19: 2K OTP Space Addressing

Word Use ID Offset A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1

Lock CustomerDBA+000089h0000010001001

0 Customer DBA+00008Ah 0000010001010

: : : :::::::::::::

127 CustomerDBA+000109h0000100001001

Lock register 1

8 words

user programmed

109h

102h

91h

8Ah

89h

88h

85h

84h

81h

80h

8 words

user programmed

Lock register 0

4 words (64 bits)

user programmed

4 words (64 bits)

Intel factory programmed

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128Mb: P8P Parallel PCM

Serial Peripheral Interface (SPI)

SPI Overview

A serial peripheral inte rface has been added as a secondary interface on P8P parallel

PCM to enable low cost, low pin count on-board programming. This interface gives

access to the P8P par al lel PCM memory by using only seven signals , i nstead of a conv en-

tional parallel interface that may take 45 signals or mor e. The seven signals consist of six

SPI-only signals plus one signal that is shared with the conventional interface.

When the SPI mode is enabled, all non-SPI P8P parallel PCM output signals are tri-

stated, and all non-SPI P8P parallel PCM inputs signals are ignored (made “ Don't Car e”).

When the conventional interface is enabled, the SPI-only output is tri-stated, and the

SPI-only inputs are ignored (made “Don't Care”).

Note: The SPI interface can only be enable upon po wer-up and to enable this interface, the

SERIAL pin must be tied to VCC for the interface to be factional. Once the SPI interface

is enabled, it is the only interface that can be accessed until the part is powered down.

The SPI mode may be disabled. Please contact Mi cron for more information.

SPI Signal Names

For P8P parallel PCM, the si x additional SP I-only signal s are implemented in addition to

the po wer pins. VCC, VCCQ, and VPP are va lid power pins during serial mode and must be

connected during SPI mode ope ration. F our of the six additional SPI signals do not share

functions with the regular interface. For pin and signal descriptions of all P8P parallel

PCM pins see Table 5 on page12. Two pins are shar ed between the i nterface modes: S# is

the same pin as CE#, and HOLD# is the same pin as OE#. The signals that are unique to

the SPI mode and require a separate connection are C, D, Q, and SERIAL.

SPI Memory Organization

The memory is orga nized as:

• 16,772,216 bytes (8 bits each)

• 128 sectors (128 Kbytes each)

• 131,072 pages (64 bytes each)

Each page can be individually prog rammed (bits ar e programmed from 1 to 0) or written

(bit alterable: 1 can be altered to 0 and 0 can be altered to 1). The device is sector or bulk

erasable (bits are erased from 0 to 1).

Ta ble 20: Memory Organization

Sector Address Range Sector Address Range

127 FE0000 FFFFFF 63 7E0000 7FFFFF

126 FC0000 FDFFFF 62 7C0000 7DFFFF

125 FA0000 FBFFFF 61 7A0000 7BFFFF

124 F80000 F9FFFF 60 780000 79FFFF

123 F60000 F7FFFF 59 760000 77FFFF

122 F40000 F5FFFF 58 740000 75FFFF

121 F20000 F3FFFF 57 720000 73FFFF

120 F00000 F1FFFF 56 700000 71FFFF

119 EE0000 EFFFFF 55 6E0000 6FFFFF

118 EC0000 EDFFFF 54 6C0000 6DFFFF

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128Mb: P8P Parallel PCM

Serial Peripheral Interface (SPI)

117 EA0000 EBFFFF 53 6A0000 6BFFFF

116 E80000 E9FFFF 52 680000 69FFFF

115 E60000 E7FFFF 51 660000 67FFFF

114 E40000 E5FFFF 50 640000 65FFFF

113 E20000 E3FFFF 49 620000 63FFFF

112 E00000 E1FFFF 48 600000 61FFFF

111 DE0000 DFFFFF 47 5E0000 5FFFFF

110 DC0000 DDFFFF 46 5C0000 5DFFFF

109 DA0000 DBFFFF 45 5A0000 5BFFFF

108 D80000 D9FFFF 44 580000 59FFFF

107 D60000 D7FFFF 43 560000 57FFFF

106 D40000 D5FFFF 42 540000 55FFFF

105 D20000 D3FFFF 41 520000 53FFFF

104 D00000 D1FFFF 40 500000 51FFFF

103 CE0000 CFFFFF 39 4E0000 4FFFFF

102 CC0000 CDFFFF 38 4C0000 4DFFFF

101 CA0000 CBFFFF 37 4A0000 4BFFFF

100 C80000 C9FFFF 36 480000 49FFFF

99 C60000 C7FFFF 35 460000 47FFFF

98 C40000 C5FFFF 34 440000 45FFFF

97 C20000 C3FFFF 33 420000 43FFFF

96 C00000 C1FFFF 32 400000 41FFFF

95 BE0000 BFFFFF 31 3E0000 3FFFFF

94 BC0000 BDFFFF 30 3C0000 3DFFFF

93 BA0000 BBFFFF 29 3A0000 3BFFFF

92 B80000 B9FFFF 28 380000 39FFFF

91 B60000 B7FFFF 27 360000 37FFFF

90 B40000 B5FFFF 26 340000 35FFFF

89 B20000 B3FFFF 25 320000 33FFFF

88 B00000 B1FFFF 24 300000 31FFFF

87 AE0000 AFFFFF 23 2E0000 2FFFFF

86 AC0000 ADFFFF 22 2C0000 2DFFFF

85 AA0000 ABFFFF 21 2A0000 2BFFFF

84 A80000 A9FFFF 20 280000 29FFFF

83 A60000 A7FFFF 19 260000 27FFFF

82 A40000 A5FFFF 18 240000 25FFFF

81 A20000 A3FFFF 17 220000 23FFFF

80 A00000 A1FFFF 16 200000 21FFFF

79 9E0000 9FFFFF 15 1E0000 1FFFFF

78 9C0000 9DFFFF 14 1C0000 1DFFFF

77 9A0000 9BFFFF 13 1A0000 1BFFFF

76 980000 99FFFF 12 180000 19FFFF

75 960000 97FFFF 11 160000 17FFFF

74 940000 95FFFF 10 140000 15FFFF

73 920000 93FFFF 9 120000 13FFFF

72 900000 91FFFF 8 100000 11FFFF

Ta ble 20: Memory Organization (Continued)

Sector Address Range Sector Address Range

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128Mb: P8P Parallel PCM

Serial Peripheral Interface (SPI)

SPI Instruction

Serial data input D is sampled on the first rising edge of serial clock (C) after chip select

(S#) is driven LOW. Then, the one-byte instruction code must be shifted in to the device,

most significant bit first, on serial data input DQ0, each bit being latched on the rising

edges of C. The instruction set is listed in Table 21 on page 35.

Every instruction se quence starts w ith a one-byte instruc ti o n cod e. Depending on the

instruction, this might be followed by address bytes, or by data bytes, or by both or none.

In the case of a read data bytes (READ), read data bytes at higher speed (FAST_READ),

re ad status register (RDSR ), or read ident ification (RDID) instruction, the shifted-in

instruction sequence is followed by a data-out sequence. S# can be driven HIGH after

any bit of the data-out sequence is being shifted out.

In the case of a page program (PP), sec tor erase (SE), write status register (WRSR), write

enable (WREN ), or w rite disable (WRDI), S# must be dri ven HIGH exactly at a byte

boundar y, otherwis e the instruction is rejected and is not executed. That is, S# must

driven HIGH when the number of clock pulses after S# being driven LOW is an exact

multiple of eight.

All attempts to access the memory array during a WRITE STATUS REGISTER cycle,

PROGRAM cycle, adn ERASE cycle are ignored, and the internal WRITE STATUS

Note: Output High-Z is defined as the point where data out is no longer driven.

71 8E0000 8FFFFF 7 0E0000 0FFFFF

70 8C0000 8DFFFF 6 0C0000 0DFFFF

69 8A0000 8BFFFF 5 0A0000 0BFFFF

68 880000 89FFFF 4 080000 09FFFF

67 860000 87FFFF 3 060000 07FFFF

66 840000 85FFFF 2 040000 05FFFF

65 820000 83FFFF 1 020000 03FFFF

64 800000 81FFFF 0 000000 01FFFF

Table 21: Instruction Set

Instruction Description One-byte Instruction Code Address

Bytes Dummy

Bytes Data

Bytes

WREN Write enable 0000 0110 06h 0 0 0

WRDI Write disable 0000 0100 04h 0 0 0

RDID Read identification 1001 1111 9Fh 0 0 1 to 3

RDSR Read status register 0000 0101 05h 0 0 1 to 

WRSR Write status register 0000 0001 01h 0 0 1

READ Read data bytes 0000 0011 03h 3 0 1 to 

FAST_READ Read data bytes at higher speed 0000 10 11 0Bh 3 1 1 to 

PP Page program (legacy program) 0000 0010 02h 3 0 1 to 64

Page program (bit-alterable write) 0010 0010 22h 3 0 1 to 64

Page program (On all 1s) 1101 0001 D1h 3 0 1 to 64

SE Sector erase 1101 1000 D8h 3 0 0

Ta ble 20: Memory Organization (Continued)

Sector Address Range Sector Address Range

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128Mb: P8P Parallel PCM

Serial Peripheral Interface (SPI)

WRITE ENABLE (WREN)

The WRITE ENABLE (WREN) instruction sets the write enable latch (WEL) bit.

The write enable latch (WEL) bit must be set prior to every PAGE PROGRAM (PP),

SECTOR ERASE (SE), or WRITE STATUS REGISTER (WRSR) instru ction.

The WREN instruction is entered by driving S# LOW, sending the instruction code and

then driving S# HIGH.

Figure 9: WRITE ENABLE (WREN) Instruction Sequence

WRITE DISABLE (WRDI)

The WRITE DISABLE (WRDI) instruction resets the write enable latch (WEL) bit.

The WRDI instruction is entered by driving S# LOW, sending the instruction code and

then driving S# HIGH.

The write enable latch (WEL) bit is reset under the following conditions:

•Power-up

• WRDI instruction completion

• WRSR instruction completion

• PP instruction completion

• SE instruction completion

Figure 10: WRITE DISABLE (WRDI) Instruction Sequence

DQ0

2134567

Command

DQ1 High-Z

DQ0

2134567

Command

DQ1 High-Z

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128Mb: P8P Parallel PCM

Serial Peripheral Interface (SPI)

READ IDENTIFICATION (RDID)

The READ IDENTIFICATION (RDID) instruction allows to read the device identification

data:

• Manufacturer identification (1 b y te)

• Device identification (2 bytes)

The manufacturer identification is assigned by JEDEC and has the value 20h for Micron.

Any RDID instruction while an ERASE or PR OGR AM cycle is in progress, is not decoded,

and has no effect on the cycle that is in progress.

The device is first se le cted by driving S# LOW. Then, the 8-bit instruction code for the

instructi o n is shifted in. After this, the 24-bi t device identification stored in the memory

will be shifted out on serial data output (DQ1). Each bit is shifted out during the falling

edge of C.

The RDID instruction is terminated by driving S# HIGH at any time during data output.

When S# is driven HIGH, the device is put in the standby power mode. Once in the

standby power mode, the device waits to be selected, so that it can receive, decode and

execute instructions.

Figure 11: READ IDENTIFICATION (RDID) Instruction Sequence and Data-Out Sequence

Read Status Register (RDSR)

The READ STATUS REGISTER (RDSR) instruction allows the status register to be read.

The status register may be read at any time, even while a PROGRAM, ERASE, WRITE

STATUS REGISTER is in progress . When one of these cycles is in progress, it is recom-

mended to check the write in progress (WIP) bit before sending a new instruction to the

device . I t is also possi ble to r ead the status re gister continuousl y, as sho wn in Fig ure8 on

page 32

RDSR is the only instruction accepted by the device whil e a PROG RAM, ERASE, WRITE

STATUS REGISTER operation is in progr ess.

15 14 13 3 210

DQ0

2134 5 6 7 8 9 10 11 12 13 14 15

Command

DQ1

Manufacturer identification

High-Z

MSB

Device identification

MSB

16 17 18 28 29 30 31

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128Mb: P8P Parallel PCM

Serial Peripheral Interface (SPI)

The status and control bits of the status register are as follo ws:

WIP Bit

The write in progress (WIP) bit indicates whether the memor y is busy with a WRITE

STATUS REGISTER, PROGRAM, ERASE cycle. When set to 1, such a cycle is in progress,

when reset to 0 no such cycle is in progress.

While WIP is 1, RDSR is the only instruction the device will accept; all other instructions

are ignored.

WEL Bit

The write enable latch (WEL) bit indicates the status of the internal write enable latch.

When set to 1, the internal write enable latch is set; when set to 0, the internal write

enable latch is reset, and no WRITE STATUS REGISTER, PROGRAM, ERASE instruction

is accepted.

BP3, BP2, BP1, BP0 Bits

The block protect bits (BP3, BP2, BP1, BP0) are nonvolatile. They define the size of the

area to be software protected against PROGRAM (or WRITE) and ERASE instructions.

These bits are written with the WRSR instruction. When one or more of the block protect

bits is set to 1, the relevant memory area (as defined in Table 1) becomes protected

against PP, DIFP, QIFP, and SE instructions. The block protect bits can be written

provided that the hardware protected mode has not been set.The bulk erase (BE)

instruction is executed if, and only if, all block protect bits are 0.

Table 22: Status Register Format

b7 b0

SRWD BP3 TB BP2 BP1 BP0 WEL WIP

Status regist er write protect RFU RFU Write enable latch bit

Write in progress bit

Table 23: Protected Area Sizes

Status Register Contents Memory Content

Bit BP

Bit 3 BP

Bit 2 BP

Bit 1 BP

Bit 0 Protected Area Unprotected Area

0 0 0 0 0 None All sectors1 (sectors 0 to 12 7)

0 0 0 0 1 Upper 128th (sector 127) Sectors 0 to 126

0 0 0 1 0 Upper 64th (sectors 126 to 127 ) Sectors 0 to 125

0 0 0 1 1 Upper 32nd (sector s 124 to 127) Sectors 0 to 123

0 0 1 0 0 Upper 16th (sectors 120 to 127 ) Sectors 0 to 119

0 0 1 0 1 Upper 8th (sectors 112 to 127) Sectors 0 to 111

0 0 1 1 0 Upper quarter (sectors 96 to 127) Sec tors 0 to 95

0 0 1 1 1 Upper half (sectors 64 to 127) Sectors 0 to 63

01X

2X2X2All sectors (sectors 0 to 127) None

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128Mb: P8P Parallel PCM

Serial Peripheral Interface (SPI)

Notes: 1. The device is ready to accept a bulk erase instruction if all block protect bits (BP3, BP2, BP1,

BP0) are 0.

2. X can be 0 or 1.

Top/Bottom Bit

The top/bottom bit reads as 0.

SRWD Bit

The status register write disable (SRWD) bit is operated in conjunction with the write

protect (W) signal. The status register write disable (SRWD) bit and the W signal allow

the device to be put in the hardware protected mode (when the status register write

disable (SR WD) bit i s set to 1, and W is drive n LO W). I n this mode, the nonvolatile bits of

the status register (SRWD, TB, BP3, BP2, BP1, BP0) become read-only bits and the write

status register (WRSR) instruction is no longer accepted for execution.

Figure 12: READ STATUS REGISTER (RDSR) Instruction Sequence and Data-Out Sequence

WRITE STATUS REGISTER (WRSR)

The WRITE STATUS REGISTER (W RSR ) instr uction allows new values to be written to

the status register. Before it can be accepted, a WREN instruction must previo usly have

been executed. After the WREN instruction has been decoded and executed, the devi ce

sets the write enable latch (WEL).

1 0 0 0 0 None All sectors1 (sectors 0 to 12 7)

1 0 0 0 1 Lower 128th (sector 0) Sectors 1 to 127

1 0 0 1 0 Lower 64th (sectors 0 to 1) Sectors 2 to 127

1 0 0 1 1 Lower 32nd (sectors 0 to 3) Sectors 4 to 127

1 0 1 0 0 Lower 16th (sectors 0 to 7) Sectors 8 to 127

1 0 1 0 1 Lower 8th (se ctors 0 to15) Sectors 16 to 127

1 0 1 1 0 Lower 4th (sectors 0 to 31) Sectors 32 to 127

1 0 1 1 1 Lower half (sectors 0 to 63) S e ctors 64 to 1 27

11X

2X2X2All sectors (sectors 0 to 127) None

Ta ble 23: Protected Area Sizes (Continued)

Status Register Contents Memory Content

Bit BP

Bit 3 BP

Bit 2 BP

Bit 1 BP

Bit 0 Protected Area Unprotected Area

6543210

76543210

DQ0

2134 5 6 7 8 9 10 11 12 13 14 15

Command

DQ1

Status register out

High-Z

MSB

Status register out

MSB

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128Mb: P8P Parallel PCM

Serial Peripheral Interface (SPI)

The WRSR instruction is entered by driving S# LOW, followed by the instruction code

and the data byte on serial data input (DQ0).

The WRSR instruction has no effect on b1 and b0 of the status register.

S# must be driven HIGH after the eighth bit of the data byte has been latched in. If not,

the WRSR instruction is not executed. As soon as S# is driven HIGH, the self-timed

WRITE STATUS REGISTER cycle (whose duration is tW) is initiated. While the WRITE

STATUS REGISTER cycle is in progress, the status register may still be read to check the

value of the write in progress (WIP) bit. The WIP bit is 1 during the self-timed WRITE

STATUS REGISTER cycle, and is 0 when it is completed. When the cycle is completed,

the WEL is reset.

The WRSR instruction allows the user to change the values of the block protect bits to

define the size of the area that is to be treated as read-only. The WRSR instruction also

allo ws the user to set and reset the SR WD bit in accor dance with the W signal. The SR WD

bit and W signal allow the device to be put in the hardware protected mode (HPM). The

WRSR instruction is not executed once the hardware protected mode (HPM) is entered.

RDSR is the only instruction accepted while WRSR operation is in progress; all other

instructions are ignored.

Figure 13: WRITE STATUS REGISTER (WRSR) Instruction Sequence

Read Data Bytes (READ)

The device is first selected by driving S# LOW. The instruction code for the READ

instruction is followed by a 3-byte address A[23:0], each bit being latched-in during the

rising edge of C. Then the memory contents, at that address, is shifted out on serial data

output (Q), each bit being shifted out, at a maximum frequency fR, during the falling

edge of C.

The first byte addressed can be at any location. The address is automatically incre-

mented to the next higher address after each byte of data is shifted out. The whole

memory can, therefore, b e read with a single R E AD ins truction. Whe n th e hig h e st

address is reached, the address counter rolls over to 000000h, allowing the read

sequence to be cont inue d in de finitely.

The READ instructi o n is terminated by driving S# HIGH. S# can be driven HIGH at any

time during data output. Any READ instru ction, while an ERASE, PROGRAM, WRITE

cycle is in prog ress, is r ejected without having any effects on the cycle that is in progress.

76543210

DQ0

2134 5 6 7 8 9 10 11 12 13 14 15

Command

DQ1

Status

High-Z MSB

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128Mb: P8P Parallel PCM

Serial Peripheral Interface (SPI)

Figure 14: Read Data Bytes (READ) Instruction Sequence and Data-Out Sequence

Read Data Bytes at Higher Speed (FAST_READ)

The device is first selected by driving S# LOW. The instruction code for the r ead data

bytes at higher speed (FAST_READ) instruction is followed by a 3-byte address A[23:0]

and a dummy byte, each bit being latched-in during the rising edge of C. Then the

memory contents, at that address, ar e shifted out on Q at a maximum frequency fC,

during the falling edge of C.

The first byte addressed can be at any location. The address is automatically incre-

mented to the next higher address after each byte of data is shifted out. The whole

memory can, therefore, be read with a single FAST_REA D ins truction. When the highe s t

address is reached, the address counter rolls over to 000000h, allowing the read

sequence to be cont inue d in de finitely.

The FAST_READ instructi on is terminated b y driving S# H IGH. S# can be driven HIGH at

any time during data output. Any FAST_READ instruction, while an ERAS E, PROGRAM,

or WRITE cycle is in progress , is rejected without having any effects on the cycle that is in

progress.

76543210

23 22 21 3210

DQ0

21345678910

Command

DQ1

MSB

High-Z Data-out 1

MSB

28 29 30 31 32 33 34 35 36 37 38 39

Data-out 2

24-bit address

note 1

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128Mb: P8P Parallel PCM

Serial Peripheral Interface (SPI)

Figure 15: FAST_READ Instruction Sequence and Data-Out Sequence

PAGE PROGRAM (PP)

Note: The following description of PAGE PROGRAM applies to all instances of PP, including

legacy program and bit alterable.

The PP instruction allows bytes to be programmed/written in the memory. Before it can

be accepted, a WREN instruction must previously have been executed. After the WREN

instruction has been decoded, the device sets the WEL.

The PP instruction is entered by driving S# LOW, followed by the instruction code, three

address bytes, and at least one data byte on serial data input (DQ0). If the six least signif-

icant address bits (A[5:0]) are not all zero, all transmitted data that goes beyond the end

of the current page are programmed from the start address of the same page (from the

address whose six least significant bits (A[5:0]) are all zero). S# must be driven LOW for

the entire duration of the sequence.

If more than 64 bytes are sent to the device, previously latched data are discarded and

the last 64 data bytes are guaranteed to be programmed/written correctly within the

same page. If fewer than 64 data bytes are sent to device, they are correctly

programmed/written at the re quested addresses without having any effects on the other

b ytes of the same page. (With PROGRAM ON ALL 1s, the entire page should already have

been set to all 1s (FFh).)

For optimized timings, it is recommended to use the PP instruction to program all

consecutive targeted bytes in a single sequence versus using several PP sequences with

each containing on ly a few bytes.

7654321076543210

76543210

DQ0

3433 35 36 37 38 39 40 41 42 43

Dummy cycles

DQ1

Data-out 1

MSB MSB MSB

44 45 46 47

Data-out 2

23 22 21 3210

DQ0

21345678910

Command

DQ1 High-Z

28 29 30 31

24-bit address

note 1

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128Mb: P8P Parallel PCM

Serial Peripheral Interface (SPI)

S# must be driven HIGH after the eighth bit of the last data byte has been latched in,

otherw is e the PP instruction is not executed .

As soon as S# is driven HIGH , the self-timed PAGE PROGRAM cycl e (whose duration is

tPP) is initiated. While the PAGE PROGRAM cycle is in progress, the status register may

be read to check the value of the WIP bit. The WIP bit is 1 during the self-timed PAGE

PROGRAM cycle, and is 0 when it is completed. At some unspecified time before the

cycle is completed, the WEL bit is reset. RDSR is the only instruction accepted while a

PAGE PROGRAM operation is in progress; all other instructions are ignored.

Figure 16: PAGE PROGRAM (PP) Instruction Sequence

SECTOR ERASE (SE)

The SECTOR ERASE (SE) instruction sets to 1 (FFh) all bits inside the chosen sector.

Before it can be accepted, a WREN instruction must previously have been executed.

After the WREN instruction has been decoded, the device sets the WEL.

The SE instruction is entered by driving S# LOW, followed by the instruction code, and

three addr ess by tes on DQ0. Any addr ess inside the sector is a valid address for the SE

instruction. S# must be driven LOW for the entire duratio n of the sequence.

S# must be driven HIGH after the eighth bit of the last address byte has been latche d in,

otherwise the SE instruction is not executed. As soon as S# is driven HIGH, the self-

timed SE cycle (whose duration is tSE) is initiated. While the SE cycle is in progress, the

status register may be read to check the value of the WIP bit. The WIP bit is 1 during the

self-timed SE cycle and is 0 wh en it is completed. At some unspe ci fie d time before the

cycle is completed, the WEL bit is reset. RDSR is the only instruction accepted while

device is busy with ERASE operation; all other in structions are ignored.

An SE instructio n appl ie d to a page which is protected by the block protect bits is not

executed.

DQ0

48 49 50 51

Data byte 2

MSB MSB

MSB

52 53 54 55

2072

2074

2075

2076

2077

2078

2079

40 41 42 43 44 45 46 47

Data byte 3

23 22 21 32103210

7654

3210

7654

Data byte 64

3210

7654

3210

7654

DQ0

21345678910

Command

028 29 30 31 32 33 34 35 36 37 38 39

Data byte 1

24-bit address

note 1

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128Mb: P8P Parallel PCM

Power and Reset Specification

Figure 17: SECTOR ERASE (SE) Instruction Sequence

Power and Reset Specification

Power-Up and Power-Down

Upon power-up the Flash memory interface is defined by the SERIAL pin being at VSS

(parallel) or VCC (serial).

• During power-up if the SERIAL pin is at VSS the Flash memory will be a x16 parallel

interface.

• During power-up if the SERIAL pin is at VCC the Flash memory will be a SPI interface.

After the interface is defined it can not be changed until a full power-down is completed

and a po wer-u p se quence is reinitiated.

Power supply sequ encing is not required if VPP is connected to VCC or VCCQ. Otherwise

VCC and VCCQ should attain their minimum operating voltage before applying VPP

Power supply transitions should only occur when RST# is LOW. This protec ts the device

from accidental programming or erasure during power transitions .

Reset Specifications

Asserting RST# during a system reset is important with automated program/erase

devices because sys te ms typically expec t to read from Flash memory when coming out

of RESET. If a CPU reset occurs without a Flash memory reset, prope r CPU initialization

may not occur. This is because the Flash memory may be providing status information,

instead of array data as expected. Connect RST# to the same active LOW RESET signal

used for CPU initialization.

Also, because the device is disabled when RST# is asse rted, it ignores its contro l inputs

during po wer -up/do wn. I nvalid bus conditions ar e masked, providing a level of memory

protection.

Notes: 1. These specifications are valid for all device versions (packages and speeds).

2. The device may reset if tPLPH is < tPLPH MIN, but this is not guaranteed.

3. Not applicable if RST# is tied to VCC.

Ta ble 24: Power and Reset

Num Symbol Parameter1Min Max Unit Notes

P1 tPLPH RST# pulse width LOW 100 - ns 1, 2, 3, 4

P2 tPLRH RST# LOW to device reset during erase - 40 us 1, 3, 4, 7

RST# LOW to device reset during program - 40 1, 3, 4,7

P3 tVCCPH VCC power valid to RST# de-assertion (HIGH) 100 - 1, 4, 5, 6

23 22 210

DQ1

213456789

Command

MSB

29 30 31

24-bit address

note 1

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128Mb: P8P Parallel PCM

Power and Reset Specification

4. Sampled, but not 100% tested.

5. When RST# is tied to the VCC supply, device will not be ready until tVCCPH after VCC  VCC-

MIN.

6. When RST# is tied to the VCCQ supply, device will not be ready until tVCCPH after VCC  VCC-

MIN.

7. Reset completes within tPLPH if RST# is asserted while no ERASE or PROGRAM operation is

executing.

Figure 18: Reset Operation Waveforms

Power Supply Decoupling

Flash memory devices require careful power supply de-coupling. Three basic power

supply current considerations are standby curre n t levels, active current levels, and tran-

sient peaks produced when CE# and OE# are asserted and de-asserted.

When the device is accessed, many internal conditions change. Circuits within the

device enable charge-pumps, and internal logic states change at high speed. All of these

internal activities produce transient signals. Transient current magnitudes depend on

the device outputs’ capacitive and inductive loading. Two-line control and correct de-

coupling capacitor selection suppress transient voltage peaks.

Flash memory devices draw their powe r from VCC and VCCQ; each po wer connection

should have a 0.1µF cer amic capac itor to ground. H igh-fr equency, inherently lo w-induc-

tance capacitors should be placed as close as possible to package leads.

Additionally, for every eight devices used in the system, a 4.7µF electrolytic capacitor

should be placed between power and ground close to the devices. The bulk capacitor is

meant to overcome voltage droop caused by PCB trace inductance.

(A) Reset during

read mode VIH

VIL

RST# [P]

(D) VCC power-up to

RST# HIGH

tPLPH tPHQV

tPHQV

VCC

tVCCPH

(B) Reset during

program or block erase

P1 ≤ P2

VIH

VIL

RST# [P]

Abort

complete

Abort

complete

tPLRH

program or block erase

P1 ≥ P2

VIH

VIL

RST# [P]

tPLRH

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128Mb: P8P Parallel PCM

Maximum Ratings and Operating Conditions

Absolute Maximum Ratings

Stresses greater than those listed in Tabl e 25 may cause per manent damage to the

device. This is a stress rating onl y, and functional operation of the device at these or any

other conditions outside those ind icated in the oper ational secti ons of this specification

is not implied. Exposure to absolute maximum rating conditions for extended periods

may adversely affect reliability.

Notes: 1. All specified voltages are with respect to VSS. During infrequent non-periodic transitions,

the voltage potential between VSS and input/output pins may undershoot to –2.0V for peri-

ods < 20ns or overshoot to VCCQ + 2.0Vfor periods < 20ns.

2. During infrequent non-periodic transitions, the voltage potential between VSS and the sup-

plies may undershoot to –2.0V for periods < 20ns or overshoot to supply voltage (max) +

2.0V for periods < 20ns.

3. Output shorted for no more than one second. No more than one output shorted at a time.

4. For functional operating voltage s, please refer to “DC Voltage Characteristics” on page 48.

5. Make sure that VCCQ is less or equal to VCC in value, otherwise the device fails to operate

correctly in the next revision of the data sheet.

Operating Conditions

Operation beyond the operating conditions is not reco mm e n de d , and extended expo-

sure may affect device reliability.

Notes: 1. TC = case temperature.

2. VCCQ = 1.7–3.6V range is intended for CMOS inputs and the 2.4–3.6V is intended for TTL

inputs.

3. In typical operation VPP program voltage is VPPL.

4. Data retention for Micron PCM is 10 years at 70°C. For additional documentation about

data retention, contact your local Micron sales representative.

Ta ble 25: Absolute Maximum Ratings

Parameter Maximum Rating

Voltage on any signal (except VCC, VCCQ, VPP)1–2.0V to +5.6V, < 20ns

VPP voltage2, 4 –2.0V to +5.6V, < 20ns

VCC voltage2, 4 –2.0V to +5.6V, < 20ns

VCCQ voltage2, 4, 5 –2.0V to +5.6V, < 20ns

Output short circuit current3100mA

Table 26: Operating Conditions

Symbol Parameter Min Max Units Notes

TCOperating temperature (115ns) 0 70 °C 1

TCOperating temperature (135 ns) –40 85 °C

VCC VCC supply voltage 2.7 3.6 V

VCCQ I/O supply voltage CMOS inputs 1.7 3.6 2

TTL inputs 2.4 3.6

VPP VPP voltage supply (logic level) 0.9 3.6 3

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128Mb: P8P Parallel PCM

Electrical Specifications

Endurance

P8P parallel PCM endurance is differ ent than tr aditional nonvol atile memory. F or PCM a

WRITE cycle is defined as any time a bit changes within a 32-byte page.

Notes: 1. In typical operation VPP program voltage is VPPL.

Electrical Specifications

DC Current Characteristics

Notes: 1. Refer Table 29 on page 48 for the notes relevant to this table.

Ta ble 27: Endurance

Parameter Condition Min Units Notes

Write cycle Main block (VPP = VPPH)1,000,000 Cycles per

32-byte page 1

Parameter block (VPP = VPPH)1,000,000

Table 28: DC Current Characteristics

Sym Parameter1Note

CMOS

Inputs

VCCQ

1.7–3.6V

TTL Inputs

VCCQ

2.4–3.6V

Unit Test ConditionTyp Max Typ Max

ILI Input load 9 – ±1 – ±2 µA VCC = VCCMAX

VCCQ = VCCQMAX

VIN = VCCQ or GND

ILO Output

leakage DQ[15:0] – – ±1 – ±10 µA VCC = VCCMAX

VCCQ = VCCQMAX

VIN = VCCQ or GND

ICCS

ICCD

VCC

standby,

power-

down

128Mb 11 80 160 80 160 µA VCC = VCCMAX, VCCQ = VCCQMAX

CE# = VCCQ, RST# = VCCQ

WP# = VIH

Must reach stated ICCS µs

after CE# = VIH

ICCR Average

VCC

READ

Asynchronous sing le

word

f = 5 MHz (1 CLK)

– 30423042mAInternal 8-word

READ VCC = VCCMAX

CE# = VIL

OE# = VIH

Inputs: VIH or

VIL

Page mode

f = 13 MHz (9 CLK) – 15 20 15 20 mA 8-word READ

ICCW,

ICCE

VCC WRITE,

VCC ERA SE 3,4,5,

12 35 50 36 51 mA PROGRAM/ERASE in progress

ICCWS

ICCES

VCC WRITE SUSPEND

VCC ERASE SUSPEND 6Refer to I

CCS for each density

above. µA CE# = VCCQ, SUSPEND in

progress

IPPS

IPPWS

IPPES

VPP STANDBY

VPP WRITE SUSPEND

VPP ERASE SUSPEND

30.250.25µAV

PP = VPPL, SUSPEND in progress

IPPR VPP READ – 215215µA V

PP  VCC

IPPW VPP WRITE 3 0.05 0.10 0.05 0.10 mA WRITE in progress

IPPE VPP ERASE 3 0.05 0.10 0.05 0.10 mA ERASE in progress

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128Mb: P8P Parallel PCM

AC Characteristics

DC Voltage Characteristics

Notes: 1. VPP; VPPLK inhibits ERASE and WRITE operations. Don’t use VPP outside the valid range.

2. VIL can undersh oot to –1.0V for duration s of 2ns or less and VIH can overshoot to

VCCQ(MAX)+1.0V for durations of 2 ns or less.

AC Characteristics

AC Test Conditions

Figure 19: AC Input/Output Reference Waveform

Notes: 1. AC test inputs are driven at VCCQ for logic 1 and 0.0V for logic 0. Input/output timing

begins/ends at VCCQ/2. Input rise and fall times (10% to 90%) < 5ns. Worst-case speed occurs

at VCC = VCC,min.

Figure 20: Transient Equivalent Testing Load Circuit

Table 29: DC Voltage Characteristics

Sym Parameter Notes

CMOS Inputs

VCCQ

1.7–3.6V

TTL Inputs

VCCQ

2.4–3.6V

Unit Test ConditionMin Max Min Max

VIL Input LOW 2 0 0.4 0 0.6 V

VIH Input HIGH 2 VCCQ – 0.4 VCCQ 2.0 VCCQ V

VOL Output LOW – 0.1 0 .1 V VCC = VCC,min

VCCQ = VCCQ,min

IOL = 100µA

VOH Output HIGH VCCQ – 0.1 – VCCQ – 0.1 – V VCC = VCC,min

VCCQ = VCCQ,min

IOH = –100µA

VPPLK VPP lock out 1 – 0.4 – 0.4 V

VLKO VCC lock 1.5 – 1.5 – V

VLKOQ VCCQ lock 0.9 – 0.9 – V

Input VCC/2 VCC/2 Output

VCC

Test Points

VIH

VIL

Device under

test Out

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128Mb: P8P Parallel PCM

AC Characteristics

Capacitance

Notes: 1. Sampled, not 100% tested.

AC Read Specifications

Notes: 1. See Figure 19 on pa ge 48 for timing measurements and maximum allowable input slew

rate.

2. OE# may be delayed by up to tELQV – tGLQV after CE#’s falling edge without impact to

tELQV.

3. Sampled, not 100% tested.

4. All specs apply to all densities.

Table 30: Test Configuration Component Value for Worst-Case Speed Conditions

Test Configuration CL (pF) (includes jig capacitance)

VCCQ,min 30

Ta ble 31: Capacitance: TA = 25°C, f = 1 MHz1

Symbol Parameter1Min Typ Max Unit Condition

CIN Input capacitance 2 6 8 pF VIN = 0.0V

COUT Output capacitance 2 4 7 pF VOUT = 0.0V

Table 32: AC Read Specifications

Number Symbol Parameter1

0°C to 70°C –40°C to 85°C

Units NotesMin Max Min Max

R1 tAVAV Read cycle time 115 – 135 – ns 1, 4

R2 tAVQV Address to output valid –115–135ns1, 4

R3 tELQV CE# LOW to output valid –115–135ns1, 4

R4 tGLQV OE# LOW to output valid – 25 – 25 ns 1, 2, 4

R5 tPHQV RST# HIGH to output valid –150–150ns1, 4

R6 tELQX CE# LOW to output in Low-Z 0–0–ns3, 4

R7 tGLQX OE# LOW to output in Low-Z 0–0–ns1, 2, 3,

R8 tEHQZ CE# HIGH to output in High-Z – 24 – 24 ns 1, 3, 4

R9 tGHQZ tOE# HIGH to output in High-Z – 24 – 24 ns 1, 3, 4

R10 tOH Output hold from first occurring address,

CE#, or OE# change 0–0–ns1, 3, 4

R11 tEHEL CE# pulse width high 20 – 20 – ns 1, 4

R108 tAPA Page address access –25–25ns

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128Mb: P8P Parallel PCM

AC Characteristics

Figure 21: Asynchronous Single-Word Read

Figure 22: Asynchronous Page Mode Read Timing

AC Write Specifications

Table 33: AC Write Characteristics

Num Sym Parameter1, 2

All Speeds

NotesMin Max Units

W1 tPHWL RST# high recovery to WE# LOW 150 – ns 3

W2 tELWL CE# setup to WE# LOW 0–ns10

W3 tWLWH WE# write pulse width LOW 50 – ns 4

W4 tDVWH Data setup to WE# HIGH 50 – ns

W5 tAVWH Address valid setup to WE# HIGH 50 – ns

W6 tWHEH CE# hold from WE# HIGH 0–ns10

W7 tWHDX Data hold from WE# HIGH 0–ns

W8 tWHAX Address hold from WE# HIGH 0–ns

W9 tWHWL WE# pulse width HIGH 20 – ns

Address

tAVAV

CE#

OE#

RST#

tAVQV

tELQV

tGLQV

tGLQX

tELQX

tPHQV

tEHQZ

tGHQZ

tOH

Address

A[3:1]

AVAV

CE#

OE#

AVQV

ELQV

GLQV

APA

ELQX

Q1 Q2 Q3 Q7

EHQZ

GHQZ

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128Mb: P8P Parallel PCM

AC Characteristics

Notes: 1. Write timing characteristics during ERASE SUSPEND are the same as write-only operations.

2. CE#- or WE#-high terminates a WRITE operation.

3. Sampled, not 100% tested.

4. Write pulse width low (tWLWH or tELEH) is defined from CE# or WE# LOW (whichever

occurs last) to CE# or WE# HIGH (whichever occurs first). Hence , tWLWH = tELEH = tWLEH =

tELWH.

5. Write pulse width HIGH (tWHWL or tEHEL) is defined from CE# or WE# HIGH (whichever is

first) to CE# or WE# LOW (whichever is last). Hence, tWHWL = tEHEL = tWHEL = tEHWL.

6. VPP and WP# should be at a valid level without changing state until erase or program suc-

cess is determined.

7. This spec is only applicable when transitio ning from a W RITE cycle to an asynchronous read.

8. When doing a READ STATUS operation following any command that alters the status regis-

ter contents, W14 is 20ns.

9. Add 10ns if the WRITE operation results in a block lock status change, for subse quen t READ

operations to reflect this change.

10. Guaranteed by design.

Figure 23: Write-to-Write Timing

W10 tVPWH VPP setup to WE# HIGH 200 – ns 3,6

W11 tQVVL VPP hold from valid status read 0 – ns 3,6

W12 tQVBL WP# hold from valid status read 0 – ns 3,6

W13 tBHWH WP# setup to WE# HIGH 200 – ns 3,6

W14 tWHGL WE# HIGH to OE# LOW 0 – ns 8

W16 tWHQV WE# HIGH to read valid tAVQV+35 – ns 3, 5, 9

Write to Asynchronous Read Specifications

W18 tWHAV WE# HIGH to address valid 0 – ns 3, 5, 7

Table 33: AC Write Characteristics (Con tinued)

Num Sym Parameter1, 2

All Speeds

NotesMin Max Units

tWHEH

tELWL tELWL

Address

CE#

WE#

RST#

WP#

OE#

tWHAV

tAVWH

tWHWL

tWLWH tWLWH

tWHAV

tAVWH

tDVWH tWHDX

tPHWL

tDVWH tWHDX

tBHWH

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128Mb: P8P Parallel PCM

AC Characteristics

Figure 24: Asynchronous Read to Write Timing

Notes: 1. See AC Read Characteristics and AC Write Characteristics sections for the values of Rs and

Ws.

Figure 25: Write to Asynchronous Read Timing

Notes: 1. See AC Read Characteristics and AC Write Characteristics sections for the values of Rs and

Ws.

tELQV tEHQZ

tGHQZ

tWHEH

tWHDX

tWLWH

tELWL

Address

OE#

CE#

RST#

WE#

tAVAV

tAVQV

tGLQV

tWHAX

tAVWH

tELQX

tGLQX

tPHQV

tDVWH

tOH

tELQV tEHQZ

tGHQZ

tWHEH

tWHAV

tWHDX

tWHGL

tWLWH

tELWL

Address

WE#

CE#

RST#

OE#

tAVAV

tAVQV

tGLQV

tWHAX

tAVWH

tPHWL

tDVWH

tOH

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128Mb: P8P Parallel PCM

AC Characteristics

SPI AC Specifications

Notes: 1. TCH + TCL must be greater than or equal to 1/fC(max).

2. Sampled, not 100% tested.

3. Expressed as a slew rate.

4. Only applicable as a constraint for a WRSR instruction when SRWD is set to 1.

Table 34: SPI AC Specifications

Sym Parameter

Speed All Speeds

UnitsNote Min Max

fCClock frequency for all instructions except READ (0°C to 70°C) DC 50 MHz

fCClock frequency for all instructions except READ (–40°C to 85°C) DC 33 MHz

fRClock frequency for READ DC 25 MHz

tCH Clock high time 19–ns

tCL Clock low time 19–ns

tCLCH Clock rise time (peak to peak) 2, 3 0.1 – V/ns

tCHCL Clock fall time (peak to peak) 2, 3 0.1 – V/ns

tSLCH S# active setup time (relative to C) 5–ns

tCHSL S# active hold time (relative to C) 5–ns

tDVCH Data input setup time 2–ns

tCHDX Data input hold time 5–ns

tCHSH S# active hold time (relative to C) 5–ns

tSHCH S# inactive hold time (relative to C) 5–ns

tSHSL S# deselect time 100 – ns

tSHQZ Output disable time 2–8ns

tCLQV Clock low to output vali d –9ns

tCLQX Output hold time 0–ns

tHLCH HOLD# assertion setup time (relative to C) 5–ns

tCHHH HOLD# assert ion hold time (relative to C) 5–ns

tHHCH HOLD# de-ass e r tion setup time (relative to C) 5–ns

tCHHL HOLD# de-assertion hold time (relative to C) 5–ns

tHHQX HOLD# de-assertion to output Low-Z 210ns

tHLQZ HOLD# de-assertion to output High-Z 210ns

tWHSL W# setup time 420–ns

tSHWL W# hold time 4100–ns

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128Mb: P8P Parallel PCM

AC Characteristics

Figure 26: Serial Input Timing

Figure 27: Write Protect Setup and Hold Timing during WRSR when SRWD = 1

Figure 28: Hold Timing

tSLCH

tCHSL

tDVCHtCHDX

tCHSHtSHCH

tSHSL

DQ0

MSBLSB

High-Z

DQ0

DQ1

WHSL

SHWL

tHLCH

tCHHL tHHCH

tHLQZ

tCHHH tHHQX

DQ0

DQ1

HOLD#

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128Mb: P8P Parallel PCM

Pr ogram and Erase Characteristics

Figure 29: Output Timing

Program and Erase Characteristics

Notes: 1. Typical values measured at TA = 25°C, typical voltage s and 50% data pattern per word.

Excludes system overhead. Performance numbers are valid for all speed versions. Sampled,

but not 100% tested.

2. Averaged over entire device.

3. W602 is the minimum time between an initial BLOCK ERASE or ERAS E RESUME command

and the a subsequent ERASE SUSPEND command. Violating the specification repeatedly

during any particular BLOCK ERASE may cause erase failures in Fla sh devices. This specifica-

tion is required if the designer wishes to maintain compatibility with the P33 NOR Flash

device. However, it is not required with PCM.

Table 35: Program and Erase Specifications

Operation1Symbol Parameter Description

VPPL4, 5

UnitMin Typ Max

Erasing and Suspending

Erase to suspend W602 3t

ERS/SUSP ERASE or ERASE RESUME

command to ERASE

SUSPEND command

– 500 – µs

Erase ti m e W500 tERS/PB 16KW parameter – 100 200 ms

W501 tERS/MB 64KW main – 400 800

Suspend latency W600 tSUSP/P Write suspend – 35 60 µs

W601 tSUSP/E Erase suspend – 35 60

Conventional Word Programming

Program time6W200 tPROG/W Single word – 60 120 µs

Buffered Programming

Program time W200 tPROG/W Single word

(legacy program and bit-

alterable write)

5 120 240 µs

W250 tPROG/PB One buffer (64 bytes/32

words)

(legacy program and bit-

alterable write)

4,5 120 360 µs

One buffer (64 bytes/32

words)

(program on all 1s)

71 280

tCLtCH

DQ0

DQ1

LSB out

Address

LSB in

tCLQX tCLQX tSHQZ

tCLQV tCLQV

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128Mb: P8P Parallel PCM

Ordering Information

4. These performance numbers are valid for all speed versions.

5. Sampled, not 100% tested.

Ordering Information

Table 36: Active Line Item Ordering Table (0°C to 70°C)

Part Number Description

NP8P128A13BSM60E P8P 128Mb TSOP 14 x 20 Bottom Boot

NP8P128A13TSM60E P8P 128Mb TSOP 14 x 20 Top Boot

NP8P128A13B1760E P 8P 128M lead-free 10 x 8 x 1.2 easy BGA Bottom Boot

NP8P128A13T1760E P8P 128 M lead-free 10 x 8 x 1.2 easy BGA Top Boot

Table 37: Active Line Item Ordering Table (–40°C to 85°C)

Part Number Description

NP8P128AE3BSM60E P8P 128Mb TSOP 14 x 20 Bottom Boot

NP8P128AE3TSM60E P 8P 128Mb TSOP 14 x 20 To p Boot

NP8P128AE3B1760E P8P 128M lead-free 10 x 8 x 1.2 easy BGA Bottom Boot

NP8P128AE3T1760E P8P 128M lead-free 10 x 8 x 1.2 easy BGA Top Boot

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128Mb: P8P Parallel PCM

Supplemental Refer ence Information

Supplemental Reference Information

Flowcharts

Figure 30: WORD PROGRAM or BIT-ALTERABLE WORD WRITE Flowchart

Notes: 1. Repeat for subsequent WRITE operations

2. Full status register check can be done after each WRITE or after a sequence of WRITE opera-

tions.

Table 38: WORD PROGRAM or BIT-ALTERABLE WORD WRITE Procedure

Bus Operation Command Notes

WRITE PROGRAM/WRITE

SETUP Data = 40h or 42h (bit alterable

Addr = Location to WRITE (WA)

WRITE DATA Data = Data to be written (WD)

Addr = Location to be written (WA)

READ Status register data; initiate a READ cycle to update status register

Standby Check SR7

1 = WSM ready

0 = WSM busy

Write

complete

SR7 =

Write 40h or 42h

word address

Start

Write data

word address

Program

setup

Confirm

data

Read status

loop

Yes

Suspend

write

Full status check

(if desired)

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128Mb: P8P Parallel PCM

Supplemental Refer ence Information

3. WRITE FFh after the last operation to end read array mode.

Figure 31: Full WRITE STATUS CHECK Flowchart

Notes: 1. SR3 must be cleared before the device will allow further WRITE attempts.

2. Only the CLEAR STATUS REGIST ER command clears SR1, SR3, and SR4.

3. If an error is detected, clear the status register before attempting a WRITE RETRY or other

error recovery.

Table 39: Full WRITE STATUS CHECK Procedure

Bus Operation Command Notes

STANDBY Check SR3

1 = VPP error

STANDBY Check SR4

1 = Data WRITE error

STANDBY Check SR1

1 = Attempted to WRITE to locked block; WRITE aborted

Write

successful

Read status

SR3 =

SR4 =

SR1 =

Write

error

Device protect

error

VPP range

error

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128Mb: P8P Parallel PCM

Supplemental Refer ence Information

Figure 32: WRITE SUSPEND/RESUME Flowchart

SR7 =

Write 70hs

Start

Write B0h

any address Program

suspend

Read

status

Write FFh Read array

Write

resume

Write D0h

any address

Read array

data

Write FFh Read array

Read array

data

Read status

SR2 =

Write

resumed

Yes

Done

reading?

Write

completed

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128Mb: P8P Parallel PCM

Supplemental Refer ence Information

Table 40: WRITE SUSPEND/RESUME Procedure

Bus Operation Command Notes

WRITE READ STATUS Data = 70h

Addr = Block to suspend (BA)

WRITE WRITE SUSPEND Data = B0h

Addr = X

READ Status register data; initiate a READ cycle to update status register

Addr = Suspended bl ock (BA)

STANDBY Check SR7

1 = WSM ready

0 = WSM busy

STANDBY Check SR2

1 = Program suspended

0 = Program completed

WRITE READ ARRAY Data = FFh

Addr = Block address to be read (BA)

READ Read array data from block other than the one being written

WRITE WRITE RESUME Data = D0h

Addr = Suspended bl ock (BA)

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128Mb: P8P Parallel PCM

Supplemental Refer ence Information

Figure 33: BUFFER PROGRAM or Bit-Alterable BUFFER WRITE Flowchart

Yes

Is WSM

ready? SR[7] =

Set timeout or

loop counter

Start

Use single

word writes

Get next

target address

Read status register

(at block address )

Timeout

or count expired?

Issue WRITE-to-BUFFER

command E8h or EAh

and block address

X = 0

Write confirm D0h

and block address

Read status

Device

supports buffer

writes?

Write word count,

block address

Write buffer data,

start address

Write buffer data,

block address

X = X + 1

0 = No

Yes

1 = Yes

Yes

X = N? Abort

bufferred

write?

0 Yes

Full status

check (if desired)

SR[7]? Suspend

write?

Another

buffered

write?

Write

complete

Write to another

block address

Suspend

write loop

Buffered write

aborted

Yes

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128Mb: P8P Parallel PCM

Supplemental Refer ence Information

Notes: 1. Word count values on DQ[7:0] are loaded into the count register. Count ranges for this

device are N = 0000h to 0001Fh.

2. The device outputs the status register when read.

3. Write buffer contents will be written at the device start address or destination Flash

address.

4. Align the start address on a write buffer boundary for maximum write performance (for

example, A[5:1] of the start address = 0).

5. The device aborts the BUFFERED PROGRAM command if the current address is outside the

original block address.

6. The status register indicates an improper command sequence if the BUFFERED PROGRAM

command is aborted. Follow this with a CLEAR STATUS REGISTER command.

7. Full status check can be done after all erase and write seque nc es are complete. Write FFh

after the last operation to reset the device to read array mode.

Table 41: BUFFER PROGRAM OR BIT-ALTERABLE BUFFER WRITE Procedure

Bus Operation Command Notes

WRITE WRITE TO BUFFER Data = E8H or EAH (bit alterable)

Addr = Block addr ess

READ SR7 = Valid

Addr = Block addr ess

STANDBY Check SR7

1 = WSM busy

0 = WSM ready

WRITE1, 2 Data = N - 1 = Word count

N = 0 corresponds to count = 1

Addr = Block addr ess

WRITE3, 4 Data = Write buffer data

Addr = Start address

WRITE5, 6 Data = Write buffer data

Addr = Block addr ess

WRITE WRITE CONFIRM Data = D0H

Addr = Block addr ess

READ Status register data

CE# and CE# LOW updat es SR

Addr = Block addr ess

STANDBY Check SR7

1 = WSM ready

0 = WSM busy

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128Mb: P8P Parallel PCM

Supplemental Refer ence Information

Figure 34: BLOCK ERASE Flowchart

Notes: 1. Repeat for subsequent block erasures

2. Full status register check can be done after each block erase or af te r a sequence of block

erasures.

3. Write FFh after the last operation to enter read array mode.

Table 42: BLOCK ERASE Procedure

Bus Operation Command Notes

WRITE BLOCK ERASE

SETUP Data = 20h

Addr = Block to be erased (BA)

WRITE ERASE CONFIRM Data = D0h

Addr = Block to be erased (BA)

READ Status register data; toddle CE# or OE# to update status register data

STANDBY Check SR7

1 = WSM ready

0 = WSM busy

Block erase

complete

SR7 =

Write 20h

block address

Start

Write data

word address

Block erase

Erase confirm

Read status

loop

Yes

Suspend

erase

Full status check

(if desired)

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128Mb: P8P Parallel PCM

Supplemental Refer ence Information

Figure 35: BLOCK ERASE FULL ERASE STATUS CHECK Flowchart

Notes: 1. Only the CLEAR STATUS REGISTER command clears SR1, SR3, SR4, and SR5.

2. If an error is detected, clear the status register before attempting an erase retry or other

error recovery.

Table 43: BLOCK ERASE FULL ERASE STATUS CHECK Procedure

Bus Operation Command Notes

STANDBY Check SR3

1 = VPP error

STANDBY Check SR4, SR5

1 = Command sequence error

STANDBY Check SR5

1 = Block erase error

STANDBY Check SR1

1 = Attempted erase of locked block er ase aborted

Read status

SR3 =

SR4, 5 =

SR5 =

Command

sequence error

Block erase

error

Block erase

successful

SR1 = Erase of locked

block aborted

VPP range

error

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128Mb: P8P Parallel PCM

Supplemental Refer ence Information

Figure 36: ERASE SUSPEND/RESUME Flowchart

SR7 =

Write 70h

any address

Start

Write B0h

any address Erase

suspend

Read status

ProgramRead

(Erase resume)

Read status

Write D0h

any address

Program

loop

Read array

data

Write 70h

any address

Write FFh

any address Read array

Read array

data

Read status

SR6 =

Erase

resumed

Yes

Done?

Read or

program?

Erase

completed

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128Mb: P8P Parallel PCM

Supplemental Refer ence Information

Table 44: ERASE SUSPEND/RESUME Procedure

Bus Operation Command Notes

WRITE READ STATUS Data = 70h

Addr = Any device address

WRITE ERASE SUSPEND Data = B0h

Addr = Same partition address as above

READ Status register data; toggle CE# or OE# to update status register

Addr = X

STANDBY Check SR7

1 = WSM ready

0 = WSM busy

STANDBY Check SR

1 = Erase suspended

0 = Erase completed

WRITE READ ARRAY OR

PROGRAM Data = FFh or 40h

Addr = Block to program or read

READ or WRITE Read array or program data from/to block other than the one being erased

WRITE PROGRAM RESUME Data = D0h

Addr = Any address

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128Mb: P8P Parallel PCM

Supplemental Refer ence Information

Figure 37: LOCKING OPERATIONS Flowchart

Table 45: LOCKING OP ERATIONS Procedure

Bus Operation Command Notes

WRITE LOCK SETUP Data = 60h

Addr = Block to lock/unlock/lo ck-down (BA)

WRITE LOCK, UNLOCK, OR

LOCKDOWN

CONFIRM

Data = 01h (Lock block)

D0h (Unlock block)

2Fh (Lock-down block)

Addr = Block to lock/unlock/lo ck-down (BA)

WRITE (optional) READ ID PLANE Data = 90h

Addr = Block address offset + 2 (BA + 2)

READ (optional) BLOCK LOCK

STATUS Block lock status data

Addr = Block address offset + 2 (BA + 2)

Yes

Locking

change?

Write 60h

block address

Start

Write

01h/D0h/2Fh

block address Lock confirm

Read ID plane

Lock setup

Read array

Optional

Write FFh

any address

Write 0x90

Read block

lock status

Lock change

complete

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128Mb: P8P Parallel PCM

Supplemental Refer ence Information

Figure 38: PROGRAM PROTECTION REGISTER Flowchart

STANDBY

(optional) Confirm lockin g change on DQ1, DQ0 (see Table 14 on page 26 for valid

combinations)

WRITE READ ARRAY Data = FFh

Addr = Block address (B A)

Table 46: PROGRAM PROTECTION REGISTER Procedure

Bus Operation Command Notes

WRITE PROGRAM PR

SETUP Data = 0xC0

Addr = First locati on to program

WRITE PROTECTION

PROGRAM Data = Data to program

Addr = Location to program

READ None Status register data

IDLE None Check SR7

1 = WSM ready

0 = WSM busy

Table 45: LOCKING OPERATIONS Procedure (Continued)

Bus Operation Command Notes

Program

complete

SR7 =

Write 0xC0,

PR address

Start

Write PR

address and data

Program

setup

Confirm

data

Read status

Full status check

(if desired)

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Supplemental Refer ence Information

Notes: 1. PROGRAM PROTECTION REGISTER operation addresses must be within the protection regis-

ter address space. Addresses outside this space will return an error.

2. Repeat for subsequent programming operations.

3. Full status register check can be done after each program or after a sequence of PROGRAM

operations.

4. Write 0xFF after the last operation to set read array state.

Figure 39: FULL STATUS CHECK Flowchart

Notes: 1. Only the CLEAR STATUS REGISTER command clears SR1, SR3, and SR4.

2. If an error is detected, clear the status register before attempting a program retry or other

error recovery.

Table 47: FULL STATUS CHECK Procedure

Bus Operation Command Notes

IDLE None Check SR3

1 = VPP range error

IDLE None Check SR4

1 = Programming error

IDLE None Check SR1

1 = Block locked; operation aborted

Program

successful

Read status

SR3 =

SR4 =

SR1 =

Program

error

program aborted

VPP range

error

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128Mb: P8P Parallel PCM

Supplemental Refer ence Information

Write State Machine

Figure 40: Write State Machine — Next State Table

Erase

Suspend

(Unlock Blk)

Setup SM Entry Busy

Busy SM Ready

Setup SM Exit Busy

Busy Ready

SM Entry SM Entry Busy SM Entry Busy

Ready (Error [Botch] ) Ready (Error [Botch] )

SM Exit SM Exit Busy SM Exit Busy

Ready (Error [Botch] )

Erase Suspend (Lock E rror [Botch])Erase Suspend (Lock E rror [Botch])Lock/CR Setup in Erase Suspend

Ready (Error [Botch] )

Read

Array (2)

Word

Program

(3,4)

Bit Alterable

Word Write

Write to

Buffered

Program

(BP)

Bit Alterable

Write to

Buffer

Streaming

Mode Entry

(SM Entry)

Streaming

Mode Exit

(SM Exit)

Erase Setup

(3,4)

BE Confirm,

P/E Resume,

ULB,

Confirm (7)

BP / Prg / Erase

Suspend Read

Status

Clear

Status

Read

ID/Query

Lock,

Unlock,

Lock-down,

CR setup (4)

(FFH) (10H/40H) (42H) (E8H) (EA H) (4AH) (4FH) (20H) (D0H) (B 0H) (70H) (50H) (90H, 98H) (60H)

Ready SM Entry

Setup SM Exit

Setup Erase Setup Lock/CR

Setup

SM Ready SM Ready SM Exit

Setup Erase Setup Lock/CR

Setup

Ready

(Unlock Block)

Setup

Bus

Setup

Busy Word Pgm

Suspend

Suspend Word Pgm

Busy

Setup

BP Load 1 (8)

BP Load 2 (8)

BP Confirm BP Busy

BP Bus

BP Sus

end

BP Suspend BP Busy

Setup Erase Bus

Busy Erase Suspend

Suspend Erase

Suspend Erase Busy

Lock/CR

Setup in

Erase

Suspend

Setup

Busy Word Program

Suspend in

Erase Suspend

Suspend Word Pgm

Busy in Erase

Suspend

Setup

BP Load 1 (8)

BP Load 2 (8)

BP Confirm BP Busy in

Erase

Suspend

BP Busy BP Suspend in

Erase Suspend

BP Suspend BP Busy in

Erase

Suspend

Ready Program Setup BP Setup Ready

Word Program Busy

BP Confirm if Data load complete; ELSE BP Load 2

Word Program SuspendWord Program Suspend

Ready (Error [Botc h BP] in Erase Sus pend)Erase Suspend (Error [Botch BP])

Erase Suspend

BP Confirm in E rase Suspend if Data load complete; ELSE B P Load 2

Command Input to Chip and resulting Chip Next State

Erase Busy

BP Suspend

BP Busy BP Busy

Word Program Busy

OTP Busy

Ready (Lock Error [Bot ch])

BP SetupProgram Setup

Word Program Busy in Erase Sus pend

Erase Busy

BP Busy in Erase S uspend BP Busy in Eras e Suspend

Word Program Busy in Erase Sus pend

Word Program Busy

Word Program Setup in

Erase Suspend BP Setup in Erase

Suspend

BP Suspend in Erase Suspend BP Suspend in Erase Suspend

Word Program Suspend in Erase Suspend

BP Suspend

BP in Erase

Suspend

Ready (Error [Botch]) Ready (Error [Botch])

Lock/CR Setup

OTP

SM Ready SM Ready

Ready (Lock Error [Bot ch])

Erase

Word Program

in Erase

Suspend

BP Confirm in E rase Suspend if Data load complete; ELSE B P Load 2

BP Load 1 in Erase Suspend

BP Load 1

Word Program Suspend in Erase Sus pend

Word Program Busy in Erase Sus pend B usy

Current Chip State (6)

Word Program

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128Mb: P8P Parallel PCM

Supplemental Refer ence Information

OTP Setup

(4)

Lock

Block

Confirm (7)

Lock-Down

Block

Confirm (7)

Write

RCR/ECR

Confirm (7)

Block

Address

(¹WA0) (9)

Illegal Cmds+U48

(1)

(C0H) (01H) (2FH ) (03H,04H) (XXXXH) (all other code s)

OTP Setup

Ready (Lock

Error [Botch])

Ready

(Lock Block)

Ready

(Lock Down

Blk)

Ready

(Set CR)

Read

N/A

Ready

BP Confirm if Data

load complete;

ELSE BP Load 2

Ready

(Error

[Botch])

(Proceed if

unlocked or

Lock error)

Ready (Error

[Botch])

Read

Ready

Erase Suspend

Ready

BP Confirm in

Erase Suspend if

Data load

complete; ELSE

BP Load 2

Ready

BP Confirm in

Erase Suspend if

Data load

complete; ELSE

BP Load 2

Ready

(Error

[Botch])

(Proceed if

unlocked or

Lock error)

Ready (Error

[Botch BP] in

Erase Suspend)

Erase Suspend

N/A

Ready

SM Ready

Word Program Busy

N/A

BP Suspend in Erase Suspend

BP Busy in Erase Suspend

Word Program Suspend in Erase Suspend

BP Load 1 in Erase Suspend

BP Confirm in Erase Suspend if Data load complete;

ELSE BP Load 2

N/A

BP Confirm in Erase Suspend if Data load complete;

ELSE BP Load 2

Ready (Error [Botch BP ] in Erase Suspend)

Ready (Error [Botch] )

BP Confirm if Data load complete; ELSE B P Load 2 N/A

N/A

BP Busy

Ready (Error [Botch] )

BP Confirm if Data load complete; ELSE B P Load 2

BP suspend

BP Load 1

Word Program Busy in Erase Suspend

Word Program Busy in Erase Suspend B usy

Erase Suspend

Erase Busy

N/A

OTP Busy

Ready (Lock Error [Bot c h ] )

WSM

Operation

Completes

Command Input to Chip and resulting Chip Next State

Word Program Busy

Word Program Suspend

Erase

Suspend

(Error

[Botch])

Erase

Suspend

(Lock Blk)

Erase

Suspend

(Lock Down

Blk)

Erase

Suspend

(Set CR)

Ready

N/A

Ready

N/A

Ready (Error [Botch])

SM Entry Busy

Ready (Error [Botch])

SM Exit Busy

Erase Suspend (Lock Error

[Botch])

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128Mb: P8P Parallel PCM

Supplemental Refer ence Information

Notes: 1. Illegal commands include commands outside of the allowed command set (allowed com-

mands: 40H [pgm], 20H [erase]).

2. If a READ ARRAY is attempted while the device is busy writing or erasing, the result will be

invalid data. The ID and query data are located at different locations in the address map.

3. First and second cycles of two cycles WRITE commands must be given to the same device

address, or unexpected results will occur.

4. The second cycle of the following two cycle co mmands will be ignored by the user interface:

word program setup, erase setup, OTP setup, and lock/unlock/lock down/CR setup when

issued in an illegal condition. Illegal conditions are such as "pgm setup while busy", “erase

setup while busy", “W ord prog ram su sp end ”, etc. For example, the second cycle of an

ERASE command issued in PROGRAM SUSPEND will NOT resume the program operation.

5. The CLEAR STATUS COMMAND only clears the error bits in the status register if the device is

not in the following modes: 1. WSM running (Pgm Busy, Eras e Busy, Pgm Busy In Erase Sus -

pend, OTP Busy, modes); 2. Suspend states (Pgm Suspend, Pgm Suspend In Er a s e Sus pend)

Read

Array (2)

Word

Program

Setup (3,4)

Bit Alterable

Word Write

Write to

Buffered

Program

(BP)

Bit Alterable

Write to

Buffer

Streaming

Mode Entry

(SM Entry)

Streaming

Mode Exit

(SM Exit)

Erase Setup

(3,4)

BE Confirm,

P/E Resume,

ULB Confirm

(7)

Program/

Erase

Suspend

Read

Status

Clear

Status

Read

ID/Query

Lock,

Unlock,

Lock-down,

CR setup (4)

(FFH) (10H/40H) (42H) (E8H) (EAH) (4AH) (4FH) (20H) (D0H) (B0H) (70H) (50H) (90H, 98H) (60H)

Status Read

BP Busy,

Word Program Busy,

Erase Busy,

BP Busy

BP Busy in Erase Suspend

Word Pgm Suspend,

Word Pgm Busy in Erase Suspend,

Pgm Suspend In Erase Suspend

BP Suspend in Erase Suspend

SM Entry Busy

SM Exit Busy

Ready, SM Ready

Erase Suspend,

BP Suspend

Lock/CR Setup,

Lock/CR Setup in Erase Susp

Erase Setup,

OTP Setup,

BP: Setup, Load 1, Load 2, Confirm,

Word Pgm Setup,

SM Entry Setup, SM Exit Setup

Read Array

Status ReadReady Array ID Read

Status

Read

Status Read

OTP Busy

Current chip state

Command Input to Chip and resulting Output Mux Next State

Status Read Output mux does not change.

OTP Setup

(4)

Lock

Block

Confirm (7)

Lock-Down

Block

Confirm (7)

Write

RCR/ECR

Confirm (7)

Block

Address

(WA0) Illegal Cmds (1)

(C0H) (01H) (2FH) (03H,04H) (FFFFH) (all other c o des)

Command Input to Chip and resulting Output Mux Next State

Status Read

Current chip state

BP Busy,

Word Program Busy,

Erase Busy,

BP Busy

BP Busy in Erase Suspen d

Word Pgm Suspend,

Word Pgm Busy in Erase Suspend,

Pgm Suspend In Erase Suspend

BP Suspend in Erase Suspend

SM Entry Busy

SM Exit Busy

Ready, SM Ready

Erase Suspend,

BP Suspend

Erase Setup ,

OTP Set up,

BP: Setup, Load 1, Load 2, Confirm,

Word Pgm Setup,

SM Entry Setup, SM Exit Setup

Lock/CR Setup,

Lock/CR Setup in Erase Susp

OTP Busy

Status Read

Read ArrayStatus Read Output mux does not change. Ready Array

Status Read Ready

Array

WSM

Operation

Completes

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128Mb: P8P Parallel PCM

Supplemental Refer ence Information

6. The current state is that of the device.

7. Confirm commands (LOCK BLOCK, UNLOCK BLOCK, LOCK DOWN BLOCK) perform the oper -

ation and then move to the ready state.

8. Buffered programmin g will botch when a different block address (as com pared to add r es s

given with E8 command) is written during the BP load1 and BP load2 states.

9. WA0 refers to the block address latched during the first WRITE cycle of the current opera-

tion.

Common Flash Interface

The P8P parallel PCM device borrows from the existing standards established for Flash

memory and supports the use of the CFI. The query is part of an overal l s peci fic atio n for

multiple comm and se t an d cont rol interface desc riptions call ed CFI. Thi s appe nd ix

defines the data st ructure or database returned by the CFI QUERY comm and . System

software should parse this structure to gain critical information, such as block size,

density, x16, and electrical spec ifications. After this inform ati on has be en obtained, the

software will know which command sets to use to enable PCM writes, block erases, and

otherwise control the PCM component.

Query Structure Output

The query database allows system software to obtain information for controlling the

PCM device. This section describes the device’s CFI-compliant interface that allows

access to query data.

Query data are presented on the lowest-order data outputs (DQ[7:0]) only. The numer-

ical offset value is the address relative to the maximum bus width supported by the

device. On this family of devices, the query table device starting address is a 10h, which

is a word address for x16 devices.

For a word-wide (x16) device, the first two query-structure bytes, ASCII “Q” and “R,”

appear on the low byte at word addresses 10h and 11h. This CFI-compliant device

outputs 00h data on upper b ytes . The device outputs ASCII “ Q” in the low byte (DQ[7:0])

and 00h in the high byte (DQ[15:8]).

At Query addresses containing two or more bytes of info rmation, the leas t sig ni f ic ant

data byte is presented at the lower address, and the most significant data byte is

presented at the higher address.

In all of the following tables , addresses and data are represented in hexadeci mal nota-

tion, so the “h” suffix has been dropped. In addition, because the upper byte of word-

wide devices is always 00h, the leading 00 has been dr opped from the table notation and

only the lower byte value is shown. Any x16 device outputs can be assumed to have 00h

on the upper byt e in this mo de.

Table 48: Summary of Query Structure Output as a Function of Device and Model

Device Hex Offset Hex Code ASCII Value

Device address 00010:

00011:

00012:

“Q”

“R”

“Y”

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128Mb: P8P Parallel PCM

Supplemental Refer ence Information

Query Structure Overview

The QUERY command causes the PCM component to display the CFI query structur e or

database. The structure subsections and address locations are summarized below.

Notes: 1. Refer to the Query Structure Output section and offset 28h for the detailed defi nition of

offset address as a function of device bus wid th and mode.

2. BA = Block addre ss beginning location (for example, 08000h is block 1s beginning location

when the block size is 32K-word).

3. Offset 15 defines “P,” which points t o the primary Micron-specific extended query table.

CFI Query Identification String

The identifica tion string provides verification that the component suppo rts the CFI

specification. It also indicates the specification version and supported vendor-specified

command set(s).

Table 49: Example of Query Structure Output of x16 Devices

Word Addressing Byte Addressing

Offset Hex Code Value Offset Hex Code Value

AX–A0D15–D0AX–A0D15–D0

00010h 0051 Q 00010h 51 Q

00011h 0052 R 00011h 52 R

00012h 0059 Y 00012h 59 Y

00013h P_IDLO PrVendor 00013h P_IDLO PrVendor

00014h P_IDIH ID# 00014h P_IDLO ID#

00015h PLO PrVendor 00015h P_IDIH ID#

00016h PIH TblAdr 00016h – –

00017h A_IDLO AltVendor 00017h – –

00018h A_IDIH ID# 00018h – –

Table 50: Query Structure

Offset Subsection Name Description1

00000h Manufact urer code

00001h Device code

(BA + 2)h2Block status register Block-specific information

00004–Fh Reserved Reserved for vendor-specific information

00010h CFI query identification setting Command set ID and vendor data offset

0001Bh System interface information Device timing and voltage information

00027h Device geometry definition Flash device layout

P3Primary Intel-specific extended query tab le Vendor-defined additional information specific to

the primary vendor algorithm

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128Mb: P8P Parallel PCM

Supplemental Refer ence Information

Table 51: Block Status Register

Offset Length Description Address Value

(BA + 2)h 1 Block lock status register BA + 2 –00 or –01

BSR 0: Block lock status

0 = Unlocked

1 = Locked

BA + 2 (bit 0): 0 or 1

BSR 1: Block lock-down status

0 = Not locked down

1 = Locked down

BA + 2 (bit 1): 0 or 1

BSR 4 EFA: Bloc k lock status

0 = Unlocked

1 = Locked

BA + 2 (bit 4): 0 or 1

BSR 5EFA: Block lock-down status

0 = Not locked down

1 = Locked down

BA + 2 (bit 5): 0 or 1

BSR 2–3, 6–7: Reserved for future use BA + 2 (bit 2–3, 6–7): 0

Ta ble 52: CFI Identification

Offset Length Description Address Hex Code Value

10h 3 Query-unique ASCII string QRY 10

–51

–52

–59

13h 2 Primary vendor command set and control

interface ID code; 16-bit ID code for vendor-

specific algorithms

14 –01

–00

15h 2 Extended query table primary algorithm

address 15

16 –0A

17h 2 Alternate vendor command set and control

interface ID code; 0000h means no second

vendor-specified algorithm exists

18 –00

–00

19h 2 Secondary algorithm extended query table

address; 0000h means none exists 19

1A –00

–00

Table 53: System Interface Information

Offset Length Description Address Hex Code Value

1Bh 1 VCC logic supply minimum PROGRAM/ERASE

voltage

bits 0–3 BCD 100mV

bits 4–7 BCD volts

1B –27 2.7V

1Ch 1 VCC logic supply maximum PROGRAM/ERASE

voltage

bits 0–3 BCD 100mV

bits 4–7 BCD volts

1C –36 3.6V

1Dh 1 VPP (programming) supply minimum

PROGRAM/ ERASE voltage

bits 0–3 BCD 100mV

bits 4–7 HEX volts

1D –09 0.9V

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128Mb: P8P Parallel PCM

Supplemental Refer ence Information

1Eh 1 VPP (programming) supply maximum

PROGRAM/ ERASE voltage

bits 0–3 BCD 100mV

bits 4–7 HEX volts

1E –36 3.6V

1Fh 1 n such that typical single word program time-

out = 2n µ-sec 1F –08 256µs

20h 1 n such that typical full buffer write time-out =

2n µ-sec 20 –09 512µs

21h 1 n such that typical block erase time-out = 2n m-

sec 21 –0A 1s

22h 1 n such that typical full chip erase time-out = 2n

m-sec 22 –00 NA

23h 1 n such that maximum word program time-out

= 2n times typical 23 –01 512µs

24h 1 n such that maximum buf fer write time-out =

2n times typical 24 –01 1024µs

25h 1 n such that maximum block erase time-out = 2n

times typical 25 –02 4s

26h 1 n such that maximum chip erase time-out = 2n

times typical 26 –00 NA

Ta ble 54: Device Geometry Definition

Offset Length Description Address Hex Code Value

27h 1 n such that device size = 2n in number of bytes 27 See Table 56 on

page 77

28h 2 Flash device interface code assignment: n such

that n + 1 specifies the bit field that represents

the Flash device width capabilities as d escribed

in Table 55 on page 77

29 -01

-00 x16

2Ah 2 n such that maximum number of bytes in write

buffer = 2n2A

2B -06

-00 64

2Ch 1 Number of erase block regions (x) within

device:

x = 0 means no erase blocking; the device

erases in bulk

x specifies the number of device regions with

one or more contiguous same-size erase blocks

Symmetrically blocked partitions have one

blocking region

2C See Table 56 on

page 77

2Dh 4 Erase block region 1 information

bits 0-15 = y, y + 1 = number of identical-size

erase blocks

bits 16-31 = z, regio n er ase block(s) size are z x

256 bytes

See Table 56 on

page 77

31h 4 Erase block region 2 information

bits 0-15 = y, y + 1 = number of identical-size

erase blocks

bits 16-31 = z, regio n er ase block(s) size are z x

256 bytes

See Table 56 on

page 77

Table 53: System Interface Information (Continued)

Offset Length Description Address Hex Code Value

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128Mb: P8P Parallel PCM

Supplemental Refer ence Information

35h 4 Reserved for futur e block erase block region

information 35

See Table 56 on

page 77

Ta ble 55: Bit Field Definitions

Bit

76543210

- - - - x64 x32 x16 x8

Bit

15 14 13 12 11 10 9 8

--------

Table 56: Hex Code and Values for Device Geometry

Address

128Mb

-B -T

27 -18 -18

29 01

00 01

2B 06

00 06

2C -02 -02

-03

-00

-80

-00

-7E

-00

-02

-7E

-00

-02

-03

-00

-80

-00

Ta ble 54: Device Geometry Definition (Continued)

Offset Length Description Address Hex Code Value

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128Mb: P8P Parallel PCM

Extended Query Tables

Table 57: Primary Vendor-Specific Extended Query

Offset

P = 10Ah Length Description (Optional Flash Features and Commands Address Hex

Code Value

(P + 0)h

(P + 1)h

(P + 2)h

3Primary extended query table; unique ASCII string PRI 10A

10B

10C

-50

-52

-49

(P + 3)h 1 Major version number, ASCII 10D -31 1

(P + 4)h 1 Minor version number, ASCII 10E -34 4

(P + 5)h

(P + 6)h

(P + 7)h

(P + 8)h

4Optional feature and command support (1 = yes, 0 = no)

bits 10-31 are reserved; undefined bit are 0. If bit 31 is 1, then

another bit31 field of op tion al features follo ws at the end o f the bit-

30 field

bit 0: Chip erase supported

bit 1: Suspend erase supported

bit 2: Suspend program supported

bit 3: Legacy lock/unlock supported

bit 4: Queued erase supported

bit 5: Instant individual block lo cking supported

bit 6: Protection bits supported

bit 7: Page mode read supported

bit 8: Synchronous read supported

bit 9: Simultaneous operations supported

bit 10: Extended Flash array blocks supported

bit 30: DFI link(s) to follow

bit 31: Another optional features field to follow

10F

110

111

112

-E6

-00

bit 0 = 0

bit 1 = 1

bit 2 = 1

bit 3 = 0

bit 4 = 0

bit 5 = 1

bit 6 = 1

bit 7 = 1

bit 8 = 0

bit 9 = 0

bit 10 = 0

bit 30 = 0

bit 31 = 0

Yes

(P + 9)h 1 Supported functions after suspend: read array, status, query

Other supported features incl ude:

bits 1-7: Reserve d; undefined bits are 0

bit 0: Program supported after erase suspend

113 -01

bit 0 = 1 Yes

(P + A)h

(P + B)h 2Block status register mask

bits 2-15: Reserved; undefined bits are 0

bit 0: Block lo ck bit status register active

bit 1: Block lock-down bit status active

bit 4: EFA block lock bit status register active

bit 5: EFA block lock-down bit status act ive

114

115 -03

-00

bit 0 = 1

bit 1 = 1

bit 4 = 0

bit 5 = 0

Yes

(P + C)h 1 VCC logic supp ly hi gh est performance program/erase voltage

bits 0-3: BCD value in 100mV

bit 4-7: BCD value in volts

116 -33 3.3V

(P + D)h 1 VPP optimum program/erase supply voltage

bits 0-3: BCD value in 100mV

bit 4-7: Hex value in volts

117 -33 3.3V

Table 58: Protection Register Information

Offset

P = 10Ah Length Description (Optional Flash Features and Commands Address Hex

Code Value

(P + E)h 1 Number of protection register fields in JEDEC ID space

000h indicates that 256 protection fields are available 118 -02 2

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128Mb: P8P Parallel PCM

Extended Query Tables

(P + F)h

(P + 10)h

(P + 11)h

(P + 12)h

4Protection field 1: Protection Description

This field describes user-available one-time programmable (OTP)

protection register bytes. Some are preprogrammed with device-

unique serial numbers. Others are user-programmable. Bits 0-15

point to the protection register lock byte, the section’ s first byte. The

following bytes ar e factory preprogrammed and user-

programmable.

bits 0–7: Lock/bytes JEDEC-plane physical low address

bits 8–15: Lock/bytes JEDEC-plane physical high address

bits 16–23: n such that 2n = factory preprogrammed bytes

bits 24–31 = n such that 2n = user-programmable bytes

119

11A

11B

11C

-80

-00

-03

80h

00h

8 byte

(P + 13)h

(P + 14)h

(P + 15)h

(P + 16)h

(P + 17)h

(P + 18)h

(P + 19)h

(P + 1A)h

(P + 1B)h

(P + 1C)h

10 Protection field 2: Protection Description

Bits 0-31 point to the protection register physical lock-word address

in the JEDEC-plane. The following bytes are factory- or user-

programmable

11D

11E

11F

120

-89

-00

89h

00h

bits 32-39: = n ¬ n = factory programmed groups (low byte)

bits 44739: = n  n = factory programmed groups (high byte)

bits 48-55: = n \ 2n = factory programmable bytes/group

121

122

123

-00

bits 56-63: = n ¬ n = user-programmed groups (low byte)

bits 64-71: = n ¬ n = user-programmed groups (high byte)

bits 72-79: = n ¬ 2n = user-programmable bytes/group

124

125

126

-10

-00

-04

Table 59: Re ad Information

Offset

P = 10Ah Length Description (Optional Flash Features and Commands Address Hex

Code Value

(P + 1D)h 1 Page mode read capability

bits 0-7 = n such that 2n hex value represents the number of read-

page bytes. See offset 28h for device word width to determine page

mode data output width. 00h indicates no read page buffer.

127 -04 16

byte

(P + 1E)h 1 Number of synchronous mode read configuration fields that follow.

00h indicates no burst capability. 128 -00 0

Table 60: Partition and Erase Block Region Information

Offset

P = 10Ah

Description (Optional Flash Features and Commands

Address

Bottom Top Length Bottom Top

(P + 1F)h (P + 1F)h Number of device hardware-partition regions within the device.

x = 0: a single hardware partition device (no fields follow)

x specifies the number of device partition regi ons co ntain in g on e

or more contiguous erase block regions.

1 129 129

Partition Region 1 Information

(P + 20)h (P + 20)h Data size of this partit ion region informati on field (number of

addressable locations, including this field) 212A

12B 12A

12B

(P + 21)h (P + 21)h

(P + 22)h (P + 22)h Number of identical partitions within the partition region 212C

12D 12C

12D

(P + 23)h (P + 23)h

Ta ble 58: Protection Register Information (Continued)

Offset

P = 10Ah Length Description (Optional Flash Features and Commands Address Hex

Code Value

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128Mb: P8P Parallel PCM

Extended Query Tables

(P + 24)h (P + 24)h Number of program or erase operations allowed in a partition

bits 0–3: number of simultaneous PROGRAM operations

bits 4–7: number of simultaneous ERASE operations

1 12E 12E

(P + 25)h (P + 25)h Simultaneous program or erase operations allowed in other

partitions while a partition in this region is in program mode

bits 0–3: number of simultaneous PROGRAM operations

bits 4–7: number of simultaneous ERASE operations

1 12F 12F

(P + 26)h (P + 26)h Simultaneous program or erase operations allowed in other

partitions while a partition in this region is in erase mode

bits 0–3: number of simultaneous PROGRAM operations

bits 4–7: number of simultaneous ERASE operations

1 130 130

(P + 27)h (P + 27)h Types of erase block regions in the partition region

x = 0: no erase blocking; the partition region erases in bulk

x = 0: number of eras e block regions with contiguous same-size

erase blocks

Symmetrically blocked partitions have one blocking region

Partition size = (type 1 blocks) × (type 1 block sizes) + (type 2

blocks) × (type 2 block sizes) + ... + (type n blocks) × (type n blo ck

sizes)

1 131 131

(P + 28)h

(P + 2A)h

(P + 2B)h

(P + 28)h

(P + 2A)h

(P + 2B)h

Partition region 1, erase block type 1 information

bits 0–15 = y, y + 1 = number of identical-size erase blocks in a

partition

bits 16–31 = z, region erase block(s) size are z × 256 bytes

4 132

133

134

135

132

133

134

135

(P + 2C)h

(P + 2D)h (P + 2C)h

(P + 2D)h Partition 1 (erase block, type 1)

Block erase cycles × 1000 2 136

137 136

137

(P + 2E)h (P + 2E)h Partition 1 (erase block, type 1) bits per cell; internal EDAC

bits 0–3: bits per cell in erase region

bit 4: internal EDAC used (1 = yes, 0 = no)

bits 5–7: reserved for future use

1 138 138

(P + 2F)h (P + 2F)h Partition 1 (erase block, type 1) page mode and synchronous

mode capabilities defined in Table 10 on page 18

bit 0: page mode host reads permitted (1 = yes, 0 = no)

bit 1: synchronous host reads permitted (1 = yes, 0 = no)

bit 2: synchronous host writes permitted (1 = yes, 0 = no)

bits 3–7: reserved for future use

1 139 139

(P + 30)h

(P + 31)h

(P + 32)h

(P + 33)h

(P + 34)h

(P + 35)h

(P + 30)h

(P + 31)h

(P + 32)h

(P + 33)h

(P + 34)h

(P + 35)h

Partition 1 (erase block, type 1) programmed region information

bits 0–7 = x, 2^x = programming region aligned size (bytes)

bits 8–14: reserved; bit 15: legacy Fla sh operation (ignore 0:7)

bits 16–23 = y = control mode valid size in bytes

bits 24–31: reserved

bits 32–39 = z = control mode invalid size in bytes

bits 40–46: reserved; bit 47: legacy Flash operation (ignore 23:16

and 39:32)

613A

13B

13C

13D

13E

13F

13A

13B

13C

13D

13E

13F

(P + 36)h

(P + 37)h

(P + 38)h

(P + 39)h

(P + 36)h

(P + 37)h

(P + 38)h

(P + 39)h

Partition 1 (erase block, type 2) information

bits 0–15 = y, y + 1 = number of identical-sized blocks in a

partition

bits 16–31 = z, region erase block(s) size are z × 256 bytes

4 140

141

142

143

140

141

142

143

(P + 3A)h

(P + 3B)h (P + 3A)h

(P + 3B)h Partition 1 (erase block type 2)

Block erase cycles × 1000 2 144

145 144

145

Table 60: Partition and Erase Block Region Information (Continued)

Offset

P = 10Ah

Description (Optional Flash Features and Commands

Address

Bottom Top Length Bottom Top

PDF: 09005aef8447d46d/Source: 09005aef845b5c96 Micron Technology, Inc., reserves the right to change products or specifica tions without notice.

128Mb: P8P Parallel PCM

Extended Query Tables

(P + 3C)h (P + 3C)h Partition 1 (erase block type 2) bits per cell; internal EDAC

bits 0–3: bits per cell in erase region

bit 4: internal EDAC used (1 = yes, 0 = no)

bits 5–7: reserved for future use

1 146 146

(P + 3D)h (P + 3D)h Partition 1 (erase block, type 2) page mode and synchronous

mode capabilities defined in Table 10 on page 18

bit 0: page mode host reads permitted (1 = yes, 0 = no)

bit 1: synchronous host reads permitted (1 = yes, 0 = no)

bit 2: synchronous host writes permitted (1 = yes, 0 = no)

bits 3–7: reserved for future use

1 147 147

(P + 3E)h

(P + 3F)h

(P + 40)h

(P + 41)h

(P + 42)h

(P + 43)h

(P + 3E)h

(P + 3F)h

(P + 40)h

(P + 41)h

(P + 42)h

(P + 43)h

Partition 1 (erase block, type 2) programming region information

bits 0–7 = x, 2^x = programming region aligned size (bytes)

bits 8–14: reserved; bit 15: legacy Fla sh operation (ignore 0:7)

bits 16–23 = y = control mode valid size in bytes

bits 24–31: reserved

bits 32–39 = z = control mode invalid size in bytes

bits 40–46: reserved; bit 47: legacy Flash operation (ignore 23:16

and 39:32)

Table 61: Hex Code and Values for Partition and Erase Block Regions

Address

128Mb

-B -T

129 –01 –01

12A

12B –24

–00 –24

–00

12C

12D –01

–00 –01

–00

12E –11 –11

12F –00 –00

130 –00 –00

131 –02 –02

132

133

134

135

–03

–00

–80

–00

–7E

–00

–02

136

137 –64

–00 –64

–00

138 –01 –01

139 –01 –01

13A

13B

13C

13D

13E

13F

–00

–80

–00

–80

–00

–80

–00

–80

Table 60: Partition and Erase Block Region Information (Continued)

Offset

P = 10Ah

Description (Optional Flash Features and Commands

Address

Bottom Top Length Bottom Top

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

www.micron.com/productsupport Customer Comment Line: 800-932-4992

Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners.

This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although

considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.

128Mb: P8P Parallel PCM

Extended Query Tables

PDF: 09005aef8447d46d/Source: 09005aef845b5c96 Micron Technology, Inc., reserves the right to change products or specifica tions without notice.

140

141

142

143

–7E

–00

–02

–03

–00

–80

–00

144

145 –64

–00 –64

–00

146 –01 –01

147 –01 –01

148

149

14A

14B

14C

14D

–00

–80

–00

–80

–00

–80

–00

–80

Table 61: Hex Code and Values for Partition and Erase Block Regions (Continued)

Address

128Mb

-B -T