ADC12D1600CIUT/NOPB - Texas Instruments High-Performance Analog

ADC12D1000, ADC12D1600

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SNAS480M –MAY 2010–REVISED MARCH 2013

ADC12D1000/ADC12D1600 12-Bit, 2.0/3.2 GSPS Ultra High-Speed ADC

Check for Samples: ADC12D1000,ADC12D1600

1FEATURES KEY SPECIFICATIONS

2• Configurable to Either 2.0/3.2 GSPS • Resolution: 12 Bits

Interleaved or 1.0/1.6 GSPS Dual ADC • Interleaved 2.0/3.2 GSPS ADC

• Pin-compatible with ADC10D1x00 and – Noise Floor: -152.6/-153.6 dBm/Hz (typ)

ADC12D1x00 – IMD3: -66/-63 dBFS (typ)

• Internally Terminated, Buffered, Differential – Noise Power Ratio: 49.5/48.5 dB (typ)

Analog Inputs – Power: 3.38/3.88 W (typ)

• Interleaved Timing Automatic and Manual – Full Power Bandwidth: 1.75/1.75 GHz (typ)

Skew Adjust • Dual 1.0/1.6 GSPS ADC, Fin = 125 MHz

• Test Patterns at Output for System Debug – ENOB: 9.6/9.4 Bits (typ)

• Programmable 15-bit Gain and 12-bit Plus Sign – SNR: 60.2/58.5 dB (typ)

Offset – Power: 3.38/3.88W (typ)

• Programmable tAD Adjust Feature – Full Power Bandwidth: 2.8/2.8GHz (typ)

• 1:1 Non-demuxed or 1:2 Demuxed LVDS

Outputs DESCRIPTION

• AutoSync Feature for Multi-chip Systems The 12-bit, 2.0/3.2 GSPS ADC12D1000/1600 is the

• Single 1.9V ± 0.1V Power Supply latest advance in TI's Ultra High-Speed ADC family

and builds upon the features, architecture and

APPLICATIONS functionality of the 10-bit GHz family of ADCs.

• Wideband Communications The ADC12D1000/1600 provides a flexible LVDS

• Data Acquisition Systems interface which has multiple SPI programmable

options to facilitate board design and FPGA/ASIC

• RADAR/LIDAR data capture. The LVDS outputs are compatible with

• Set-top Box IEEE 1596.3-1996 and support programmable

• Consumer RF common mode voltage.

• Software Defined Radio The ADC12D1000/1600 is packaged in a leaded or

lead-free 292-ball thermally enhanced BGA package

over the rated industrial temperature range of -40°C

to +85°C.

1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

ADC12D1000, ADC12D1600

SNAS480M –MAY 2010–REVISED MARCH 2013

www.ti.com

Simplified Block Diagram

Wideband Performance

Figure 1. Wideband Performance

Product Folder Links: ADC12D1000 ADC12D1600

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

AGND V_A SDO TPM NDM V_A GND V_E GND_E DId0+ V_DR DId3+ GND_DR DId6+ V_DR DId9+ GND_DR DId11+ DId11- GND_DR A

BVbg GND ECEb SDI CalRun V_A GND GND_E V_E DId0- DId2+ DId3- DId5+ DId6- DId8+ DId9- DId10+ DI0+ DI1+ DI1- B

CRtrim+ Vcmo Rext+ SCSb SCLK V_A NC V_E GND_E DId1+ DId2- DId4+ DId5- DId7+ DId8- DId10- DI0- V_DR DI2+ DI2- C

DDNC Rtrim- Rext- GND GND CAL DNC V_A V_A DId1- V_DR DId4- GND_DR DId7- V_DR GND_DR V_DR DI3+ DI4+ DI4- D

EV_A Tdiode+ DNC GND GND_DR DI3- DI5+ DI5- E

FV_A GND_TC Tdiode- DNC GND_DR DI6+ DI6- GND_DR F

GV_TC GND_TC V_TC V_TC DI7+ DI7- DI8+ DI8- G

HVinI+ V_TC GND_TC V_A GND GND GND GND GND GND DI9+ DI9- DI10+ DI10- H

JVinI- GND_TC V_TC VbiasI GND GND GND GND GND GND V_DR DI11+ DI11- V_DR J

KGND VbiasI V_TC GND_TC GND GND GND GND GND GND ORI+ ORI- DCLKI+ DCLKI- K

LGND VbiasQ V_TC GND_TC GND GND GND GND GND GND ORQ+ ORQ- DCLKQ+ DCLKQ- L

MVinQ- GND_TC V_TC VbiasQ GND GND GND GND GND GND GND_DR DQ11+ DQ11- GND_DR M

NVinQ+ V_TC GND_TC V_A GND GND GND GND GND GND DQ9+ DQ9- DQ10+ DQ10- N

PV_TC GND_TC V_TC V_TC DQ7+ DQ7- DQ8+ DQ8- P

RV_A GND_TC V_TC V_TC V_DR DQ6+ DQ6- V_DR R

TV_A GND_TC GND_TC GND V_DR DQ3- DQ5+ DQ5- T

UGND_TC CLK+ PDI GND GND RCOut1- DNC V_A V_A DQd1- V_DR DQd4- GND_DR DQd7- V_DR V_DR GND_DR DQ3+ DQ4+ DQ4- U

VCLK- DCLK

_RST+ PDQ CalDly DES RCOut2+ RCOut2- V_E GND_E DQd1+ DQd2- DQd4+ DQd5- DQd7+ DQd8- DQd10- DQ0- GND_DR DQ2+ DQ2- V

WDCLK

_RST- GND DNC DDRPh RCLK- V_A GND GND_E V_E DQd0- DQd2+ DQd3- DQd5+ DQd6- DQd8+ DQd9- DQd10+ DQ0+ DQ1+ DQ1- W

YGND V_A FSR RCLK+ RCOut1+ V_A GND V_E GND_E DQd0+ V_DR DQd3+ GND_DR DQd6+ V_DR DQd9+ GND_DR DQd11+ DQd11- GND_DR Y

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

ADC12D1000, ADC12D1600

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SNAS480M –MAY 2010–REVISED MARCH 2013

Connection Diagram

Figure 2. ADC12D1000/1600 Connection Diagram

The center ground pins are for thermal dissipation and must be soldered to a ground plane to ensure rated

performance. See SUPPLY/GROUNDING, LAYOUT AND THERMAL RECOMMENDATIONS for more

information.

Product Folder Links: ADC12D1000 ADC12D1600

AGND

100

AGND

100 VBIAS

50k

AGND

50k

Control from VCMO

VCMO

100

ADC12D1000, ADC12D1600

SNAS480M –MAY 2010–REVISED MARCH 2013

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Ball Descriptions and Equivalent Circuits

Table 1. Analog Front-End and Clock Balls

Ball No. Name Equivalent Circuit Description

Differential signal I- and Q-inputs. In the Non-Dual

Edge Sampling (Non-DES) Mode, each I- and Q-

input is sampled and converted by its respective

channel with each positive transition of the CLK

input. In Non-ECM (Non-Extended Control Mode)

and DES Mode, both channels sample the I-input.

In Extended Control Mode (ECM), the Q-input

may optionally be selected for conversion in DES

Mode by the DEQ Bit (Addr: 0h, Bit 6).

Each I- and Q-channel input has an internal

common mode bias that is disabled when DC-

H1/J1 VinI+/- coupled Mode is selected. Both inputs must be

N1/M1 VinQ+/- either AC- or DC-coupled. The coupling mode is

selected by the VCMO Pin.

In Non-ECM, the full-scale range of these inputs is

determined by the FSR Pin; both I- and Q-

channels have the same full-scale input range. In

ECM, the full-scale input range of the I- and Q-

channel inputs may be independently set via the

Control Register (Addr: 3hand Addr: Bh). Note

that the high and low full-scale input range setting

in Non-ECM corresponds to the mid and minimum

full-scale input range in ECM.

The input offset may also be adjusted in ECM.

Differential Converter Sampling Clock. In the Non-

DES Mode, the analog inputs are sampled on the

positive transitions of this clock signal. In the DES

U2/V1 CLK+/- Mode, the selected input is sampled on both

transitions of this clock. This clock must be AC-

coupled.

Differential DCLK Reset. A positive pulse on this

input is used to reset the DCLKI and DCLKQ

outputs of two or more ADC12D1000/1600s in

order to synchronize them with other

ADC12D1000/1600s in the system. DCLKI and

DCLKQ are always in phase with each other,

V2/W1 DCLK_RST+/- unless one channel is powered down, and do not

require a pulse from DCLK_RST to become

synchronized. The pulse applied here must meet

timing relationships with respect to the CLK input.

Although supported, this feature has been

superseded by AutoSync.

Product Folder Links: ADC12D1000 ADC12D1600

GND

Tdiode_P

Tdiode_N

GND

200k

8 pF

VCMO

Enable AC

Coupling

ADC12D1000, ADC12D1600

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Table 1. Analog Front-End and Clock Balls (continued)

Ball No. Name Equivalent Circuit Description

Common Mode Voltage Output or Signal Coupling

Select. If AC-coupled operation at the analog

inputs is desired, this pin should be held at logic-

low level. This pin is capable of sourcing/ sinking

up to 100 µA. For DC-coupled operation, this pin

C2 VCMO should be left floating or terminated into high-

impedance. In DC-coupled Mode, this pin provides

an output voltage which is the optimal common-

mode voltage for the input signal and should be

used to set the common-mode voltage of the

driving buffer.

Bandgap Voltage Output or LVDS Common-mode

Voltage Select. This pin provides a buffered

version of the bandgap output voltage and is

capable of sourcing/sinking 100 uA and driving a

B1 VBG load of up to 80 pF. Alternately, this pin may be

used to select the LVDS digital output common-

mode voltage. If tied to logic-high, the 1.2V LVDS

common-mode voltage is selected; 0.8V is the

default.

External Reference Resistor terminals. A 3.3 kΩ

±0.1% resistor should be connected between

Rext+/-. The Rext resistor is used as a reference

C3/D3 Rext+/- to trim internal circuits which affect the linearity of

the converter; the value and precision of this

resistor should not be compromised.

Input Termination Trim Resistor terminals. A 3.3

kΩ±0.1% resistor should be connected between

Rtrim+/-. The Rtrim resistor is used to establish

the calibrated 100Ωinput impedance of VinI, VinQ

C1/D2 Rtrim+/- and CLK. These impedances may be fine tuned

by varying the value of the resistor by a

corresponding percentage; however, the tuning

range and performance is not ensured for such an

alternate value.

Temperature Sensor Diode Positive (Anode) and

Negative (Cathode) Terminals. This set of pins is

E2/F3 Tdiode+/- used for die temperature measurements. It has

not been fully characterized.

Product Folder Links: ADC12D1000 ADC12D1600

GND

A GND

100:100:

AGND

100 VBIAS

50k

ADC12D1000, ADC12D1600

SNAS480M –MAY 2010–REVISED MARCH 2013

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Table 1. Analog Front-End and Clock Balls (continued)

Ball No. Name Equivalent Circuit Description

Reference Clock Input. When the AutoSync

feature is active, and the ADC12D1000/1600 is in

Slave Mode, the internal divided clocks are

Y4/W5 RCLK+/- synchronized with respect to this input clock. The

delay on this clock may be adjusted when

synchronizing multiple ADCs. This feature is

available in ECM via Control Register (Addr: Eh).

Reference Clock Output 1 and 2. These signals

provide a reference clock at a rate of CLK/4, when

enabled, independently of whether the ADC is in

Master or Slave Mode. They are used to drive the

RCLK of another ADC12D1000/1600, to enable

automatic synchronization for multiple ADCs

Y5/U6 RCOut1+/- (AutoSync feature). The impedance of each trace

V6/V7 RCOut2+/- from RCOut1 and RCOut2 to the RCLK of another

ADC12D1000/1600 should be 100Ωdifferential.

Having two clock outputs allows the auto-

synchronization to propagate as a binary tree. Use

the DOC Bit (Addr: Eh, Bit 1) to enable/ disable

this feature; default is disabled.

Table 2. Control and Status Balls

Ball No. Name Equivalent Circuit Description

Dual Edge Sampling (DES) Mode select. In the

Non-Extended Control Mode (Non-ECM), when

this input is set to logic-high, the DES Mode of

operation is selected, meaning that the VinI input

is sampled by both channels in a time-interleaved

manner. The VinQ input is ignored. When this

V5 DES input is set to logic-low, the device is in Non-DES

Mode, i.e. the I- and Q-channels operate

independently. In the Extended Control Mode

(ECM), this input is ignored and DES Mode

selection is controlled through the Control Register

by the DES Bit (Addr: 0h, Bit 7); default is Non-

DES Mode operation.

Calibration Delay select. By setting this input logic-

high or logic-low, the user can select the device to

wait a longer or shorter amount of time,

V4 CalDly respectively, before the automatic power-on self-

calibration is initiated. This feature is pin-controlled

only and is always active during ECM and Non-

ECM.

Product Folder Links: ADC12D1000 ADC12D1600

GND

50 k:

GND

ADC12D1000, ADC12D1600

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SNAS480M –MAY 2010–REVISED MARCH 2013

Table 2. Control and Status Balls (continued)

Ball No. Name Equivalent Circuit Description

Calibration cycle initiate. The user can command

the device to execute a self-calibration cycle by

holding this input high a minimum of tCAL_H after

having held it low a minimum of tCAL_L. If this input

is held high at the time of power-on, the automatic

power-on calibration cycle is inhibited until this

D6 CAL input is cycled low-then-high. This pin is active in

both ECM and Non-ECM. In ECM, this pin is

logically OR'd with the CAL Bit (Addr: 0h, Bit 15)

in the Control Register. Therefore, both pin and bit

must be set low and then either can be set high to

execute an on-command calibration.

Calibration Running indication. This output is

B5 CalRun logic-high while the calibration sequence is

executing. This output is logic-low otherwise.

Power Down I- and Q-channel. Setting either input

to logic-high powers down the respective I- or Q-

channel. Setting either input to logic-low brings the

respective I- or Q-channel to an operational state

U3 PDI after a finite time delay. This pin is active in both

V3 PDQ ECM and Non-ECM. In ECM, each Pin is logically

OR'd with its respective Bit. Therefore, either this

pin or the PDI and PDQ Bit in the Control Register

can be used to power-down the I- and Q-channel

(Addr: 0h, Bit 11 and Bit 10), respectively.

Test Pattern Mode select. With this input at logic-

high, the device continuously outputs a fixed,

repetitive test pattern at the digital outputs. In the

A4 TPM ECM, this input is ignored and the Test Pattern

Mode can only be activated through the Control

Non-Demuxed Mode select. Setting this input to

logic-high causes the digital output bus to be in

the 1:1 Non-Demuxed Mode. Setting this input to

A5 NDM logic-low causes the digital output bus to be in the

1:2 Demuxed Mode. This feature is pin-controlled

only and remains active during ECM and Non-

ECM.

Product Folder Links: ADC12D1000 ADC12D1600

GND

100 k:

GND

100 k:

GND

50 k:

GND

ADC12D1000, ADC12D1600

SNAS480M –MAY 2010–REVISED MARCH 2013

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Table 2. Control and Status Balls (continued)

Ball No. Name Equivalent Circuit Description

Full-Scale input Range select. In Non-ECM, when

this input is set to logic-low or logic-high, the full-

scale differential input range for both I- and Q-

channel inputs is set to the lower or higher FSR

value, respectively. In the ECM, this input is

Y3 FSR ignored and the full-scale range of the I- and Q-

channel inputs is independently determined by the

setting of Addr: 3hand Addr: Bh, respectively.

Note that the high (lower) FSR value in Non-ECM

corresponds to the mid (min) available selection in

ECM; the FSR range in ECM is greater.

DDR Phase select. This input, when logic-low,

selects the 0° Data-to-DCLK phase relationship.

When logic-high, it selects the 90° Data-to-DCLK

phase relationship, i.e. the DCLK transition

indicates the middle of the valid data outputs. This

W4 DDRPh pin only has an effect when the chip is in 1:2

Demuxed Mode, i.e. the NDM pin is set to logic-

low. In ECM, this input is ignored and the DDR

phase is selected through the Control Register by

the DPS Bit (Addr: 0h, Bit 14); the default is 0°

Mode.

Extended Control Enable bar. Extended feature

control through the SPI interface is enabled when

this signal is asserted (logic-low). In this case,

most of the direct control pins have no effect.

B3 ECE When this signal is de-asserted (logic-high), the

SPI interface is disabled, all SPI registers are

reset to their default values, and all available

settings are controlled via the control pins.

Serial Chip Select bar. In ECM, when this signal is

asserted (logic-low), SCLK is used to clock in

serial data which is present on SDI and to source

C4 SCS serial data on SDO. When this signal is de-

asserted (logic-high), SDI is ignored and SDO is

at TRI-STATE.

Serial Clock. In ECM, serial data is shifted into

and out of the device synchronously to this clock

C5 SCLK signal. This clock may be disabled and held logic-

low, as long as timing specifications are not

violated when the clock is enabled or disabled.

Product Folder Links: ADC12D1000 ADC12D1600

GND

100 k:

ADC12D1000, ADC12D1600

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SNAS480M –MAY 2010–REVISED MARCH 2013

Table 2. Control and Status Balls (continued)

Ball No. Name Equivalent Circuit Description

Serial Data-In. In ECM, serial data is shifted into

B4 SDI the device on this pin while SCS signal is asserted

(logic-low).

Serial Data-Out. In ECM, serial data is shifted out

of the device on this pin while SCS signal is

A3 SDO asserted (logic-low). This output is at TRI-STATE

when SCS is de-asserted.

Do Not Connect. These pins are used for internal

D1, D7, E3, F4, DNC NONE purposes and should not be connected, i.e. left

W3, U7 floating. Do not ground.

Not Connected. This pin is not bonded and may

C7 NC NONE be left floating or connected to any potential.

Table 3. Power and Ground Balls

Ball No. Name Equivalent Circuit Description

A2, A6, B6, C6,

D8, D9, E1, F1, Power Supply for the Analog circuitry. This supply

H4, N4, R1, T1, VANONE is tied to the ESD ring. Therefore, it must be

U8, U9, W6, Y2, powered up before or with any other supply.

G1, G3, G4, H2,

J3, K3, L3, M3, Power Supply for the Track-and-Hold and Clock

VTC NONE

N2, P1, P3, P4, circuitry.

R3, R4

A11, A15, C18,

D11, D15, D17,

J17, J20, R17, VDR NONE Power Supply for the Output Drivers.

R20, T17, U11,

U15, U16, Y11,

Y15

A8, B9, C8, V8, VENONE Power Supply for the Digital Encoder.

W9, Y8 Bias Voltage I-channel. This is an externally

decoupled bias voltage for the I-channel. Each pin

J4, K2 VbiasI NONE should individually be decoupled with a 100 nF

capacitor via a low resistance, low inductance

path to GND.

Bias Voltage Q-channel. This is an externally

decoupled bias voltage for the Q-channel. Each

L2, M4 VbiasQ NONE pin should individually be decoupled with a 100 nF

capacitor via a low resistance, low inductance

path to GND.

Product Folder Links: ADC12D1000 ADC12D1600

VDR

DR GND

VDR

DR GND

ADC12D1000, ADC12D1600

SNAS480M –MAY 2010–REVISED MARCH 2013

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Table 3. Power and Ground Balls (continued)

Ball No. Name Equivalent Circuit Description

A1, A7, B2, B7,

D4, D5, E4, K1,

L1, T4, U4, U5, GND NONE Ground Return for the Analog circuitry.

W2, W7, Y1, Y7,

H8:N13

F2, G2, H3, J2,

K4, L4, M2, N3, Ground Return for the Track-and-Hold and Clock

GNDTC NONE

P2, R2, T2, T3, circuitry.

A13, A17, A20,

D13, D16, E17,

F17, F20, M17, GNDDR NONE Ground Return for the Output Drivers.

M20, U13, U17,

V18, Y13, Y17,

Y20

A9, B8, C9, V9, GNDENONE Ground Return for the Digital Encoder.

W8, Y9

Table 4. High-Speed Digital Outputs

Ball No. Name Equivalent Circuit Description

Data Clock Output for the I- and Q-channel data

bus. These differential clock outputs are used to

latch the output data and, if used, should always

be terminated with a 100Ωdifferential resistor

placed as closely as possible to the differential

receiver. Delayed and non-delayed data outputs

K19/K20 DCLKI+/- are supplied synchronously to this signal. In 1:2

L19/L20 DCLKQ+/- Demux Mode or Non-Demux Mode, this signal is

at ¼ or ½ the sampling clock rate, respectively.

DCLKI and DCLKQ are always in phase with each

other, unless one channel is powered down, and

do not require a pulse from DCLK_RST to

become synchronized.

Out-of-Range Output for the I- and Q-channel.

This differential output is asserted logic-high while

the over- or under-range condition exists, i.e. the

differential signal at each respective analog input

K17/K18 ORI+/- exceeds the full-scale value. Each OR result

L17/L18 ORQ+/- refers to the current Data, with which it is clocked

out. If used, each of these outputs should always

be terminated with a 100Ωdifferential resistor

placed as closely as possible to the differential

receiver.

Product Folder Links: ADC12D1000 ADC12D1600

VDR

DR GND

VDR

DR GND

ADC12D1000, ADC12D1600

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SNAS480M –MAY 2010–REVISED MARCH 2013

Table 4. High-Speed Digital Outputs (continued)

Ball No. Name Equivalent Circuit Description

J18/J19 DI11+/-

H19/H20 DI10+/-

H17/H18 DI9+/-

G19/G20 DI8+/-

G17/G18 DI7+/-

F18/F19 DI6+/-

E19/E20 DI5+/- I- and Q-channel Digital Data Outputs. In Non-

D19/D20 DI4+/- Demux Mode, this LVDS data is transmitted at the

D18/E18 DI3+/- sampling clock rate. In Demux Mode, these

C19/C20 DI2+/- outputs provide ½ the data at ½ the sampling

B19/B20 DI1+/- clock rate, synchronized with the delayed data, i.e.

B18/C17 DI0+/- the other ½ of the data which was sampled one

· · clock cycle earlier. Compared with the DId and

M18/M19 DQ11+/- DQd outputs, these outputs represent the later

N19/N20 DQ10+/- time samples. If used, each of these outputs

N17/N18 DQ9+/- should always be terminated with a 100Ω

P19/P20 DQ8+/- differential resistor placed as closely as possible

P17/P18 DQ7+/- to the differential receiver.

R18/R19 DQ6+/-

T19/T20 DQ5+/-

U19/U20 DQ4+/-

U18/T18 DQ3+/-

V19/V20 DQ2+/-

W19/W20 DQ1+/-

W18/V17 DQ0+/-

A18/A19 DId11+/-

B17/C16 DId10+/-

A16/B16 DId9+/-

B15/C15 DId8+/-

C14/D14 DId7+/-

A14/B14 DId6+/-

B13/C13 DId5+/-

C12/D12 DId4+/- Delayed I- and Q-channel Digital Data Outputs. In

A12/B12 DId3+/- Non-Demux Mode, these outputs are at TRI-

B11/C11 DId2+/- STATE. In Demux Mode, these outputs provide ½

C10/D10 DId1+/- the data at ½ the sampling clock rate,

A10/B10 DId0+/- synchronized with the non-delayed data, i.e. the

· · other ½ of the data which was sampled one clock

Y18/Y19 DQd11+/- cycle later. Compared with the DI and DQ outputs,

W17/V16 DQd10+/- these outputs represent the earlier time samples.

Y16/W16 DQd9+/- If used, each of these outputs should always be

W15/V15 DQd8+/- terminated with a 100Ωdifferential resistor placed

V14/U14 DQd7+/- as closely as possible to the differential receiver.

Y14/W14 DQd6+/-

W13/V13 DQd5+/-

V12/U12 DQd4+/-

Y12/W12 DQd3+/-

W11/V11 DQd2+/-

V10/U10 DQd1+/-

Y10/W10 DQd0+/-

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Product Folder Links: ADC12D1000 ADC12D1600

ADC12D1000, ADC12D1600

SNAS480M –MAY 2010–REVISED MARCH 2013

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Absolute Maximum Ratings(1)(2)

Supply Voltage (VA, VTC, VDR, VE) 2.2V

Supply Difference

max(VA/TC/DR/E)-

min(VA/TC/DR/E) 0V to 100 mV

Voltage on Any Input Pin −0.15V to

(except VIN+/-) (VA+ 0.15V)

VIN+/- Voltage Range -0.5V to 2.5V

Ground Difference

max(GNDTC/DR/E)

-min(GNDTC/DR/E) 0V to 100 mV

Input Current at Any Pin(3) ±50 mA

ADC12D1000 Package Power Dissipation at TA≤75°C(3) 4.06 W

ADC12D1600 Package Power Dissipation at TA≤65°C(3) 4.37 W

ESD Susceptibility(4) Human Body Model 2500V

Charged Device Model 1000V

Machine Model 250V

Storage Temperature −65°C to +150°C

(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. There is no specification of operation at the

Absolute Maximum Ratings. Operating Ratings indicate conditions for which the device is functional, but do not ensure specific

performance limits. For ensured specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply

only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test

conditions.

(2) All voltages are measured with respect to GND = GNDTC = GNDDR = GNDE= 0V, unless otherwise specified.

(3) When the input voltage at any pin exceeds the power supply limits, i.e. less than GND or greater than VA, the current at that pin should

be limited to 50 mA. In addition, over-voltage at a pin must adhere to the maximum voltage limits. Simultaneous over-voltage at multiple

pins requires adherence to the maximum package power dissipation limits. These dissipation limits are calculated using JEDEC

JESD51-7 thermal model. Higher dissipation may be possible based on specific customer thermal situation and specified package

thermal resistances from junction to case.

(4) Human body model is 100 pF capacitor discharged through a 1.5 kΩresistor. Machine model is 220 pF discharged through 0Ω.

Charged device model simulates a pin slowly acquiring charge (such as from a device sliding down the feeder in an automated

assembler) then rapidly being discharged.

Operating Ratings(1)(2)

Ambient Temperature Range ADC12D1000 (Standard JEDEC thermal

model) −40°C ≤TA≤+75°C

ADC12D1600 (Standard JEDEC thermal

model) −40°C ≤TA≤+65°C

ADC12D1000/1600 (Enhanced thermal

model/heatsink) −40°C ≤TA≤+85°C

Junction Temperature Range - applies only to ADC12D1000 Junction Temperature Range TJ≤+140°C

maximum operating speed. ADC12D1600 Junction Temperature Range TJ≤+135°C

Supply Voltage (VA, VTC, VE) +1.8V to +2.0V

Driver Supply Voltage (VDR) +1.8V to VA

VIN+/- Voltage Range(3) -0.4V to 2.4V

(d.c.-coupled)

VIN+/- Differential Voltage(4) 1.0V (d.c.-coupled @100% duty cycle)

2.0V (d.c.-coupled @20% duty cycle)

2.8V (d.c.-coupled @10% duty cycle)

VIN+/- Current Range(3) ±50 mA peak

(a.c.-coupled)

(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. There is no specification of operation at the

Absolute Maximum Ratings. Operating Ratings indicate conditions for which the device is functional, but do not ensure specific

performance limits. For ensured specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply

only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test

conditions.

(2) All voltages are measured with respect to GND = GNDTC = GNDDR = GNDE= 0V, unless otherwise specified.

(3) Proper common mode voltage must be maintained to ensure proper output codes, especially during input overdrive.

(4) This rating is intended for d.c.-coupled applications; the voltages listed may be safely applied to VIN+/- for the life-time duty-cycle of the

part.

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Operating Ratings(1)(2) (continued)

VIN+/- Power 15.3 dBm

(maintaining common mode voltage, a.c.-

coupled)

17.1 dBm

(not maintaining common mode

voltage,a.c.-coupled)

Ground Difference

max(GNDTC/DR/E)

-min(GNDTC/DR/E) 0V

CLK+/- Voltage Range 0V to VA

Differential CLK Amplitude 0.4VP-P to 2.0VP-P

Common Mode Input Voltage VCMO - 150mV < VCMI < VCMO +150mV

Package Thermal Resistance

Package θJA θJC1 θJC2

292-Ball BGA Thermally Enhanced Package 16°C/W 2.9°C/W 2.5°C/W

Soldering process must comply with Reflow Temperature Profile specifications. Refer to http://www.ti.com/packaging.(1)

(1) Reflow temperature profiles are different for lead-free and non-lead-free packages.

Converter Electrical Characteristics

Static Converter Characteristics

Unless otherwise specified, the following apply after calibration for VA= VDR = VTC = VE= +1.9V; I- and Q-channels, AC-

coupled, unused channel terminated to AC ground, FSR Pin = High; CL= 10 pF; Differential, AC coupled Sine Wave

Sampling Clock, fCLK = 1.0/1.6 GHz at 0.5 VP-P with 50% duty cycle (as specified); VBG = Floating; Non-Extended Control

Mode; Rext = Rtrim = 3300Ω± 0.1%; Analog Signal Source Impedance = 100ΩDifferential; 1:2 Demultiplex Non-DES Mode;

Duty Cycle Stabilizer on. Boldface limits apply for TA= TMIN to TMAX. All other limits TA= 25°C, unless otherwise

noted.(1)(2)(3)

ADC12D1000 ADC12D1600 Units

Symbol Parameter Conditions (Limits)

Typ Lim Typ Lim

Resolution with No Missing Codes 12 12 bits

INL Integral Non-Linearity 1 MHz DC-coupled over-ranged ±2.5 ±4.8 ±2.5 ±4.8 LSB (max)

(Best fit) sine wave

DNL Differential Non-Linearity 1 MHz DC-coupled over-ranged ±0.4 ±0.9 ±0.4 ±0.9 LSB (max)

sine wave

VOFF Offset Error 5 5 LSB

VOFF_ADJ Input Offset Adjustment Range Extended Control Mode ±45 ±45 mV

PFSE Positive Full-Scale Error See(4) ±25 ±25 mV (max)

NFSE Negative Full-Scale Error See(4) ±25 ±25 mV (max)

Out-of-Range Output Code(5) (VIN+) −(VIN−) > + Full Scale 4095 4095

(VIN+) −(VIN−) < −Full Scale 0 0

(1) The analog inputs, labeled "I/O", are protected as shown below. Input voltage magnitudes beyond the Absolute Maximum Ratings may

damage this device (see Figure 3).

(2) To ensure accuracy, it is required that VA, VTC, VEand VDR be well-bypassed. Each supply pin must be decoupled with separate bypass

capacitors.

(3) Typical figures are at TA= 25°C, and represent most likely parametric norms. Test limits are ensured to TI's AOQL (Average Outgoing

Quality Level).

(4) Calculation of Full-Scale Error for this device assumes that the actual reference voltage is exactly its nominal value. Full-Scale Error for

this device, therefore, is a combination of Full-Scale Error and Reference Voltage Error. See Figure 6. For relationship between Gain

Error and Full-Scale Error, see Specification Definitions for Gain Error.

(5) This parameter is specified by design and is not tested in production.

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Dynamic Converter Characteristics ADC12D1000 ADC12D1600 Units

Symbol Parameter Conditions (Limits)

Typ Lim Typ Lim

FPBW Full Power Bandwidth Non-DES Mode 2.8 2.8 GHz

DESI, DESQ Mode 1.25 1.25 GHz

DESIQ Mode 1.75 1.75 GHz

Gain Flatness Non-DES Mode

D.C. to Fs/2 0.35 0.5 dB

D.C. to Fs 0.5 1.0 dB

DESI, DESQ Mode

D.C. to Fs/2 2.4 4.0 dB

DESIQ Mode

D.C. to Fs/2 1.9 2.0 dB

CER Code Error Rate Error/Sam

10-18 10-18 ple

NPR Noise Power Ratio See(1) 49.5 48.5 dB

IMD3 3rd order Intermodulation FIN1 = 1212.52 MHz @ -7dBFS -66 -63 dBFS

Distortion FIN2 = 1217.52 MHz @ -7dBFS -59 -56 dBc

DESIQ Mode

Noise Floor Density 50Ωsingle-ended termination, -152.6 -153.6 dBm/Hz

DES Mode -151.6 -152.6 dBFS/Hz

Wideband input, DES Mode(2) -151.5 -152.6 dBm/Hz

-150.5 -151.6 dBFS/Hz

Non-DES Mode(3)(4)

ENOB Effective Number of Bits AIN = 125 MHz @ -0.5 dBFS 9.6 9.4 bits

AIN = 248 MHz @ -0.5 dBFS 9.5 8.7 9.4 8.6 bits (min)

AIN = 498 MHz @ -0.5 dBFS 9.4 8.7 9.3 8.6 bits (min)

AIN = 998 MHz @ -0.5 dBFS 8.9 8.9 bits

AIN = 1448 MHz @ -0.5 dBFS 8.6 8.6 bits

SINAD Signal-to-Noise Plus Distortion AIN = 125 MHz @ -0.5 dBFS 59.7 58.2 dB

Ratio AIN = 248 MHz @ -0.5 dBFS 59 54.1 58 53.5 dB (min)

AIN = 498 MHz @ -0.5 dBFS 58.2 54.1 57.8 53.5 dB (min)

AIN = 998 MHz @ -0.5 dBFS 55.4 55.1 dB

AIN = 1448 MHz @ -0.5 dBFS 53.6 53.8 dB

SNR Signal-to-Noise Ratio AIN = 125 MHz @ -0.5 dBFS 60.2 58.5 dB

AIN = 248 MHz @ -0.5 dBFS 59.7 55.1 58.7 54.6 dB (min)

AIN = 498 MHz @ -0.5 dBFS 58.7 55.1 58.5 54.6 dB (min)

AIN = 998 MHz @ -0.5 dBFS 56.3 56.5 dB

AIN = 1448 MHz @ -0.5 dBFS 54.1 55 dB

(1) The NPR was measured using an Agilent N6030A Arbitrary Waveform Generator (ARB) to generate the input signal. See the Wideband

Performance for an example spectrum. The "noise" portion of the signal was created by tones spaced at 500kHz and the "notch" was a

25MHz absence of tones centered at 320MHz. The bandwidth of this equipment is only 500MHz, so the final reported NPR was

extrapolated from the measured NPR as if the entire Nyquist band were occupied with noise.

(2) The Noise Floor was measured for two conditions: the analog input terminated with 50Ω, and in the presence of a 500MHz wideband

noise signal with total power just below the maximum input level to the ADC. In both cases, the spurs at DC, Fs/4 and Fs/2 were

removed. The power over the entire Nyquist band (except the noise signal) was integrated and the average number is reported.

(3) The Dynamic Specifications are ensured for room to hot ambient temperature only (25°C to 85°C). Refer to the plots of the dynamic

performance vs. temperature in the Typical Performance Plots to see typical performance from cold to room temperature (-40°C to

25°C).

(4) The Fs/2 spur was removed from all the dynamic performance spectifications.

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Dynamic Converter Characteristics (continued) ADC12D1000 ADC12D1600 Units

Symbol Parameter Conditions (Limits)

Typ Lim Typ Lim

THD Total Harmonic Distortion AIN = 125 MHz @ -0.5 dBFS -68.7 -70.3 dB

AIN = 248 MHz @ -0.5 dBFS -67 -61 -66.6 -60 dB (max)

AIN = 498 MHz @ -0.5 dBFS -67.4 -61 -66 -60 dB (max)

AIN = 998 MHz @ -0.5 dBFS -62.9 -60.8 dB

AIN = 1448 MHz @ -0.5 dBFS -63 -60 dB

2nd Harm Second Harmonic Distortion AIN = 125 MHz @ -0.5 dBFS -75.7 -75 dBc

AIN = 248 MHz @ -0.5 dBFS -75.7 -80 dBc

AIN = 498 MHz @ -0.5 dBFS -79.8 -71 dBc

AIN = 998 MHz @ -0.5 dBFS -70 -73 dBc

AIN = 1448 MHz @ -0.5 dBFS -67 -67 dBc

3rd Harm Third Harmonic Distortion AIN = 125 MHz @ -0.5 dBFS -71 -74 dBc

AIN = 248 MHz @ -0.5 dBFS -68.4 -68 dBc

AIN = 498 MHz @ -0.5 dBFS -68.7 -69 dBc

AIN = 998 MHz @ -0.5 dBFS -66 -62 dBc

AIN = 1448 MHz @ -0.5 dBFS -67 -61 dBc

SFDR Spurious-Free Dynamic Range AIN = 125 MHz @ -0.5 dBFS 71 70.3 dBc

AIN = 248 MHz @ -0.5 dBFS 68.4 61 68 60 dBc (min)

AIN = 498 MHz @ -0.5 dBFS 68.7 61 68.2 60 dBc (min)

AIN = 998 MHz @ -0.5 dBFS 66 62 dBc

AIN = 1448 MHz @ -0.5 dBFS 67 61.9 dBc

DES Mode(3)(5)(4)

ENOB Effective Number of Bits AIN = 125 MHz @ -0.5 dBFS 9.5 9.4 bits

AIN = 248 MHz @ -0.5 dBFS 9.4 8.7 9.2 8.6 bits (min)

AIN = 498 MHz @ -0.5 dBFS 9.2 9.1 bits

AIN = 998 MHz @ -0.5 dBFS 8.8 8.5 bits

AIN = 1448 MHz @ -0.5 dBFS 8.6 8.5 bits

SINAD Signal-to-Noise Plus Distortion AIN = 125 MHz @ -0.5 dBFS 59 58.2 dB

Ratio AIN = 248 MHz @ -0.5 dBFS 58.6 54 57 53.5 dB (min)

AIN = 498 MHz @ -0.5 dBFS 57.3 56.9 dB

AIN = 998 MHz @ -0.5 dBFS 54.5 52.7 dB

AIN = 1448 MHz @ -0.5 dBFS 53.9 52.7 dB

SNR Signal-to-Noise Ratio AIN = 125 MHz @ -0.5 dBFS 59.2 58.6 dB

AIN = 248 MHz @ -0.5 dBFS 58.9 55.3 57.9 54.6 dB (min)

AIN = 498 MHz @ -0.5 dBFS 58.3 57.6 dB

AIN = 998 MHz @ -0.5 dBFS 55.9 53.6 dB

AIN = 1448 MHz @ -0.5 dBFS 54.2 53.3 dB

THD Total Harmonic Distortion AIN = 125 MHz @ -0.5 dBFS -74 -68.2 dB

AIN = 248 MHz @ -0.5 dBFS -71.2 -60 -64.6 -60 dB (max)

AIN = 498 MHz @ -0.5 dBFS -63.8 -66.3 dB

AIN = 998 MHz @ -0.5 dBFS -60 -60 dB

AIN = 1448 MHz @ -0.5 dBFS -65 -61.7 dB

(5) These measurements were taken in Extended Control Mode (ECM) with the DES Timing Adjust feature enabled (Addr: 7h). This feature

is used to reduce the interleaving timing spur amplitude, which occurs at fs/2-fin, and thereby increase the SFDR, SINAD and ENOB.

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Dynamic Converter Characteristics (continued) ADC12D1000 ADC12D1600 Units

Symbol Parameter Conditions (Limits)

Typ Lim Typ Lim

2nd Harm Second Harmonic Distortion AIN = 125 MHz @ -0.5 dBFS -82 -77.3 dBc

AIN = 248 MHz @ -0.5 dBFS -82 -82.7 dBc

AIN = 498 MHz @ -0.5 dBFS -72 -71.6 dBc

AIN = 998 MHz @ -0.5 dBFS -63.2 -63 dBc

AIN = 1448 MHz @ -0.5 dBFS -75 -75.6 dBc

3rd Harm Third Harmonic Distortion AIN = 125 MHz @ -0.5 dBFS -82 -69.8 dBc

AIN = 248 MHz @ -0.5 dBFS -73 -65.3 dBc

AIN = 498 MHz @ -0.5 dBFS -65 -67.3 dBc

AIN = 998 MHz @ -0.5 dBFS -65 -63 dBc

AIN = 1448 MHz @ -0.5 dBFS -67 -62.4 dBc

SFDR Spurious-Free Dynamic Range AIN = 125 MHz @ -0.5 dBFS 69 69.8 dBc

AIN = 248 MHz @ -0.5 dBFS 69 60 65.3 60 dBc (min)

AIN = 498 MHz @ -0.5 dBFS 65 67.3 dBc

AIN = 998 MHz @ -0.5 dBFS 64 60.2 dBc

AIN = 1448 MHz @ -0.5 dBFS 66 60 dBc

Analog Input/Output and Reference Characteristics ADC12D1000 ADC12D1600 Units

Symbol Parameter Conditions (Limits)

Typ Lim Typ Lim

Analog Inputs

VIN_FSR Analog Differential Input Full Non-Extended Control Mode

Scale Range FSR Pin Low 540 540 mVP-P (min)

600 600 mVP-P

660 660 (max)

FSR Pin High 740 740 mVP-P (min)

800 800 mVP-P

860 860 (max)

Extended Control Mode

FM(14:0) = 0000h600 600 mVP-P

FM(14:0) = 4000h800 800 mVP-P

(default)

FM(14:0) = 7FFFh1000 1000 mVP-P

CIN Analog Input Capacitance, Differential 0.02 0.02 pF

Non-DES Mode(1)(2) Each input pin to ground 1.6 1.6 pF

Analog Input Capacitance, Differential 0.08 0.08 pF

DES Mode(1)(2) Each input pin to ground 2.2 2.2 pF

RIN Differential Input Resistance 91 91 Ω(min)

100 100

109 109 Ω(max)

(1) This parameter is specified by design and is not tested in production.

(2) The differential and pin-to-ground input capacitances are lumped capacitance values from design; they are defined as shown below (see

Figure 4).

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Analog Input/Output and Reference Characteristics (continued)

ADC12D1000 ADC12D1600 Units

Symbol Parameter Conditions (Limits)

Typ Lim Typ Lim

Common Mode Output

VCMO Common Mode Output Voltage ICMO = ±100 µA 1.15 1.15 V (min)

1.25 1.25

1.35 1.35 V (max)

TC_VCMO Common Mode Output Voltage ICMO = ±100 µA 38 38 ppm/°C

Temperature Coefficient

VCMO_LVL VCMO input threshold to set 0.63 0.63 V

DC-coupling Mode

CL_VCMO Maximum VCMO Load See(3) 80 80 pF

Capacitance

Bandgap Reference

VBG Bandgap Reference Output IBG = ±100 µA 1.15 1.15 V (min)

1.25 1.25

Voltage 1.35 1.35 V (max)

TC_VBG Bandgap Reference Voltage IBG = ±100 µA 32 32 ppm/°C

Temperature Coefficient

CL_VBG Maximum Bandgap Reference See(3) 80 80 pF

load Capacitance

(3) This parameter is specified by design and is not tested in production.

I-Channel to Q-Channel Characteristics ADC12D1000 ADC12D1600 Units

Symbol Parameter Conditions (Limits)

Typ Lim Typ Lim

Offset Match 2 2 LSB

Positive Full-Scale Match Zero offset selected in 2 2 LSB

Control Register

Negative Full-Scale Match Zero offset selected in 2 2 LSB

Control Register

Phase Matching (I, Q) fIN = 1.0 GHz < 1 < 1 Degree

X-TALK Crosstalk from I-channel Aggressor = 867 MHz F.S. −70 −70 dB

(Aggressor) to Q-channel (Victim) Victim = 100 MHz F.S.

Crosstalk from Q-channel Aggressor = 867 MHz F.S. −70 −70 dB

(Aggressor) to I-channel (Victim) Victim = 100 MHz F.S.

Converter Electrical Characteristics Sampling Clock Characteristics

ADC12D1000 ADC12D1600 Units

Symbol Parameter Conditions (Limits)

Typ Lim Typ Lim

VIN_CLK Differential Sampling Clock Input Sine Wave Clock 0.4 0.4 VP-P (min)

0.6 0.6

Level(1) Differential Peak-to-Peak 2.0 2.0 VP-P (max)

Square Wave Clock 0.4 0.4 VP-P (min)

0.6 0.6

Differential Peak-to-Peak 2.0 2.0 VP-P (max)

CIN_CLK Sampling Clock Input Differential 0.1 0.1 pF

Capacitance(2) Each input to ground 1 1 pF

RIN_CLK Sampling Clock Differential Input 100 100 Ω

Resistance

(1) This parameter is specified by design and/or characterization and is not tested in production.

(2) This parameter is specified by design and is not tested in production.

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AutoSync Feature Characteristics ADC12D1000 ADC12D1600 Units

Symbol Parameter Conditions (Limits)

Typ Lim Typ Lim

VIN_RCLK Differential RCLK Input Level Differential Peak-to-Peak 360 360 mVP-P

CIN_RCLK RCLK Input Capacitance Differential 0.1 0.1 pF

Each input to ground 1 1 pF

RIN_RCLK RCLK Differential Input 100 100 Ω

Resistance

IIH_RCLK Input Leakage Current; 22 22 µA

VIN = VA

IIL_RCLK Input Leakage Current; -33 -33 µA

VIN = GND

VO_RCOUT Differential RCOut Output Voltage 360 360 mV

Digital Control and Output Pin Characteristics ADC12D1000 ADC12D1600 Units

Symbol Parameter Conditions (Limits)

Typ Lim Typ Lim

Digital Control Pins (DES, CalDly, CAL, PDI, PDQ, TPM, NDM, FSR, DDRPh, ECE, SCLK, SDI, SCS)

VIH Logic High Input Voltage 0.7×VA0.7×VAV (min)

VIL Logic Low Input Voltage 0.3×VA0.3×VAV (max)

IIH Input Leakage Current; 0.02 0.02 μA

VIN = VA

IIL Input Leakage Current; FSR, CalDly, CAL, NDM, TPM, -0.02 -0.02 μA

VIN = GND DDRPh, DES

SCS, SCLK, SDI -17 -17 μA

PDI, PDQ, ECE -38 -38 μA

CIN_DIG Digital Control Pin Input Measured from each control pin to 1.5 1.5 pF

Capacitance(1) GND

Digital Output Pins (Data, DCLKI, DCLKQ, ORI, ORQ)

VOD LVDS Differential Output Voltage VBG = Floating, OVS = High mVP-P

400 400 (min)

630 630 mVP-P

800 800 (max)

VBG = Floating, OVS = Low mVP-P

230 230 (min)

460 460 mVP-P

630 630 (max)

VBG = VA, OVS = High 670 670 mVP-P

VBG = VA, OVS = Low 500 500 mVP-P

ΔVO DIFF Change in LVDS Output Swing ±1 ±1 mV

Between Logic Levels

VOS Output Offset Voltage VBG = Floating 0.8 0.8 V

VBG = VA1.2 1.2 V

ΔVOS Output Offset Voltage Change ±1 ±1 mV

Between Logic Levels

IOS Output Short Circuit Current VBG = Floating; ±4 ±4 mA

D+ and D−connected to 0.8V

ZODifferential Output Impedance 100 100 Ω

VOH Logic High Output Level CalRun, IOH =−100 µA(2),1.65 1.65 V

SDO, IOH =−400 µA(2)

VOL Logic Low Output Level CalRun, IOL = 100 µA(2),0.15 0.15 V

SDO, IOL = 400 µA(2)

(1) This parameter is specified by design and is not tested in production.

(2) This parameter is specified by design and/or characterization and is not tested in production.

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Digital Control and Output Pin Characteristics (continued) ADC12D1000 ADC12D1600 Units

Symbol Parameter Conditions (Limits)

Typ Lim Typ Lim

Differential DCLK Reset Pins (DCLK_RST)

VCMI_DRST DCLK_RST Common Mode Input 1.25 1.25 V

Voltage

VID_DRST Differential DCLK_RST Input VIN_CLK VIN_CLK VP-P

Voltage

RIN_DRST Differential DCLK_RST Input See(1) 100 100 Ω

Resistance

Power Supply Characteristics ADC12D1000 ADC12D1600 Units

Symbol Parameter Conditions (Limits)

Typ Lim Typ Lim

IAAnalog Supply Current PDI = PDQ = Low 1110 1235 mA

PDI = Low; PDQ = High 610 670 mA

PDI = High; PDQ = Low 610 670 mA

PDI = PDQ = High 15 15 mA

ITC Track-and-Hold and Clock Supply PDI = PDQ = Low 400 470 mA

Current PDI = Low; PDQ = High 240 280 mA

PDI = High; PDQ = Low 240 280 mA

PDI = PDQ = High 4 4 mA

IDR Output Driver Supply Current PDI = PDQ = Low 305 325 mA

PDI = Low; PDQ = High 160 170 mA

PDI = High; PDQ = Low 160 170 mA

PDI = PDQ = High 3 3 mA

IEDigital Encoder Supply Current PDI = PDQ = Low 80 140 mA

PDI = Low; PDQ = High 40 70 mA

PDI = High; PDQ = Low 40 70 mA

PDI = PDQ = High 1 1 mA

ITOTAL Total Supply Current 1:2 Demux Mode 1895 2105 2170 2310 mA (max)

PDI = PDQ = Low

Non-Demux Mode 1780 2040 mA (max)

PDI = PDQ = Low

PCPower Consumption 1:2 Demux Mode

PDI = PDQ = Low 3.60 44.12 4.4 W (max)

PDI = Low; PDQ = High 1.99 2.26 W

PDI = High; PDQ = Low 1.99 2.26 W

PDI = PDQ = High 43 43 mW

Non-Demux Mode

PDI = PDQ = Low 3.38 3.88 W (max)

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AC Electrical Characteristics ADC12D1000 ADC12D1600 Units

Symbol Parameter Conditions (Limits)

Typ Lim Typ Lim

Sampling Clock (CLK)

fCLK (max) Maximum Sampling Clock 1.0 1.6 GHz

Frequency

fCLK (min) Minimum Sampling Clock Non-DES Mode; LFS = 0b 300 300 MHz

Frequency Non-DES Mode; LFS = 1b 150 150 MHz

DES Mode 500 500 MHz

Sampling Clock Duty Cycle fCLK(min) ≤fCLK ≤fCLK(max)(1) 20 20 % (min)

50 50

80 80 % (max)

tCL Sampling Clock Low Time See(2) 500 200 312.5 125 ps (min)

tCH Sampling Clock High Time See(2) 500 200 312.5 125 ps (min)

Data Clock (DCLKI, DCLKQ)

DCLK Duty Cycle See(2) 45 45 % (min)

50 50

55 55 % (max)

tSR Setup Time DCLK_RST± See(1) 45 45 ps

tHR Hold Time DCLK_RST± See(1) 45 45 ps

tPWR Pulse Width DCLK_RST± See(2) Sampling

Clock

5 5 Cycles

(min)

tSYNC_DLY DCLK Synchronization Delay 90° Mode(2) 4 4 Sampling

Clock

0° Mode(2) 5 5 Cycles

tLHT Differential Low-to-High Transition 10%-to-90%, CL= 2.5 pF 200 200 ps

Time

tHLT Differential High-to-Low Transition 10%-to-90%, CL= 2.5 pF 200 200 ps

Time

tSU Data-to-DCLK Setup Time 90° Mode(2) 870 500 ps

tHDCLK-to-Data Hold Time 90° Mode(2) 870 500 ps

tOSK DCLK-to-Data Output Skew 50% of DCLK transition to 50% of ±50 ±50 ps (max)

Data transition(2)

Data Input-to-Output

tAD Aperture Delay Sampling CLK+ Rise to 1.15 1.15 ns

Acquisition of Data

tAJ Aperture Jitter 0.2 0.2 ps (rms)

tOD Sampling Clock-to Data Output 50% of Sampling Clock transition 3.2 3.2 ns

Delay (in addition to Latency) to 50% of Data transition

tLAT Latency in 1:2 Demux Non-DES DI, DQ Outputs 34 34

Mode(2) DId, DQd Outputs 35 35

Latency in 1:4 Demux DES DI Outputs 34 34

Mode(2) DQ Outputs 34.5 34.5 Sampling

DId Outputs 35 35 Clock

DQd Outputs 35.5 35.5 Cycles

Latency in Non-Demux Non-DES DI Outputs 34 34

Mode(2) DQ Outputs 34 34

Latency in Non-Demux DES DI Outputs 34 34

Mode(2) DQ Outputs 34.5 34.5

tORR Over Range Recovery Time Differential VIN step from ±1.2V to Sampling

0V to accurate conversion 1 1 Clock

Cycle

(1) This parameter is specified by design and/or characterization and is not tested in production.

(2) This parameter is specified by design and is not tested in production.

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I / O

GND

TO INTERNAL

CIRCUITRY

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AC Electrical Characteristics (continued) ADC12D1000 ADC12D1600 Units

Symbol Parameter Conditions (Limits)

Typ Lim Typ Lim

tWU Wake-Up Time (PDI/PDQ low to Non-DES Mode(2) 500 500 ns

Rated Accuracy Conversion) DES Mode(2) 1 1 µs

Serial Port Interface ADC12D1000 ADC12D1600 Units

Symbol Parameter Conditions (Limits)

Typ Lim Typ Lim

fSCLK Serial Clock Frequency See(1) 15 15 MHz

Serial Clock Low Time 30 30 ns (min)

Serial Clock High Time 30 30 ns (min)

tSSU Serial Data-to-Serial Clock Rising See(1) 2.5 2.5 ns (min)

Setup Time

tSH Serial Data-to-Serial Clock Rising See(1) 1 1 ns (min)

Hold Time

tSCS SCS-to-Serial Clock Rising Setup 2.5 2.5 ns

Time

tHCS SCS-to-Serial Clock Falling Hold 1.5 1.5 ns

Time

tBSU Bus turn-around time 10 10 ns

(1) This parameter is specified by design and is not tested in production.

Calibration ADC12D1000 ADC12D1600 Units

Symbol Parameter Conditions (Limits)

Typ Lim Typ Lim

tCAL Calibration Cycle Time CSS = 0bSampling

5.2·1075.2·107Clock

CSS = 1bCycles

tCAL_L CAL Pin Low Time See(1) 1280 1280 Sampling

Clock

tCAL_H CAL Pin High Time See(1) Cycles

1280 1280 (min)

tCalDly Calibration delay determined by CalDly = Low 224 224 Sampling

CalDly Pin(1) Clock

CalDly = High Cycles

230 230 (max)

(1) This parameter is specified by design and is not tested in production.

Figure 3.

Product Folder Links: ADC12D1000 ADC12D1600

CIN, DIFF

CIN, PIN-TO-GND

VIN+

VIN-

ADC12D1000, ADC12D1600

SNAS480M –MAY 2010–REVISED MARCH 2013

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Figure 4.

Specification Definitions

APERTURE (SAMPLING) DELAY is the amount of delay, measured from the sampling edge of the CLK input,

after which the signal present at the input pin is sampled inside the device.

APERTURE JITTER (tAJ)is the variation in aperture delay from sample-to-sample. Aperture jitter can be

effectively considered as noise at the input.

CODE ERROR RATE (CER) is the probability of error and is defined as the probable number of word errors on

the ADC output per unit of time divided by the number of words seen in that amount of time. A CER of 10-18

corresponds to a statistical error in one word about every 31.7 years for the ADC12D1000.

CLOCK DUTY CYCLE is the ratio of the time that the clock waveform is at a logic high to the total time of one

clock period.

DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1

LSB. It is measured at the relevant sample rate, fCLK, with fIN = 1MHz sine wave.

EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise

and Distortion Ratio, or SINAD. ENOB is defined as (SINAD −1.76) / 6.02 and states that the converter is

equivalent to a perfect ADC of this many (ENOB) number of bits.

FULL POWER BANDWIDTH (FPBW) is a measure of the frequency at which the reconstructed output

fundamental drops to 3 dB below its low frequency value for a full-scale input.

GAIN ERROR is the deviation from the ideal slope of the transfer function. It can be calculated from Offset and

Full-Scale Errors. The Positive Gain Error is the Offset Error minus the Positive Full-Scale Error. The Negative

Gain Error is the Negative Full-Scale Error minus the Offset Error. The Gain Error is the Negative Full-Scale

Error minus the Positive Full-Scale Error; it is also equal to the Positive Gain Error plus the Negative Gain Error.

INTEGRAL NON-LINEARITY (INL) is a measure of worst case deviation of the ADC transfer function from an

ideal straight line drawn through the ADC transfer function. The deviation of any given code from this straight line

is measured from the center of that code value step. The best fit method is used.

INTERMODULATION DISTORTION (IMD) is a measure of the near-in 3rd order distortion products (2f2- f1, 2f1-

f2) which occur when two tones which are close in frequency (f1, f2) are applied to the ADC input. It is measured

from the input tones level to the higher of the two distortion products (dBc) or simply the level of the higher of the

two distortion products (dBFS). The input tones are typically -7dBFS.

LSB (LEAST SIGNIFICANT BIT) is the bit that has the smallest value or weight of all bits. This value is

VFS / 2N(1)

where VFS is the differential full-scale amplitude VIN_FSR as set by the FSR input and "N" is the ADC resolution in

bits, which is 10 for the ADC12D1000/1600.

Product Folder Links: ADC12D1000 ADC12D1600

VD+

VD-

VOS

GND ½×VOD = | VD+ - VD- |

½×VOD

VD-

VD+

ADC12D1000, ADC12D1600

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SNAS480M –MAY 2010–REVISED MARCH 2013

LOW VOLTAGE DIFFERENTIAL SIGNALING (LVDS) DIFFERENTIAL OUTPUT VOLTAGE (VID and VOD)is

two times the absolute value of the difference between the VD+ and VD- signals; each signal measured with

respect to Ground. VOD peak is VOD,P= (VD+-VD-) and VOD peak-to-peak is VOD,P-P= 2*(VD+-VD-); for this

product, the VOD is measured peak-to-peak.

Figure 5. LVDS Output Signal Levels

LVDS OUTPUT OFFSET VOLTAGE (VOS)is the midpoint between the D+ and D- pins output voltage with

respect to ground; i.e., [(VD+) +( VD-)]/2. See Figure 5.

MISSING CODES are those output codes that are skipped and will never appear at the ADC outputs. These

codes cannot be reached with any input value.

MSB (MOST SIGNIFICANT BIT) is the bit that has the largest value or weight. Its value is one half of full scale.

NEGATIVE FULL-SCALE ERROR (NFSE) is a measure of how far the first code transition is from the ideal 1/2

LSB above a differential −VIN/2 with the FSR pin low. For the ADC12D1000/1600 the reference voltage is

assumed to be ideal, so this error is a combination of full-scale error and reference voltage error.

NOISE FLOOR DENSITY is a measure of the power density of the noise floor, expressed in dBFS/Hz and

dBm/Hz. '0 dBFS' is defined as the power of a sinusoid which precisely uses the full-scale range of the ADC.

NOISE POWER RATIO (NPR) is the ratio of the sum of the power outside the notched bins to the sum of the

power in an equal number of bins inside the notch, expressed in dB.

OFFSET ERROR (VOFF)is a measure of how far the mid-scale point is from the ideal zero voltage differential

input.

Offset Error = Actual Input causing average of 8k samples to result in an average code of 2047.5.

OUTPUT DELAY (tOD)is the time delay (in addition to Latency) after the rising edge of CLK+ before the data

update is present at the output pins.

OVER-RANGE RECOVERY TIME is the time required after the differential input voltages goes from ±1.2V to 0V

for the converter to recover and make a conversion with its rated accuracy.

PIPELINE DELAY (LATENCY) is the number of input clock cycles between initiation of conversion and when

that data is presented to the output driver stage. The data lags the conversion by the Latency plus the tOD.

POSITIVE FULL-SCALE ERROR (PFSE) is a measure of how far the last code transition is from the ideal 1-1/2

LSB below a differential +VIN/2. For the ADC12D1000/1600 the reference voltage is assumed to be ideal, so this

error is a combination of full-scale error and reference voltage error.

SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the fundamental for a single-

tone to the rms value of the sum of all other spectral components below one-half the sampling frequency, not

including harmonics or DC.

SIGNAL TO NOISE PLUS DISTORTION (S/(N+D) or SINAD) is the ratio, expressed in dB, of the rms value of

the fundamental for a single-tone to the rms value of all of the other spectral components below half the input

clock frequency, including harmonics but excluding DC.

SPURIOUS-FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the rms values of the

input signal at the output and the peak spurious signal, where a spurious signal is any signal present in the

output spectrum that is not present at the input, excluding DC.

θJA is the thermal resistance between the junction to ambient.

Product Folder Links: ADC12D1000 ADC12D1600

ACTUAL

POSITIVE

FULL-SCALE

TRANSITION

-VIN/2

ACTUAL NEGATIVE

FULL-SCALE TRANSITION

1111 1111 1111 (4095)

1111 1111 1110 (4094)

1111 1111 1101 (4093)

MID-SCALE

TRANSITION

(VIN+) < (VIN-) (VIN+) > (VIN-)

0.0V

Differential Analog Input Voltage (+VIN/2) - (-VIN/2)

Output

Code

OFFSET

ERROR

1000 0000 0000 (2048)

0111 1111 1111 (2047)

IDEAL

POSITIVE

FULL-SCALE

TRANSITION

POSITIVE

FULL-SCALE

ERROR

NEGATIVE

FULL-SCALE

ERROR

IDEAL NEGATIVE

FULL-SCALE TRANSITION

+VIN/2

0000 0000 0000 (0)

0000 0000 0001 (1)

0000 0000 0010 (2)

THD = 20 x log + . . . + AAf22

f102

Af12

ADC12D1000, ADC12D1600

SNAS480M –MAY 2010–REVISED MARCH 2013

www.ti.com

θJC1 represents the thermal resistance between the die and the exposed metal area on the top of the HSBGA

package.

θJC2 represents the thermal resistance between the die and the center group of balls on the bottom of the

HSBGA package.

TOTAL HARMONIC DISTORTION (THD) is the ratio expressed in dB, of the rms total of the first nine harmonic

levels at the output to the level of the fundamental at the output. THD is calculated as

where

• where Af1 is the RMS power of the fundamental (output) frequency and Af2 through Af10 are the RMS power of

the first 9 harmonic frequencies in the output spectrum. (2)

Second Harmonic Distortion (2nd Harm) is the difference, expressed in dB, between the RMS power in

the input frequency seen at the output and the power in its 2nd harmonic level at the output.

Third Harmonic Distortion (3rd Harm) is the difference expressed in dB between the RMS power in the

input frequency seen at the output and the power in its 3rd harmonic level at the output.

Transfer Characteristic

Figure 6. Input / Output Transfer Characteristic

Product Folder Links: ADC12D1000 ADC12D1600

tOD

tAD

Sample N

Sample N+1

Sample N-1

VINQ+/-

CLK+

DCLKQ+/-

(0° Phase)

DQ Sample N-35

Sample N-36

tOSK

Sample N-34 Sample N-33

Sample N-37

tOD

tAD

Sample N

Sample N+1

DId

Sample N-1

VINI+/-

CLK+

DCLKI+/-

(0° Phase)

DId, DI Sample N-35 and Sample N-34

Sample N-37 and Sample N-36

Sample N-39 and

Sample N-38

tOSK

tSU tH

DCLKI+/-

(90° Phase)

ADC12D1000, ADC12D1600

www.ti.com

SNAS480M –MAY 2010–REVISED MARCH 2013

TEST CIRCUIT DIAGRAMS

Timing Diagrams

Figure 7. Clocking in 1:2 Demux Non-DES Mode*

Figure 8. Clocking in Non-Demux Non-DES Mode*

Product Folder Links: ADC12D1000 ADC12D1600

tOD

tAD

Sample N

Sample N+1

Sample N-1

VINQ+/-

CLK+

DCLKQ+/-

(0° Phase)

DQ, DI Sample N-35.5, N-35

tOSK

Sample N-34.5, N-34 Sample N-33.5, N-33

Sample N-36.5, N-36Sample N-37.5, N-37

Sample N + 0.5

Sample N - 0.5

tOD

tAD

Sample N

Sample N+1

DId

Sample N-1

VINQ+/-

CLK+/-

DCLKQ+/-

(0° Phase)

DQd, DId,

DQ, DI Sample N-35.5, N-35,

N-34.5, N-34

Sample N-37.5, N-37,

N-36.5, N-36

Sample N-39.5, N-39,

N-38.5, N-38

tOSK

tSU tH

DCLKQ+/-

(90° Phase)

Sample N-0.5

Sample

N-1.5

DQd

ADC12D1000, ADC12D1600

SNAS480M –MAY 2010–REVISED MARCH 2013

www.ti.com

Figure 9. Clocking in 1:4 Demux DES Mode*

Figure 10. Clocking in Non-Demux Mode DES Mode*

* The timing for these figures is shown for the one input only (I or Q). However, both I- and Q-inputs may be

used. For this case, the I-channel functions precisely the same as the Q-channel, with VinI, DCLKI, DId and DI

instead of VinQ, DCLKQ, DQd and DQ. Both I- and Q-channel use the same CLK.

Product Folder Links: ADC12D1000 ADC12D1600

SCLK

18 9 24

Single Register Access

SCS

SDI Command Field

MSB LSB

Data Field

tSSU

tSH

tSCS

tHCS

SDO

read mode)

MSB LSB

Data Field

tBSU

High Z High Z

CalRun

POWER

SUPPLY

CAL

tCAL

Calibration Delay

determined by

CalDly (Pin V4)

tCalDly

tCAL_L

tCAL_H

CLK

Synchronizing Edge

DCLKI+

DCLKQ+

tHR

DCLK_RST-

tPWR

tSR

DCLK_RST+ tOD

tSYNC_DLY

ADC12D1000, ADC12D1600

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SNAS480M –MAY 2010–REVISED MARCH 2013

Figure 11. Data Clock Reset Timing (Demux Mode)

Figure 12. Power-on and On-Command Calibration Timing

Figure 13. Serial Interface Timing

Product Folder Links: ADC12D1000 ADC12D1600

0 4,095

-0.75

-0.50

-0.25

0.00

0.25

0.50

0.75

DNL (LSB)

OUTPUT CODE

0 4,095

-0.75

-0.50

-0.25

0.00

0.25

0.50

0.75

DNL (LSB)

OUTPUT CODE

-50 0 50 100

-1.0

-0.5

0.0

0.5

1.0

INL (LSB)

TEMPERATURE (°C)

+INL

-INL

-50 0 50 100

-1.0

-0.5

0.0

0.5

1.0

INL (LSB)

TEMPERATURE (°C)

+INL

-INL

0 4,095

-3

-2

-1

INL (LSB)

OUTPUT CODE

0 4,095

-3

-2

-1

INL (LSB)

OUTPUT CODE

ADC12D1000, ADC12D1600

SNAS480M –MAY 2010–REVISED MARCH 2013

www.ti.com

Typical Performance Plots

VA= VDR = VTC = VE= 1.9V, fCLK = 1.0/1.6 GHz, fIN = 498 MHz, TA= 25°C, I-channel, 1:2 Demux Non-DES Mode (1:1 Demux

Non-DES Mode has similar performance), unless otherwise stated. For NPR plots, notch width = 25MHz, fc = 320 MHz.

INL vs. CODE (ADC12D1000) INL vs. CODE (ADC12D1600)

Figure 14. Figure 15.

INL vs. TEMPERATURE (ADC12D1000) INL vs. TEMPERATURE (ADC12D1600)

Figure 16. Figure 17.

DNL vs. CODE (ADC12D1000) DNL vs. CODE (ADC12D1600)

Figure 18. Figure 19.

Product Folder Links: ADC12D1000 ADC12D1600

1.6 1.8 2.0 2.2

ENOB

VA(V)

NON-DES MODE

DES MODE

1.6 1.8 2.0 2.2

ENOB

VA(V)

NON-DES MODE

DES MODE

-50 0 50 100

ENOB

TEMPERATURE (°C)

NON-DES MODE

DES MODE

-50 0 50 100

ENOB

TEMPERATURE (°C)

NON-DES MODE

DES MODE

-50 0 50 100

-0.50

-0.25

0.00

0.25

0.50

DNL (LSB)

TEMPERATURE (°C)

+DNL

-DNL

-50 0 50 100

-0.50

-0.25

0.00

0.25

0.50

DNL (LSB)

TEMPERATURE (°C)

+DNL

-DNL

ADC12D1000, ADC12D1600

www.ti.com

SNAS480M –MAY 2010–REVISED MARCH 2013

Typical Performance Plots (continued)

VA= VDR = VTC = VE= 1.9V, fCLK = 1.0/1.6 GHz, fIN = 498 MHz, TA= 25°C, I-channel, 1:2 Demux Non-DES Mode (1:1 Demux

Non-DES Mode has similar performance), unless otherwise stated. For NPR plots, notch width = 25MHz, fc = 320 MHz.

DNL vs. TEMPERATURE (ADC12D1000) DNL vs. TEMPERATURE (ADC12D1600)

Figure 20. Figure 21.

ENOB vs. TEMPERATURE (ADC12D1000) ENOB vs. TEMPERATURE (ADC12D1600)

Figure 22. Figure 23.

ENOB vs. SUPPLY VOLTAGE (ADC12D1000) ENOB vs. SUPPLY VOLTAGE (ADC12D1600)

Figure 24. Figure 25.

Product Folder Links: ADC12D1000 ADC12D1600

0.75 1.00 1.25 1.50 1.75

ENOB

VCMI(mV)

NON-DES MODE

DES MODE

0.75 1.00 1.25 1.50 1.75

ENOB

VCMI(mV)

NON-DES MODE

DES MODE

0 500 1,000 1,500

ENOB

INPUT FREQUENCY (MHz)

NON-DES MODE

DES MODE

0 500 1,000 1,500

ENOB

INPUT FREQUENCY (MHz)

NON-DES MODE

DES MODE

0 250 500 750 1,000

ENOB

CLOCK FREQUENCY (MHz)

NON-DES MODE

DES MODE

0 400 800 1,200 1,600

ENOB

CLOCK FREQUENCY (MHz)

NON-DES MODE

DES MODE

ADC12D1000, ADC12D1600

SNAS480M –MAY 2010–REVISED MARCH 2013

www.ti.com

Typical Performance Plots (continued)

VA= VDR = VTC = VE= 1.9V, fCLK = 1.0/1.6 GHz, fIN = 498 MHz, TA= 25°C, I-channel, 1:2 Demux Non-DES Mode (1:1 Demux

Non-DES Mode has similar performance), unless otherwise stated. For NPR plots, notch width = 25MHz, fc = 320 MHz.

ENOB vs. CLOCK FREQUENCY (ADC12D1000) ENOB vs. CLOCK FREQUENCY (ADC12D1600)

Figure 26. Figure 27.

ENOB vs. INPUT FREQUENCY (ADC12D1000) ENOB vs. INPUT FREQUENCY (ADC12D1600)

Figure 28. Figure 29.

ENOB vs. VCMI (ADC12D1000) ENOB vs. VCMI (ADC12D1600)

Figure 30. Figure 31.

Product Folder Links: ADC12D1000 ADC12D1600

0 250 500 750 1,000

SNR (dB)

CLOCK FREQUENCY (MHz)

NON-DES MODE

DES MODE

0 400 800 1,200 1,600

SNR (dB)

CLOCK FREQUENCY (MHz)

NON-DES MODE

DES MODE

1.6 1.8 2.0 2.2

SNR (dB)

VA(V)

NON-DES MODE

DES MODE

1.6 1.8 2.0 2.2

SNR (dB)

VA(V)

NON-DES MODE

DES MODE

-50 0 50 100

SNR (dB)

TEMPERATURE (°C)

NON-DES MODE

DES MODE

-50 0 50 100

SNR (dB)

TEMPERATURE (°C)

NON-DES MODE

DES MODE

ADC12D1000, ADC12D1600

www.ti.com

SNAS480M –MAY 2010–REVISED MARCH 2013

Typical Performance Plots (continued)

VA= VDR = VTC = VE= 1.9V, fCLK = 1.0/1.6 GHz, fIN = 498 MHz, TA= 25°C, I-channel, 1:2 Demux Non-DES Mode (1:1 Demux

Non-DES Mode has similar performance), unless otherwise stated. For NPR plots, notch width = 25MHz, fc = 320 MHz.

SNR vs. TEMPERATURE (ADC12D1000) SNR vs. TEMPERATURE (ADC12D1600)

Figure 32. Figure 33.

SNR vs. SUPPLY VOLTAGE (ADC12D1000) SNR vs. SUPPLY VOLTAGE (ADC12D1600)

Figure 34. Figure 35.

SNR vs. CLOCK FREQUENCY (ADC12D1000) SNR vs. CLOCK FREQUENCY (ADC12D1600)

Figure 36. Figure 37.

Product Folder Links: ADC12D1000 ADC12D1600

1.6 1.8 2.0 2.2

-80

-70

-60

-50

-40

THD (dBc)

VA(V)

NON-DES MODE

DES MODE

1.6 1.8 2.0 2.2

-80

-70

-60

-50

-40

THD (dBc)

VA(V)

NON-DES MODE

DES MODE

-50 0 50 100

-80

-70

-60

-50

-40

THD (dBc)

TEMPERATURE (°C)

NON-DES MODE

DES MODE

-50 0 50 100

-80

-70

-60

-50

-40

THD (dBc)

TEMPERATURE (°C)

NON-DES MODE

DES MODE

0 500 1,000 1,500

SNR (dB)

INPUT FREQUENCY (MHz)

NON-DES MODE

DES MODE

0 500 1,000 1,500

SNR (dB)

INPUT FREQUENCY (MHz)

NON-DES MODE

DES MODE

ADC12D1000, ADC12D1600

SNAS480M –MAY 2010–REVISED MARCH 2013

www.ti.com

Typical Performance Plots (continued)

VA= VDR = VTC = VE= 1.9V, fCLK = 1.0/1.6 GHz, fIN = 498 MHz, TA= 25°C, I-channel, 1:2 Demux Non-DES Mode (1:1 Demux

Non-DES Mode has similar performance), unless otherwise stated. For NPR plots, notch width = 25MHz, fc = 320 MHz.

SNR vs. INPUT FREQUENCY (ADC12D1000) SNR vs. INPUT FREQUENCY (ADC12D1600)

Figure 38. Figure 39.

THD vs. TEMPERATURE (ADC12D1000) THD vs. TEMPERATURE (ADC12D1600)

Figure 40. Figure 41.

THD vs. SUPPLY VOLTAGE (ADC12D1000) THD vs. SUPPLY VOLTAGE (ADC12D1600)

Figure 42. Figure 43.

Product Folder Links: ADC12D1000 ADC12D1600

-50 0 50 100

SFDR (dBc)

TEMPERATURE (°C)

NON-DES MODE

DES MODE

-50 0 50 100

SFDR (dBc)

TEMPERATURE (°C)

NON-DES MODE

DES MODE

0 500 1,000 1,500

-80

-70

-60

-50

-40

THD (dBc)

INPUT FREQUENCY (MHz)

NON-DES MODE

DES MODE

0 500 1,000 1,500

-80

-70

-60

-50

-40

THD (dBc)

INPUT FREQUENCY (MHz)

NON-DES MODE

DES MODE

0 250 500 750 1,000

-80

-70

-60

-50

-40

THD (dBc)

CLOCK FREQUENCY (MHz)

NON-DES MODE

DES MODE

0 400 800 1,200 1,600

-80

-70

-60

-50

-40

THD (dBc)

CLOCK FREQUENCY (MHz)

NON-DES MODE

DES MODE

ADC12D1000, ADC12D1600

www.ti.com

SNAS480M –MAY 2010–REVISED MARCH 2013

Typical Performance Plots (continued)

VA= VDR = VTC = VE= 1.9V, fCLK = 1.0/1.6 GHz, fIN = 498 MHz, TA= 25°C, I-channel, 1:2 Demux Non-DES Mode (1:1 Demux

Non-DES Mode has similar performance), unless otherwise stated. For NPR plots, notch width = 25MHz, fc = 320 MHz.

THD vs. CLOCK FREQUENCY (ADC12D1000) THD vs. CLOCK FREQUENCY (ADC12D1600)

Figure 44. Figure 45.

THD vs. INPUT FREQUENCY (ADC12D1000) THD vs. INPUT FREQUENCY (ADC12D1600)

Figure 46. Figure 47.

SFDR vs. TEMPERATURE (ADC12D1000) SFDR vs. TEMPERATURE (ADC12D1600)

Figure 48. Figure 49.

Product Folder Links: ADC12D1000 ADC12D1600

0 500 1,000 1,500

SFDR (dBc)

INPUT FREQUENCY (MHz)

NON-DES MODE

DES MODE

0 500 1,000 1,500

SFDR (dBc)

INPUT FREQUENCY (MHz)

NON-DES MODE

DES MODE

0 250 500 750 1,000

SFDR (dBc)

CLOCK FREQUENCY (MHz)

NON-DES MODE

DES MODE

0 400 800 1,200 1,600

SFDR (dBc)

CLOCK FREQUENCY (MHz)

NON-DES MODE

DES MODE

1.6 1.8 2.0 2.2

SFDR (dBc)

VA(V)

NON-DES MODE

DES MODE

1.6 1.8 2.0 2.2

SFDR (dBc)

VA(V)

NON-DES MODE

DES MODE

ADC12D1000, ADC12D1600

SNAS480M –MAY 2010–REVISED MARCH 2013

www.ti.com

Typical Performance Plots (continued)

VA= VDR = VTC = VE= 1.9V, fCLK = 1.0/1.6 GHz, fIN = 498 MHz, TA= 25°C, I-channel, 1:2 Demux Non-DES Mode (1:1 Demux

Non-DES Mode has similar performance), unless otherwise stated. For NPR plots, notch width = 25MHz, fc = 320 MHz.

SFDR vs. SUPPLY VOLTAGE (ADC12D1000) SFDR vs. SUPPLY VOLTAGE (ADC12D1600)

Figure 50. Figure 51.

SFDR vs. CLOCK FREQUENCY (ADC12D1000) SFDR vs. CLOCK FREQUENCY (ADC12D1600)

Figure 52. Figure 53.

SFDR vs. INPUT FREQUENCY (ADC12D1000) SFDR vs. INPUT FREQUENCY (ADC12D1600)

Figure 54. Figure 55.

Product Folder Links: ADC12D1000 ADC12D1600

0 250 500 750 1,000

-100

-75

-50

-25

AMPLITUDE (dBFS)

FREQUENCY (MHz)

DES MODE

0 400 800 1,200 1,600

-100

-75

-50

-25

AMPLITUDE (dBFS)

FREQUENCY (MHz)

DES MODE

0 100 200 300 400 500

-100

-75

-50

-25

AMPLITUDE (dBFS)

FREQUENCY (MHz)

NON-DES MODE

0 200 400 600 800

-100

-75

-50

-25

AMPLITUDE (dBFS)

FREQUENCY (MHz)

NON-DES MODE

ADC12D1000, ADC12D1600

www.ti.com

SNAS480M –MAY 2010–REVISED MARCH 2013

Typical Performance Plots (continued)

VA= VDR = VTC = VE= 1.9V, fCLK = 1.0/1.6 GHz, fIN = 498 MHz, TA= 25°C, I-channel, 1:2 Demux Non-DES Mode (1:1 Demux

Non-DES Mode has similar performance), unless otherwise stated. For NPR plots, notch width = 25MHz, fc = 320 MHz.

SPECTRAL RESPONSE AT FIN = 498 MHz (ADC12D1000) SPECTRAL RESPONSE AT FIN = 498 MHz (ADC12D1600)

Figure 56. Figure 57.

SPECTRAL RESPONSE AT FIN = 498 MHz (ADC12D1000) SPECTRAL RESPONSE AT FIN = 498 MHz (ADC12D1600)

Figure 58. Figure 59.

Product Folder Links: ADC12D1000 ADC12D1600

0 1,000 2,000 3,000

-15

-12

-9

-6

-3

SIGNAL GAIN (dB)

INPUT FREQUENCY (MHz)

NONDES

DES

DESIQ

0 1,000 2,000 3,000

-15

-12

-9

-6

-3

SIGNAL GAIN (dB)

INPUT FREQUENCY (MHz)

NONDES

DES

DESIQ

0 1,000 2,000 3,000

-90

-80

-70

-60

-50

-40

CROSSTALK (dBFS)

AGGRESSOR INPUT FREQUENCY (MHz)

NONDES MODE

0 1,000 2,000 3,000

-90

-80

-70

-60

-50

-40

CROSSTALK (dBFS)

AGGRESSOR INPUT FREQUENCY (MHz)

NONDES MODE

ADC12D1000, ADC12D1600

SNAS480M –MAY 2010–REVISED MARCH 2013

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Typical Performance Plots (continued)

VA= VDR = VTC = VE= 1.9V, fCLK = 1.0/1.6 GHz, fIN = 498 MHz, TA= 25°C, I-channel, 1:2 Demux Non-DES Mode (1:1 Demux

Non-DES Mode has similar performance), unless otherwise stated. For NPR plots, notch width = 25MHz, fc = 320 MHz.

CROSSTALK vs. SOURCE FREQUENCY

(ADC12D1000) CROSSTALK vs. SOURCE FREQUENCY (ADC12D1600)

Figure 60. Figure 61.

FULL POWER BANDWIDTH (ADC12D1000) FULL POWER BANDWIDTH (ADC12D1600)

Figure 62. Figure 63.

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-40 -30 -20 -10 0

NPR (dB)

VRMSLOADING LEVEL (dB)

-40 -30 -20 -10 0

NPR (dB)

VRMSLOADING LEVEL (dB)

0 250 500 750 1,000

2.0

2.5

3.0

3.5

4.0

4.5

5.0

POWER (W)

CLOCK FREQUENCY (MHz)

DEMUX

NON-DEMUX

0 400 800 1,200 1,600

2.0

2.5

3.0

3.5

4.0

4.5

5.0

POWER (W)

CLOCK FREQUENCY (MHz)

DEMUX

NON-DEMUX

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Typical Performance Plots (continued)

VA= VDR = VTC = VE= 1.9V, fCLK = 1.0/1.6 GHz, fIN = 498 MHz, TA= 25°C, I-channel, 1:2 Demux Non-DES Mode (1:1 Demux

Non-DES Mode has similar performance), unless otherwise stated. For NPR plots, notch width = 25MHz, fc = 320 MHz.

POWER CONSUMPTION vs. CLOCK FREQUENCY POWER CONSUMPTION vs. CLOCK FREQUENCY

(ADC12D1000) (ADC12D1600)

Figure 64. Figure 65.

NPR vs. RMS NOISE LOADING LEVEL (ADC12D1000) NPR vs. RMS NOISE LOADING LEVEL (ADC12D1600)

Figure 66. Figure 67.

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FUNCTIONAL DESCRIPTION

The ADC12D1000/1600 is a versatile A/D converter with an innovative architecture which permits very high

speed operation. The controls available ease the application of the device to circuit solutions. Optimum

performance requires adherence to the provisions discussed here and in the Applications Information Section.

This section covers an overview, a description of control modes (Extended Control Mode and Non-Extended

Control Mode), and features.

OVERVIEW

The ADC12D1000/1600 uses a calibrated folding and interpolating architecture that achieves a high Effective

Number of Bits (ENOB). The use of folding amplifiers greatly reduces the number of comparators and power

consumption. Interpolation reduces the number of front-end amplifiers required, minimizing the load on the input

signal and further reducing power requirements. In addition to correcting other non-idealities, on-chip calibration

reduces the INL bow often seen with folding architectures. The result is an extremely fast, high performance, low

power converter.

The analog input signal (which is within the converter's input voltage range) is digitized to twelve bits at speeds

of 150/150 MSPS to 2.0/3.2 GSPS, typical. Differential input voltages below negative full-scale will cause the

output word to consist of all zeroes. Differential input voltages above positive full-scale will cause the output word

to consist of all ones. Either of these conditions at the I- or Q-input will cause the Out-of-Range I-channel or Q-

channel output (ORI or ORQ), respectively, to output a logic-high signal.

In ECM, an expanded feature set is available via the Serial Interface. The ADC12D1000/1600 builds upon

previous architectures, introducing a new DES Mode timing adjust feature, AutoSync feature for multi-chip

synchronization and increasing to 15-bit for gain and 12-bit plus sign for offset the independent programmable

adjustment for each channel.

Each channel has a selectable output demultiplexer which feeds two LVDS buses. If the 1:2 Demux Mode is

selected, the output data rate is reduced to half the input sample rate on each bus. When Non-Demux Mode is

selected, the output data rate on each channel is at the same rate as the input sample clock and only one 12-bit

bus per channel is active.

CONTROL MODES

The ADC12D1000/1600 may be operated in one of two control modes: Non-extended Control Mode (Non-ECM)

or Extended Control Mode (ECM). In the simpler Non-ECM (also sometimes referred to as Pin Control Mode),

the user affects available configuration and control of the device through the control pins. The ECM provides

additional configuration and control options through a serial interface and a set of 16 registers, most of which are

available to the customer.

Non-Extended Control Mode

In Non-extended Control Mode (Non-ECM), the Serial Interface is not active and all available functions are

controlled via various pin settings. Non-ECM is selected by setting the ECE Pin to logic-high. Note that, for the

control pins, "logic-high" and "logic-low" refer to VAand GND, respectively. Nine dedicated control pins provide a

wide range of control for the ADC12D1000/1600 and facilitate its operation. These control pins provide DES

Mode selection, Demux Mode selection, DDR Phase selection, execute Calibration, Calibration Delay setting,

Power Down I-channel, Power Down Q-channel, Test Pattern Mode selection, and Full-Scale Input Range

selection. In addition to this, two dual-purpose control pins provide for AC/DC-coupled Mode selection and LVDS

output common-mode voltage selection. See Table 5 for a summary.

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Table 5. Non-ECM Pin Summary

Pin Name Logic-Low Logic-High Floating

Dedicated Control Pins

DES

DES Non-DES Mode Not valid

Mode

Demux

NDM Non-Demux Mode Not valid

Mode

DDRPh 0° Mode 90° Mode Not valid

CAL See Calibration Pin (CAL) Not valid

CalDly Shorter delay Longer delay Not valid

Power Down Power Down

PDI I-channel active I-channel I-channel

Power Down Power Down

PDQ Q-channel active Q-channel Q-channel

TPM Non-Test Pattern Mode Test Pattern Mode Not valid

FSR Lower FS input Range Higher FS input Range Not valid

Dual-purpose Control Pins

VCMO AC-coupled operation Not allowed DC-coupled operation

Higher LVDS common-mode Lower LVDS common-mode

VBG Not allowed voltage voltage

Dual Edge Sampling Pin (DES)

The Dual Edge Sampling (DES) Pin selects whether the ADC12D1000/1600 is in DES Mode (logic-high) or Non-

DES Mode (logic-low). DES Mode means that a single analog input is sampled by both I- and Q-channels in a

time-interleaved manner. One of the ADCs samples the input signal on the rising sampling clock edge (duty cycle

corrected); the other ADC samples the input signal on the falling sampling clock edge (duty cycle corrected). In

Non-ECM, only the I-input may be used for DES Mode, a.k.a. DESI Mode. In ECM, the Q-input may be selected

via the DEQ Bit (Addr: 0h, Bit: 6), a.k.a. DESQ Mode. In ECM, both the I- and Q-inputs may be selected, a.k.a.

DESIQ Mode.

To use this feature in ECM, use the DES bit in the Configuration Register (Addr: 0h; Bit: 7). See DES/Non-DES

Mode for more information.

Non-Demultiplexed Mode Pin (NDM)

The Non-Demultiplexed Mode (NDM) Pin selects whether the ADC12D1000/1600 is in Demux Mode (logic-low)

or Non-Demux Mode (logic-high). In Non-Demux Mode, the data from the input is produced at the sampled rate

at a single 12-bit output bus. In Demux Mode, the data from the input is produced at half the sampled rate at

twice the number of output buses. For Non-DES Mode, each I- or Q-channel will produce its data on one or two

buses for Non-Demux or Demux Mode, respectively. For DES Mode, the selected channel will produce its data

on two or four buses for Non-Demux or Demux Mode, respectively.

This feature is pin-controlled only and remains active during both Non-ECM and ECM. See Demux/Non-demux

Mode for more information.

Dual Data Rate Phase Pin (DDRPh)

The Dual Data Rate Phase (DDRPh) Pin selects whether the ADC12D1000/1600 is in 0° Mode (logic-low) or 90°

Mode (logic-high). The Data is always produced in DDR Mode on the ADC12D1000/1600. The Data may

transition either with the DCLK transition (0° Mode) or halfway between DCLK transitions (90° Mode). The

DDRPh Pin selects 0° Mode or 90° Mode for both the I-channel: DI- and DId-to-DCLKI phase relationship and for

the Q-channel: DQ- and DQd-to-DCLKQ phase relationship.

To use this feature in ECM, use the DPS bit in the Configuration Register (Addr: 0h; Bit: 14). See DDR Clock

Phase for more information.

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Calibration Pin (CAL)

The Calibration (CAL) Pin may be used to execute an on-command calibration or to disable the power-on

calibration. The effect of calibration is to maximize the dynamic performance. To initiate an on-command

calibration via the CAL pin, bring the CAL pin high for a minimum of tCAL_H input clock cycles after it has been low

for a minimum of tCAL_L input clock cycles. Holding the CAL pin high upon power-on will prevent execution of the

power-on calibration. In ECM, this pin remains active and is logically OR'd with the CAL bit.

To use this feature in ECM, use the CAL bit in the Configuration Register (Addr: 0h; Bit: 15). See Calibration

Feature for more information.

Calibration Delay Pin (CalDly)

The Calibration Delay (CalDly) Pin selects whether a shorter or longer delay time is present, after the application

of power, until the start of the power-on calibration. The actual delay time is specified as tCalDly and may be found

in Calibration. This feature is pin-controlled only and remains active in ECM. It is recommended to select the

desired delay time prior to power-on and not dynamically alter this selection.

See Calibration Feature for more information.

Power Down I-channel Pin (PDI)

The Power Down I-channel (PDI) Pin selects whether the I-channel is powered down (logic-high) or active (logic-

low). The digital data output pins, DI and DId, (both positive and negative) are put into a high impedance state

when the I-channel is powered down. Upon return to the active state, the pipeline will contain meaningless

information and must be flushed. The supply currents (typicals and limits) are available for the I-channel powered

down or active and may be found in Power Supply Characteristics. The device should be recalibrated following a

power-cycle of PDI (or PDQ).

This pin remains active in ECM. In ECM, either this pin or the PDI bit (Addr: 0h; Bit: 11) in the Control Register

may be used to power-down the I-channel. See Power Down for more information.

Power Down Q-channel Pin (PDQ)

The Power Down Q-channel (PDQ) Pin selects whether the Q-channel is powered down (logic-high) or active

(logic-low). This pin functions similarly to the PDI pin, except that it applies to the Q-channel. The PDI and PDQ

pins function independently of each other to control whether each I- or Q-channel is powered down or active.

This pin remains active in ECM. In ECM, either this pin or the PDQ bit (Addr: 0h; Bit: 10) in the Control Register

may be used to power-down the Q-channel. See Power Down for more information.

Test Pattern Mode Pin (TPM)

The Test Pattern Mode (TPM) Pin selects whether the output of the ADC12D1000/1600 is a test pattern (logic-

high) or the converted analog input (logic-low). The ADC12D1000/1600 can provide a test pattern at the four

output buses independently of the input signal to aid in system debug. In TPM, the ADC is disengaged and a test

pattern generator is connected to the outputs, including ORI and ORQ. SeeTest Pattern Mode for more

information.

Full-Scale Input Range Pin (FSR)

The Full-Scale Input Range (FSR) Pin selects whether the full-scale input range for both the I- and Q-channel is

higher (logic-high) or lower (logic-low). The input full-scale range is specified as VIN_FSR in Analog Input/Output

and Reference Characteristics. In Non-ECM, the full-scale input range for each I- and Q-channel may not be set

independently, but it is possible to do so in ECM. The device must be calibrated following a change in FSR to

obtain optimal performance.

To use this feature in ECM, use the Configuration Registers (Addr: 3hand Bh). See Input Control and Adjust for

more information.

AC/DC-Coupled Mode Pin (VCMO)

The VCMO Pin serves a dual purpose. When functioning as an output, it provides the optimal common-mode

voltage for the DC-coupled analog inputs. When functioning as an input, it selects whether the device is AC-

coupled (logic-low) or DC-coupled (floating). This pin is always active, in both ECM and Non-ECM.

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LVDS Output Common-mode Pin (VBG)

The VBG Pin serves a dual purpose. When functioning as an output, it provides the bandgap reference. When

functioning as an input, it selects whether the LVDS output common-mode voltage is higher (logic-high) or lower

(floating). The LVDS output common-mode voltage is specified as VOS and may be found in Digital Control and

Output Pin Characteristics. This pin is always active, in both ECM and Non-ECM.

Extended Control Mode

In Extended Control Mode (ECM), most functions are controlled via the Serial Interface. In addition to this,

several of the control pins remain active. See Table 8 for details. ECM is selected by setting the ECE Pin to

logic-low. If the ECE Pin is set to logic-high (Non-ECM), then the registers are reset to their default values. So, a

simple way to reset the registers is by toggling the ECE pin. Four pins on the ADC12D1000/1600 control the

Serial Interface: SCS, SCLK, SDI and SDO. This section covers the Serial Interface. The Register Definitions are

located at the end of the datasheet so that they are easy to find, see Register Definitions.

The Serial Interface

The ADC12D1000/1600 offers a Serial Interface that allows access to the sixteen control registers within the

device. The Serial Interface is a generic 4-wire (optionally 3-wire) synchronous interface that is compatible with

SPI type interfaces that are used on many micro-controllers and DSP controllers. Each serial interface access

cycle is exactly 24 bits long. A register-read or register-write can be accomplished in one cycle. The signals are

defined in such a way that the user can opt to simply join SDI and SDO signals in his system to accomplish a

single, bidirectional SDI/O signal. A summary of the pins for this interface may be found in Table 6. See

Figure 13 for the timing diagram and Serial Port Interface for timing specification details. Control register contents

are retained when the device is put into power-down mode. If this feature is unused, the SCLK, SDI, and SCS

pins may be left floating because they each have an internal pull-up.

Table 6. Serial Interface Pins

Pin Name

C4 SCS (Serial Chip Select bar)

C5 SCLK (Serial Clock)

B4 SDI (Serial Data In)

A3 SDO (Serial Data Out)

SCS: Each assertion (logic-low) of this signal starts a new register access, i.e. the SDI command field must be

ready on the following SCLK rising edge. The user is required to de-assert this signal after the 24th clock. If the

SCS is de-asserted before the 24th clock, no data read/write will occur. For a read operation, if the SCS is

asserted longer than 24 clocks, the SDO output will hold the D0 bit until SCS is de-asserted. For a write

operation, if the SCS is asserted longer than 24 clocks, data write will occur normally through the SDI input upon

the 24th clock. Setup and hold times, tSCS and tHCS, with respect to the SCLK must be observed. SCS must be

toggled in between register access cycles.

SCLK: This signal is used to register the input data (SDI) on the rising edge; and to source the output data

(SDO) on the falling edge. The user may disable the clock and hold it at logic-low. There is no minimum

frequency requirement for SCLK; see fSCLK in Serial Port Interface for more details.

SDI: Each register access requires a specific 24-bit pattern at this input, consisting of a command field and a

data field. If the SDI and SDO wires are shared (3-wire mode), then during read operations, it is necessary to tri-

state the master which is driving SDI while the data field is being output by the ADC on SDO. The master must

be at TRI-STATE before the falling edge of the 8th clock. If SDI and SDO are not shared (4-wire mode), then this

is not necessary. Setup and hold times, tSH and tSSU, with respect to the SCLK must be observed.

SDO: This output is normally at TRI-STATE and is driven only when SCS is asserted, the first 8 bits of command

data have been received and it is a READ operation. The data is shifted out, MSB first, starting with the 8th

clock's falling edge. At the end of the access, when SCS is de-asserted, this output is at TRI-STATE once again.

If an invalid address is accessed, the data sourced will consist of all zeroes. If it is a read operation, there will be

a bus turnaround time, tBSU, from when the last bit of the command field was read in until the first bit of the data

field is written out.

Table 7 shows the Serial Interface bit definitions.

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SDI

SDO

R/W 1 0 A3 A2 A1 A0 X D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

21 43 65 87 109 1211 1413 1615 1817 2019 2221 2423 25

SCLK

SCSb

SDI

SDO

R/W 1 0 A3 A2 A1 A0 X

D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0D15

21 43 65 87 109 1211 1413 1615 1817 2019 2221 2423 25

*Only required to be tri-stated in 3-wire mode.

SCLK

SCSb

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Table 7. Command and Data Field Definitions

Bit No. Name Comments

1bindicates a read operation

1 Read/Write (R/W) 0bindicates a write operation

2-3 Reserved Bits must be set to 10b

16 registers may be addressed. The order is

4-7 A<3:0> MSB first

8 X This is a "don't care" bit

Data written to or read from addressed

9-24 D<15:0> register

The serial data protocol is shown for a read and write operation in Figure 68 and Figure 69, respectively.

Figure 68. Serial Data Protocol - Read Operation

Figure 69. Serial Data Protocol - Write Operation

FEATURES

The ADC12D1000/1600 offers many features to make the device convenient to use in a wide variety of

applications. Table 8 is a summary of the features available, as well as details for the control mode chosen.

"N/A" means "Not Applicable."

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Table 8. Features and Modes

Control Pin

Feature Non-ECM ECM Default ECM State

Active in ECM

Input Control and Adjust

AC/DC-coupled Mode Selected via VCMO Yes Not available N/A

Selection (Pin C2)

Selected via FSR Selected via the Config Reg

Input Full-scale Range Adjust No Mid FSR value

(Pin Y3) (Addr: 3hand Bh)

Selected via the Config Reg

Input Offset Adjust Setting Not available N/A Offset = 0 mV

(Addr: 2hand Ah)

Selected via DES Selected via the DES Bit

DES/Non-DES Mode Selection No Non-DES Mode

(Pin V5) (Addr: 0h; Bit: 7)

Selected via the DES Timing

DES Timing Adjust Not available N/A Adjust Reg Mid skew offset

(Addr: 7h)

Selected via the Config Reg

Sampling Clock Phase Adjust Not available N/A tAD adjust disabled

(Addr: Chand Dh)

Output Control and Adjust

Selected via DDRPh Selected via the DPS Bit

DDR Clock Phase Selection No 0° Mode

(Pin W4) (Addr: 0h; Bit: 14)

LVDS Differential Voltage Selected via the OVS Bit

Higher amplitude only N/A Higher amplitude

Amplitude Selection (Addr: 0h; Bit: 13)

LVDS Common-Mode Voltage Selected via VBG Yes Not available N/A

Amplitude Selection (Pin B1) Selected via the 2SC Bit

Output Formatting Selection Offset Binary only N/A Offset Binary

(Addr: 0h; Bit: 4)

Selected via TPM Selected via the TPM Bit

Test Pattern Mode at Output No TPM disabled

(Pin A4) (Addr: 0h; Bit: 12)

Demux/Non-Demux Mode Selected via NDM Yes Not available N/A

Selection (Pin A5) Selected via the Config Reg Master Mode,

AutoSync Not available N/A (Addr: Eh) RCOut1/2 disabled

Selected via the Config Reg

DCLK Reset Not available N/A DCLK Reset disabled

(Addr: Eh; Bit: 0)

Selected via the TSE Bit

Time Stamp Not available N/A Time Stamp disabled

(Addr: 0h; Bit: 3)

Calibration

Selected via CAL Selected via the CAL Bit N/A

On-command Calibration Yes

(Pin D6) (Addr: 0h; Bit: 15) (CAL = 0)

Power-on Calibration Delay Selected via CalDly Yes Not available N/A

Selection (Pin V4) Selected via the Config Reg

Calibration Adjust Not available N/A tCAL

(Addr: 4h)

Read/Write Calibration Selected via the SSC Bit R/W calibration values

Not available N/A

Settings (Addr: 4h; Bit: 7) disabled

Power-Down

Selected via PDI Selected via the PDI Bit

Power down I-channel Yes I-channel operational

(Pin U3) (Addr: 0h; Bit: 11)

Selected via PDQ Selected via the PDQ Bit

Power down Q-channel Yes Q-channel operational

(Pin V3) (Addr: 0h; Bit: 10)

Input Control and Adjust

There are several features and configurations for the input of the ADC12D1000/1600 so that it may be used in

many different applications. This section covers AC/DC-coupled Mode, input full-scale range adjust, input offset

adjust, DES/Non-DES Mode, and sampling clock phase adjust.

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AC/DC-coupled Mode

The analog inputs may be AC or DC-coupled. See AC/DC-Coupled Mode Pin (VCMO)for information on how to

select the desired mode and DC-coupled Input Signals and AC-coupled Input Signals for applications

information.

Input Full-Scale Range Adjust

The input full-scale range for the ADC12D1000/1600 may be adjusted via Non-ECM or ECM. In Non-ECM, a

control pin selects a higher or lower value; see Full-Scale Input Range Pin (FSR). In ECM, the input full-scale

range may be adjusted with 15-bits of precision. See VIN_FSR in Analog Input/Output and Reference

Characteristics for electrical specification details. Note that the higher and lower full-scale input range settings in

Non-ECM correspond to the mid and min full-scale input range settings in ECM. It is necessary to execute an on-

command calibration following a change of the input full-scale range. See Register Definitions for information

about the registers.

Input Offset Adjust

The input offset adjust for the ADC12D1000/1600 may be adjusted with 12-bits of precision plus sign via ECM.

See Register Definitions for information about the registers.

DES/Non-DES Mode

The ADC12D1000/1600 can operate in Dual-Edge Sampling (DES) or Non-DES Mode. The DES Mode allows

for a single analog input to be sampled by both I- and Q-channels. One channel samples the input on the rising

edge of the sampling clock and the other samples the same input signal on the falling edge of the sampling

clock. A single input is thus sampled twice per clock cycle, resulting in an overall sample rate of twice the

sampling clock frequency, e.g. 2.0/3.2 GSPS with a 1.0/1.6 GHz sampling clock. Since DES Mode uses both I-

and Q-channels to process the input signal, both channels must be powered up for the DES Mode to function

properly.

In Non-ECM, only the I-input may be used for the DES Mode input. See Dual Edge Sampling Pin (DES) for

information on how to select the DES Mode. In ECM, either the I- or Q-input may be selected by first using the

DES bit (Addr: 0h, Bit 7) to select the DES Mode. The DEQ Bit (Addr: 0h, Bit: 6) is used to select the Q-input,

but the I-input is used by default. Also, both I- and Q-inputs may be driven externally, i.e. DESIQ Mode, by using

the DIQ bit (Addr: 0h, Bit 5). See Driving the ADC in DES Mode for more information about how to drive the ADC

in DES Mode.

The DESIQ Mode results in the best DES Mode bandwidth. In general, the bandwidth decreases from Non-DES

Mode to DES Mode (specifically, DESI or DESQ) because both channels are sampling off the same input signal

and non-ideal effects introduced by interleaving the two channels lower the bandwidth. Driving both I- and Q-

channels externally (DESIQ Mode) results in better bandwidth for the DES Mode because each channel is being

driven, which reduces routing losses.

In the DES Mode, the outputs must be carefully interleaved in order to reconstruct the sampled signal. If the

device is programmed into the 1:4 Demux DES Mode, the data is effectively demultiplexed by 1:4. If the

sampling clock is 1.0/1.6 GHz, the effective sampling rate is doubled to 2.0/3.2 GSPS and each of the 4 output

buses has an output rate of 500/800 MSPS. All data is available in parallel. To properly reconstruct the sampled

waveform, the four bytes of parallel data that are output with each DCLK must be correctly interleaved. The

sampling order is as follows, from the earliest to the latest: DQd, DId, DQ, DI. See Figure 9. If the device is

programmed into the Non-Demux DES Mode, two bytes of parallel data are output with each edge of the DCLK

in the following sampling order, from the earliest to the latest: DQ, DI. See Figure 10.

DES Timing Adjust

The performance of the ADC12D1000/1600 in DES Mode depends on how well the two channels are

interleaved, i.e. that the clock samples either channel with precisely a 50% duty-cycle, each channel has the

same offset (nominally code 2047/2048), and each channel has the same full-scale range. The

ADC12D1000/1600 includes an automatic clock phase background adjustment in DES Mode to automatically

and continuously adjust the clock phase of the I- and Q-channels. In addition to this, the residual fixed timing

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skew offset may be further manually adjusted, and further reduce timing spurs for specific applications. See the

DES Timing Adjust (Addr: 7h). As the DES Timing Adjust is programmed from 0dto 127d, the magnitude of the

Fs/2-Fin timing interleaving spur will decrease to a local minimum and then increase again. The default, nominal

setting of 64dmay or may not coincide with this local minimum. The user may manually skew the global timing to

achieve the lowest possible timing interleaving spur.

Sampling Clock Phase Adjust

The sampling clock (CLK) phase may be delayed internally to the ADC up to 825 ps in ECM. This feature is

intended to help the system designer remove small imbalances in clock distribution traces at the board level

when multiple ADCs are used, or to simplify complex system functions such as beam steering for phase array

antennas.

Additional delay in the clock path also creates additional jitter when using the sampling clock phase adjust.

Because the sampling clock phase adjust delays all clocks, including the DCLKs and output data, the user is

strongly advised to use the minimal amount of adjustment and verify the net benefit of this feature in his system

before relying on it.

Output Control and Adjust

There are several features and configurations for the output of the ADC12D1000/1600 so that it may be used in

many different applications. This section covers DDR clock phase, LVDS output differential and common-mode

voltage, output formatting, Demux/Non-demux Mode, Test Pattern Mode, and Time Stamp.

DDR Clock Phase

The ADC12D1000/1600 output data is always delivered in Double Data Rate (DDR). With DDR, the DCLK

frequency is half the data rate and data is sent to the outputs on both edges of DCLK; see Figure 70. The DCLK-

to-Data phase relationship may be either 0° or 90°. For 0° Mode, the Data transitions on each edge of the DCLK.

Any offset from this timing is tOSK; see AC Electrical Characteristics for details. For 90° Mode, the DCLK

transitions in the middle of each Data cell. Setup and hold times for this transition, tSU and tH, may also be found

in AC Electrical Characteristics . The DCLK-to-Data phase relationship may be selected via the DDRPh Pin in

Non-ECM (see Dual Data Rate Phase Pin (DDRPh)) or the DPS bit in the Configuration Register (Addr: 0h; Bit:

14) in ECM.

Figure 70. DDR DCLK-to-Data Phase Relationship

LVDS Output Differential Voltage

The ADC12D1000/1600 is available with a selectable higher or lower LVDS output differential voltage. This

parameter is VOD and may be found in Digital Control and Output Pin Characteristics. The desired voltage may

be selected via the OVS Bit (Addr: 0h, Bit 13). For many applications, in which the LVDS outputs are very close

to an FPGA on the same board, for example, the lower setting is sufficient for good performance; this will also

reduce the possibility for EMI from the LVDS outputs to other signals on the board. See Register Definitions for

more information.

LVDS Output Common-Mode Voltage

The ADC12D1000/1600 is available with a selectable higher or lower LVDS output common-mode voltage. This

parameter is VOS and may be found in Digital Control and Output Pin Characteristics. See LVDS Output

Common-mode Pin (VBG)for information on how to select the desired voltage.

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Output Formatting

The formatting at the digital data outputs may be either offset binary or two's complement. The default formatting

is offset binary, but two's complement may be selected via the 2SC Bit (Addr: 0h, Bit 4); see Register Definitions

for more information.

Demux/Non-demux Mode

The ADC12D1000/1600 may be in one of two demultiplex modes: Demux Mode or Non-Demux Mode (also

sometimes referred to as 1:1 Demux Mode). In Non-Demux Mode, the data from the input is simply output at the

sampling rate on one 12-bit bus. In Demux Mode, the data from the input is output at half the sampling rate, on

twice the number of buses. Demux/Non-Demux Mode may only be selected by the NDM pin. In Non-DES Mode,

the output data from each channel may be demultiplexed by a factor of 1:2 (1:2 Demux Non-DES Mode) or not

demultiplexed (Non-Demux Non-DES Mode). In DES Mode, the output data from both channels interleaved may

be demultiplexed (1:4 Demux DES Mode) or not demultiplexed (Non-Demux DES Mode).

Test Pattern Mode

The ADC12D1000/1600 can provide a test pattern at the four output buses independently of the input signal to

aid in system debug. In Test Pattern Mode, the ADC is disengaged and a test pattern generator is connected to

the outputs, including ORI and ORQ. The test pattern output is the same in DES Mode or Non-DES Mode. Each

port is given a unique 12-bit word, alternating between 1's and 0's. When the part is programmed into the Demux

Mode, the test pattern’s order is described in Table 9. If the I- or Q-channel is powered down, the test pattern will

not be output for that channel.

Table 9. Test Pattern by Output Port in

Demux Mode

Time Qd Id Q I ORQ ORI Comments

T0 000h004h008h010h0b0b

T1 FFFhFFBhFF7hFEFh1b1bPattern

T2 000h004h008h010h0b0bSequence

T3 FFFhFFBhFF7hFEFh1b1b

T4 000h004h008h010h0b0b

T5 000h004h008h010h0b0b

T6 FFFhFFBhFF7hFEFh1b1bPattern

T7 000h004h008h010h0b0bSequence

n+1

T8 FFFhFFBhFF7hFEFh1b1b

T9 000h004h008h010h0b0b

T10 000h004h008h010h0b0bPattern

T11 FFFhFFBhFF7hFEFh1b1bSequence

T12 000h004h008h010h0b0bn+2

T13 ... ... ... ... ... ...

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When the part is programmed into the Non-Demux Mode, the test pattern’s order is described in Table 10.

Table 10. Test Pattern by Output Port in

Non-Demux Mode

Time Q I ORQ ORI Comments

T0 000h004h0b0b

T1 000h004h0b0b

T2 FFFhFFBh1b1b

T3 FFFhFFBh1b1bPattern

T4 000h004h0b0bSequence

T5 FFFhFFBh1b1bn

T6 000h004h0b0b

T7 FFFhFFBh1b1b

T8 FFFhFFBh1b1b

T9 FFFhFFBh1b1b

T10 000h004h0b0b

T11 000h004h0b0bPattern

T12 FFFhFFBh1b1bSequence

n+1

T13 FFFhFFBh1b1b

T14 ... ... ... ...

Time Stamp

The Time Stamp feature enables the user to capture the timing of an external trigger event, relative to the

sampled signal. When enabled via the TSE Bit (Addr: 0h; Bit: 3), the LSB of the digital outputs (DQd, DQ, DId,

DI) captures the trigger information. In effect, the 12-bit converter becomes an 11-bit converter and the LSB acts

as a 1-bit converter with the same latency as the 11-bit converter. The trigger should be applied to the

DCLK_RST input. It may be asynchronous to the ADC sampling clock.

Calibration Feature

The ADC12D1000/1600 calibration must be run to achieve specified performance. The calibration procedure is

exactly the same regardless of how it was initiated or when it is run. Calibration trims the analog input differential

termination resistors, the CLK input resistor, and sets internal bias currents which affect the linearity of the

converter. This minimizes full-scale error, offset error, DNL and INL, which results in the maximum dynamic

performance, as measured by: SNR, THD, SINAD (SNDR) and ENOB.

Calibration Control Pins and Bits

Table 11 is a summary of the pins and bits used for calibration. See Ball Descriptions and Equivalent Circuits for

complete pin information and Figure 12 for the timing diagram.

Table 11. Calibration Pins

Pin (Bit) Name Function

D6 CAL Initiate calibration

(Addr: 0h; Bit 15) (Calibration)

CalDly

V4 Select power-on calibration delay

(Calibration Delay)

(Addr: 4h) Calibration Adjust Adjust calibration sequence

CalRun

B5 Indicates while calibration is running

(Calibration Running)

Rtrim+/-

C1/D2 External resistor used to calibrate analog and CLK inputs

(Input termination trim resistor)

Rext+/-

C3/D3 External resistor used to calibrate internal linearity

(External Reference resistor)

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How to Execute a Calibration

Calibration may be initiated by holding the CAL pin low for at least tCAL_L clock cycles, and then holding it high for

at least another tCAL_H clock cycles, as defined in Calibration. The minimum tCAL_L and tCAL_H input clock cycle

sequences are required to ensure that random noise does not cause a calibration to begin when it is not desired.

The time taken by the calibration procedure is specified as tCAL. The CAL Pin is active in both ECM and Non-

ECM. However, in ECM, the CAL Pin is logically OR'd with the CAL Bit, so both the pin and bit are required to be

set low before executing another calibration via either pin or bit.

Power-on Calibration

For standard operation, power-on calibration begins after a time delay following the application of power, as

determined by the setting of the CalDly Pin and measured by tCalDly (see Calibration). This delay allows the

power supply to come up and stabilize before the power-on calibration takes place. The best setting (short or

long) of the CalDly Pin depends upon the settling time of the power supply.

It is strongly recommended to set CalDly Pin (to either logic-high or logic-low) before powering the device on

since this pin affects the power-on calibration timing. This may be accomplished by setting CalDly via an external

1kΩresistor connected to GND or VA. If the CalDly Pin is toggled while the device is powered-on, it can execute

a calibration even though the CAL Pin/Bit remains logic-low.

The power-on calibration will be not be performed if the CAL pin is logic-high at power-on. In this case, the

calibration cycle will not begin until the on-command calibration conditions are met. The ADC12D1000/1600 will

function with the CAL pin held high at power up, but no calibration will be done and performance will be impaired.

If it is necessary to toggle the CalDly Pin before the system power up sequence, then the CAL Pin/Bit must be

set to logic-high during the toggling and afterwards for 109Sampling Clock cycles. This will prevent the power-on

calibration, so an on-command calibration must be executed or the performance will be impaired.

On-command Calibration

In addition to the power-on calibration, it is recommended to execute an on-command calibration whenever the

settings or conditions to the device are altered significantly, in order to obtain optimal parametric performance.

Some examples include: changing the FSR via either ECM or Non-ECM, power-cycling either channel, and

switching into or out of DES Mode. For best performance, it is also recommended that an on-command

calibration be run 20 seconds or more after application of power and whenever the operating temperature

changes significantly, relative to the specific system performance requirements.

Due to the nature of the calibration feature, it is recommended to avoid unnecessary activities on the device

while the calibration is taking place. For example, do not read or write to the Serial Interface or use the DCLK

Reset feature while calibrating the ADC. Doing so will impair the performance of the device until it is re-calibrated

correctly. Also, it is recommended to not apply a strong narrow-band signal to the analog inputs during calibration

because this may impair the accuracy of the calibration; broad spectrum noise is acceptable.

Calibration Adjust

The sequence of the calibration event itself may be adjusted. This feature can be used if a shorter calibration

time than the default is required; see tCAL in Calibration. However, the performance of the device, when using this

feature is not ensured.

The calibration sequence may be adjusted via CSS (Addr: 4h, Bit 14). The default setting of CSS = 1bexecutes

both RIN and RIN_CLK Calibration (using Rtrim) and internal linearity Calibration (using Rext). Executing a

calibration with CSS = 0bexecutes only the internal linearity Calibration. The first time that Calibration is

executed, it must be with CSS = 1bto trim RIN and RIN_CLK. However, once the device is at its operating

temperature and RIN has been trimmed at least one time, it will not drift significantly. To save time in subsequent

calibrations, trimming RIN and RIN_CLK may be skipped, i.e. by setting CSS = 0b.

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Read/Write Calibration Settings

When the ADC performs a calibration, the calibration constants are stored in an array which is accessible via the

Calibration Values register (Addr: 5h). To save the time which it takes to execute a calibration, tCAL, or to allow

re-use of a previous calibration result, these values can be read from and written to the register at a later time.

For example, if an application requires the same input impedance, RIN, this feature can be used to load a

previously determined set of values. For the calibration values to be valid, the ADC must be operating under the

same conditions, including temperature, at which the calibration values were originally determined by the ADC.

To read calibration values from the SPI, do the following:

1. Set ADC to desired operating conditions.

2. Set SSC (Addr: 4h, Bit 7) to 1.

3. Read exactly 240 times the Calibration Values register (Addr: 5h). The register values are R0, R1, R2... R239

where R0 is adummy value. The contents of R<239:1> should be stored.

4. Set SSC (Addr: 4h, Bit 7) to 0.

5. Continue with normal operation.

To write calibration values to the SPI, do the following:

1. Set ADC to operating conditions at which Calibration Values were previously read.

2. Set SSC (Addr: 4h, Bit 7) to 1.

3. Write exactly 239 times the Calibration Values register (Addr: 5h). The registers should be written with stored

4. Make two additional dummy writes of 0000h.

5. Set SSC (Addr: 4h, Bit 7) to 0.

6. Continue with normal operation.

Calibration and Power-Down

If PDI and PDQ are simultaneously asserted during a calibration cycle, the ADC12D1000/1600 will immediately

power down. The calibration cycle will continue when either or both channels are powered back up, but the

calibration will be compromised due to the incomplete settling of bias currents directly after power up. Therefore,

a new calibration should be executed upon powering the ADC12D1000/1600 back up. In general, the

ADC12D1000/1600 should be recalibrated when either or both channels are powered back up, or after one

channel is powered down. For best results, this should be done after the device has stabilized to its operating

temperature.

Calibration and the Digital Outputs

During calibration, the digital outputs (including DI, DId, DQ, DQd and OR) are set logic-low, to reduce noise.

The DCLK runs continuously during calibration. After the calibration is completed and the CalRun signal is logic-

low, it takes an additional 60 Sampling Clock cycles before the output of the ADC12D1000/1600 is valid

converted data from the analog inputs. This is the time it takes for the pipeline to flush, as well as for other

internal processes.

Power Down

On the ADC12D1000/1600, the I- and Q-channels may be powered down individually. This may be accomplished

via the control pins, PDI and PDQ, or via ECM. In ECM, the PDI and PDQ pins are logically OR'd with the

Control Register setting. See Power Down I-channel Pin (PDI) andPower Down Q-channel Pin (PDQ) for more

information.

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Applications Information

THE ANALOG INPUTS

The ADC12D1000/1600 will continuously convert any signal which is present at the analog inputs, as long as a

CLK signal is also provided to the device. This section covers important aspects related to the analog inputs

including: acquiring the input, driving the ADC in DES Mode, the reference voltage and FSR, out-of-range

indication, AC/DC-coupled signals, and single-ended input signals.

Acquiring the Input

Data is acquired at the rising edge of CLK+ in Non-DES Mode and both the falling and rising edges of CLK+ in

DES Mode. The digital equivalent of that data is available at the digital outputs a constant number of sampling

clock cycles later for the DI, DQ, DId and DQd output buses, a.k.a. Latency, depending on the demultiplex mode

which is selected. See tLAT in AC Electrical Characteristics . In addition to the Latency, there is a constant output

delay, tOD, before the data is available at the outputs. See tOD in AC Electrical Characteristics and the Timing

Diagrams.

The output latency versus Demux/Non-Demux Mode is shown in Table 12 and Table 13, respectively. For DES

Mode, note that the I- and Q-channel inputs are available in ECM, but only the I-channel input is available in

Non-ECM.

Table 12. Output Latency in Demux Mode

DES Mode

Data Non-DES Mode Q-input* I-input

I-input sampled with rise of CLK, Q-input sampled with rise of CLK, I-input sampled with rise of CLK,

DI 34 cycles earlier 34 cycles earlier 34 cycles earlier

Q-input sampled with rise of CLK, Q-input sampled with fall of CLK, I-input sampled with fall of CLK,

DQ 34 cycles earlier 34.5 cycles earlier 34.5 cycles earlier

I-input sampled with rise of CLK, Q-input sampled with rise of CLK, I-input sampled with rise of CLK,

DId 35 cycles earlier 35 cycles earlier 35 cycles earlier

Q-input sampled with rise of CLK, Q-input sampled with fall of CLK, I-input sampled with fall of CLK,

DQd 35 cycles earlier 35.5 cycles earlier 35.5 cycles earlier

Table 13. Output Latency in Non-Demux Mode

DES Mode

Data Non-DES Mode Q-input* I-input

I-input sampled with rise of CLK, Q-input sampled with rise of CLK, I-input sampled with rise of CLK,

DI 34 cycles earlier 34 cycles earlier 34 cycles earlier

Q-input sampled with rise of CLK, Q-input sampled with rise of CLK, I-input sampled with rise of CLK,

DQ 34 cycles earlier 34.5 cycles earlier 34.5 cycles earlier

No output;

DId high impedance.

No output;

DQd high impedance.

*Available in ECM only.

Driving the ADC in DES Mode

The ADC12D1000/1600 can be configured as either a 2-channel, 1.0/1.6GSPS device (Non-DES Mode) or a 1-

channel 2.0/3.2GSPS device (DES Mode). When the device is configured in DES Mode, there is a choice for

with which input to drive the single-channel ADC. These are the 3 options:

DES – externally driving the I-channel input only. This is the default selection when the ADC is configured in DES

Mode. It may also be referred to as “DESI” for added clarity.

DESQ – externally driving the Q-channel input only.

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DESIQ – externally driving both the I- and Q-channel inputs. VinI+ and VinQ+ should be driven with the exact

same signal. VinI- and VinQ- should be driven with the exact same signal, which is the differential complement to

the one driving VinI+ and VinQ+.

The input impedance for each I- and Q-input is 100Ωdifferential (or 50Ωsingle-ended), so the trace to each

VinI+, VinI-, VinQ+, and VinQ- should always be 50Ωsingle-ended. If a single I- or Q-input is being driven, then

that input will present a 100Ωdifferential load. For example, if a 50Ωsingle-ended source is driving the ADC,

then a 1:2 balun will transform the impedance to 100Ωdifferential. However, if the ADC is being driven in DESIQ

Mode, then the 100Ωdifferential impedance from the I-input will appear in parallel with the Q-input for a

composite load of 50Ωdifferential and a 1:1 balun would be appropriate. See Figure 71 for an example circuit

driving the ADC in DESIQ Mode. A recommended part selection is using the Mini-Circuits TC1-1-13MA+ balun

with Ccouple = 0.22µF.

Figure 71. Driving DESIQ Mode

In the case that only one channel is used in Non-DES Mode or that the ADC is driven in DESI or DESQ Mode,

the unused analog input should be terminated to reduce any noise coupling into the ADC. See Table 14 for

details.

Table 14. Unused Analog Input Recommended Termination

Mode Power Down Coupling Recommended Termination

Non-DES Yes AC/DC Tie Unused+ and Unused- to Vbg

DES/Non-DES No DC Tie Unused+ and Unused- to Vbg

DES/Non-DES No AC Tie Unused+ to Unused-

FSR and the Reference Voltage

The full-scale analog differential input range (VIN_FSR) of the ADC12D1000/1600 is derived from an internal

bandgap reference. In Non-ECM, this full-scale range has two settings controlled by the FSR Pin; see Full-Scale

Input Range Pin (FSR). The FSR Pin operates on both I- and Q-channels. In ECM, the full-scale range may be

independently set for each channel via Addr:3hand Bhwith 15 bits of precision; see Register Definitions. The

best SNR is obtained with a higher full-scale input range, but better distortion and SFDR are obtained with a

lower full-scale input range. It is not possible to use an external analog reference voltage to modify the full-scale

range, and this adjustment should only be done digitally, as described.

A buffered version of the internal bandgap reference voltage is made available at the VBG Pin for the user. The

VBG pin can drive a load of up to 80 pF and source or sink up to 100 μA. It should be buffered if more current

than this is required. This pin remains as a constant reference voltage regardless of what full-scale range is

selected and may be used for a system reference. VBG is a dual-purpose pin and it may also be used to select a

higher LVDS output common-mode voltage; see LVDS Output Common-mode Pin (VBG).

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Out-Of-Range Indication

Differential input signals are digitized to 12 bits, based on the full-scale range. Signal excursions beyond the full-

scale range, i.e. greater than +VIN_FSR/2 or less than -VIN_FSR/2, will be clipped at the output. An input signal

which is above the FSR will result in all 1's at the output and an input signal which is below the FSR will result in

all 0's at the output. When the conversion result is clipped for the I-channel input, the Out-of-Range I-channel

(ORI) output is activated such that ORI+ goes high and ORI- goes low while the signal is out of range. This

output is active as long as accurate data on either or both of the buses would be outside the range of 000hto

FFFh. The Q-channel has a separate ORQ which functions similarly.

Maximum Input Range

The recommended operating and absolute maximum input range may be found in Operating Ratings and

Absolute Maximum Ratings, respectively. Under the stated allowed operating conditions, each Vin+ and Vin-

input pin may be operated in the range from 0V to 2.15V if the input is a continuous 100% duty cycle signal and

from 0V to 2.5V if the input is a 10% duty cycle signal. The absolute maximum input range for Vin+ and Vin- is

from -0.15V to 2.5V. These limits apply only for input signals for which the input common mode voltage is

properly maintained.

AC-coupled Input Signals

The ADC12D1000/1600 analog inputs require a precise common-mode voltage. This voltage is generated on-

chip when AC-coupling Mode is selected. See AC/DC-Coupled Mode Pin (VCMO)for more information about how

to select AC-coupled Mode.

In AC-coupled Mode, the analog inputs must of course be AC-coupled. For an ADC12D1000/1600 used in a

typical application, this may be accomplished by on-board capacitors, as shown in Figure 72. For the

ADC12D1000/1600RB, the SMA inputs on the Reference Board are directly connected to the analog inputs on

the ADC12D1000/1600, so this may be accomplished by DC blocks (included with the hardware kit).

When the AC-coupled Mode is selected, an analog input channel that is not used (e.g. in DES Mode) should be

connected to AC ground, e.g. through capacitors to ground . Do not connect an unused analog input directly to

ground.

Figure 72. AC-coupled Differential Input

The analog inputs for the ADC12D1000/1600 are internally buffered, which simplifies the task of driving these

inputs and the RC pole which is generally used at sampling ADC inputs is not required. If the user desires to

place an amplifier circuit before the ADC, care should be taken to choose an amplifier with adequate noise and

distortion performance, and adequate gain at the frequencies used for the application.

DC-coupled Input Signals

In DC-coupled Mode, the ADC12D1000/1600 differential inputs must have the correct common-mode voltage.

This voltage is provided by the device itself at the VCMO output pin. It is recommended to use this voltage

because the VCMO output potential will change with temperature and the common-mode voltage of the driving

device should track this change. Full-scale distortion performance falls off as the input common mode voltage

deviates from VCMO. Therefore, it is recommended to keep the input common-mode voltage within 100 mV of

VCMO (typical), although this range may be extended to ±150 mV (maximum). See VCMI in Analog Input/Output

and Reference Characteristics and ENOB vs. VCMI in Typical Performance Plots . Performance in AC- and DC-

coupled Mode are similar, provided that the input common mode voltage at both analog inputs remains within

100 mV of VCMO.

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Single-Ended Input Signals

The analog inputs of the ADC12D1000/1600 are not designed to accept single-ended signals. The best way to

handle single-ended signals is to first convert them to differential signals before presenting them to the ADC. The

easiest way to accomplish single-ended to differential signal conversion is with an appropriate balun-transformer,

as shown in Figure 73.

Figure 73. Single-Ended to Differential Conversion Using a Balun

When selecting a balun, it is important to understand the input architecture of the ADC. The impedance of the

analog source should be matched to the ADC12D1000/1600's on-chip 100Ωdifferential input termination resistor.

The range of this termination resistor is specified as RIN in Analog Input/Output and Reference Characteristics.

THE CLOCK INPUTS

The ADC12D1000/1600 has a differential clock input, CLK+ and CLK-, which must be driven with an AC-

coupled, differential clock signal. This provides the level shifting necessary to allow for the clock to be driven with

LVDS, PECL, LVPECL, or CML levels. The clock inputs are internally terminated to 100Ωdifferential and self-

biased. This section covers coupling, frequency range, level, duty-cycle, jitter, and layout considerations.

CLK Coupling

The clock inputs of the ADC12D1000/1600 must be capacitively coupled to the clock pins as indicated in

Figure 74.

Figure 74. Differential Input Clock Connection

The choice of capacitor value will depend on the clock frequency, capacitor component characteristics and other

system economic factors. For example, on the ADC12D1000/1600RB, the capacitors have the value Ccouple = 4.7

nF which yields a highpass cutoff frequency, fc= 677.2 kHz.

CLK Frequency

Although the ADC12D1000/1600 is tested and its performance is ensured with a differential 1.0/1.6 GHz

sampling clock, it will typically function well over the input clock frequency range; see fCLK(min) and fCLK(max) in

AC Electrical Characteristics . Operation up to fCLK(max) is possible if the maximum ambient temperatures

indicated are not exceeded. Operating at sample rates above fCLK(max) for the maximum ambient temperature

may result in reduced device reliability and product lifetime. This is due to the fact that higher sample rates

results in higher power consumption and die temperatures. If fCLK < 300 MHz, enable LFS in the Control Register

(Addr: 0h, Bit 8).

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CLK Level

The input clock amplitude is specified as VIN_CLK in Converter Electrical Characteristics Sampling Clock

Characteristics . Input clock amplitudes above the max VIN_CLK may result in increased input offset voltage. This

would cause the converter to produce an output code other than the expected 2047/2048 when both input pins

are at the same potential. Insufficient input clock levels will result in poor dynamic performance. Both of these

results may be avoided by keeping the clock input amplitude within the specified limits of VIN_CLK.

CLK Duty Cycle

The duty cycle of the input clock signal can affect the performance of any A/D converter. The ADC12D1000/1600

features a duty cycle clock correction circuit which can maintain performance over the 20%-to-80% specified

clock duty-cycle range. This feature is enabled by default and provides improved ADC clocking, especially in the

Dual-Edge Sampling (DES) Mode.

CLK Jitter

High speed, high performance ADCs such as the ADC12D1000/1600 require a very stable input clock signal with

minimum phase noise or jitter. ADC jitter requirements are defined by the ADC resolution (number of bits),

maximum ADC input frequency and the input signal amplitude relative to the ADC input full scale range. The

maximum jitter (the sum of the jitter from all sources) allowed to prevent a jitter-induced reduction in SNR is

found to be

tJ(MAX) = ( VIN(P-P)/ VFSR) x (1/(2(N+1) xπx fIN)) (3)

where tJ(MAX) is the rms total of all jitter sources in seconds, VIN(P-P) is the peak-to-peak analog input signal, VFSR

is the full-scale range of the ADC, "N" is the ADC resolution in bits and fIN is the maximum input frequency, in

Hertz, at the ADC analog input.

tJ(MAX) is the square root of the sum of the squares (RSS) of the jitter from all sources, including: the ADC input

clock, system, input signals and the ADC itself. Since the effective jitter added by the ADC is beyond user

control, it is recommended to keep the sum of all other externally added jitter to a minimum.

CLK Layout

The ADC12D1000/1600 clock input is internally terminated with a trimmed 100Ωresistor. The differential input

clock line pair should have a characteristic impedance of 100Ωand (when using a balun), be terminated at the

clock source in that (100Ω) characteristic impedance.

It is good practice to keep the ADC input clock line as short as possible, tightly coupled, keep it well away from

any other signals, and treat it as a transmission line. Otherwise, other signals can introduce jitter into the input

clock signal. Also, the clock signal can introduce noise into the analog path if it is not properly isolated.

THE LVDS OUTPUTS

The Data, ORI, ORQ, DCLKI and DCLKQ outputs are LVDS. The electrical specifications of the LVDS outputs

are compatible with typical LVDS receivers available on ASIC and FPGA chips; but they are not IEEE or ANSI

communications standards compliant due to the low +1.9V supply used on this chip. These outputs should be

terminated with a 100Ωdifferential resistor placed as closely to the receiver as possible. If the 100Ωdifferential

resistance is built in to the receiver, then an externally placed resistor is not necessary. This section covers

common-mode and differential voltage, and data rate.

Common-mode and Differential Voltage

The LVDS outputs have selectable common-mode and differential voltage, VOS and VOD; see Digital Control and

Output Pin Characteristics. See Output Control and Adjust for more information.

Selecting the higher VOS will also increase VOD slightly. The differential voltage, VOD, may be selected for the

higher or lower value. For short LVDS lines and low noise systems, satisfactory performance may be realized

with the lower VOD. This will also result in lower power consumption. If the LVDS lines are long and/or the system

in which the ADC12D1000/1600 is used is noisy, it may be necessary to select the higher VOD.

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Output Data Rate

The data is produced at the output at the same rate it is sampled at the input. The minimum recommended input

clock rate for this device is fCLK(MIN); see AC Electrical Characteristics . However, it is possible to operate the

device in 1:2 Demux Mode and capture data from just one 12-bit bus, e.g. just DI (or DId) although both DI and

DId are fully operational. This will decimate the data by two and effectively halve the data rate.

Terminating Unused LVDS Output Pins

If the ADC is used in Non-Demux Mode, then only the DI and DQ data outputs will have valid data present on

them. The DId and DQd data outputs may be left not connected; if unused, they are internally at TRI-STATE.

Similarly, if the Q-channel is powered-down (i.e. PDQ is logic-high), the DQ data output pins, DCLKQ and ORQ

may be left not connected.

SYNCHRONIZING MULTIPLE ADC12D1000/1600S IN A SYSTEM

The ADC12D1000/1600 has two features to assist the user with synchronizing multiple ADCs in a system;

AutoSync and DCLK Reset. The AutoSync feature is new and designates one ADC12D1000/1600 as the Master

ADC and other ADC12D1000/1600s in the system as Slave ADCs. The DCLK Reset feature performs the same

function as the AutoSync feature, but is the first generation solution to synchronizing multiple ADCs in a system;

it is disabled by default. For the application in which there are multiple Master and Slave ADC12D1000/1600s in

a system, AutoSync may be used to synchronize the Slave ADC12D1000/1600(s) to each respective Master

ADC12D1000/1600 and the DCLK Reset may be used to synchronize the Master ADC12D1000/1600s to each

other.

If the AutoSync or DCLK Reset feature is not used, see Table 15 for recommendations about terminating unused

pins.

Table 15. Unused AutoSync and DCLK Reset Pin Recommendation

Pin(s) Unused termination

RCLK+/- Do not connect.

RCOUT1+/- Do not connect.

RCOUT2+/- Do not connect.

DCLK_RST+ Connect to GND via 1kΩresistor.

DCLK_RST- Connect to VAvia 1kΩresistor.

AutoSync Feature

AutoSync is a new feature which continuously synchronizes the outputs of multiple ADC12D1000/1600s in a

system. It may be used to synchronize the DCLK and data outputs of one or more Slave ADC12D1000/1600s to

one Master ADC12D1000/1600. Several advantages of this feature include: no special synchronization pulse

required, any upset in synchronization is recovered upon the next DCLK cycle, and the Master/Slave

ADC12D1000/1600s may be arranged as a binary tree so that any upset will quickly propagate out of the

system.

An example system is shown below in Figure 75 which consists of one Master ADC and two Slave ADCs. For

simplicity, only one DCLK is shown; in reality, there is DCLKI and DCLKQ, but they are always in phase with one

another.

Product Folder Links: ADC12D1000 ADC12D1600

CLK

Master

ADC12D1XXX

Slave 1

ADC12D1XXX Slave 2

ADC12D1XXX

CLK

RCLK

RCOut1

RCOut2

DCLK

DCLK DCLK

RCLK

RCOut1

RCOut2

RCOut1

RCOut2

ADC12D1000, ADC12D1600

SNAS480M –MAY 2010–REVISED MARCH 2013

www.ti.com

Figure 75. AutoSync Example

In order to synchronize the DCLK (and Data) outputs of multiple ADCs, the DCLKs must transition at the same

time, as well as be in phase with one another. The DCLK at each ADC is generated from the CLK after some

latency, plus tOD minus tAD. Therefore, in order for the DCLKs to transition at the same time, the CLK signal must

reach each ADC at the same time. To tune out any differences in the CLK path to each ADC, the tAD adjust

feature may be used. However, using the tAD adjust feature will also affect when the DCLK is produced at the

output. If the device is in Demux Mode, then there are four possible phases which each DCLK may be generated

on because the typical CLK = 1GHz and DCLK = 250 MHz for this case. The RCLK signal controls the phase of

the DCLK, so that each Slave DCLK is on the same phase as the Master DCLK.

The AutoSync feature may only be used via the Control Registers. For more information, see AN-2132

(SNAA073).

DCLK Reset Feature

The DCLK reset feature is available via ECM, but it is disabled by default. DCLKI and DCLKQ are always

synchronized, by design, and do not require a pulse from DCLK_RST to become synchronized.

The DCLK_RST signal must observe certain timing requirements, which are shown in Figure 11 of the Timing

Diagrams. The DCLK_RST pulse must be of a minimum width and its deassertion edge must observe setup and

hold times with respect to the CLK input rising edge. These timing specifications are listed as tPWR, tSR and tHR

and may be found in AC Electrical Characteristics .

The DCLK_RST signal can be asserted asynchronously to the input clock. If DCLK_RST is asserted, the DCLK

output is held in a designated state (logic-high) in Demux Mode; in Non-Demux Mode, the DCLK continues to

function normally. Depending upon when the DCLK_RST signal is asserted, there may be a narrow pulse on the

DCLK line during this reset event. When the DCLK_RST signal is de-asserted, there are tSYNC_DLY CLK cycles of

systematic delay and the next CLK rising edge synchronizes the DCLK output with those of other

ADC12D1000/1600s in the system. For 90° Mode (DDRPh = logic-high), the synchronizing edge occurs on the

rising edge of CLK, 4 cycles after the first rising edge of CLK after DCLK_RST is released. For 0° Mode (DDRPh

= logic-low), this is 5 cycles instead. The DCLK output is enabled again after a constant delay of tOD.

For both Demux and Non-Demux Modes, there is some uncertainty about how DCLK comes out of the reset

state for the first DCLK_RST pulse. For the second (and subsequent) DCLK_RST pulses, the DCLK will come

out of the reset state in a known way. Therefore, if using the DCLK Reset feature, it is recommended to apply

one "dummy" DCLK_RST pulse before using the second DCLK_RST pulse to synchronize the outputs. This

recommendation applies each time the device or channel is powered-on.

When using DCLK_RST to synchronize multiple ADC12D1000/1600s, it is required that the Select Phase bits in

the Control Register (Addr: Eh, Bits 3,4) be the same for each Master ADC12D1000/1600.

Product Folder Links: ADC12D1000 ADC12D1600

ADC12D1000, ADC12D1600

www.ti.com

SNAS480M –MAY 2010–REVISED MARCH 2013

SUPPLY/GROUNDING, LAYOUT AND THERMAL RECOMMENDATIONS

Power Planes

All supply buses for the ADC should be sourced from a common linear voltage regulator. This ensures that all

power buses to the ADC are turned on and off simultaneously. This single source will be split into individual

sections of the power plane, with individual decoupling and connection to the different power supply buses of the

ADC. Due to the low voltage but relatively high supply current requirement, the optimal solution may be to use a

switching regulator to provide an intermediate low voltage, which is then regulated down to the final ADC supply

voltage by a linear regulator. Please refer to the documentation provided for the ADC12D1000/1600RB for

additional details on specific regulators that are recommended for this configuration.

Power for the ADC should be provided through a broad plane which is located on one layer adjacent to the

ground plane(s). Placing the power and ground planes on adjacent layers will provide low impedance decoupling

of the ADC supplies, especially at higher frequencies. The output of a linear regulator should feed into the power

plane through a low impedance multi-via connection. The power plane should be split into individual power

peninsulas near the ADC. Each peninsula should feed a particular power bus on the ADC, with decoupling for

that power bus connecting the peninsula to the ground plane near each power/ground pin pair. Using this

technique can be difficult on many printed circuit CAD tools. To work around this, zero ohm resistors can be used

to connect the power source net to the individual nets for the different ADC power buses. As a final step, the

zero ohm resistors can be removed and the plane and peninsulas can be connected manually after all other error

checking is completed.

Bypass Capacitors

The general recommendation is to have one 100nF capacitor for each power/ground pin pair. The capacitors

should be surface mount multi-layer ceramic chip capacitors similar to Panasonic part number ECJ-0EB1A104K.

Ground Planes

Grounding should be done using continuous full ground planes to minimize the impedance for all ground return

paths, and provide the shortest possible image/return path for all signal traces.

Power System Example

The ADC12D1000/1600RB uses continuous ground planes (except where clear areas are needed to provide

appropriate impedance management for specific signals), see Figure 76. Power is provided on one plane, with

the 1.9V ADC supply being split into multiple zones or peninsulas for the specific power buses of the ADC.

Decoupling capacitors are connected between these power bus peninsulas and the adjacent ground planes

using vias. The capacitors are located as close to the individual power/ground pin pairs of the ADC as possible.

In most cases, this means the capacitors are located on the opposite side of the PCB to the ADC.

Product Folder Links: ADC12D1000 ADC12D1600

Cross Section Line IC Die Not to Scale

Mold Compound Copper Heat Slug

Substrate

4JC_2

4JC_1

1.9V ADC Main

Switching

Regulator

Linear

Regulator

VDR

VTC

HV or Unreg

Voltage

Intermediate

Voltage

ADC

Dielectric 1

Dielectric 2

Dielectric 3

Dielectric 4

Dielectric 5

Dielectric 6

Dielectric 7

Top Layer ± Signal 1

Ground 1

Signal 2

Ground 2

Power 1

Ground 3

Bottom Layer ± Signal X

Signal 3

Cross Section

Line

ADC12D1000, ADC12D1600

SNAS480M –MAY 2010–REVISED MARCH 2013

www.ti.com

Figure 76. Power and Grounding Example

Thermal Management

The Heat Slug Ball Grid Array (HSBGA) package is a modified version of the industry standard plastic BGA (Ball

Grid Array) package. Inside the package, a copper heat spreader cap is attached to the substrate top with

exposed metal in the center top area of the package. This results in a 20% improvement (typical) in thermal

performance over the standard plastic BGA package.

Figure 77. HSBGA Conceptual Drawing

The center balls are connected to the bottom of the die by vias in the package substrate, Figure 77. This gives a

low thermal resistance between the die and these balls. Connecting these balls to the PCB ground planes with a

low thermal resistance path is the best way dissipate the heat from the ADC. These pins should also be

connected to the ground plane via a low impedance path for electrical purposes. The direct connection to the

ground planes is an easy method to spread heat away from the ADC. Along with the ground plane, the parallel

power planes will provide additional thermal dissipation.

Product Folder Links: ADC12D1000 ADC12D1600

ADC12D1000, ADC12D1600

www.ti.com

SNAS480M –MAY 2010–REVISED MARCH 2013

The center ground balls should be soldered down to the recommended ball pads (See AN-1126 [SNOA021]).

These balls will have wide traces which in turn have vias which connect to the internal ground planes, and a

bottom ground pad/pour if possible. This ensures a good ground is provided for these balls, and that the optimal

heat transfer will occur between these balls and the PCB ground planes.

In spite of these package enhancements, analysis using the standard JEDEC JESD51-7 four-layer PCB thermal

model shows that ambient temperatures must be limited to 70/77°C to ensure a safe operating junction

temperature for the ADC12D1000/1600. However, most applications using the ADC12D1000/1600 will have a

printed circuit board which is more complex than that used in JESD51-7. Typical circuit boards will have more

layers than the JESD51-7 (eight or more), several of which will be used for ground and power planes. In those

applications, the thermal resistance parameters of the ADC12D1000/1600 and the circuit board can be used to

determine the actual safe ambient operating temperature up to a maximum of 85°C.

Three key parameters are provided to allow for modeling and calculations. Because there are two main thermal

paths between the ADC die and external environment, the thermal resistance for each of these paths is provided.

θJC1 represents the thermal resistance between the die and the exposed metal area on the top of the HSBGA

package. θJC2 represents the thermal resistance between the die and the center group of balls on the bottom of

the HSBGA package. The final parameter is the allowed maximum junction temperature, TJ.

In other applications, a heat sink or other thermally conductive path can be added to the top of the HSBGA

package to remove heat. In those cases, θJC1 can be used along with the thermal parameters for the heat sink or

other thermal coupling added. Representative heat sinks which might be used with the ADC12D1000/1600

include the Cool Innovations p/n 3-1212XXG and similar products from other vendors. In many applications, the

printed circuit board will provide the primary thermal path conducting heat away from the ADC package. In those

cases, θJC2 can be used in conjunction with printed circuit board thermal modeling software to determine the

allowed operating conditions that will maintain the die temperature below the maximum allowable limit. Additional

dissipation can be achieved by coupling a heat sink to the copper pour area on the bottom side of the printed

circuit board.

Typically, dissipation will occur through one predominant thermal path. In these cases, the following calculations

can be used to determine the maximum safe ambient operating temperature for the ADC12D1600, for example:

TJ= TA+ PD× (θJC+θCA) (4)

TJ= TA+ PC(MAX) × (θJC+θCA) (5)

For θJC, the value for the primary thermal path in the given application environment should be used (θJC1 or θJC2).

θCA is the thermal resistance from the case to ambient, which would typically be that of the heat sink used. Using

this relationship and the desired ambient temperature, the required heat sink thermal resistance can be found.

Alternately, the heat sink thermal resistance can be used to find the maximum ambient temperature. For more

complex systems, thermal modeling software can be used to evaluate the printed circuit board system and

determine the expected junction temperature given the total system dissipation and ambient temperature.

SYSTEM POWER-ON CONSIDERATIONS

There are a couple important topics to consider associated with the system power-on event including

configuration and calibration, and the Data Clock.

Power-on, Configuration, and Calibration

Following the application of power to the ADC12D1000/1600, several events must take place before the output

from the ADC12D1000/1600 is valid and at full performance; at least one full calibration must be executed with

the device configured in the desired mode.

Following the application of power to the ADC12D1000/1600, there is a delay of tCalDly and then the Power-on

Calibration is executed. This is why it is recommended to set the CalDly Pin via an external pull-up or pull-down

resistor. This ensures that the state of that input will be properly set at the same time that power is applied to the

ADC and tCalDly will be a known quantity. For the purpose of this section, it is assumed that CalDly is set as

recommended.

The Control Bits or Pins must be set or written to configure the ADC12D1000/1600 in the desired mode. This

must take place via either Extended Control Mode or Non-ECM (Pin Control Mode) before subsequent

calibrations will yield an output at full performance in that mode. Some examples of modes include DES/Non-

DES Mode, Demux/Non-demux Mode, and Full-Scale Range.

Product Folder Links: ADC12D1000 ADC12D1600

FPGA writes

Control Pins

Power-on

Calibration On-command

Calibration

Power to

ADC

Calibration

CalDly ADC output

valid

Power-on

Calibration On-command

Calibration

Power to

ADC

Calibration

CalDly

Pull-up/down

resistors set

Control Pins

ADC output

valid

ADC12D1000, ADC12D1600

SNAS480M –MAY 2010–REVISED MARCH 2013

www.ti.com

The simplest case is when device is in Non-ECM and the Control Pins are set by pull-up/down resistors, see

Figure 78. For this case, the settings to the Control Pins ramp concurrently to the ADC voltage. Following the

delay of tCalDly and the calibration execution time, tCAL, the output of the ADC12D1000/1600 is valid and at full

performance. If it takes longer than tCalDly for the system to stabilize at its operating temperature, it is

recommended to execute an on-command calibration at that time.

Another case is when the FPGA configures the Control Pins (Non-ECM) or writes to the SPI (ECM), see

Figure 79. It is always necessary to comply with the Operating Ratings and Absolute Maximum ratings, i.e. the

Control Pins may not be driven below the ground or above the supply, regardless of what the voltage currently

applied to the supply is. Therefore, it is not recommended to write to the Control Pins or SPI before power is

applied to the ADC12D1000/1600. As long as the FPGA has completed writing to the Control Pins or SPI, the

Power-on Calibration will result in a valid output at full performance. Once again, if it takes longer than tCalDly for

the system to stabilize at its operating temperature, it is recommended to execute an on-command calibration at

that time.

Due to system requirements, it may not be possible for the FPGA to write to the Control Pins or SPI before the

Power-on Calibration takes place, see Figure 80. It is not critical to configure the device before the Power-on

Calibration, but it is critical to realize that the output for such a case is not at its full performance. Following an

On-command Calibration, the device will be at its full performance.

Figure 78. Power-on with Control Pins set by Pull-up/down Resistors

Figure 79. Power-on with Control Pins set by FPGA pre Power-on Cal

Product Folder Links: ADC12D1000 ADC12D1600

DCLK

1900

1710

time

660

635

1490

520

300

1210

Slope = 1.22V/ms

FPGA writes

Control Pins

Power-on

Calibration On-command

Calibration

Power to

ADC

Calibration

CalDly

ADC12D1000, ADC12D1600

www.ti.com

SNAS480M –MAY 2010–REVISED MARCH 2013

Figure 80. Power-on with Control Pins set by FPGA post Power-on Cal

Power-on and Data Clock (DCLK)

Many applications use the DCLK output for a system clock. For the ADC12D1000/1600, each I- and Q-channel

has its own DCLKI and DCLKQ, respectively. The DCLK output is always active, unless that channel is powered-

down or the DCLK Reset feature is used while the device is in Demux Mode. As the supply to the

ADC12D1000/1600 ramps, the DCLK also comes up, see this example from the ADC12D1000/1600RB:

Figure 81. While the supply is too low, there is no output at DCLK. As the supply continues to ramp, DCLK

functions intermittently with irregular frequency, but the amplitude continues to track with the supply. Much below

the low end of operating supply range of the ADC12D1000/1600, the DCLK is already fully operational.

Figure 81. Supply and DCLK Ramping

RECOMMENDED SYSTEM CHIPS

TI recommends these other chips including temperature sensors, clocking devices, and amplifiers in order to

support the ADC12D1000/1600 in a system design.

Temperature Sensor

The ADC12D1000/1600 has an on-die temperature diode connected to pins Tdiode+/- which may be used to

monitor the die temperature. TI also provides a family of temperature sensors for this application which monitor

different numbers of external devices, see Table 16.

Product Folder Links: ADC12D1000 ADC12D1600

LM95213

100 pF

ADC12D1XXX

IE = IF

100 pF

D1+

D2+

5D-

FPGA

IE = IF

ADC12D1000, ADC12D1600

SNAS480M –MAY 2010–REVISED MARCH 2013

www.ti.com

Table 16. Temperature Sensor Recommendation

Number of External Devices Monitored Recommended Temperature Sensor

1 LM95235

2 LM95213

4 LM95214

The temperature sensor (LM95235/13/14) is an 11-bit digital temperature sensor with a 2-wire System

Management Bus (SMBus) interface that can monitor the temperature of one, two, or four remote diodes as well

as its own temperature. It can be used to accurately monitor the temperature of up to one, two, or four external

devices such as the ADC12D1000/1600, a FPGA, other system components, and the ambient temperature.

The temperature sensor reports temperature in two different formats for +127.875°C/-128°C range and 0°/255°C

range. It has a Sigma-Delta ADC core which provides the first level of noise immunity. For improved performance

in a noisy environment, the temperature sensor includes programmable digital filters for Remote Diode

temperature readings. When the digital filters are invoked, the resolution for the Remote Diode readings

increases to 0.03125°C. For maximum flexibility and best accuracy, the temperature sensor includes offset

registers that allow calibration for other types of diodes.

Diode fault detection circuitry in the temperature sensor can detect the absence or fault state of a remote diode:

whether D+ is shorted to the power supply, D- or ground, or floating.

In the following typical application, the LM95213 is used to monitor the temperature of an ADC12D1000/1600 as

well as an FPGA, see Figure 82. If this feature is unused, the Tdiode+/- pins may be left floating.

Figure 82. Typical Temperature Sensor Application

Clocking Device

The clock source can be a PLL/VCO device such as the LMX2531LQxxxx family of products. The specific device

should be selected according to the desired ADC sampling clock frequency. The ADC12D1000/1600RB uses the

LMX2531LQ1910E/1570E, with the ADC clock source provided by the Aux PLL output. Other devices which may

be considered based on clock source, jitter cleaning, and distribution purposes are the LMK01XXX, LMK02XXX,

LMK03XXX and LMK04XXX product families.

Amplifiers for the Analog Input

The following amplifiers can be used for ADC12D1000/1600 applications which require DC coupled input or

signal gain, neither of which can be provided with a transformer coupled input circuit:

Table 17. Amplifier Recommendations

Amplifier Bandwidth Brief features

LMH6552 1.5 GHz Configurable gain

LMH6553 900 MHz Output clamp and configurable gain

LMH6554 2.8 GHz Configurable gain

LMH6555 1.2 GHz Fixed gain

Product Folder Links: ADC12D1000 ADC12D1600

ADC12D1000, ADC12D1600

www.ti.com

SNAS480M –MAY 2010–REVISED MARCH 2013

Balun Recommendations for Analog Input

The following baluns are recommended for the ADC12D1000/1600 for applications which require no gain. When

evaluating a balun for the application of driving an ADC, some important qualities to consider are phase error

and magnitude error.

Table 18. Balun Recommendations

Balun Bandwidth

Mini Circuits TC1-1-13MA+ 4.5 - 3000MHz

Anaren B0430J50100A00 400 - 3000 MHz

Mini Circuits ADTL2-18 30 - 1800 MHz

Ten read/write registers provide several control and configuration options in the Extended Control Mode. These

registers have no effect when the device is in the Non-extended Control Mode. Each register description below

also shows the Power-On Reset (POR) state of each control bit. See Table 19 for a summary. For a description

of the functionality and timing to read/write the control registers, see The Serial Interface.

Table 19. Register Addresses

A3 A2 A1 A0 Hex Register Addressed

00000hConfiguration Register 1

00011hReserved

00102hI-channel Offset

00113hI-channel Full-Scale Range

01004hCalibration Adjust

01015hCalibration Values

01106hReserved

01117hDES Timing Adjust

10008hReserved

10019hReserved

1010AhQ-channel Offset

1011BhQ-channel Full-Scale Range

1100ChAperture Delay Coarse Adjust

1101DhAperture Delay Fine Adjust

1110EhAutoSync

1111FhReserved

Product Folder Links: ADC12D1000 ADC12D1600

ADC12D1000, ADC12D1600

SNAS480M –MAY 2010–REVISED MARCH 2013

www.ti.com

Table 20. Configuration Register 1

Addr: 0h(0000b) POR state: 2000h

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name CAL DPS OVS TPM PDI PDQ Res LFS DES DEQ DIQ 2SC TSE Res

POR 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 CAL: Calibration Enable. When this bit is set to 1b, an on-command calibration is initiated. This bit is not reset automatically

upon completion of the calibration. Therefore, the user must reset this bit to 0band then set it to 1bagain to execute another

calibration. This bit is logically OR'd with the CAL Pin; both bit and pin must be set to 0bbefore either is used to execute a

calibration.

Bit 14 DPS: DCLK Phase Select. In DDR, set this bit to 0bto select the 0° Mode DDR Data-to-DCLK phase relationship and to 1bto

select the 90° Mode. If the device is in Non-Demux Mode, this bit has no effect; the device will always be in 0°DDR Mode.

Bit 13 OVS: Output Voltage Select. This bit sets the differential voltage level for the LVDS outputs including Data, OR, and DCLK. 0b

selects the lower level and 1bselects the higher level. See VOD in Digital Control and Output Pin Characteristics for details.

Bit 12 TPM: Test Pattern Mode. When this bit is set to 1b, the device will continually output a fixed digital pattern at the digital Data

and OR outputs. When set to 0b, the device will continually output the converted signal, which was present at the analog

inputs. See Test Pattern Mode for details about the TPM pattern.

Bit 11 PDI: Power-down I-channel. When this bit is set to 0b, the I-channel is fully operational; when it is set to 1b, the I-channel is

powered-down. The I-channel may be powered-down via this bit or the PDI Pin, which is active, even in ECM.

Bit 10 PDQ: Power-down Q-channel. When this bit is set to 0b, the Q-channel is fully operational; when it is set to 1b, the Q-channel

is powered-down. The Q-channel may be powered-down via this bit or the PDQ Pin, which is active, even in ECM.

Bit 9 Reserved. Must be set to 0b.

Bit 8 LFS: Low-Frequency Select. If the sampling clock (CLK) is at or below 300 MHz, set this bit to 1bfor improved performance.

Bit 7 DES: Dual-Edge Sampling Mode select. When this bit is set to 0b, the device will operate in the Non-DES Mode; when it is set

to 1b, the device will operate in the DES Mode. See DES/Non-DES Mode for more information.

Bit 6 DEQ: DES Q-input select, a.k.a. DESQ Mode. When the device is in DES Mode, this bit selects the input that the device will

operate on. The default setting of 0bselects the I-input and 1bselects the Q-input.

Bit 5 DIQ: DES I- and Q-input, a.k.a. DESIQ Mode. When in DES Mode, setting this bit to 1bshorts the I- and Q-inputs internally to

the device. If the bit is left at its default 0b, the I- and Q-inputs remain electrically separate. To operate the device in DESIQ

Mode, Bits<7:5> must be set to 101b. In this mode, both the I- and Q-inputs must be externally driven; see DES/Non-DES

Mode for more information.

Bit 4 2SC: Two's Complement output. For the default setting of 0b, the data is output in Offset Binary format; when set to 1b, the

data is output in Two's Complement format.

Bit 3 TSE: Time Stamp Enable. For the default setting of 0b, the Time Stamp feature is not enabled; when set to 1b, the feature is

enabled. See Output Control and Adjust for more information about this feature.

Bits 2:0 Reserved. Must be set as shown.

Table 21. Reserved

Addr: 1h(0001b) POR state: 2A0Eh

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Res

POR 0 0 1 0 1 0 1 0 0 0 0 0 1 1 1 0

Bits 15:0 Reserved. Must be set as shown.

Product Folder Links: ADC12D1000 ADC12D1600

ADC12D1000, ADC12D1600

www.ti.com

SNAS480M –MAY 2010–REVISED MARCH 2013

Table 22. I-channel Offset Adjust

Addr: 2h(0010b) POR state: 0000h

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Res OS OM(11:0)

POR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bits 15:13 Reserved. Must be set to 0b.

Bit 12 OS: Offset Sign. The default setting of 0bincurs a positive offset of a magnitude set by Bits 11:0 to the ADC output. Setting

this bet to 1bincurs a negative offset of the set magnitude.

Bits 11:0 OM(11:0): Offset Magnitude. These bits determine the magnitude of the offset set at the ADC output (straight binary coding).

The range is from 0 mV for OM(11:0) = 0dto 45 mV for OM(11:0) = 4095din steps of ~11 µV. Monotonicity is ensured by

design only for the 9 MSBs.

Code Offset [mV]

0000 0000 0000 (default) 0

1000 0000 0000 22.5

1111 1111 1111 45

Table 23. I-channel Full Scale Range Adjust

Addr: 3h(0011b) POR state: 4000h

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Res FM(14:0)

POR 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 Reserved. Must be set to 0b.

Bits 14:0 FM(14:0): FSR Magnitude. These bits increase the ADC full-scale range magnitude (straight binary coding.) The range is from

600 mV (0d) to 1000 mV (32767d) with the default setting at 800 mV (16384d). Monotonicity is ensured by design only for the

9 MSBs. The mid-range (low) setting in ECM corresponds to the nominal (low) setting in Non-ECM. A greater range of FSR

values is available in ECM, i.e. FSR values above 800 mV. See VIN_FSR in Analog Input/Output and Reference Characteristics

for characterization details.

Code FSR [mV]

000 0000 0000 0000 600

100 0000 0000 0000 (default) 800

111 1111 1111 1111 1000

Table 24. Calibration Adjust

Addr: 4h(0100b) POR state: DF4Bh

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Res CSS Res SSC Res

POR 1 1 0 1 1 1 1 1 0 1 0 0 1 0 1 1

Bit 15 Reserved. Must be set as shown.

Bit 14 CSS: Calibration Sequence Select. The default 1bselects the following calibration sequence: reset all previously calibrated

elements to nominal values, do RIN Calibration, do internal linearity Calibration. Setting CSS = 0bselects the following

calibration sequence: do not reset RIN to its nominal value, skip RIN calibration, do internal linearity Calibration. The calibration

must be completed at least one time with CSS = 1bto calibrate RIN. Subsequent calibrations may be run with CSS = 0b(skip

RIN calibration) or 1b(full RIN and internal linearity Calibration).

Bits 13:8 Reserved. Must be set as shown.

Bit 7 SSC: SPI Scan Control. Setting this control bit to 1ballows the calibration values, stored in Addr: 5h, to be read/written. When

not reading/writing the calibration values, this control bit should left at its default 0bsetting. See Calibration Feature for more

information.

Bits 6:0 Reserved. Must be set as shown.

Product Folder Links: ADC12D1000 ADC12D1600

ADC12D1000, ADC12D1600

SNAS480M –MAY 2010–REVISED MARCH 2013

www.ti.com

Table 25. Calibration Values

Addr: 5h(0101b) POR state: XXXXh

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name SS(15:0)

POR X X X X X X X X X X X X X X X X

Bits 15:0 SS(15:0): SPI Scan. When the ADC performs a self-calibration, the values for the calibration are stored in this register and may

be read from/ written to it. Set SSC (Addr: 4h, Bit 7) to read/write. See Calibration Feature for more information.

Table 26. Reserved

Addr: 6h(0110b) POR state: 1C20h

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Res

POR 0 0 0 1 1 1 0 0 0 0 1 0 0 0 0 0

Bits 15:0 Reserved. Must be set as shown.

Table 27. DES Timing Adjust

Addr: 7h(0111b) POR state: 8140h

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name DTA(6:0) Res

POR 1 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0

Bits 15:9 DTA(6:0): DES Mode Timing Adjust. In the DES Mode, the time at which the falling edge sampling clock samples relative to

the rising edge of the sampling clock may be adjusted; the automatic duty cycle correction continues to function. See Input

Control and Adjust for more information. The nominal step size is 30fs.

Bits 8:0 Reserved. Must be set as shown.

Table 28. Reserved

Addr: 8h(1000b) POR state: 0000h

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Res

POR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bits 15:0 Reserved. Must be set as shown.

Table 29. Reserved

Addr: 9h(1001b) POR state: 0000h

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Res

POR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bits 15:0 Reserved. Must be set as shown.

Product Folder Links: ADC12D1000 ADC12D1600

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SNAS480M –MAY 2010–REVISED MARCH 2013

Table 30. Q-channel Offset Adjust

Addr: Ah(1010b) POR state: 0000h

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Res OS OM(11:0)

POR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bits 15:13 Reserved. Must be set to 0b.

Bit 12 OS: Offset Sign. The default setting of 0bincurs a positive offset of a magnitude set by Bits 11:0 to the ADC output. Setting

this bet to 1bincurs a negative offset of the set magnitude.

Bits 11:0 OM(11:0): Offset Magnitude. These bits determine the magnitude of the offset set at the ADC output (straight binary coding).

The range is from 0 mV for OM(11:0) = 0dto 45 mV for OM(11:0) = 4095din steps of ~11 µV. Monotonicity is ensured by

design only for the 9 MSBs.

Code Offset [mV]

0000 0000 0000 (default) 0

1000 0000 0000 22.5

1111 1111 1111 45

Table 31. Q-channel Full-Scale Range Adjust

Addr: Bh(1011b) POR state: 4000h

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Res FM(14:0)

POR 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 Reserved. Must be set to 0b.

Bits 14:0 FM(14:0): FSR Magnitude. These bits increase the ADC full-scale range magnitude (straight binary coding.) The range is from

600 mV (0d) to 1000 mV (32767d) with the default setting at 800 mV (16384d). Monotonicity is ensured by design only for the

9 MSBs. The mid-range (low) setting in ECM corresponds to the nominal (low) setting in Non-ECM. A greater range of FSR

values is available in ECM, i.e. FSR values above 800 mV. See VIN_FSR in Analog Input/Output and Reference Characteristics

for characterization details.

Code FSR [mV]

000 0000 0000 0000 600

100 0000 0000 0000 (default) 800

111 1111 1111 1111 1000

Table 32. Aperture Delay Coarse Adjust

Addr: Ch(1100b) POR state: 0004h

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name CAM(11:0) STA DCC Res

POR 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0

Bits 15:4 CAM(11:0): Coarse Adjust Magnitude. This 12-bit value determines the amount of delay that will be applied to the input CLK

signal. The range is 0 ps delay for CAM(11:0) = 0dto a maximum delay of 825 ps for CAM(11:0) = 2431d(±95 ps due to PVT

variation) in steps of ~340 fs. For code CAM(11:0) = 2432dand above, the delay saturates and the maximum delay applies.

Additional, finer delay steps are available in register Dh. The STA (Bit 3) must be selected to enable this function.

Bit 3 STA: Select tAD Adjust. Set this bit to 1bto enable the tAD adjust feature, which will make both coarse and fine adjustment

settings, i.e. CAM(11:0) and FAM(5:0), available.

Bit 2 DCC: Duty Cycle Correct. This bit can be set to 0bto disable the automatic duty-cycle stabilizer feature of the chip. This

feature is enabled by default.

Bits 1:0 Reserved. Must be set to 0b.

Product Folder Links: ADC12D1000 ADC12D1600

ADC12D1000, ADC12D1600

SNAS480M –MAY 2010–REVISED MARCH 2013

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Table 33. Aperture Delay Fine Adjust

Addr: Dh(1101b) POR state: 0000h

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name FAM(5:0) Res Res

POR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bits 15:10 FAM(5:0): Fine Aperture Adjust Magnitude. This 6-bit value determines the amount of additional delay that will be applied to

the input CLK when the Clock Phase Adjust feature is enabled via STA (Addr: Ch, Bit 3). The range is straight binary from 0 ps

delay for FAM(5:0) = 0dto 2.3 ps delay for FAM(5:0) = 63d(±300 fs due to PVT variation) in steps of ~36 fs.

Bits 9:0 Reserved. Must be set as shown.

Table 34. AutoSync

Addr: Eh(1110b) POR state: 0003h

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name DRC(8:0) Res SP(1:0) ES DOC DR

POR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1

Bits 15:7 DRC(8:0): Delay Reference Clock (8:0). These bits may be used to increase the delay on the input reference clock when

synchronizing multiple ADCs. The delay may be set from a minimum of 0s (0d) to a maximum of 1000 ps (319d). The delay

remains the maximum of 1000 ps for any codes above or equal to 319d. See SYNCHRONIZING MULTIPLE

ADC12D1000/1600S IN A SYSTEM for more information.

Bits 6:5 Reserved. Must be set as shown.

Bits 4:3 SP(1:0): Select Phase. These bits select the phase of the reference clock which is latched. The codes correspond to the

following phase shift:

00 = 0°

01 = 90°

10 = 180°

11 = 270°

Bit 2 ES: Enable Slave. Set this bit to 1bto enable the Slave Mode of operation. In this mode, the internal divided clocks are

synchronized with the reference clock coming from the master ADC. The master clock is applied on the input pins RCLK. If this

bit is set to 0b, then the device is in Master Mode.

Bit 1 DOC: Disable Output reference Clocks. Setting this bit to 0bsends a CLK/4 signal on RCOut1 and RCOut2. The default

setting of 1bdisables these output drivers. This bit functions as described, regardless of whether the device is operating in

Master or Slave Mode, as determined by ES (Bit 2).

Bit 0 DR: Disable Reset. The default setting of 1bleaves the DCLK_RST functionality disabled. Set this bit to 0bto enable

DCLK_RST functionality.

Table 35. Reserved

Addr: Fh(1111b) POR state: 0018h

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Res

POR 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0

Bits 15:0 Reserved. This address is read only.

Product Folder Links: ADC12D1000 ADC12D1600

ADC12D1000, ADC12D1600

www.ti.com

SNAS480M –MAY 2010–REVISED MARCH 2013

REVISION HISTORY

Changes from Revision L (March 2013) to Revision M Page

• Changed layout of National Data Sheet to TI format .......................................................................................................... 63

Product Folder Links: ADC12D1000 ADC12D1600

PACKAGE OPTION ADDENDUM

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Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

ADC12D1000CIUT NRND BGA NXA 292 40 TBD Call TI Call TI -40 to 85 ADC12D1000CIUT

ADC12D1000CIUT/NOPB ACTIVE BGA NXA 292 40 Green (RoHS

& no Sb/Br) NI/AU Level-3-250C-168 HR -40 to 85 ADC12D1000CIUT

ADC12D1600CIUT NRND BGA NXA 292 40 TBD Call TI Call TI -40 to 85 ADC12D1600CIUT

ADC12D1600CIUT/NOPB ACTIVE BGA NXA 292 40 Green (RoHS

& no Sb/Br) NI/AU Level-3-250C-168 HR -40 to 85 ADC12D1600CIUT

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

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Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

PACKAGE OPTION ADDENDUM

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Addendum-Page 2

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

MECHANICAL DATA

NXA0292A

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