7-1029
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
CD4076BMS
CMOS 4 -Bit D-Type Registers
Pinout
CD4076BMS
TOP VIEW
Functional Diagram
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
M
N
Q1
Q2
Q3
Q4
VSS
CLOCK
VDD
DATA 1
DATA 2
DATA 3
DATA 4
G2
G1
RESET
DATA
INPUT
DISABLE
OUTPUT
DISABLE
4D - TYPE
FLIP-FLOPS
WITH
AND-OR
LOGIC
CLOCK
RESET
7
15
G1 G2 M N
910 1 2
D1
D2
D3
D4
14
13
12
11
Q1
Q2
Q3
Q4
3
4
5
6
VSS = 8
VDD = 16
DATA INPUT
DISABLE OUTPUT
DISABLE
Features
• High Voltage Type (20V Rating)
• Three State Outputs
• Input Disabled Without Gating the Clock
• Gated Output Control Lines for Enabling or Disabling
the Outputs
• Standardized Symmetrical Output Characteristics
• 100% Tested for Quiescent Current at 20V
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25oC
• Noise Margin (Over Full Package/Temperature Range)
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• 5V, 10V and 15V Parametric Ratings
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
Description
CD4076BMS types are four-bit registers consisting of D-type
flip-flops that feature three-state outputs. Data Disable inputs
are provided to control the entry of data into the flip-flops.
When both Data Disable inputs are low, data at the D inputs
are loaded into their respective flip-flops on the next positive
transition of the clock input. Output Disable inputs are also
provided. When the Output Disable inputs are both low, the
normal logic states of the four outputs are available to the
load. The outputs are disabled independently of the clock by
a high logic level at either Output Disable input, and present
a high impedance.
The CD4076BMS is supplied in these 16 lead outline pack-
ages:
Braze Seal DIP H4T
Frit Seal DIP H1E
Ceramic Flatpack H6W
December 1992
File Number 3325
7-1030
Specifications CD4076BMS
Absolute Maximum Ratings Reliability Information
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V
(Voltage Referenced to VSS Terminals)
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA
Operating Temperature Range. . . . . . . . . . . . . . . . -55oC to +125oC
Package Types D, F, K, H
Storage Temperature Range (TSTG). . . . . . . . . . . -65oC to +150oC
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC
At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for
10s Maximum
Thermal Resistance . . . . . . . . . . . . . . . . θja θjc
Ceramic DIP and FRIT Package. . . . . 80oC/W 20oC/W
Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W
Maximum Package Power Dissipation (PD) at +125oC
For TA = -55oC to +100oC (Package Type D, F, K). . . . . . 500mW
For TA = +100oC to +125oC (Package Type D, F, K) . . . . .Derate
Linearity at 12mW/oC to 200mW
Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
For TA = Full Package Temperature Range (All Package Types)
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER SYMBOL CONDITIONS (NOTE 1)
GROUP A
SUBGROUP
S TEMPERATURE
LIMITS UNIT
SMIN MAX
Supply Current IDD VDD = 20V, VIN = VDD or GND 1 +25oC-10µA
2 +125oC - 1000 µA
VDD = 18V, VIN = VDD or GND 3 -55oC-10µA
Input Leakage Current IIL VIN = VDD or GND VDD = 20 1 +25oC -100 - nA
2 +125oC -1000 - nA
VDD = 18V 3 -55oC -100 - nA
Input Leakage Current IIH VIN = VDD or GND VDD = 20 1 +25oC - 100 nA
2 +125oC - 1000 nA
VDD = 18V 3 -55oC - 100 nA
Output Voltage VOL15 VDD = 15V, No Load 1, 2, 3 +25oC, +125oC, -
55oC-50mV
Output Voltage VOH15 VDD = 15V, No Load (Note 3) 1, 2, 3 +25oC, +125oC, -
55oC14.95 - V
Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1 +25oC 0.53 - mA
Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1 +25oC 1.4 - mA
Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1 +25oC 3.5 - mA
Output Current
(Source) IOH5A VDD = 5V, VOUT = 4.6V 1 +25oC - -0.53 mA
Output Current
(Source) IOH5B VDD = 5V, VOUT = 2.5V 1 +25oC - -1.8 mA
Output Current
(Source) IOH10 VDD = 10V, VOUT = 9.5V 1 +25oC - -1.4 mA
Output Current
(Source) IOH15 VDD = 15V, VOUT = 13.5V 1 +25oC - -3.5 mA
N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1 +25oC -2.8 -0.7 V
P Threshold Voltage VPTH VSS = 0V, IDD = 10µA 1 +25oC 0.7 2.8 V
Functional F VDD = 2.8V, VIN = VDD or GND 7 +25oC VOH >
VDD/2 VOL
<
VDD/2
V
VDD = 20V, VIN = VDD or GND 7 +25oC
VDD = 18V, VIN = VDD or GND 8A +125oC
VDD = 3V, VIN = VDD or GND 8B -55oC
Input Voltage Low
(Note 2) VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -
55oC- 1.5 V
Input Voltage High
(Note 2) VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -
55oC3.5 - V
Input Voltage Low
(Note 2) VIL VDD = 15V, VOH > 13.5V,
VOL < 1.5V 1, 2, 3 +25oC, +125oC, -
55oC-4V
Input Voltage High
(Note 2) VIH VDD = 15V, VOH > 13.5V,
VOL < 1.5V 1, 2, 3 +25oC, +125oC, -
55oC11 - V
Tri-State Output
Leakage IOZL VIN = VDD or GND
VOUT = 0V VDD = 20V 1 +25oC -0.4 - µA
2 +125oC -12 - µA
VDD = 18V 3 -55oC -0.4 - µA
7-1031
Specifications CD4076BMS
Tri-State Output
Leakage IOZH VIN = VDD or GND
VOUT = VDD VDD = 20V 1 +25oC - 0.4 µA
2 +125oC-12µA
VDD = 18V 3 -55oC - 0.4 µA
NOTES: 1. All voltages referenced to device GND, 100% testing being
implemented.
2. Go/No Go test with limits applied to inputs.
3. For accuracy, voltage is measured differentially to VDD.
Limit is 0.050V max.
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER SYMBOL CONDITIONS (Notes 1, 2) GROUP A
SUBGROUPS TEMPERATURE
LIMITS
UNITSMIN MAX
Propagation Delay
Clock to Q Output TPHL
TPLH VDD = 5V, VIN = VDD or GND 9 +25oC - 600 ns
10, 11 +125oC, -55oC - 810 ns
Transition Time TTHL
TTLH VDD = 5V, VIN = VDD or GND 9 +25oC - 200 ns
10, 11 +125oC, -55oC - 270 ns
NOTES:
1. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
2. -55oC and +125oC limits guaranteed, 100% testing being implemented.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE
LIMITS
UNITSMIN MAX
Supply Current IDD VDD = 5V, VIN = VDD or GND 1, 2 -55oC, +25oC- 5 µA
+125oC - 150 µA
VDD = 10V, VIN = VDD or GND 1, 2 -55oC, +25oC- 10µA
+125oC - 300 µA
VDD = 15V, VIN = VDD or GND 1, 2 -55oC, +25oC- 10µA
+125oC - 600 µA
Output Voltage VOL VDD = 5V, No Load 1, 2 +25oC, +125oC,
-55oC-50mV
Output Voltage VOL VDD = 10V, No Load 1, 2 +25oC, +125oC,
-55oC-50mV
Output Voltage VOH VDD = 5V, No Load 1, 2 +25oC, +125oC,
-55oC4.95 - V
Output Voltage VOH VDD = 10V, No Load 1, 2 +25oC, +125oC,
-55oC9.95 - V
Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1, 2 +125oC 0.36 - mA
-55oC 0.64 - mA
Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1, 2 +125oC 0.9 - mA
-55oC 1.6 - mA
Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1, 2 +125oC 2.4 - mA
-55oC 4.2 - mA
Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1, 2 +125oC - -0.36 mA
-55oC - -0.64 mA
Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1, 2 +125oC - -1.15 mA
-55oC - -2.0 mA
Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1, 2 +125oC - -0.9 mA
-55oC - -2.6 mA
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER SYMBOL CONDITIONS (NOTE 1)
GROUP A
SUBGROUP
S TEMPERATURE
LIMITS UNIT
SMIN MAX
7-1032
Specifications CD4076BMS
Output Current (Source) IOH15 VDD =15V, VOUT = 13.5V 1, 2 +125oC - -2.4 mA
-55oC - -4.2 mA
Input Voltage Low VIL VDD = 10V, VOH > 9V, VOL <
1V 1, 2 +25oC, +125oC,
-55oC-3V
Input Voltage High VIH VDD = 10V, VOH > 9V, VOL <
1V 1, 2 +25oC, +125oC,
-55oC7-V
Propagation Delay
Clock to Q Output TPHL1
TPLH1 VDD = 10V 1, 2, 3 +25oC - 250 ns
VDD = 15V 1, 2, 3 +25oC - 180 ns
Propagation Delay
Reset TPHL2 VDD = 5V 1, 2, 3 +25oC - 460 ns
VDD = 10V 1, 2, 3 +25oC - 200 ns
VDD = 15V 1, 2, 3 +25oC - 150 ns
Propagation Delay
3 - State TPHZ
TPLZ VDD = 5V 1, 2, 4 +25oC - 300 ns
VDD = 10V 1, 2, 4 +25oC - 150 ns
VDD = 15V 1, 2, 4 +25oC - 120 ns
Propagation Delay
3 - State TPZH
TPZL VDD = 5V 1, 2, 4 +25oC - 300 ns
VDD = 10V 1, 2, 4 +25oC - 150 ns
VDD = 15V 1, 2, 4 +25oC - 120 ns
Transition Time TTHL
TTLH VDD = 10V 1, 2, 3 +25oC - 100 ns
VDD = 15V 1, 2, 3 +25oC - 80 ns
Transition Time TTLH VDD = 10V 1, 2, 3 +25oC--ns
VDD = 15V 1, 2, 3 +25oC--ns
Maximum Clock Input
Frequency FCL VDD = 5V 1, 2, 3 +25oC 3 - MHz
VDD = 10V 1, 2, 3 +25oC 6 - MHz
VDD = 15V 1, 2, 3 +25oC 8 - MHz
Minimum Data Setup
Time TS VDD = 5V 1, 2, 3 +25oC - 200 ns
VDD = 10V 1, 2, 3 +25oC - 80 ns
VDD = 15V 1, 2, 3 +25oC - 60 ns
Minimum Data Hold Time
Reset Pulse Width TW VDD = 5V 1, 2, 3 +25oC - 120 ns
VDD = 10V 1, 2, 3 +25oC - 50 ns
VDD = 15V 1, 2, 3 +25oC - 40 ns
Minimum Clock Pulse
Width TW VDD = 5V 1, 2, 3 +25oC - 200 ns
VDD = 10V 1, 2, 3 +25oC - 100 ns
VDD = 15V 1, 2, 3 +25oC - 80 ns
Minimum Data Input Set-
Up Time TS VDD = 5V 1, 2, 3 +25oC - 180 ns
VDD = 10V 1, 2, 3 +25oC - 100 ns
VDD = 15V 1, 2, 3 +25oC - 70 ns
Maximum Clock Input
Rise and Fall Time TRCL
TFCL VDD = 5V 1, 2, 3, 5 +25oC-15µs
VDD = 10V 1, 2, 3, 5 +25oC-5µs
VDD = 15V 1, 2, 3, 5 +25oC-5µs
Input Capacitance CIN Any Input 1, 2 +25oC - 7.5 pF
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE
LIMITS
UNITSMIN MAX
7-1033
Specifications CD4076BMS
NOTES:
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized
on initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
4. CL = 50pF, RL = 1K, Input TR, TF < 20ns.
5. If more than one unit is cascaded, TRCL should be made less than or equal to the sum of the transition time and the fixed propagation
delay of the output of the driving stage for the estimated capacitive load.
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE
LIMITS
UNITSMIN MAX
Supply Current IDD VDD = 20V, VIN = VDD or GND 1, 4 +25oC-25µA
N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1, 4 +25oC -2.8 -0.2 V
N Threshold Voltage
Delta ∆VTN VDD = 10V, ISS = -10µA 1, 4 +25oC-±1V
P Threshold Voltage VTP VSS = 0V, IDD = 10µA 1, 4 +25oC 0.2 2.8 V
P Threshold Voltage
Delta ∆VTP VSS = 0V, IDD = 10µA 1, 4 +25oC-±1V
Functional F VDD = 18V, VIN = VDD or GND 1 +25oC VOH >
VDD/2 VOL <
VDD/2 V
VDD = 3V, VIN = VDD or GND
Propagation Delay Time TPHL
TPLH VDD = 5V 1, 2, 3, 4 +25oC - 1.35 x
+25oC
Limit
ns
NOTES: 1. All voltages referenced to device GND.
2. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 3. See Table 2 for +25oC limit.
4. Read and Record
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC
PARAMETER SYMBOL DELTA LIMIT
Supply Current - MSI-2 IDD ± 1.0µA
Output Current (Sink) IOL5 ± 20% x Pre-Test Reading
Output Current (Source) IOH5A ± 20% x Pre-Test Reading
TABLE 6. APPLICABLE SUBGROUPS
CONFORMANCE GROUP MIL-STD-883
METHOD GROUP A SUBGROUPS READ AND RECORD
Initial Test (Pre Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
Interim Test 1 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
Interim Test 2 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
PDA (Note 1) 100% 5004 1, 7, 9, Deltas
Interim Test 3 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
PDA (Note 1) 100% 5004 1, 7, 9, Deltas
Final Test 100% 5004 2, 3, 8A, 8B, 10, 11
Group A Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11
Group B Subgroup B-5 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Subgroups 1, 2, 3, 9, 10, 11
Subgroup B-6 Sample 5005 1, 7, 9
Group D Sample 5005 1, 2, 3, 8A, 8B, 9 Subgroups 1, 2 3
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE
LIMITS
UNITSMIN MAX
7-1034
Specifications CD4076BMS
FIGURE 1. CD4076BMS LOGIC DIAGRAM
TABLE 7. TOTAL DOSE IRRADIATION
CONFORMANCE GROUPS MIL-STD-883
METHOD
TEST READ AND RECORD
PRE-IRRAD POST-IRRAD PRE-IRRAD POST-IRRAD
Group E Subgroup 2 5005 1, 7, 9 Table 4 1, 9 Table 4
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
FUNCTION OPEN GROUND VDD 9V ± -0.5V
OSCILLATOR
50kHz 25kHz
Static Burn-In 1 Note 1 3 - 6 1, 2, 7 - 15 16
Static Burn-In 2 Note 1 3 - 6 8 1, 2, 7, 9 -16
Dynamic Burn-In Note 1 - 1, 2, 8 - 10, 15 16 3 - 6 7 11 - 14
Irradiation (Note 2) 3 - 6 8 1, 2, 7, 9 - 16
NOTE:
1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
2. Each pin except VDD and GND will have a series resistor of 47K±5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V ± 0.5V
D
CL
R
Q
Q
D
CL
R
Q
Q
D
CL
R
Q
Q
D
CL
R
Q
Q
OUTPUT
DISABLE
DATA
INPUT
DISABLE
M
N
G1
G2
DATA
1
*
*
*
*
*
DATA
2*
CLOCK *
1
2
14
9
10
13
7
12
11
15
DATA
3*
DATA
4
*
RESET
16 VDD
3Q1
4Q2
5Q3
6Q4
8 VSS
VDD
VSS
* ALL INPUTS PROTECTED BY
CMOS PROTECTION NETWORK
*
7-1035
CD4076BMS
TRUTH TABLE
RESET CLOCK
DATA INPUT DISABLE DATA NEXT STATE
OUTPUT
G1 G2 D Q
1XXXX0
00XXXQNC
01XXQNC
0X1XQNC
00011
00000
01XXXQNC
0XXXQNC
When either Output Disable M or N is high, the outputs are disabled (high impedance state), however sequential operation of the flip-flops is not affected.
1 = High Level X = Don’t Care
0 = Low Level NC = No Change
Typical Performance Characteristics
FIGURE 2. TYPICAL OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS FIGURE 3. MINIMUM OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS
FIGURE 4. TYPICAL OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS FIGURE 5. MINIMUM OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS
10V
5V
AMBIENT TEMPERATURE (T A) = +25oC
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
0 5 10 15
15
10
5
20
25
30
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
OUTPUT LOW (SINK) CURRENT (IOL) (mA)
10V
5V
AMBIENT TEMPERATURE (T A) = +25oC
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
0 5 10 15
7.5
5.0
2.5
10.0
12.5
15.0
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
OUTPUT LOW (SINK) CURRENT (IOL) (mA)
-10V
-15V
AMBIENT TEMPERATURE (T A) = +25oC
GATE-TO-SOURCE VOLTAGE (VGS) = -5V
0
-5
-10
-15
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
-20
-25
-30
0-5-10-15
OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)
-10V
-15V
AMBIENT TEMPERATURE (T A) = +25oC0
-5
-10
-15
DRAIN-TO-SOURCE VOLTAGE (VDS) (V) 0-5-10-15
OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)
GATE-TO-SOURCE VOLTAGE (VGS) = -5V
7-1036
CD4076BMS
FIGURE 10. FUNCTIONAL WAVEFORM
FIGURE 6. TYPICAL PROPAGATION DELAY TIME vs LOAD
CAPACITANCE (CLOCK TO Q) FIGURE 7. TYPICAL TRANSITION TIME vs LOAD
CAPACITANCE
FIGURE 8. TYPICAL MAXIMUM CLOCK INPUT FREQUENCY vs
SUPPLY VOLTAGE FIGURE 9. TYPICAL DYNAMIC POWER DISSIPATION vs
FREQUENCY
Typical Performance Characteristics (Continued)
AMBIENT TEMPERATURE (T A) = +25oC
LOAD CAPACITANCE (CL) (pF)
020
100
SUPPLY VOLTAGE (VDD) = 5V
10V
15V
PROPAGATION DELAY TIME (tPHL, tPLH) (ns)
40 60 80 100 120 140
200
300
400
500
AMBIENT TEMPERATURE (T A) = +25oC
LOAD CAPACITANCE (CL) (pF)
0 40 60 80 10020
0
50
100
150
200
SUPPLY VOLTAGE (VDD) = 5V
10V
5V
TRANSITION TIME (tTHL, tTLH) (ns)
AMBIENT TEMPERATURE (TA) = +25oC
LOAD CAPACITANCE (CL) = 50pF
5
0 5 10 15 20
SUPPLY VOLTAGE (VDD) (V)
10
15
MAXIMUM CLOCK FREQUENCY
(fCL MAX) (MHz)
10V
5V 10V
86428642
INPUT FREQUENCY (f) (kHz)
10-1 11010
2
8
6
4
2
8
6
4
2
103
102
10
1
104
POWER DISSIPATION PER GATE (PD) (µW)
AMBIENT TEMPERATURE (TA) = +25oC
SUPPLY VOLTAGE (VDD) = 15V
CL = 15pF
CL = 50pF
86428642 1038642 1048642
8
6
4
2
8
6
4
2
8
6
4
2
105
10%
90%
50%
50%
tW tW
tStS
tS
DATA
INPUT
DIABLE
RESET
Q
OUTPUT
tW
tPHL
tTHL tTLH
tPLH tPHL
50%
50%
CLOCK 50%
1037
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notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
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CD4076BMS
FIGURE 11. FUNCTIONAL WAVEFORM
tPHZ
VDD
VSS
VDD
VOL
VOH
VSS
50%
90%
10%
50%
tPZH
10%
90%
tPZLtPLZ
Q OUTPUT
Q OUTPUT
OUTPUT DISABLE CHARACTER
TEST VOLTAGE
AT D AT Q
tPHZ VDD VSS
tPLZ VSS VDD
tPZL VSS VDD
tPZH VDD VSS
Chip Dimensions and Pad Layout
METALLIZATION: Thickness: 11kÅ−14kÅ, AL.
PASSIVATION: 10.4kÅ - 15.6kÅ, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN
DIE THICKNESS: 0.0198 inches - 0.0218 inches
Dimensions in parentheses are in millimeters
and are derived from the basic inch dimensions
as indicated. Grid graduations are in mils (10-3 inch)
