BCM20730A1KMLG - CYPRESS SEMICONDUCTOR

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Document Number: 002-14824 Rev. *H Revised October 17, 2016

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“Broadcom”, the company that originally developed the specification, Cypress will continue to offer these products to

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been made are the result of normal document improvements and are noted in the document history page, where

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Broadcom Ordering Part Number

Cypress Ordering Part Number

BCM20730A2KML2GT

BCM20730A1KML2G

BCM20730A1KMLG

BCM20730A1KFBGT

BCM20730A2KFBG

BCM20730A1KFBG

BCM20730A1KML2GT

BCM20730A2KML2G

BCM20730A1KMLGT

BCM20730A2KFBGT

CYW20730A2KML2GT

CYW20730A1KML2G

CYW20730A1KMLG

CYW20730A1KFBGT

CYW20730A2KFBG

CYW20730A1KFBG

CYW20730A1KML2GT

CYW20730A2KML2G

CYW20730A1KMLGT

CYW20730A2KFBGT

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Data Sheet

BCM20730

20730-DS108-R

5300 California Avenue • Irvine, CA 92617 • Phone: 949-926-5000 • Fax: 949-926-5203 September 9, 2013

Single-Chip Bluetooth Transceiver for Wireless

Input Devices

GENERAL DESCRIPTION

FEATURES

The Broadcom® BCM20730 is a Bluetooth 3.0-

compliant, stand-alone baseband processor with an

integrated 2.4 GHz transceiver. It is ideal for wireless

input device applications including game controllers,

keyboards, 3D glasses, remote controls, gestural

input devices, and sensor devices. Built-in firmware

adheres to the Bluetooth Human Interface Device

(HID) profile and Bluetooth Device ID profile

specifications.

The BCM20730 radio has been designed to provide

low power, low cost, and robust communications for

applications operating in the globally available

2.4 GHz unlicensed ISM band. It is fully compliant

with Bluetooth Radio Specification 3.0.

The single-chip Bluetooth transceiver is a monolithic

component implemented in a standard digital CMOS

process and requires minimal external components

to make a fully compliant Bluetooth device. The

BCM20730 is available in three package options: a

32-pin, 5 mm × 5 mm QFN, a 40-pin, 6 mm × 6 mm

QFN, and a 64-pin, 7 mm × 7 mm BGA.

APPLICATIONS

• Wireless pointing devices: mice, trackballs,

gestural controls

•Wireless keyboards

• 3D glasses

•Remote controls

• Game controllers

• Point-of-sale (POS) input devices

•Remote sensors

• Home automation

• Personal health and fitness monitoring

• On-chip support for common keyboard and

mouse interfaces eliminates external processor

• Programmable keyscan matrix interface, up to

8 × 20 key-scanning matrix

• 3-axis quadrature signal decoder

• Shutter control for 3D glasses

• Infrared modulator

• IR learning

• Triac control

• Triggered Broadcom Fast Connect

• Supports Adaptive Frequency Hopping

• Excellent receiver sensitivity

• Bluetooth specification 3.0 compatible, including

enhanced power control (Unicast Connectionless

Data)

• Bluetooth HID profile version 1.0 compliant

• Bluetooth Device ID profile version 1.3 compliant

• Bluetooth AVRCP-CT profile version 1.3

compliant

• 10-bit auxiliary ADC with 28 analog channels

• On-chip support for serial peripheral interface

(master and slave modes)

• Broadcom Serial Communications (BSC) interface

(compatible with Philips® (now NXP) I2C slaves)

• Programmable output power control meets

Class 2 or Class 3 requirements

• Class 1 operation supported with external PA and

T/R switch

• Integrated ARM Cortex™-M3 based

microprocessor core

• On-chip power-on reset (POR)

• Support for EEPROM and serial flash interfaces

• Integrated low-dropout regulator (LDO)

• On-chip software controlled power management

unit

• Three package types are available:

– 32-pin QFN package (5 mm × 5 mm)

– 40-pin QFN package (6 mm × 6 mm)

– 64-pin BGA package (7 mm × 7 mm)

• RoHS compliant

Revision HistoryBCM20730 Data Sheet

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September 9, 2013 • 20730-DS108-R Page 2

BROADCOM CONFIDENTIAL

Figure 1: Functional Block Diagram

Keyboard

Matrix

Scanner

w/FIFO

3-Axis

Mouse

Signal

Controller

Processing

Unit

(ARM -CM3)

System Bus

Bluetooth

Baseband

Core

2.4 GHz

Radio

RF Control

and Data

T/R

Switch

RF I/O

GPIO

Control/

Status

Registers

Frequency

Synthesizer

14 GPIO on the 32-pin QFN

24 MHz Ref. Xtal

PMU

I/O Ring Bus

I/O Ring

Control

Registers

Peripheral

Interface

Block

1.2V VDD_CORE

Domain

VDD_IO

Domain

WAKE

1.2V

LDO 1.425V to 3.6V

1.2V

VDD_CORE

320K

ROM 60K

RAM

BSC/SPI

Master

Interface

(BSC is I

C-

compaƟble)

SDA/

MOSI

SCL/

SCK

6 Quadrature

Inputs (3 pair) +

High Current

Driver Controls

8 x 20

Scan

Matrix

40 GPIO

32 kHz

LPCLK

28 ADC

Inputs

MHz

hclk

(24 MHz to 1 MHz)

AutoCal

MISO

1.2V VDD_RF

Domain PWM

WDT

128 kHz

LPO

÷4

32 kHz

LPCLK

128 kHz

LPCLK

32 kHzyƚĂů;ŽƉƟŽŶĂůͿ

Power

1.62V to 3.6V

VDD_IO

1.2V

POR

1.2V

Test

UART

I/O

Mod.

and

Learning

SPI

M/S

MIA

POR

28 ADC

Inputs

CT ɇѐ

ADC

VSS,

VDDO,

VDDC

Periph

UART

UART_RXD

UART_TXD Tx

RTS_N

CTS_N

Muxed on GPIO

Volt. Trans

3-D Glasses

and Triac

1.62V to 3.6V

Revision HistoryBCM20730 Data Sheet

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Revision History

Revision Date Change Description

20730-DS108-R 09/09/13 Revised:

•Section : “Shutter Control for 3D Glasses,” on page 13

•Table 27: “Ordering Information,” on page 58

Added:

•Table 15: “ESD Tolerance,” on page 45

20730-DS107-R 10/10/12 Revised:

• “SPI Timing” on page 49

20730-DS106-R 09/20/11 Changed from a Preliminary Data Sheet to a Data Sheet.

20730-DS105-R 06/29/11 Added:

• Figure 9: “32-Pin QFN Ball Map,” on page 39

• Figure 16: “32-Pin QFN Package,” on page 52

• Table 20: “BCM20730 5 × 5 × 1 mm QFN, 32-Pin Tape Reel

Specifications,” on page 55

Revised:

• General Description and Features on Cover

• Figure 1: “Functional Block Diagram,” on page 2

•“ADC Port” on page 17

• Table 2: “BCM20730 First SPI Set (Master Mode),” on page 18

• Figure 5: “External Reset Timing,” on page 22

•“GPIO Port” on page 27

• “BBC Power Management” on page 29

• Table 7: “Pin Descriptions,” on page 30

• Table 8: “GPIO Pin Descriptions,” on page 32

• Table 12: “ADC Specifications,” on page 44

20730-DS104-R 05/09/2011 Revised:

• Figure 1: “Functional Block Diagram,” on page 2

•“ADC Port” on page 17

• Table 10: “Power Supply,” on page 39

20730-DS103-R 04/06/11 Revised:

• Table 14: “Current Consumption,” on page 42

• Table 23: “Ordering Information,” on page 54

Revision HistoryBCM20730 Data Sheet

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20730-DS102-R 03/23/11 Added:

• Table 1: “ADC Modes,” on page 18

Revised:

• Figure 1: “Functional Block Diagram,” on page 2

•“ADC Port” on page 17

• “Internal LDO Regulator” on page 22

•“UART Interface” on page 23

• Table 6: “XTAL Oscillator Characteristics,” on page 25

• Table 8: “GPIO Pin Descriptions,” on page 30

• Table 10: “Power Supply,” on page 39

• Table 11: “LDO Regulator Electrical Specifications,” on page 40

• Table 12: “ADC Specifications,” on page 41

• Table 14: “Current Consumption,” on page 42

• Table 15: “Receiver RF Specifications,” on page 43

• Table 16: “Transmitter RF Specifications,” on page 44

• Table 18: “SPI Interface Timing Specifications,” on page 46

• Table 21: “BCM20730 6 × 6 × 1 mm QFN, 40-Pin Tape Reel

Specifications,” on page 52

• Table 22: “BCM20730 7 × 7 × .8 mm WFBGA, 64-Pin Tape Reel

Specifications,” on page 52

Deleted:

• Placeholder for Figure 4: Triac Control

• Placeholder for Figure 18: BCM20730, 6 x 6 QFN Package Tray

• Placeholder for Figure 19: BCM20730, 7 x 7 FBGA Package Tray

Revision Date Change Description

Broadcom®, the pulse logo, Connecting everything®, and the Connecting everything logo are among the

registered trademarks of Broadcom Corporation and/or its subsidiaries in the United States, certain other

countries, and/or the EU. Bluetooth® is a trademark of the Bluetooth SIG. Any other trademarks or trade

names mentioned are the property of their respective owners.

Confidential and Proprietary Information: This document and the software are proprietary properties of

Broadcom Corporation. This software package may only be used in accordance with the Broadcom Corporation

license agreement.

This data sheet (including, without limitation, the Broadcom component(s) identified herein) is not designed,

intended, or certified for use in any military, nuclear, medical, mass transportation, aviation, navigations,

pollution control, hazardous substances management, or other high risk application. BROADCOM PROVIDES

THIS DATA SHEET "AS-IS", WITHOUT WARRANTY OF ANY KIND. BROADCOM DISCLAIMS ALL WARRANTIES,

EXPRESSED AND IMPLIED, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF

MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT.

Broadcom Corporation

5300 California Avenue

Irvine, CA 92617

Printed in the U.S.A.

20730-DS101-R 6/25/10 Added:

• “Shutter Control for 3D Glasses” on page 10.

• “Infrared Modulator” on page 10.

• “Infrared Learning” on page 11.

• “Triac Control” on page 12.

• “Broadcom Proprietary Control Signalling and Triggered Baseband

Fast Connect” on page 12.

• Figure 5: “Internal Reset Timing,” on page 17.

• Figure 6: “External Reset Timing,” on page 17.

• Figure 10: “40-pin QFN Ball Map,” on page 33.

• Figure 11: “64-pin BGA Ball Map,” on page 34.

• “SPI Timing” on page 41.

• Figure 16: “40-pin QFN,” on page 44.

• Figure 17: “64-pin FBGA,” on page 45.

Revised:

• “Microprocessor Unit” on page 16.

• Table 6: “Pin Descriptions,” on page 25.

• Table 11: “ADC Specifications,” on page 36.

• Table 14: “Receiver RF Specifications,” on page 38.

• Table 15: “Transmitter RF Specifications,” on page 39.

• Table 21: “Ordering Information,” on page 50.

20730-DS100-RI 4/27/10 Initial release.

Revision Date Change Description

Table of Contents BCM20730 Data Sheet

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September 9, 2013 • 20730-DS108-R Page 6

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Table of Contents

About This Document...................................................................................................................................11

Purpose and Audience ...........................................................................................................................11

Acronyms and Abbreviations.................................................................................................................11

References .............................................................................................................................................11

Technical Support.........................................................................................................................................11

Section 1: Functional Description .................................................................................... 12

Keyboard Scanner.........................................................................................................................................12

Theory of Operation ..............................................................................................................................12

Idle ..................................................................................................................................................12

Scan ................................................................................................................................................12

Scan End .........................................................................................................................................13

Mouse Quadrature Signal Decoder..............................................................................................................13

Theory of Operation ..............................................................................................................................13

Shutter Control for 3D Glasses.....................................................................................................................13

Infrared Modulator ......................................................................................................................................14

Infrared Learning ..........................................................................................................................................15

Triac Control .................................................................................................................................................15

Broadcom Proprietary Control Signaling and Triggered Broadcom Fast Connect .....................................15

Bluetooth Baseband Core ............................................................................................................................16

Frequency Hopping Generator ..............................................................................................................16

E0 Encryption .........................................................................................................................................16

Link Control Layer ..................................................................................................................................16

Adaptive Frequency Hopping.................................................................................................................17

Bluetooth Version 3.0 Features .............................................................................................................17

Test Mode Support ................................................................................................................................17

ADC Port .......................................................................................................................................................17

Serial Peripheral Interface ...........................................................................................................................18

Microprocessor Unit.....................................................................................................................................21

EEPROM Interface..................................................................................................................................21

Serial Flash Interface..............................................................................................................................21

Internal Reset.........................................................................................................................................22

External Reset ........................................................................................................................................22

Integrated Radio Transceiver.......................................................................................................................23

Transmitter Path ....................................................................................................................................23

Table of Contents BCM20730 Data Sheet

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September 9, 2013 • 20730-DS108-R Page 7

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Digital Modulator............................................................................................................................23

Power Amplifier..............................................................................................................................23

Receiver Path .........................................................................................................................................23

Digital Demodulator and Bit Synchronizer .....................................................................................23

Receiver Signal Strength Indicator..................................................................................................23

Local Oscillator.......................................................................................................................................24

Calibration..............................................................................................................................................24

Internal LDO Regulator ..........................................................................................................................24

Peripheral Transport Unit ............................................................................................................................24

Broadcom Serial Communications Interface .........................................................................................24

UART Interface.......................................................................................................................................25

Clock Frequencies .........................................................................................................................................25

Crystal Oscillator ....................................................................................................................................25

HID Peripheral Block .......................................................................................................................26

32 kHz Crystal Oscillator .................................................................................................................26

GPIO Port ......................................................................................................................................................27

Port 0–Port 1, Port 8–Port 23, and Port 28–Port 38..............................................................................27

Port 26–Port 29......................................................................................................................................27

PWM .............................................................................................................................................................27

Power Management Unit.............................................................................................................................28

RF Power Management .........................................................................................................................28

Host Controller Power Management.....................................................................................................29

BBC Power Management.......................................................................................................................29

Section 2: Pin Assignments.............................................................................................. 30

Pin Descriptions............................................................................................................................................30

Ball Maps ......................................................................................................................................................39

Section 3: Specifications.................................................................................................. 42

Electrical Characteristics ..............................................................................................................................42

RF Specifications...........................................................................................................................................46

Timing and AC Characteristics......................................................................................................................48

UART Timing ..........................................................................................................................................48

SPI Timing...............................................................................................................................................49

BSC Interface Timing..............................................................................................................................51

Section 4: Mechanical Information.................................................................................. 53

Tape Reel and Packaging Specifications ................................................................................................56

Table of Contents BCM20730 Data Sheet

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September 9, 2013 • 20730-DS108-R Page 8

BROADCOM CONFIDENTIAL

Section 5: Ordering Information...................................................................................... 58

Appendix A: Acronyms and Abbreviations....................................................................... 59

List of Figures BCM20730 Data Sheet

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September 9, 2013 • 20730-DS108-R Page 9

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List of Figures

Figure 1: Functional Block Diagram....................................................................................................................2

Figure 2: Infrared TX.........................................................................................................................................14

Figure 3: Infrared RX.........................................................................................................................................15

Figure 4: Internal Reset Timing ........................................................................................................................22

Figure 5: External Reset Timing........................................................................................................................22

Figure 6: Recommended Oscillator Configuration — 12 pF Load Crystal..........................................................25

Figure 7: 32 kHz Oscillator Block Diagram........................................................................................................26

Figure 8: PWM Channel Block Diagram............................................................................................................28

Figure 9: 32-Pin QFN Ball Map .........................................................................................................................39

Figure 10: 40-pin QFN Ball Map .......................................................................................................................40

Figure 11: 64-pin BGA Ball Map .......................................................................................................................41

Figure 12: UART Timing ....................................................................................................................................48

Figure 13: SPI Timing Diagram..........................................................................................................................49

Figure 14: BSC Interface Timing Diagram.........................................................................................................52

Figure 15: 32-Pin QFN Package ........................................................................................................................53

Figure 16: 40-pin QFN Package ........................................................................................................................54

Figure 17: 64-pin FBGA Package.......................................................................................................................55

Figure 18: Pin 1 Orientation .............................................................................................................................57

List of Tables BCM20730 Data Sheet

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September 9, 2013 • 20730-DS108-R Page 10

BROADCOM CONFIDENTIAL

List of Tables

Table 1: ADC Modes .........................................................................................................................................18

Table 2: BCM20730 First SPI Set (Master Mode) .............................................................................................18

Table 3: BCM20730 Second SPI Set (Master Mode).........................................................................................18

Table 4: BCM20730 Second SPI Set (Slave Mode)............................................................................................19

Table 5: Reference Crystal Electrical Specifications .........................................................................................26

Table 6: XTAL Oscillator Characteristics ...........................................................................................................27

Table 7: Pin Descriptions ..................................................................................................................................30

Table 8: GPIO Pin Descriptions.........................................................................................................................32

Table 9: Maximum Electrical Rating .................................................................................................................42

Table 10: Power Supply ....................................................................................................................................42

Table 11: LDO Regulator Electrical Specifications ............................................................................................43

Table 12: ADC Specifications ............................................................................................................................44

Table 13: Digital Level ......................................................................................................................................44

Table 14: Current Consumption ......................................................................................................................45

Table 15: ESD Tolerance ...................................................................................................................................45

Table 16: Receiver RF Specifications ................................................................................................................46

Table 17: Transmitter RF Specifications ...........................................................................................................47

Table 18: UART Timing Specifications ..............................................................................................................48

Table 19: SPI1 Timing Values — SCLK = 12 MHz and VDDM = 3.2V ..................................................................49

Table 20: SPI1 Timing Values — SCLK = 6 MHz and VDDM = 1.62V ..................................................................50

Table 21: SPI2 Timing Values — SCLK = 12 MHz and VDDM = 3.2V ..................................................................50

Table 22: SPI2 Timing Values — SCLK = 6 MHz and VDDM = 1.62V ..................................................................51

Table 23: BSC Interface Timing Specifications..................................................................................................51

Table 24: BCM20730 5 × 5 × 1 mm QFN, 32-Pin Tape Reel Specifications.......................................................56

Table 25: BCM20730 6 × 6 × 1 mm QFN, 40-Pin Tape Reel Specifications.......................................................56

Table 26: BCM20730 7 × 7 × 0.8 mm WFBGA, 64-Pin Tape Reel Specifications ..............................................56

Table 27: Ordering Information .......................................................................................................................58

About This Document

BROADCOM

September 9, 2013 • 20730-DS108-R Page 11

BCM20730 Data Sheet

BROADCOM CONFIDENTIAL

About This Document

Purpose and Audience

This data sheet provides a description of the major blocks, interfaces, pin assignments, and specifications of

the BCM20730 single-chip Bluetooth transceiver. This is a required document for designers responsible for

adding the BCM20730 Bluetooth transceiver to wireless input device applications including game controllers,

keyboards, 3D glasses, remote controls, gestural input devices, and sensor devices.

Acronyms and Abbreviations

In most cases, acronyms and abbreviations are defined on first use. Acronyms and abbreviations in this

document are also defined in Appendix A: “Acronyms and Abbreviations,” on page 59.

For a comprehensive list of acronyms and other terms used in Broadcom documents, go to:

http://www.broadcom.com/press/glossary.php.

References

The references in this section may be used in conjunction with this document.

For Broadcom documents, replace the “x” in the document number with the largest number available in the

repository to ensure that you have the most current version of the document.

Technical Support

Broadcom provides customer access to a wide range of information, including technical documentation,

schematic diagrams, product bill of materials, PCB layout information, and software updates through its

customer support portal (https://support.broadcom.com). For a CSP account, contact your Sales or Engineering

support representative.

In addition, Broadcom provides other product support through its Downloads & Support site

(http://www.broadcom.com/support/).

Note: Broadcom provides customer access to technical documentation and software through its

Customer Support Portal (CSP) and Downloads & Support site (see Technical Support).

Document Name Number

Broadcom Items

[1] Single-Chip Bluetooth® Transceiver and Baseband Processor 20702-DS10x-R

Functional Description

BROADCOM

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BCM20730 Data Sheet

BROADCOM CONFIDENTIAL

Section 1: Functional Description

Keyboard Scanner

The keyboard scanner is designed to autonomously sample keys and store them into buffer registers without

the need for the host microcontroller to intervene. The scanner has the following features:

• Ability to turn off its clock if no keys pressed.

• Sequential scanning of up to 160 keys in an 8 x 20 matrix.

• Programmable number of columns from 1 to 20.

• Programmable number of rows from 1 to 8.

• 16-byte key-code buffer (can be augmented by firmware).

• 128 kHz clock – allows scanning of full 160-key matrix in about 1.2 ms.

• N-key rollover with selective 2-key lockout if ghost is detected.

• Keys are buffered until host microcontroller has a chance to read it, or until overflow occurs.

• Hardware debouncing and noise/glitch filtering.

• Low-power consumption. Single-digit µA-level sleep current.

Theory of Operation

The key scan block is controlled by a state machine with the following states:

Idle

The state machine begins in the idle state. In this state, all column outputs are driven high. If any key is pressed,

a transition occurs on one of the row inputs. This transition causes the 128 kHz clock to be enabled (if it is not

already enabled by another peripheral) and the state machine to enter the scan state. Also in this state, an 8-

bit row-hit register and an 8-bit key-index counter is reset to 0.

Scan

In the scan state, a row counter counts from 0 up to a programmable number of rows minus 1. Once the last

row is reached, the row counter is reset and the column counter is incremented. This cycle repeats until the

row and column counters are both at their respective terminal count values. At that point, the state machine

moves into the Scan-End state.

As the keys are being scanned, the key-index counter is incremented. This counter is the value compared to the

modifier key codes stored, or in the key-code buffer if the key is not a modifier key. It can be used by the

microprocessor as an index into a lookup table of usage codes.

Mouse Quadrature Signal Decoder

BROADCOM

September 9, 2013 • 20730-DS108-R Page 13

BCM20730 Data Sheet

BROADCOM CONFIDENTIAL

Also, as the n-th row is scanned, the row-hit register is ORed with the current 8-bit row input values if the

current column contains two or more row hits. During the scan of any column, if a key is detected at the current

row, and the row-hit register indicates that a hit was detected in that same row on a previous column, then a

ghost condition may have occurred, and a bit in the status register is set to indicate this.

Scan End

This state determines whether any keys were detected while in the scan state. If yes, the state machine returns

to the scan state. If no, the state machine returns to the idle state, and the 128 kHz clock request signal is made

inactive.

The microcontroller can poll the key status register.

Mouse Quadrature Signal Decoder

The mouse signal decoder is designed to autonomously sample two quadrature signals commonly generated

by optomechanical mouse apparatus. The decoder has the following features:

• Three pairs of inputs for X, Y, and Z (typical scroll wheel) axis signals. Each axis has two options:

– For the X axis, choose P2 or P32 as X0 and P3 or P33 as X1.

– For the Y axis, choose P4 or P34 as Y0 and P5 or P35 as Y1.

– For the Z axis, choose P6 or P36 as Z0 and P7 or P37 as Z1.

• Control of up to four external high current GPIOs to power external optoelectronics:

– Turn-on and turn-off time can be staggered for each HC-GPIO to avoid simultaneous switching of high

currents and having multiple high-current devices on at the same time.

– Sample time can be staggered for each axis.

– Sense of the control signal can be active high or active low.

– Control signal can be tristated for off condition or driven high or low, as appropriate.

Theory of Operation

The mouse decoder block has four 16-bit PWMs for controlling external quadrature devices and sampling the

quadrature inputs at its core.

The GPIO signals may be used to control such items as LEDs, external ICs that may emulate quadrature signals,

photodiodes, and photodetectors.

Shutter Control for 3D Glasses

The BCM20730, combined with the BCM20702, provides full system support for 3D glasses on televisions. The

BCM20702 gets frame synchronization signals from the TV, converts them into proprietary timing control

messages, then passes these messages to the BCM20730. The BCM20730 uses these messages to synchronize

the shutter control for the 3D glasses with the television frames.

Infrared Modulator

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The BCM20730 can provide up to four synchronized control signals for left and right eye shutter control. These

four lines can output pulses with microsecond resolution for on and off timing. The total cycle time can be set

for any period up to 65535 msec. The pulses are synchronized to each other for left and right eye shutters.

The BCM20730 seamlessly adjusts the timing of the control signals based on control messages from the

BCM20702, ensuring that the 3D glasses remain synchronized to the TV display frame.

3D hardware control on the BCM20730 works independently of the rest of the system. The BCM20730

negotiates sniff with the BCM20702 and, except for sniff resynchronization periods, most of the BCM20730

circuitry remains in a low power state while the 3D glasses subsystem continues to provide shutter timing and

control pulses. This significantly reduces total system power consumption.

The BCM20730A2 has the new BT SIG 3DG profile, as well as legacy mode 3DG, included in ROM. This allows it

to support a smaller and lower cost external memory of 4 KB.

Infrared Modulator

The BCM20730 includes hardware support for infrared TX. The hardware can transmit both modulated and

unmodulated waveforms. For modulated waveforms, hardware inserts the desired carrier frequency into all IR

transmissions. IR TX can be sourced from firmware-supplied descriptors, a programmable bit, or the peripheral

UART transmitter.

If descriptors are used, they include IR on/off state and the duration between 1–32767 µsec. The BCM20730

IR TX firmware driver inserts this information in a hardware FIFO and makes sure that all descriptors are played

out without a glitch due to underrun. See Figure 2.

Figure 2: Infrared TX

Infrared Learning

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Infrared Learning

The BCM20730 includes hardware support for infrared learning. The hardware can detect both modulated and

unmodulated signals. For modulated signals, the BCM20730 can detect carrier frequencies between 10 kHz

and 500 kHz and the duration that the signal is present or absent. The BCM20730 firmware driver supports

further analysis and compression of learned signal. The learned signal can then be played back through the

BCM20730 IR TX subsystem. See Figure 3.

Figure 3: Infrared RX

Triac Control

The BCM20730 includes hardware support for zero-crossing detection and trigger control for up to four triacs.

The BCM20730 detects zero-crossing on the AC zero detection line and uses that to provide a pulse that is

offset from the zero-crossing. This allows the BCM20730 to be used in dimmer applications, as well as any other

applications that require a control signal that is offset from an input event.

Broadcom Proprietary Control Signaling and Triggered

Broadcom Fast Connect

Broadcom Proprietary Control Signaling (BPCS) and Triggered Broadcom Fast Connect (TBFC) are Broadcom-

proprietary baseband (ACL) suspension and low latency reconnection mechanisms that reestablish the

baseband connection with the peer controller that also supports BPCS/TBFC.

The BCM20730 uses BPCS primitives to allow a Human Interface Device (HID) to suspend all RF traffic after a

configurable idle period with no reportable activity. To conserve power, it can then enter one of its low power

states while still logically remaining connected at the L2CAP and HID layers with the peer device. When an

event requires the HID to deliver a report to the peer device, the BCM20730 uses the TBFC and BPCS

mechanisms to reestablish the baseband connection and can immediately resume L2CAP traffic, greatly

reducing latency between the event and delivery of the report to the peer device.

Bluetooth Baseband Core

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BCM20730 Data Sheet

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Certain applications may make use of the BCM20730 Baseband Fast Connect (BFC) mechanism for power

savings and lower latencies not achievable by using even long sniff intervals by completely eliminating the need

to maintain an RF link, while still being able to establish ACL and L2CAP connections much faster than regular

methods.

Bluetooth Baseband Core

The Bluetooth Baseband Core (BBC) implements all of the time-critical functions required for high performance

Bluetooth operation. The BBC manages the buffering, segmentation, and data routing for all connections. It

also buffers data that passes through it, handles data flow control, schedules ACL TX/RX transactions, monitors

Bluetooth slot usage, optimally segments and packages data into baseband packets, manages connection

status indicators, and composes and decodes HCI packets. In addition to these functions, it independently

handles HCI event types and HCI command types.

The following transmit and receive functions are also implemented in the BBC hardware to increase TX/RX data

reliability and security before sending over the air:

• Receive Functions: symbol timing recovery, data deframing, forward error correction (FEC), header error

control (HEC), cyclic redundancy check (CRC), data decryption, and data dewhitening.

• Transmit Functions: data framing, FEC generation, HEC generation, CRC generation, link key generation,

data encryption, and data whitening.

Frequency Hopping Generator

The frequency hopping sequence generator selects the correct hopping channel number depending on the link

controller state, Bluetooth clock, and device address.

E0 Encryption

The encryption key and the encryption engine are implemented using dedicated hardware to reduce software

complexity and provide minimal processor intervention.

Link Control Layer

The link control layer is part of the Bluetooth link control functions that are implemented in dedicated logic in

the Link Control Unit (LCU). This layer consists of the Command Controller, which takes software commands,

and other controllers that are activated or configured by the Command Controller to perform the link control

tasks. Each task performs a different Bluetooth link controller state. STANDBY and CONNECTION are the two

major states. In addition, there are five substates: page, page scan, inquiry, inquiry scan, and sniff.

ADC Port

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BCM20730 Data Sheet

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Adaptive Frequency Hopping

The BCM20730 gathers link quality statistics on a channel-by-channel basis to facilitate channel assessment

and channel map selection. The link quality is determined by using both RF and baseband signal processing to

provide a more accurate frequency hop map.

Bluetooth Version 3.0 Features

The BCM20730 supports Bluetooth 3.0, including the following options:

•Enhanced Power Control

• Unicast Connectionless Data

• HCI Read Encryption Key Size command

The BCM20730 also supports the following Bluetooth version 2.1 features:

• Extended Inquiry Response

• Sniff Subrating

• Encryption Pause and Resume

• Secure Simple Pairing

• Link Supervision Timeout Changed Event

• Erroneous Data Reporting

• Non-Automatically-Flushable Packet Boundary Flag

• Security Mode 4

Test Mode Support

The BCM20730 fully supports Bluetooth Test mode, as described in Part 1 of the Bluetooth 3.0 specification.

This includes the transmitter tests, normal and delayed loopback tests, and the reduced hopping sequence.

In addition to the standard Bluetooth Test mode, the device supports enhanced testing features to simplify RF

debugging and qualification as well as type-approval testing.

ADC Port

The BCM20730 contains a 16-bit ADC (effective number of bits is 10).

Additionally:

• There are 28 analog input channels in the 64-pin package, 12 analog input channels in the 40-pin package,

and 9 analog input channels in the 32-pin package. All channels are multiplexed on various GPIOs.

• The conversion time is 10 μs.

• There is a built-in reference with supply- or band-gap based reference modes.

• The maximum conversion rate is 187 kHz.

• There is a rail-to-rail input swing.

Serial Peripheral Interface

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BCM20730 Data Sheet

BROADCOM CONFIDENTIAL

The ADC consists of an analog ADC core that performs the actual analog-to-digital conversion and digital

hardware that processes the output of the ADC core into valid ADC output samples. Directed by the firmware,

the digital hardware also controls the input multiplexers that select the ADC input signal Vinp and the ADC

reference signals Vref.

Serial Peripheral Interface

The BCM20730 has two independent SPI interfaces. One is a master-only interface and the other can be either

a master or a slave. Each interface has a 16-byte transmit buffer and a 16-byte receive buffer. To support more

flexibility for user applications, the BCM20730 has optional I/O ports that can be configured individually and

separately for each functional pin, as shown in Table 2. The BCM20730 acts as an SPI master device that

supports 1.8V or 3.3V SPI slaves, as shown in Table 2. The BCM20730 can also act as an SPI slave device that

supports a 1.8V or 3.3V SPI master, as shown in Table 2.

Table 1: ADC Modes

Mode ENOB (Typical) Maximum Sampling Rate (kHz) Latencya (

a. Settling time after switching channels.

0 13 5.859 171

1 12.6 11.7 85

212 46.875 21

3 11.5 93.75 11

410 187 5

Table 2: BCM20730 First SPI Set (Master Mode)

Pin Name SPI_CLK SPI_MOSI SPI_MISO SPI_CSa

a. Any GPIO can be used as SPI_CS when SPI is in master mode.

Configuration set 1 SCL SDA P24 –

Configuration set 2 SCL SDA P26 –

Configuration set 3

(Default for serial flash)

SCL SDA P32 P33

Configuration set 4 SCL SDA P39 –

Table 3: BCM20730 Second SPI Set (Master Mode)

Pin Name SPI_CLK SPI_MOSI SPI_MISO SPI_CSa

Configuration set 1 P3 P0 P1 –

Configuration set 2 P3 P0 P5 –

Configuration set 3 P3 P2 P1 –

Configuration set 4 P3 P2 P5 –

Serial Peripheral Interface

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Configuration set 5 P3 P4 P1 –

Configuration set 6 P3 P4 P5 –

Configuration set 7 P3 P27 P1 –

Configuration set 8 P3 P27 P5 –

Configuration set 9 P3 P38 P1 –

Configuration set 10 P3 P38 P5 –

Configuration set 11 P7 P0 P1 –

Configuration set 12 P7 P0 P5 –

Configuration set 13 P7 P2 P1 –

Configuration set 14 P7 P2 P5 –

Configuration set 15 P7 P4 P1 –

Configuration set 16 P7 P4 P5 –

Configuration set 17 P7 P27 P1 –

Configuration set 18 P7 P27 P5 –

Configuration set 19 P7 P38 P1 –

Configuration set 20 P7 P38 P5 –

Configuration set 21 P24 P0 P25 –

Configuration set 22 P24 P2 P25 –

Configuration set 23 P24 P4 P25 –

Configuration set 24 P24 P27 P25 –

Configuration set 25 P24 P38 P25 –

Configuration set 26 P36 P0 P25 –

Configuration set 27 P36 P2 P25 –

Configuration set 28 P36 P4 P25 –

Configuration set 29 P36 P27 P25 –

Configuration set 30 P36 P38 P25 –

a. Any GPIO can be used as SPI_CS when SPI is in master mode.

Table 4: BCM20730 Second SPI Set (Slave Mode)a

Pin Name SPI_CLK SPI_MOSI SPI_MISO SPI_CS

Configuration set 1 P3 P0 P1 P2

Configuration set 2 P3 P0 P5 P2

Configuration set 3 P3 P4 P1 P2

Configuration set 4 P3 P4 P5 P2

Configuration set 5 P7 P0 P1 P2

Table 3: BCM20730 Second SPI Set (Master Mode) (Cont.)

Pin Name SPI_CLK SPI_MOSI SPI_MISO SPI_CSa

Serial Peripheral Interface

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BROADCOM CONFIDENTIAL

Configuration set 6 P7 P0 P5 P2

Configuration set 7 P7 P4 P1 P2

Configuration set 8 P7 P4 P5 P2

Configuration set 9 P3 P0 P1 P6

Configuration set 10 P3 P0 P5 P6

Configuration set 11 P3 P4 P1 P6

Configuration set 12 P3 P4 P5 P6

Configuration set 13 P7 P0 P1 P6

Configuration set 14 P7 P0 P5 P6

Configuration set 15 P7 P4 P1 P6

Configuration set 16 P7 P4 P5 P6

Configuration set 17 P24 P27 P25 P26

Configuration set 18 P24 P33 P25 P26

Configuration set 19 P24 P38 P25 P26

Configuration set 20 P36 P27 P25 P26

Configuration set 21 P36 P33 P25 P26

Configuration set 22 P36 P38 P25 P26

Configuration set 23 P24 P27 P25 P32

Configuration set 24 P24 P33 P25 P32

Configuration set 25 P24 P38 P25 P32

Configuration set 26 P36 P27 P25 P32

Configuration set 27 P36 P33 P25 P32

Configuration set 28 P36 P38 P25 P32

Configuration set 29 P24 P27 P25 P39

Configuration set 30 P24 P33 P25 P39

Configuration set 31 P24 P38 P25 P39

Configuration set 32 P36 P27 P25 P39

Configuration set 33 P36 P33 P25 P39

Configuration set 34 P36 P38 P25 P39

a. Additional configuration sets are available upon request.

Table 4: BCM20730 Second SPI Set (Slave Mode)a

Pin Name SPI_CLK SPI_MOSI SPI_MISO SPI_CS

Microprocessor Unit

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Microprocessor Unit

The BCM20730 microprocessor unit (µPU) executes software from the link control (LC) layer up to the

application layer components that ensure adherence to the Bluetooth Human Interface Device (HID) profile

and Audio/Video Remote Control Profile (AVRCP). The microprocessor is based on an ARM Cortex™-M3, 32-bit

RISC processor with embedded ICE-RT debug and JTAG interface units. The µPU has 320 KB of ROM for program

storage and boot-up, 60 KB of RAM for scratch-pad data, and patch RAM code.

The internal boot ROM provides power-on reset flexibility, which enables the same device to be used in

different HID applications with an external serial EEPROM or with an external serial flash memory. At power-

up, the lowest layer of the protocol stack is executed from the internal ROM memory.

External patches may be applied to the ROM-based firmware to provide flexibility for bug fixes and feature

additions. The device can also support the integration of user applications.

EEPROM Interface

The BCM20730 provides a Broadcom Serial Control (BSC) master interface. The BSC is programmed by the CPU

to generate four types of BSC bus transfers: read-only, write-only, combined read/write, and combined write/

read. BSC supports both low-speed and fast mode devices. The BSC is compatible with a Philips® (now NXP) I2C

slave device, except that master arbitration (multiple I2C masters contending for the bus) is not supported.

The EEPROM can contain customer application configuration information including: application code,

configuration data, patches, pairing information, BD_ADDR, baud rate, SDP service record, and file system

information used for code.

Native support for the Microchip® 24LC128, Microchip 24AA128, and ST Micro® M24128-BR is included.

Serial Flash Interface

The BCM20730 includes an SPI master controller that can be used to access serial flash memory. The SPI master

contains an AHB slave interface, transmit and receive FIFOs, and the SPI core PHY logic.

Devices natively supported include the following:

• Atmel® AT25BCM512B

• MXIC® MX25V512ZUI-20G

Microprocessor Unit

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BCM20730 Data Sheet

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Internal Reset

Figure 4: Internal Reset Timing

External Reset

The BCM20730 has an integrated power-on reset circuit that completely resets all circuits to a known power-

on state. An external active low reset signal, RESET_N, can be used to put the BCM20730 in the reset state. The

RESET_N pin has an internal pull-up resistor and, in most applications, it does not require that anything be

connected to it. RESET_N should only be released after the VDDO supply voltage level has been stabilized.

Figure 5: External Reset Timing

VDDO

VDDO POR

VDDC

VDDO POR threshold

VDDO POR delay

~ 2 ms

VDDC POR

VDDC POR threshold

VDDC POR delay

~ 2 ms

Baseband Reset

Crystal

warm-up

delay:

~ 5 ms

Crystal Enable

Start reading EEPROM and

firmware boot

RESET_N

Pulse width

>50 µs

Crystal Enable

Baseband Reset

Start reading EEPROM and

firmware boot

Crystal

warm-up

delay:

~ 5 ms

Integrated Radio Transceiver

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BCM20730 Data Sheet

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Integrated Radio Transceiver

The BCM20730 has an integrated radio transceiver that is optimized for 2.4 GHz Bluetooth® wireless systems.

It has been designed to provide low power, low cost, and robust communications for applications operating in

the globally available 2.4 GHz unlicensed ISM band. It is fully compliant with Bluetooth Radio Specification 3.0

and meets or exceeds the requirements to provide the highest communication link quality of service.

Transmitter Path

The BCM20730 features a fully integrated transmitter. The baseband transmit data is GFSK modulated in the

2.4 GHz ISM band.

Digital Modulator

The digital modulator performs the data modulation and filtering required for the GFSK signal. The fully digital

modulator minimizes any frequency drift or anomalies in the modulation characteristics of the transmitted

signal.

Power Amplifier

The BCM20730 has an integrated power amplifier (PA) that can transmit up to +4 dBm for class 2 operation.

Receiver Path

The receiver path uses a low IF scheme to downconvert the received signal for demodulation in the digital

demodulator and bit synchronizer. The receiver path provides a high degree of linearity, an extended dynamic

range, and high-order, on-chip channel filtering to ensure reliable operation in the noisy 2.4 GHz ISM band. The

front-end topology, which has built-in out-of-band attenuation, enables the BCM20730 to be used in most

applications without off-chip filtering.

Digital Demodulator and Bit Synchronizer

The digital demodulator and bit synchronizer take the low-IF received signal and perform an optimal frequency

tracking and bit synchronization algorithm.

Receiver Signal Strength Indicator

The radio portion of the BCM20730 provides a receiver signal strength indicator (RSSI) to the baseband. This

enables the controller to take part in a Bluetooth power-controlled link by providing a metric of its own receiver

signal strength to determine whether the transmitter should increase or decrease its output power.

Peripheral Transport Unit

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BCM20730 Data Sheet

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Local Oscillator

The local oscillator (LO) provides fast frequency hopping (1600 hops/second) across the 79 maximum available

channels. The BCM20730 uses an internal loop filter.

Calibration

The BCM20730 radio transceiver features a self-contained automated calibration scheme. No user interaction

is required during normal operation or during manufacturing to provide optimal performance. Calibration

compensates for filter, matching network, and amplifier gain and phase characteristics to yield radio

performance within 2% of what is optimal. Calibration takes process and temperature variations into account,

and it takes place transparently during normal operation and hop setting times.

Internal LDO Regulator

The BCM20730 has an integrated 1.2V LDO regulator that provides power to the digital and RF circuits. The

1.2V LDO regulator operates from a 1.425V to 3.63V input supply with a 30 mA maximum load current.

Peripheral Transport Unit

Broadcom Serial Communications Interface

The BCM20730 provides a 2-pin master BSC interface, which can be used to retrieve configuration information

from an external EEPROM or to communicate with peripherals such as track-ball or touch-pad modules, and

motion tracking ICs used in mouse devices. The BSC interface is compatible with I2C slave devices. The BSC does

not support multimaster capability or flexible wait-state insertion by either master or slave devices.

The following transfer clock rates are supported by the BSC:

•100 kHz

•400 kHz

• 800 kHz (Not a standard I2C-compatible speed.)

• 1 MHz (Compatibility with high-speed I2C-compatible devices is not guaranteed.)

The following transfer types are supported by the BSC:

• Read (Up to 16 bytes can be read.)

• Write (Up to 16 bytes can be written.)

• Read-then-Write (Up to 16 bytes can be read and up to 16 bytes can be written.)

• Write-then-Read (Up to 16 bytes can be written and up to 16 bytes can be read.)

Hardware controls the transfers, requiring minimal firmware setup and supervision.

Note: Always place the decoupling capacitors near the pins as closely together as possible.

Clock Frequencies

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BCM20730 Data Sheet

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The clock pin (SCL) and data pin (SDA) are both open-drain I/O pins. Pull-up resistors external to the BCM20730

are required on both the SCL and SDA pins for proper operation.

UART Interface

The UART is a standard 2-wire interface (RX and TX) and has adjustable baud rates from 9600 bps to 1.5 Mbps.

The baud rate can be selected via a vendor-specific UART HCI command. The interface supports the Bluetooth

3.0 UART HCI (H5) specification. The default baud rate for H5 is 115.2 kbaud.

Both high and low baud rates can be supported by running the UART clock at 24 MHz.

The BCM20730 UART operates correctly with the host UART as long as the combined baud rate error of the two

devices is within ±5%.

Clock Frequencies

The BCM20730 is set with crystal frequency of 24 MHz.

Crystal Oscillator

The crystal oscillator requires a crystal with an accuracy of ±20 ppm as defined by the Bluetooth specification.

Two external load capacitors in the range of 5 pF to 30 pF are required to work with the crystal oscillator. The

selection of the load capacitors is crystal dependent. Table 5 on page 26 shows the recommended crystal

specification.

Figure 6: Recommended Oscillator Configuration — 12 pF Load Crystal

22 pF

20 pF

Crystal

XIN

XOUT

Clock Frequencies

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BCM20730 Data Sheet

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HID Peripheral Block

The peripheral blocks of the BCM20730 all run from a single 128 kHz low-power RC oscillator. The oscillator can

be turned on at the request of any of the peripherals. If the peripheral is not enabled, it shall not assert its clock

request line.

The keyboard scanner is a special case in that it may drop its clock request line even when enabled and then

reassert the clock request line if a keypress is detected.

32 kHz Crystal Oscillator

Figure 7 shows the 32 kHz crystal (XTAL) oscillator with external components and Table 6 on page 27 lists the

oscillator’s characteristics. It is a standard Pierce oscillator using a comparator with hysteresis on the output to

create a single-ended digital output. The hysteresis was added to eliminate any chatter when the input is

around the threshold of the comparator and is ~100 mV. This circuit can be operated with a 32 kHz or 32.768

kHz crystal oscillator or be driven with a clock input at similar frequency. The default component values are: R1

= 10 MΩ, C1 = C2 = ~10 pF. The values of C1 and C2 are used to fine-tune the oscillator.

Figure 7: 32 kHz Oscillator Block Diagram

Table 5: Reference Crystal Electrical Specifications

Parameter Conditions Minimum Typical Maximum Unit

Nominal frequency – – 24.000 – MHz

Oscillation mode – Fundamental –

Frequency tolerance @25°C – ±10 – ppm

Tolerance stability over temp @0°C to +70°C – ±10 – ppm

Equivalent series resistance – – – 50 W

Load capacitance – – 12 – pF

Operating temperature range – 0 – +70 °C

Storage temperature range – –40 – +125 °C

Drive level – – – 200 μW

Aging – ––±10ppm/year

Shunt capacitance – – – 2 pF

R1 32.768 kHz

XTAL

GPIO Port

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BCM20730 Data Sheet

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GPIO Port

The BCM20730 has 14 general-purpose I/Os (GPIOs) in the 32-pin package, 22 GPIOs in the 40-pin package, and

40 GPIOs in the 64-pin package. All GPIOs support programmable pull-up and pull-down resistors, and all

support a 2 mA drive strength except P26, P27, P28, and P29, which provide a 16 mA drive strength at 3.3V

supply.

Port 0–Port 1, Port 8–Port 23, and Port 28–Port 38

All of these pins can be programmed as ADC inputs.

Port 26–Port 29

P[26:29] consists of four pins. All pins are capable of sinking up to 16 mA for LED. These pins also have the PWM

function, which can be used for LED dimming.

PWM

The BCM20730 has four internal PWM channels. The PWM module consists of the following:

•PWM1–4

• Each of the four PWM channels, PWM1–4, contains the following registers:

– 10-bit initial value register (read/write)

– 10-bit toggle register (read/write)

– 10-bit PWM counter value register (read)

Table 6: XTAL Oscillator Characteristics

Parameter Symbol Conditions Minimum Typical Maximum Unit

Output

frequency

Foscout – – 32.768 – kHz

Frequency

tolerance

– Crystal dependent – 100 – ppm

Start-up time Tstartup –––500ms

XTAL drive level Pdrv For crystal

selection

0.5 – – μW

XTAL series

resistance

Rseries For crystal

selection

–– 70kΩ

XTAL shunt

capacitance

Cshunt For crystal

selection

–– 1.3pF

Power Management Unit

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BCM20730 Data Sheet

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• The PWM configuration register is shared among PWM1–4 (read/write). This 12-bit register is used:

– To configure each PWM channel.

– To select the clock of each PWM channel

– To change the phase of each PWM channel

Figure 8 shows the structure of one PWM channel.

Figure 8: PWM Channel Block Diagram

Power Management Unit

The Power Management Unit (PMU) provides power management features that can be invoked by software

through power management registers or packet-handling in the baseband core.

RF Power Management

The BBC generates power-down control signals for the transmit path, receive path, PLL, and power amplifier

to the 2.4 GHz transceiver, which then processes the power-down functions accordingly.

pwm_cfg_adr register pwm#_init_val_adr register pwm#_togg_val_adr register

pwm#_cntr_adr

enable

cntr value is CM3 readable

clk_sel

o_flip

10'H000

10'H3FF

10 10

Example: PWM cntr w/ pwm#_init_val = 0 (dashed line)

PWM cntr w/ pwm#_init_val = x (solid line)

10'Hx

pwm_out

pwm_togg_val_adr

pwm_out

Power Management Unit

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BCM20730 Data Sheet

BROADCOM CONFIDENTIAL

Host Controller Power Management

Power is automatically managed by the firmware based on input device activity. As a power-saving task, the

firmware controls the disabling of the on-chip regulator when in deep Sleep mode.

BBC Power Management

There are several low-power operations for the BBC:

• Physical layer packet handling turns RF on and off dynamically within packet TX and RX.

• Bluetooth-specified low-power connection sniff mode. While in these low-power connection modes, the

BCM20730 runs on the Low Power Oscillator and wakes up after a predefined time period.

The BCM20730 automatically adjusts its power dissipation based on user activity. The following power modes

are supported:

•Active mode

•Idle mode

•Sleep mode

• HIDOFF mode

The BCM20730 transitions to the next lower state after a programmable period of user inactivity. Busy mode

is immediately entered when user activity resumes.

In HIDOFF mode, the BCM20730 baseband and core are powered off by disabling power to LDOOUT. The VDDO

domain remains powered up and will turn the remainder of the chip on when it detects user events. This mode

minimizes chip power consumption and is intended for long periods of inactivity.

Pin Assignments

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BCM20730 Data Sheet

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Section 2: Pin Assignments

Pin Descriptions

Table 7: Pin Descriptions

Pin Number

Pin Name I/O

Power

Domain Description32-Pin QFN 40-pin QFN 64-pin BGA

Radio I/O

6 8 F1 RF I/O VDD_RF RF antenna port

RF Power Supplies

4 6 D1 VDDIF I VDD_RF IFPLL power supply

5 7 E1 VDDFE I VDD_RF RF front-end supply

7 9 H1 VDDVCO I VDD_RF VCO, LOGEN supply

8 10 H2 VDDPLL I VDD_RF RFPLL and crystal oscillator supply

Power Supplies

11 13 H6 VDDC I N/A Baseband core supply

––D4, E2, E5,

F2, G1, G2

VSS I N/A Ground

28 34 A6, D7 VDDO I VDDO I/O pad and core supply

14 16 – VDDM I VDDM I/O pad supply

Clock Generator and Crystal Interface

9 11 H3 XTALI I VDD_RF Crystal oscillator input. See “Crystal

Oscillator” on page 25 for options.

10 12 G3 XTALO O VDD_RF Crystal oscillator output.

1 40 A3 XTALI32K I VDDO Low-power oscillator (LPO) input is

used.

Alternative Function:

• P11 and P27 in 32-QFN only

• P11 in 40-QFN only

• P39 in 64-BGA only

32 39 B3 XTALO32K O VDDO Low-power oscillator (LPO) output.

Alternative Function:

• P12 and P26 in 32-QFN only

• P12 in 40-QFN only

• P38 in 64-BGA only

Pin Descriptions

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BCM20730 Data Sheet

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Core

18 20 G8 RESET_N I/O

VDDO Active-low system reset with open-

drain output & internal pull-up

resistor

17 19 G7 TMC I VDDO Test mode control

High: test mode

Connect to GND if not used.

UART

12 14 H5 UART_RXD I VDDMaUART serial input – Serial data input

for the HCI UART interface. Leave

unconnected if not used.

Alternative function:

•GPIO3

13 15 G5 UART_TXD O, PU VDDMaUART serial output – Serial data

output for the HCI UART interface.

Leave unconnected if not used.

Alternative Function:

•GPIO2

BSC

15 17 F7 SDA I/O,

VDDMaData signal for an external I2C device.

Alternative function:

• SPI_1: MOSI (master only)

•GPIO0

•CTS

16 18 E8 SCL I/O,

VDDMaClock signal for an external I2C

device.

Alternative function:

• SPI_1: SPI_CLK (master only)

•GPIO1

•RTS

LDO Regulator Power Supplies

2 4 B1 LDOIN I LDO Battery input supply for the LDO

3 5 C1 LDOOUT O LDO LDO output

a. VDDO for 64-pin package.

Table 7: Pin Descriptions (Cont.)

Pin Number

Pin Name I/O

Power

Domain Description32-Pin QFN 40-pin QFN 64-pin BGA

Pin Descriptions

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BCM20730 Data Sheet

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Table 8: GPIO Pin Descriptionsa

Pin Number

Pin Name

Default

Direction

After

POR

Power

Domain Alternate Function Description

32-Pin

QFN

40-pin

QFN

64-pin

BGA

19 21 F6 P0 Input Floating VDDO • GPIO: P0

• Keyboard scan input (row): KSI0

• A/D converter input

• Peripheral UART: puart_tx

• SPI_2: MOSI (master and slave)

• IR_RX

•60 Hz_main

• Not available during TMC=1

20 22 G6 P1 Input Floating VDDO • GPIO: P1

• Keyboard scan input (row): KSI1

• A/D converter input

• Peripheral UART: puart_rts

• SPI_2: MISO (master and slave)

•IR_TX

22 24 H8 P2 Input Floating VDDO • GPIO: P2

• Keyboard scan input (row): KSI2

• Quadrature: QDX0

• Peripheral UART: puart_rx

•Triac control 2

• SPI_2: SPI_CS (slave only)

• SPI_2: SPI_MOSI (master only)

21 23 F8 P3 Input Floating VDDO • GPIO: P3

• Keyboard scan input (row): KSI3

• Quadrature: QDX1

• Peripheral UART: puart_cts

• SPI_2: SPI_CLK (master and slave)

23 25 H7 P4 Input Floating VDDO • GPIO: P4

• Keyboard scan input (row): KSI4

• Quadrature: QDY0

• Peripheral UART: puart_rx

• SPI_2: MOSI (master and slave)

•IR_TX

– 26 E6 P5 Input Floating VDDO • GPIO: P5

• Keyboard scan input (row): KSI5

• Quadrature: QDY1

• Peripheral UART: puart_tx

• SPI_2: MISO (master and slave)

Pin Descriptions

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–27F5P6

PWM2

Input Floating VDDO • GPIO: P6

• Keyboard scan input (row): KSI6

• Quadrature: QDZ0

• Peripheral UART: puart_rts

• SPI_2: SPI_CS (slave only)

•60Hz_main

•Triac control 1

– 28 C5 P7 Input Floating VDDO • GPIO: P7

• Keyboard scan input (row): KSI7

• Quadrature: QDZ1

• Peripheral UART: puart_cts

• SPI_2: SPI_CLK (master and slave)

24 29 F4 P8 Input Floating VDDO • GPIO: P8

• Keyboard scan output (column):

KSO0

• A/D converter input

• External T/R switch control: ~tx_pd

Alternative Function:

• P33 in 32-QFN only

– 3 A1 P9 Input Floating VDDO • GPIO: P9

• Keyboard scan output (column):

KSO1

• A/D converter input

• External T/R switch control: tx_pd

–2D2P10

PWM3

Input Floating VDDO • GPIO: P10

• Keyboard scan output (column):

KSO2

• A/D converter input

1 40 C2 P11 Input Floating VDDO • GPIO: P11

• Keyboard scan output (column):

KSO3

• A/D converter input

• XTALI32K (32-QFN and 40-QFN only)

Alternative Function:

• P27 in 32-QFN only

Table 8: GPIO Pin Descriptionsa (Cont.)

Pin Number

Pin Name

Default

Direction

After

POR

Power

Domain Alternate Function Description

32-Pin

QFN

40-pin

QFN

64-pin

BGA

Pin Descriptions

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32 39 B2 P12 Input Floating VDDO • GPIO: P12

• Keyboard scan output (column):

KSO4

• A/D converter input

• XTALO32K (32-QFN and 40-QFN

only)

Alternative Function:

• P26 in 32-QFN only

29 35 F3 P13

PWM3

Input Floating VDDO • GPIO: P13

• Keyboard scan output (column):

KSO5

• A/D converter input

•Triac control 3

Alternative Function:

• P28 in 32-QFN only

30 36 D3 P14

PWM2

Input Floating VDDO • GPIO: P14

• Keyboard scan output (column):

KSO6

• A/D converter input

•Triac control 4

Alternative Function:

• P38 in 32-QFN only

31 37 A2 P15 Input Floating VDDO • GPIO: P15

• Keyboard scan output (column):

KSO7

• A/D converter input

• IR_RX

•60Hz_main

– – C8 P16 Input Floating VDDO • GPIO: P16

• Keyboard scan output (column):

KSO8

– – H4 P17 Input Floating VDDO • GPIO: P17

• Keyboard scan output (column):

KSO9

• A/D converter input

– – C7 P18 Input Floating VDDO • GPIO: P18

• Keyboard scan output (column):

KSO10

• A/D converter input

Table 8: GPIO Pin Descriptionsa (Cont.)

Pin Number

Pin Name

Default

Direction

After

POR

Power

Domain Alternate Function Description

32-Pin

QFN

40-pin

QFN

64-pin

BGA

Pin Descriptions

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BROADCOM CONFIDENTIAL

– – B8 P19 Input Floating VDDO • GPIO: P19

• Keyboard scan output (column):

KSO11

• A/D converter input

– – A8 P20 Input Floating VDDO • GPIO: P20

• Keyboard scan output (column):

KSO12

• A/D converter input

– – C6 P21 Input Floating VDDO • GPIO: P21

• Keyboard scan output (column):

KSO13

• A/D converter input

•Triac control 3

– – G4 P22 Input Floating VDDO • GPIO: P22

• Keyboard scan output (column):

KSO14

• A/D converter input

•Triac control 4

– – E3 P23 Input Floating VDDO • GPIO: P23

• Keyboard scan output (column):

KSO15

• A/D converter input

27 33 A7 P24 Input Floating VDDO • GPIO: P24

• Keyboard scan output (column):

KSO16

• SPI_2: SPI_CLK (master and slave)

• SPI_1: MISO (master only)

• Peripheral UART: puart_tx

26 32 B7 P25 Input Floating VDDO • GPIO: P25

• Keyboard scan output (column):

KSO17

• SPI_2: MISO (master and slave)

• Peripheral UART: puart_rx

Table 8: GPIO Pin Descriptionsa (Cont.)

Pin Number

Pin Name

Default

Direction

After

POR

Power

Domain Alternate Function Description

32-Pin

QFN

40-pin

QFN

64-pin

BGA

Pin Descriptions

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32 38 A4 P26

PWM0

Input Floating VDDO • GPIO: P26

• Keyboard scan output (column):

KSO18

• SPI_2: SPI_CS (slave only)

• SPI_1: MISO (master only)

• Optical control output: QOC0

•Triac control 1

Alternative Function:

• P12 in 32-QFN only

Current: 16 mA

11B4P27

PWM1

Input Floating VDDO • GPIO: P27

• Keyboard scan output (column):

KSO19

• SPI_2: MOSI (master and slave)

• Optical control output: QOC1

•Triac control 2

Alternative Function:

• P11 in 32-QFN only

Current: 16 mA

29 – B5 P28

PWM2

Input Floating VDDO • GPIO: P28

• Optical control output: QOC2

• A/D converter input

•LED1

•IR_TX

Alternative Function:

• P13 in 32-QFN only

Current: 16 mA

––A5P29

PWM3

Input Floating VDDO • GPIO: P29

• Optical control output: QOC3

• A/D converter input

•LED2

• IR_RX

Current: 16 mA

– – E4 P30 Input Floating VDDO • GPIO: P30

• A/D converter input

• Pairing button pin in default FW

• Peripheral UART: puart_rts

Table 8: GPIO Pin Descriptionsa (Cont.)

Pin Number

Pin Name

Default

Direction

After

POR

Power

Domain Alternate Function Description

32-Pin

QFN

40-pin

QFN

64-pin

BGA

Pin Descriptions

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BROADCOM CONFIDENTIAL

– – E7 P31 Input Floating VDDO • GPIO: P31

• A/D converter input

• EEPROM WP pin in default FW

• Peripheral UART: puart_tx

25 31 D6 P32 Input Floating VDDO • GPIO: P32

• A/D converter input

• Quadrature: QDX0

• SPI_2: SPI_CS (slave only)

• SPI_1: MISO (master only)

• Auxiliary clock output: ACLK0

• Peripheral UART: puart_tx

24 30 D8 P33 Input Floating VDDO • GPIO: P33

• A/D converter input

• Quadrature: QDX1

• SPI_2: MOSI (slave only)

• Auxiliary clock output: ACLK1

• Peripheral UART: puart_rx

Alternative Function:

• P8 in 32-QFN only

– – B6 P34 Input Floating VDDO • GPIO: P34

• A/D converter input

• Quadrature: QDY0

• Peripheral UART: puart_rx

• External T/R switch control: tx_pd

– – D5 P35 Input Floating VDDO • GPIO: P35

• A/D converter input

• Quadrature: QDY1

• Peripheral UART: puart_cts

– – C4 P36 Input Floating VDDO • GPIO: P36

• A/D converter input

• Quadrature: QDZ0

• SPI_2: SPI_CLK (master and slave)

• Auxiliary Clock Output: ACLK0

• Battery detect pin in default FW

• External T/R switch control: ~tx_pd

Table 8: GPIO Pin Descriptionsa (Cont.)

Pin Number

Pin Name

Default

Direction

After

POR

Power

Domain Alternate Function Description

32-Pin

QFN

40-pin

QFN

64-pin

BGA

Pin Descriptions

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BROADCOM CONFIDENTIAL

– – C3 P37 Input Floating VDDO • GPIO: P37

• A/D converter input

• Quadrature: QDZ1

• SPI_2: MISO (slave only)

• Auxiliary clock output: ACLK1

30 – B3 P38 Input Floating VDDO • GPIO: P38

• A/D converter input

• SPI_2: MOSI (master and slave)

•IR_TX

•XTALO32K (64-BGA only)

Alternative Function:

• P14 in 32-QFN only

– – A3 P39 Input Floating VDDO • GPIO: P39

• SPI_2: SPI_CS (slave only)

• SPI_1: MISO (master only)

• Infrared control: IR_RX

• External PA ramp control: PA_Ramp

• XTALI32K (64-BGA only)

•60Hz_main

a. During Power-On Reset, all inputs are disabled.

Table 8: GPIO Pin Descriptionsa (Cont.)

Pin Number

Pin Name

Default

Direction

After

POR

Power

Domain Alternate Function Description

32-Pin

QFN

40-pin

QFN

64-pin

BGA

Ball Maps

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BROADCOM CONFIDENTIAL

Ball Maps

Figure 9: 32-Pin QFN Ball Map

89 10111213141516

2526272829303132

P11/P27/XTALI32K

LDO_IN

LDO_OUT

VDDIF

VDDFE

VDDVCO

VDDPLL

XTALI

XTALO

VDDC

UART_RXD

UART_TXD

VDDM

SDA

SCL

TMC

RST_N

P8/P33

P32

P25

P24

VDDO

P13/P28

P14/P38

P15

P12/P26/XTALO32K

Ball Maps

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BROADCOM CONFIDENTIAL

Figure 10: 40-pin QFN Ball Map

1P27/PWM1

P10

LDOIN

LDOOUT

VDDIF

VDDFE

VDDVCO

VDDPLL

XTALI

XTALO

VDDC

UART_RXD

UART_TXD

VDDM

SDA

SCL

TMC

RESET_N

11 12 13 14 15 16 17 18 19 20

P33

XTALI32K/P11

XTALO32K/P12

P26/PWM0

P15

P14

P13

VDDO

P24

P25

P32

40 39 38 37 36 35 34 33 32 31

Ball Maps

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BROADCOM CONFIDENTIAL

Figure 11: 64-pin BGA Ball Map

P9 P15 P39/

XTALI32K

P26/

PWM0

P29/

PWM3 VDDO P24 P20

LDOIN P12 P38/

XTALO32K

P27/

PWM1

P28/

PWM2 P34 P25 P19

LDOOUT P11 P37 P36 P7 P21 P18 P16

VDDIF P10 P14 VSS P35 P32 VDDO P33

VDDFE VSS P23 P30 VSS P5 P31 SCL

RF VSS P13 P8 P6 P0 SDA P3

VSS VSS XTALO P22 UART_

TXD P1 TMC RESET

VDDVCO VDDPLL XTALI P17 UART_

RXD VDDC P4 P2

12345678

Specifications

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BROADCOM CONFIDENTIAL

Section 3: Specifications

Electrical Characteristics

Table 9 shows the maximum electrical rating for voltages referenced to VDD pin.

Table 10 shows the power supply characteristics for the range TJ = 0 to 125°C.

Table 9: Maximum Electrical Rating

Rating Symbol Value Unit

DC supply voltage for RF domain – 1.4 V

DC supply voltage for core domain – 1.4 V

DC supply voltage for VDDM domain (UART/I2C) – 3.8 V

DC supply voltage for VDDO domain – 3.8 V

DC supply voltage for VR3V – 3.8 V

DC supply voltage for VDDFE – 1.4 V

Voltage on input or output pin – VSS – 0.3 to VDD + 0.3 V

Operating ambient temperature range Topr 0 to +70 °C

Storage temperature range Tstg –40 to +125 °C

Table 10: Power Supply

Parameter Minimuma

a. Overall performance degrades beyond minimum and maximum supply voltages.

Typical MaximumaUnit

DC supply voltage for RF 1.14 1.2 1.26 V

DC supply voltage for Core 1.14 1.2 1.26 V

DC supply voltage for VDDM (UART/I2C) 1.62 – 3.63 V

DC supply voltage for VDDO 1.62 – 3.63 V

DC supply voltage for LDOIN 1.425 – 3.63 V

DC supply voltage for VDDFE 1.14 1.2b

b. 1.2V for Class 2 output with internal VREG.

1.26 V

Supply noise for VDDO (peak-to-peak) – – 100 mV

Supply noise for LDOIN (peak-to-peak) – – 100 mV

Electrical Characteristics

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BCM20730 Data Sheet

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Table 12 shows the digital level characteristics for (VSS = 0V).

Table 11: LDO Regulator Electrical Specifications

Parameter Conditions Min Typ Max Unit

Input voltage range – 1.425 – 3.63 V

Default output voltage – – 1.2 – V

Output voltage Range 0.8 – 1.4 V

Step size – 40 or 80 – mV

Accuracy at any step –5 – +5 %

Load current – ––30mA

Line regulation Vin from 1.425 to 3.63V, Iload = 30 mA –0.2 – 0.2 %VO/V

Load regulation Iload from 1 µA to 30 mA, Vin = 3.3V,

Bonding R = 0.3Ω

–0.10.2%V

O/mA

Quiescent current No load @Vin = 3.3V

*Current limit enabled

–6–µA

Power-down current Vin = 3.3V, worst@70°C – 5 200 nA

Electrical Characteristics

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Table 12: ADC Specifications

Parameter Symbol Conditions Min Typ Max Unit

ADC Characteristics

Number of Input

channels

–– –28––

Channel switching rate fch – – – 133.33 kch/s

Input signal range Vinp –0–3.63V

Reference settling time – Changing refsel 7.5 – – μs

Input resistance Rinp Effective, single-ended – 500 – kΩ

Input capacitance Cinp –––5pF

Conversion rate fC–5.859–187kHz

Conversion time TC– 5.35 – 170.7 μs

Resolution R – – 16 – bits

Effective number of

bits

–– –See

Table 1 on

page 18

–

Absolute voltage

measurement error

– Using on-chip ADC firmware

driver

–±2– %

Current I Iavdd1p2 + Iavdd3p3 –– 1 mA

Power P – – 1.5 – mW

Leakage current Ileakage T = 25°C – – 100 nA

Power-up time Tpowerup – – – 200 μs

Integral nonlinearity3INL – –1 – 1 LSBa

a. LSBs are expressed at the 10-bit level.

Differential

nonlinearityaDNL – –1 – 1 LSBa

Table 13: Digital Levela

a. This table is also applicable to VDDMEM domain.

Characteristics Symbol Min Typ Max Unit

Input low voltage VIL ––0.4V

Input high voltage VIH 0.75 × VDDO – – V

Input low voltage (VDDO = 1.62V) VIL ––0.4V

Input high voltage (VDDO = 1.62V) VIH 1.2 – – V

Output low voltageb

b. At the specified drive current for the pad.

VOL ––0.4V

Output high voltagebVOH VDDO – 0.4 – – V

Input capacitance (VDDMEM domain) CIN –0.12–pF

Electrical Characteristics

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BCM20730 Data Sheet

BROADCOM CONFIDENTIAL

Table 14: Current Consumption a

a. Current consumption measurements are taken at VBAT with the assumption that VBAT is connected to VDDIO

and LDOIN.

Operational Mode Conditions Typ Max Unit

Receive Receiver and baseband are both operating, 100%

ON.

–26.6 mA

Transmit Transmitter and baseband are both operating,

100% ON.

–24 at 2 dBm,

19 at 0 dBm

DM1 Average current when the device is in the transmit

state, 100% utilization of available slots.

15.2 – mA

DH1 Average current when the device is in the receive

state, 100% utilization of available slots.

16.67 – mA

Sleep Internal LPO is in use. 28.4 – μA

HIDOFF – 1.5 – μA

Sniff mode, 11.25 ms Slave 2.8 – mA

Sniff mode, 22.5 ms Slave 1.27 – mA

Sniff mode, 60 ms Slave 750 – μA

Sniff mode, 100 ms Slave 500 – μA

Sniff mode, 495 ms Slave 125 – μA

Caution! This device is susceptible to permanent damage from electrostatic discharge (ESD). Proper

precautions are required during handling and mounting to avoid excessive ESD.

Table 15: ESD Tolerance

Model Tolerance

Human Body Model (HBM) ± 2000V

Charged Device Model (CDM) ± 400V

Machine Model (MM) ± 150V

RF Specifications

BROADCOM

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BCM20730 Data Sheet

BROADCOM CONFIDENTIAL

RF Specifications

Table 16: Receiver RF Specifications

Parameter Mode and Conditions Min Typ Max Unit

Receiver Section

Frequency range – 2402 – 2480 MHz

RX sensitivity (standard) GFSK, 0.1%BER, 1 Mbps – –88.0 –84.0 dBm

RX sensitivity (low current) – –84.0 – dBm

Input IP3 – –16 – – dBm

Maximum input – –10 – – dBm

Interference Performance

C/I cochannel GFSK, 0.1%BERa

a. Desired signal is 10 dB above the reference sensitivity level (defined as –70 dBm).

––11.0dB

C/I 1 MHz adjacent channel GFSK, 0.1%BERa––0.0dB

C/I 2 MHz adjacent channel GFSK, 0.1%BERa– – –30.0 dB

C/I ≥ 3 MHz adjacent channel GFSK, 0.1%BERb

b. Desired signal is 3 dB above the reference sensitivity level (defined as –70 dBm).

– – –40.0 dB

C/I image channel GFSK, 0.1%BERa–––9.0dB

C/I 1 MHz adjacent to image

channel

GFSK, 0.1%BERa– – –20.0 dB

Out-of-Band Blocking Performance (CW)b

30 MHz to 2000 MHz 0.1%BER – –10.0 – dBm

2000 MHz to 2399 MHz 0.1%BER – –27 – dBm

2498 MHz to 3000 MHz 0.1%BER – –27 – dBm

3000 MHz to 12.75 GHz 0.1%BER – –10.0 – dBm

Spurious Emissions

30 MHz to 1 GHz – – – –57.0 dBm

1 GHz to 12.75 GHz – – – –55.0 dBm

RF Specifications

BROADCOM

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BCM20730 Data Sheet

BROADCOM CONFIDENTIAL

Table 17: Transmitter RF Specifications

Parameter Min Typ Max Unit

Transmitter Section

Frequency range 2402 – 2480 MHz

Output power adjustment range –6.0 – 4.0 dBm

Default output power – 4.0 – dBm

Output power variation – 2.0 – dB

20 dB bandwidth – 900 1000 kHz

Adjacent Channel Power

|M – N| = 2 – – –20 dBm

|M – N| ≥ 3– – –40dBm

Out-of-Band Spurious Emission

30 MHz to 1 GHz – – –36.0 dBm

1 GHz to 12.75 GHz – – –30.0 dBm

1.8 GHz to 1.9 GHz – – –47.0 dBm

5.15 GHz to 5.3 GHz – – –47.0 dBm

LO Performance

Initial carrier frequency tolerance – – ±75 kHz

Frequency Drift

DH1 packet – – ±25 kHz

DH3 packet – – ±40 kHz

DH5 packet – – ±40 kHz

Drift rate – – 20 kHz/50 µs

Frequency Deviation

Average deviation in payload

(sequence used is 00001111)

140 – 175 kHz

Maximum deviation in payload

(sequence used is 10101010)

115 – – kHz

Channel spacing – 1 – MHz

Timing and AC Characteristics

BROADCOM

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BCM20730 Data Sheet

BROADCOM CONFIDENTIAL

Timing and AC Characteristics

In this section, use the numbers listed in the Reference column of each table to interpret the following timing

diagrams.

UART Timing

Figure 12: UART Timing

Table 18: UART Timing Specifications

Reference Characteristics Min Max Unit

1 Delay time, UART_CTS_N low to UART_TXD valid – 24 Baud out

cycles

2 Setup time, UART_CTS_N high before midpoint of stop

bit

– 10 ns

3 Delay time, midpoint of stop bit to UART_RTS_N high – 2 Baud out

cycles

Timing and AC Characteristics

BROADCOM

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BCM20730 Data Sheet

BROADCOM CONFIDENTIAL

SPI Timing

The SPI interface supports clock speeds up to 12 MHz with VDDIO ≥ 2.2V. The supported clock speed is 6 MHz

when 2.2V ≥ VDDIO ≥ 1.62V.

Figure 13 shows the timing diagram. SPI timing values for different values of SCLK and VDDM are shown in

Table 19, Table 20 on page 50, Table 21 on page 50, Table 22 on page 51.

Figure 13: SPI Timing Diagram

Table 19: SPI1 Timing Values — SCLK = 12 MHz and VDDM = 3.2Va

a. The SCLK period is based on the limitation of Tds_mi. SCLK is designed for a maximum speed of 12 MHz. The

speed can be adjusted to as low as 400 Hz by configuring the firmware.

Reference Characteristics Symbol Min Typicalb

b. Typical timing based on 20 pF/1 MΩ load and SCLK = 12 MHz.

Max Unit

1 Output setup time, from MOSI

data valid to sample edge of SCLK

Tds_mo – 20 – ns

2 Output hold time, from sample

edge of SCLK to MOSI data update

Tdh_mo – 63 – ns

3 Input setup time, from MISO data

valid to sample edge of SCLK

Tds_mi – TBD – ns

4 Input hold time, from sample

edge of SCLK to MISO data update

Tdh_mi – TBD – ns

c. CS timing is firmware controlled.

Time from CS assert to first SCLK

edge

Tsu_cs ½ SCLK period – 1 – – ns

6cTime from first SCLK edge to CS

deassert

Thd_cs ½ SCLK period – – ns

MOSI

SCLK

Mode 1

MISO

CS 5

Invalid bit MSB

MSB

LSB

SCLK

Mode 3

Timing and AC Characteristics

BROADCOM

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BCM20730 Data Sheet

BROADCOM CONFIDENTIAL

Table 20: SPI1 Timing Values — SCLK = 6 MHz and VDDM = 1.62Va

a. The SCLK period is based on the limitation of Tds_mi. SCLK is designed for a maximum speed of 6 MHz. The

speed can be adjusted to as low as 400 Hz by configuring the firmware.

Reference Characteristics Symbol Min Typicalb

b. Typical timing based on 20 pF/1 MΩ load and SCLK = 6 MHz.

Max Unit

1 Output setup time, from MOSI data

valid to sample edge of SCLK

Tds_mo – 41 – ns

2 Output hold time, from sample

edge of SCLK to MOSI data update

Tdh_mo – 120 – ns

3 Input setup time, from MISO

data valid to sample edge of SCLK

Tds_mi – TBD – ns

4 Input hold time, from sample

edge of SCLK to MISO data update

Tdh_mi – TBD – ns

c. CS timing is firmware controlled.

Time from CS assert to first SCLK

edge

Tsu_cs ½ SCLK period – 1 – – ns

6cTime from first SCLK edge to CS

deassert

Thd_cs ½ SCLK period – – ns

Table 21: SPI2 Timing Values — SCLK = 12 MHz and VDDM = 3.2Va

a. The SCLK period is based on the limitation of Tds_mi. SCLK is designed for a maximum speed of 12 MHz. The

speed can be adjusted to as low as 400 Hz by configuring the firmware.

Reference Characteristics Symbol Min Typicalb

b. Typical timing based on 20 pF//1 MΩ load and SCLK = 12 MHz.

Max Unit

1 Output setup time, from MOSI

data valid to sample edge of SCLK

Tds_mo – 26 – ns

2 Output hold time, from sample

edge of SCLK to MOSI data update

Tdh_mo – 56 – ns

3 Input setup time, from MISO

data valid to sample edge of SCLK

Tds_mi – TBD – ns

4 Input hold time, from sample

edge of SCLK to MISO data update

Tdh_mi – TBD – ns

c. CS timing is firmware controlled in master mode and can be adjusted as required in slave mode.

Time from CS assert to first SCLK

edge

Tsu_cs ½ SCLK period – 1 – – ns

6cTime from first SCLK edge to CS

deassert

Thd_cs ½ SCLK period – – ns

Timing and AC Characteristics

BROADCOM

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BCM20730 Data Sheet

BROADCOM CONFIDENTIAL

BSC Interface Timing

Table 22: SPI2 Timing Values — SCLK = 6 MHz and VDDM = 1.62Va

a. The SCLK period is based on the limitation of Tds_mi. SCLK is designed for a maximum speed of 6 MHz. The

speed can be adjusted to as low as 400 Hz by configuring the firmware.

Reference Characteristics Symbol Min Typicalb

b. Typical timing based on 20 pF//1 MΩ load and SCLK = 6 MHz.

Max Unit

1 Output setup time, from MOSI

data valid to sample edge of SCLK

Tds_mo – 50 – ns

2 Output hold time, from sample

edge of SCLK to MOSI data update

Tdh_mo – 120 – ns

3 Input setup time, from MISO

data valid to sample edge of SCLK

Tds_mi – TBD – ns

4 Input hold time, from sample

edge of SCLK to MISO data update

Tdh_mi – TBD – ns

c. CS timing is firmware controlled in master mode and can be adjusted as required in slave mode.

Time from CS assert to first SCLK

edge

Tsu_cs ½ SCLK period – 1 – – ns

6cTime from first SCLK edge to CS

deassert

Thd_cs ½ SCLK period – – ns

Table 23: BSC Interface Timing Specifications

Reference Characteristics Min Max Unit

1 Clock frequency – 100 kHz

400

800

1000

2 START condition setup time 650 – ns

3 START condition hold time 280 – ns

4 Clock low time 650 – ns

5 Clock high time 280 – ns

6 Data input hold timea

a. As a transmitter, 300 ns of delay is provided to bridge the undefined region of the falling edge of SCL to avoid

unintended generation of START or STOP conditions.

0 – ns

7 Data input setup time 100 – ns

8 STOP condition setup time 280 – ns

9 Output valid from clock – 400 ns

10 Bus free timeb

b. Time that the cbus must be free before a new transaction can start.

650 – ns

Timing and AC Characteristics

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Figure 14: BSC Interface Timing Diagram

Mechanical Information

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Section 4: Mechanical Information

Figure 15: 32-Pin QFN Package

Mechanical Information

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Figure 16: 40-pin QFN Package

Mechanical Information

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Figure 17: 64-pin FBGA Package

Mechanical Information

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Tape Reel and Packaging Specifications

The top left corner of the BCM20730 package is situated near the sprocket holes, as shown in Figure 18.

Table 24: BCM20730 5 × 5 × 1 mm QFN, 32-Pin Tape Reel Specifications

Parameter Value

Quantity per reel 2500 pieces

Reel diameter 13 inches

Hub diameter 7 inches

Tape width 12 mm

Tape pitch 8 mm

Table 25: BCM20730 6 × 6 × 1 mm QFN, 40-Pin Tape Reel Specifications

Parameter Value

Quantity per reel 4000 pieces

Reel diameter 13 inches

Hub diameter 4 inches

Tape width 16 mm

Tape pitch 12 mm

Table 26: BCM20730 7 × 7 × 0.8 mm WFBGA, 64-Pin Tape Reel Specifications

Parameter Value

Quantity per reel 2500 pieces

Reel diameter 13 inches

Hub diameter 4 inches

Tape width 16 mm

Tape pitch 12 mm

Mechanical Information

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Figure 18: Pin 1 Orientation

Pin 1: Top left corner of package toward sprocket holes

Ordering Information

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Section 5: Ordering Information

Table 27: Ordering Information

Part Number Package Ambient Operating Temperature

BCM20730A2KML2G 32-pin QFN 0°C to 70°C

BCM20730A2KMLG 40-pin QFN 0°C to 70°C

BCM20730A2KFBG 64-pin BGA 0°C to 70°C

BCM20730A1KML2G 32-pin QFN 0°C to 70°C

BCM20730A1KMLG 40-pin QFN 0°C to 70°C

BCM20730A1KFBG 64-pin BGA 0°C to 70°C

Acronyms and Abbreviations

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Appendix A: Acronyms and Abbreviations

The following list of acronyms and abbreviations may appear in this document.

Term Description

ADC analog-to-digital converter

AFH adaptive frequency hopping

AHB advanced high-performance bus

APB advanced peripheral bus

APU audio processing unit

ARM7TDMI-S™ Acorn RISC Machine 7 Thumb instruction, Debugger, Multiplier, Ice, Synthesizable

BSC Broadcom Serial Control

BTC Bluetooth controller

COEX coexistence

DFU device firmware update

DMA direct memory access

EBI external bus interface

HCI Host Control Interface

HV high voltage

IDC initial digital calibration

IF intermediate frequency

IRQ interrupt request

JTAG Joint Test Action Group

LCU link control unit

LDO low drop-out

LHL lean high land

LPO low power oscillator

LV LogicVision™

MIA multiple interface agent

PCM pulse code modulation

PLL phase locked loop

PMU power management unit

POR power-on reset

PWM pulse width modulation

QD quadrature decoder

RAM random access memory

RF radio frequency

Acronyms and Abbreviations

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ROM read-only memory

RX/TX receive, transmit

SPI serial peripheral interface

SW software

UART universal asynchronous receiver/transmitter

UPI µ-processor interface

WD watchdog

Term Description

Phone: 949-926-5000

Fax: 949-926-5203

E-mail: info@broadcom.com

Web: www.broadcom.com

BROADCOM CORPORATION

5300 California Avenue

Irvine, CA 92617

20730-DS108-R September 9, 2013

Broadcom® Corporation reserves the right to make changes without further notice to any products

or data herein to improve reliability, function, or design.

Information furnished by Broadcom Corporation is believed to be accurate and reliable. However,

Broadcom Corporation does not assume any liability arising out of the application or use of this

information, nor the application or use of any product or circuit described herein, neither does it

convey any license under its patent rights nor the rights of others.

BCM20730 Data Sheet