SN74LS193N - ON Semiconductor

5-1

FAST AND LS TTL DATA

PRESETTABLE BCD/DECADE

UP/DOWN COUNTER

PRESETTABLE 4-BIT BINARY

UP/DOWN COUNTER

The SN54/74LS192 is an UP/DOWN BCD Decade (8421) Counter and the

SN54/74LS193 is an UP/DOWN MODULO-16 Binary Counter. Separate

Count Up and Count Down Clocks are used and in either counting mode the

circuits operate synchronously. The outputs change state synchronous with

the LOW-to-HIGH transitions on the clock inputs.

Separate Terminal Count Up and Terminal Count Down outputs are

provided which are used as the clocks for a subsequent stages without extra

logic, thus simplifying multistage counter designs. Individual preset inputs

allow the circuits to be used as programmable counters. Both the Parallel

Load (PL) and the Master Reset (MR) inputs asynchronously override the

clocks.

•Low Power . . . 95 mW Typical Dissipation

•High Speed . . . 40 MHz Typical Count Frequency

•Synchronous Counting

•Asynchronous Master Reset and Parallel Load

•Individual Preset Inputs

•Cascading Circuitry Internally Provided

•Input Clamp Diodes Limit High Speed Termination Effects

NOTE:

The Flatpak version

has the same pinouts

(Connection Diagram) as

the Dual In-Line Package.

CONNECTION DIAGRAM DIP (TOP VIEW)

14 13 12 11 10 9

1234567

16 15

VCC

P0MR TCDTCUP2

PL P3

Q1Q0CPDCPUQ2Q3GND

PIN NAMES LOADING (Note a)

HIGH LOW

CPU

CPD

TCD

TCU

Count Up Clock Pulse Input

Count Down Clock Pulse Input

Asynchronous Master Reset (Clear) Input

Asynchronous Parallel Load (Active LOW) Input

Parallel Data Inputs

Flip-Flop Outputs (Note b)

Terminal Count Down (Borrow) Output (Note b)

Terminal Count Up (Carry) Output (Note b)

0.5 U.L.

10 U.L.

0.25 U.L.

5 (2.5) U.L.

NOTES:

a. 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.

b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)

b. Temperature Ranges.

SN54/74LS192

SN54/74LS193

PRESETTABLE BCD/DECADE

UP/DOWN COUNTER

PRESETTABLE 4-BIT BINARY

UP/DOWN COUNTER

LOW POWER SCHOTTKY

J SUFFIX

CERAMIC

CASE 620-09

N SUFFIX

PLASTIC

CASE 648-08

16 1

ORDERING INFORMATION

SN54LSXXXJ Ceramic

SN74LSXXXN Plastic

SN74LSXXXD SOIC

16 1

D SUFFIX

SOIC

CASE 751B-03

LOGIC SYMBOL

VCC = PIN 16

GND = PIN 8

3267

91011511

CPDQ0Q1Q2Q3TCD

CPUTCU

5-2

FAST AND LS TTL DATA

SN54/74LS192 •SN54/74LS193

STATE DIAGRAMS

LS192 LOGIC EQUATIONS

FOR TERMINAL COUNT

LS192 LS193

COUNT UP

COUNT DOWN

01234

891011

01234

891011

TCU = Q0 ⋅ Q3 ⋅ CPU

TCD = Q0 ⋅ Q1 ⋅ Q2 ⋅ Q3 ⋅ CPD

LS193 LOGIC EQUATIONS

FOR TERMINAL COUNT

TCU = Q0 ⋅ Q1⋅ Q2⋅ Q3 ⋅ CPU

TCD = Q0 ⋅ Q1 ⋅ Q2 ⋅ Q3 ⋅ CPD

LOGIC DIAGRAMS

VCC = PIN 16

GND = PIN 8

= PIN NUMBERS

LS192

P0P1P2P3

TCU

(CARRY

OUTPUT)

Q0Q1Q2Q3

(CLEAR)

(DOWN

COUNT)

CPD

(UP COUNT)

CPU

(LOAD)

PL1

267

911

TCD

(BORROW

OUTPUT)

SDQ

5-3

FAST AND LS TTL DATA

SN54/74LS192 •SN54/74LS193

LOGIC DIAGRAMS (continued)

VCC = PIN 16

GND = PIN 8

= PIN NUMBERS

LS193

P0P1P2P3

Q0Q1Q2Q3

(CLEAR)

(DOWN

COUNT)

CPD

(UP COUNT)

CPU

(LOAD)

PL1

267

911

SDQ

TCU

(CARRY

OUTPUT)

TCD

(BORROW

OUTPUT)

5-4

FAST AND LS TTL DATA

SN54/74LS192 •SN54/74LS193

FUNCTIONAL DESCRIPTION

The LS192 and LS193 are Asynchronously Presettable

Decade and 4-Bit Binary Synchronous UP/DOWN (Revers-

able) Counters. The operating modes of the LS192 decade

counter and the LS193 binary counter are identical, with the

only difference being the count sequences as noted in the

State Diagrams. Each circuit contains four master/slave

flip-flops, with internal gating and steering logic to provide

master reset, individual preset, count up and count down

operations.

Each flip-flop contains JK feedback from slave to master

such that a LOW-to-HIGH transition on its T input causes the

slave, and thus the Q output to change state. Synchronous

switching, as opposed to ripple counting, is achieved by

driving the steering gates of all stages from a common Count

Up line and a common Count Down line, thereby causing all

state changes to be initiated simultaneously . A LOW-to-HIGH

transition on the Count Up input will advance the count by one;

a similar transition on the Count Down input will decrease the

count by one. While counting with one clock input, the other

should be held HIGH. Otherwise, the circuit will either count by

twos or not at all, depending on the state of the first flip-flop,

which cannot toggle as long as either Clock input is LOW.

The Terminal Count Up (TCU) and Terminal Count Down

(TCD) outputs are normally HIGH. When a circuit has reached

the maximum count state (9 for the LS192, 15 for the LS193),

the next HIGH-to-LOW transition of the Count Up Clock will

cause TCU to go LOW. TCU will stay LOW until CPU goes

HIGH again, thus effectively repeating the Count Up Clock,

but delayed by two gate delays. Similarly, the TCD output will

go LOW when the circuit is in the zero state and the Count

Down Clock goes LOW. Since the TC outputs repeat the clock

waveforms, they can be used as the clock input signals to the

next higher order circuit in a multistage counter.

Each circuit has an asynchronous parallel load capability

permitting the counter to be preset. When the Parallel Load

(PL) and the Master Reset (MR) inputs are LOW , information

present on the Parallel Data inputs (P0, P3) is loaded into the

counter and appears on the outputs regardless of the

conditions of the clock inputs. A HIGH signal on the Master

Reset input will disable the preset gates, override both Clock

inputs, and latch each Q output in the LOW state. If one of the

Clock inputs is LOW during and after a reset or load operation,

the next LOW-to-HIGH transition of that Clock will be

interpreted as a legitimate signal and will be counted.

MODE SELECT TABLE

MR PL CPUCPDMODE

H X X X Reset (Asyn.)

L L X X Preset (Asyn.)

L H H H No Change

L H H Count Up

L H H Count Down

L = LOW Voltage Level

H = HIGH Voltage Level

X = Don’t Care

= LOW-to-HIGH Clock Transition

5-5

FAST AND LS TTL DATA

SN54/74LS192 •SN54/74LS193

GUARANTEED OPERATING RANGES

Symbol Parameter Min Typ Max Unit

VCC Supply Voltage 54

74 4.5

4.75 5.0

5.0 5.5

5.25 V

TAOperating Ambient Temperature Range 54

74 –55

025

25 125

70 °C

IOH Output Current — High 54, 74 –0.4 mA

IOL Output Current — Low 54

74 4.0

8.0 mA

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)

Sbl

Limits

T C di i

Symbol Parameter Min Typ Max Unit Test Conditions

VIH Input HIGH Voltage 2.0 V Guaranteed Input HIGH Voltage for

All Inputs

VIL

Input LOW Voltage

54 0.7

Guaranteed Input LOW Voltage for

npu

LOW

age 74 0.8

All Inputs

VIK Input Clamp Diode Voltage –0.65 –1.5 V VCC = MIN, IIN = –18 mA

VOH

Output HIGH Voltage

54 2.5 3.5 V VCC = MIN, IOH = MAX, VIN = VIH

HIGH

age 74 2.7 3.5 V

CC ,OH ,IN IH

or VIL per T ruth Table

VOL

Output LOW Voltage

54, 74 0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN,

VIN =V

IL or VIH

LOW

age 74 0.35 0.5 V IOL = 8.0 mA

IN =

IL or

per T ruth Table

IIH

Input HIGH Current

20 µA VCC = MAX, VIN = 2.7 V

npu

HIGH

urren

0.1 mA VCC = MAX, VIN = 7.0 V

IIL Input LOW Current –0.4 mA VCC = MAX, VIN = 0.4 V

IOS Short Circuit Current (Note 1) –20 –100 mA VCC = MAX

ICC Power Supply Current 34 mA VCC = MAX

Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.

AC CHARACTERISTICS (TA = 25°C)

Sbl

Limits

T C di i

Symbol Parameter Min Typ Max Unit T est Conditions

fMAX Maximum Clock Frequency 25 32 MHz

V50V

tPLH

tPHL CPU Input to

TCU Output 17

18 26

24 ns

V50V

tPLH

tPHL CPD Input to

TCD Output 16

15 24

24 ns VCC = 5.0 V

tPLH

tPHL Clock to Q 27

30 38

47 ns

CL = 15 pF

tPLH

tPHL PL to Q 24

25 40

40 ns

tPHL MR Input to Any Output 23 35 ns

5-6

FAST AND LS TTL DATA

SN54/74LS192 •SN54/74LS193

AC SETUP REQUIREMENTS (TA = 25°C)

Sbl

Limits

T C di i

Symbol Parameter Min Typ Max Unit T est Conditions

tWAny Pulse Width 20 ns

V50V

tsData Setup T ime 20 ns

VCC =50V

thData Hold T ime 5.0 ns

CC =

trec Recovery Time 40 ns

DEFINITIONS OF TERMS

SETUP TIME (ts) is defined as the minimum time required for

the correct logic level to be present at the logic input prior to the

PL transition from LOW-to-HIGH in order to be recognized and

transferred to the outputs.

HOLD TIME (th) is defined as the minimum time following the

PL transition from LOW-to-HIGH that the logic level must be

maintained at the input in order to ensure continued recogni-

tion. A negative HOLD TIME indicates that the correct logic

level may be released prior to the PL transition from

LOW-to-HIGH and still be recognized.

RECOVERY TIME (trec) is defined as the minimum time

required between the end of the reset pulse and the clock

transition from LOW-to-HIGH in order to recognize and

transfer HIGH data to the Q outputs.

5-7

FAST AND LS TTL DATA

SN54/74LS192 •SN54/74LS193

AC WAVEFORMS

Figure 1

Figure 2 Figure 3

Figure 4 Figure 5

Figure 6 Figure 7

1.3 V

CPU or CPD

TCU or TCD

tPHL tPLH

tPLH

NOTE: PL = LOW

tPHL

ts(H) ts(L)

th(H) th(L)

* The shaded areas indicate when the input is permitted

* to change for predictable output performance

Q = P Q = P

tPLH

trec

tPLH tPHL

tPHL

1.3 V

1.3 V 1.3 V

1.3 V

trec