LTC2360/LTC2361/LTC2362
1
236012fa
TYPICAL APPLICATION
FEATURES
APPLICATIONS
DESCRIPTION
100ksps/250ksps/500ksps,
12-Bit Serial ADCs in TSOT-23
The LTC
®
2360/LTC2361/LTC2362 are 100ksps/250ksps/
500ksps, 12-bit, sampling A/D converters that draw only
0.5mA, 0.75mA and 1.1mA, respectively, from a single
3V supply. The supply current drops at lower sampling
rates because these devices automatically power down
after conversions. The full-scale input of the LTC2360/
LTC2361/LTC2362 is 0V to VDD or VREF. These ADCs are
available in tiny 6- and 8-lead TSOT-23 packages.
The serial interface, tiny TSOT-23 package and extremely
high sample rate-to-power ratio make the LTC2360/
LTC2361/LTC2362 ideal for compact, low power, high
speed systems.
The high impedance single-ended analog input and the
ability to operate with reduced spans (down to 1.4V full
scale) allow direct connection to sensors and transducers in
many applications, eliminating the need for gain stages.
Single 3V Supply, 500ksps, 12-Bit Sampling ADC
n 12-Bit Resolution
n Low Noise: 73dB SNR
n Low Power Dissipation: 1.5mW at 100ksps
n 100ksps/250ksps/500ksps Sampling Rates
n Single Supply 2.35V to 3.6V Operation
n No Data Latency
n Sleep Mode with 0.1µA Typical Supply Current
n Dedicated External Reference (TSOT23-8)
n 1V to 3.6V Digital Output Supply (TSOT23-8)
n SPI/MICROWIRE™ Compatible Serial I/O
n Guaranteed Operation from –40°C to 125°C
n Tiny 6- and 8-Lead TSOT-23 Packages
n Communication Systems
n Data Acquisition Systems
n Handheld Portable Devices
n Uninterrupted Power Supplies
n Battery-Operated Systems
n Automotive
Supply Current vs Sample Rate
VDD
VREF
GND
AIN
CONV
SCK
SDO
OVDD
LTC2362
2.2µF
3V
236012 TA01a
SERIAL DATA LINK TO
ASIC, PLD, MPU, DSP
OR SHIFT REGISTORS
DIGITAL OUTPUT SUPPLY
1V TO VDD
ANALOG INPUT
0V TO 3V
2.2µF
SAMPLE RATE (ksps)
SUPPLY CURRENT (µA)
236012 TA01b
1200
1000
800
400
600
200
01 100 100010
VDD = 3.6V
TA = 25°C
LTC2361
LTC2362
LTC2360
12-Bit TSOT23-6/-8 ADC Family
DATA OUTPUT RATE 3Msps 1Msps 500ksps 250ksps 100ksps
Part Number LTC2366 LTC2365 LTC2362 LTC2361 LTC2360
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
LTC2360/LTC2361/LTC2362
2
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ABSOLUTE MAXIMUM RATINGS
Supply Voltage (VDD) ..................................................4V
Supply Voltage (OVDD) ................ Min (VDD + 0.3V, 4.0V)
VREF and Analog Input Voltage
(Note 3) .........................................–0.3V to (VDD + 0.3V)
Digital Input Voltage ......................–0.3V to (VDD + 0.3V)
Digital Output Voltage ...................–0.3V to (VDD + 0.3V)
Power Dissipation ...............................................100mW
(Notes 1, 2)
ORDER INFORMATION
VDD 1
VREF 2
GND 3
AIN 4
8 CONV
7 SCK
6 SDO
5 OVDD
TOP VIEW
TS8 PACKAGE
8-LEAD PLASTIC TSOT-23
TJMAX = 150°C, θJA = 250°C/W
VDD 1
GND 2
AIN 3
6 CONV
5 SDO
4 SCK
TOP VIEW
S6 PACKAGE
6-LEAD PLASTIC TSOT-23
TJMAX = 150°C, θJA = 250°C/W
PIN CONFIGURATION
Operating Temperature Range
LTC2360C/LTC2361C/LTC2362C .............. 0°C to 70°C
LTC2360I/LTC2361I/LTC2362I .............. –40°C to 85°C
LTC2360H/LTC2361H/LTC2362H (Note 12) .. –40°C to 125°C
Storage Temperature Range ................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec) .................. 300°C
Lead Free Finish
TAPE AND REEL (MINI) TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC2362CTS8#TRMPBF LTC2362CTS8#TRPBF LTDBV 8-Lead Plastic TSOT23 0°C to 70°C
LTC2362ITS8#TRMPBF LTC2362ITS8#TRPBF LTDBV 8-Lead Plastic TSOT23 -40°C to 85°C
LTC2362HTS8#TRMPBF LTC2362HTS8#TRPBF LTDBV 8-Lead Plastic TSOT23 -40°C to 125°C
LTC2362CS6#TRMPBF LTC2362CS6#TRPBF LTDGP 6-Lead Plastic TSOT23 0°C to 70°C
LTC2362IS6#TRMPBF LTC2362IS6#TRPBF LTDGP 6-Lead Plastic TSOT23 -40°C to 85°C
LTC2362HS6#TRMPBF LTC2362HS6#TRPBF LTDGP 6-Lead Plastic TSOT23 -40°C to 125°C
LTC2361CTS8#TRMPBF LTC2361CTS8#TRPBF LTDGM 8-Lead Plastic TSOT23 0°C to 70°C
LTC2361ITS8#TRMPBF LTC2361ITS8#TRPBF LTDGM 8-Lead Plastic TSOT23 -40°C to 85°C
LTC2361HTS8#TRMPBF LTC2361HTS8#TRPBF LTDGM 8-Lead Plastic TSOT23 -40°C to 125°C
LTC2361CS6#TRMPBF LTC2361CS6#TRPBF LTDGN 6-Lead Plastic TSOT23 0°C to 70°C
LTC2361IS6#TRMPBF LTC2361IS6#TRPBF LTDGN 6-Lead Plastic TSOT23 -40°C to 85°C
LTC2361HS6#TRMPBF LTC2361HS6#TRPBF LTDGN 6-Lead Plastic TSOT23 -40°C to 125°C
LTC2360CTS8#TRMPBF LTC2360CTS8#TRPBF LTDGJ 8-Lead Plastic TSOT23 0°C to 70°C
LTC2360ITS8#TRMPBF LTC2360ITS8#TRPBF LTDGJ 8-Lead Plastic TSOT23 -40°C to 85°C
LTC2360HTS8#TRMPBF LTC2360HTS8#TRPBF LTDGJ 8-Lead Plastic TSOT23 -40°C to 125°C
LTC2360CS6#TRMPBF LTC2360CS6#TRPBF LTDGK 6-Lead Plastic TSOT23 0°C to 70°C
LTC2360IS6#TRMPBF LTC2360IS6#TRPBF LTDGK 6-Lead Plastic TSOT23 -40°C to 85°C
LTC2360HS6#TRMPBF LTC2360HS6#TRPBF LTDGK 6-Lead Plastic TSOT23 -40°C to 125°C
TRM = 500 pieces. *Temperature grades are identifi ed by a label on the shipping container.
Consult LTC Marketing for information on lead based fi nish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifi cations, go to: http://www.linear.com/tapeandreel/
LTC2360/LTC2361/LTC2362
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CONVERTER CHARACTERISTICS
PARAMETER CONDITIONS MIN TYP MAX UNITS
Resolution (No Missing Codes) l12 Bits
Integral Linearity Error (Notes 5, 6) l±0.25 ±1 LSB
Differential Linearity Error (Note 6) l±0.25 ±1 LSB
Transition Noise (Note 7) 0.25 LSBRMS
Offset Error (Note 6) l1±3.5 LSB
Gain Error (Note 6) l0.1 ±2 LSB
Total Unadjusted Error (Note 6) l1.1 ±3.5 LSB
The l denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C. (Note 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN Analog Input Voltage S6 Package
TS8 Package
l
l
–0.05
–0.05
VDD + 0.05
VREF + 0.05
V
IIN Analog Input Leakage Current CONV = High l±1 µA
CIN Analog Input Capacitance Between Conversions
During Conversions
20
4
pF
pF
VREF Reference Input Voltage TS8 Package l1.4 VDD + 0.05 V
IREF Reference Input Leakage Current TS8 Package l±1 µA
CREF Reference Input Capacitance TS8 Package 20 pF
tAP Sample-and-Hold Aperture Delay Time 1 ns
tJITTER Sample-and-Hold Aperture Delay Time Jitter 0.3 ns
ANALOG INPUT
The l denotes the specifi cations which apply over the full operating temperature range, otherwise
specifi cations are at TA = 25°C. (Note 4)
DYNAMIC ACCURACY
The l denotes the specifi cations which apply over the full operating temperature range,
otherwise specifi cations are at TA = 25°C. (Note 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
SINAD Signal-to-(Noise + Distortion) Ratio fIN = 49kHz for LTC2360/LTC2361,
fIN = 100kHz for LTC2362
72 dB
SNR Signal-to-Noise Ratio fIN = 49kHz for LTC2360/LTC2361,
fIN = 100kHz for LTC2362
73 dB
THD Total Harmonic Distortion fIN = 49kHz for LTC2360/LTC2361,
fIN = 100kHz for LTC2362
–85 dB
SFDR Spurious Free Dynamic Range fIN = 49kHz for LTC2360/LTC2361,
fIN = 100kHz for LTC2362
86 dB
IMD Intermodulation Distortion fIN1 = 97kHz, fIN2 = 100kHz for LTC2362
fIN1 = 47kHz, fIN2 = 49kHz for LTC2360/LTC2361
–75 dB
Full-Power Bandwidth at 3dB
at 0.1dB
10
2
MHz
MHz
Full-Linear Bandwidth SINAD ≥ 68dB 1 MHz
LTC2360/LTC2361/LTC2362
4
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DIGITAL INPUTS AND DIGITAL OUTPUTS
The l denotes the specifi cations which apply over the
full operating temperature range, otherwise specifi cations are at TA = 25°C. (Note 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIH High Level Input Voltage 2.7V < VDD ≤ 3.6V
2.35V ≤ VDD ≤ 2.7V
l
l
2
1.7
V
V
VIL Low Level Input Voltage 2.7V < VDD ≤ 3.6V
2.35V ≤ VDD ≤ 2.7V
l
l
0.8
0.7
V
V
IIH High Level Input Current VIN = VDD l2.5 µA
IIL Low Level Input Current VIN = 0V l–2.5 µA
CIN Digital Input Capacitance 2pF
VOH High Level Output Voltage VDD = 2.35V to 3.6V, ISOURCE = 200µA lVDD – 0.2 V
VOL Low Level Output Voltage VDD = 2.35V to 3.6V, ISINK = 200µA l0.2 V
IOZ Hi-Z Output Leakage CONV = VDD l±3 µA
COZ Hi-Z Output Capacitance CONV = VDD 4pF
ISOURCE Output Source Current VOUT = 0V –10 mA
ISINK Output Sink Current VOUT = VDD 10 mA
POWER REQUIREMENT
The l denotes the specifi cations which apply over the full operating temperature range,
otherwise specifi cations are at TA = 25°C. (Note 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VDD Supply Voltage l2.35 3.0 3.6 V
OVDD Digital Output Supply Voltage l1.0V VDD V
IDD Supply Current
Operational Mode, LTC2362
Operational Mode, LTC2361
Operational Mode, LTC2360
Sleep Mode
Sleep Mode
Sleep Mode
fSMPL = 500ksps
fSMPL = 250ksps
fSMPL = 100ksps
0°C to 70°C
–40°C to 85°C
–40°C to 125°C
l
l
l
l
l
l
1.1
0.75
0.5
0.1
0.1
0.1
2
1.5
1
2
2
5
mA
mA
mA
µA
µA
µA
PDPower Dissipation
Operational Mode, LTC2362
Operational Mode, LTC2361
Operational Mode, LTC2360
Sleep Mode
Sleep Mode
Sleep Mode
fSMPL = 500ksps
fSMPL = 250ksps
fSMPL = 100ksps
0°C to 70°C
–40°C to 85°C
–40°C to 125°C
l
l
l
l
l
l
3.3
2.25
1.5
0.3
0.3
0.3
7.2
5.4
3.6
7.2
7.2
18
mW
mW
mW
µW
µW
µW
LTC2360/LTC2361/LTC2362
5
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TIMING CHARACTERISTICS
The l denotes the specifi cations which apply over the full operating temperature
range, otherwise specifi cations are at TA = 25°C. (Note 4)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND.
Note 3: When pins AIN and VREF are taken below GND or above VDD,
they will be clamped by internal diodes. These products can handle input
currents greater than 100mA below GND or above VDD without latch-up.
Note 4: VDD = OVDD = VREF = 2.35V to 3.6V, fSMPL = fSMPL(MAX) and
fSCK = fSCK(MAX) unless otherwise specifi ed.
Note 5: Integral linearity is defi ned as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
SYMBOL PARAMETER CONDITIONS
LTC2360 LTC2361 LTC2362
UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX
fSMPL(MAX) Maximum Sampling Frequency (Notes 8, 9) l100 250 500 kHz
fSCK Shift Clock Frequency (Notes 8, 9) l10 25 50 MHz
tSCK Shift Clock Period l100 40 20 ns
tTHROUGHPUT Minimum Throughput Time, tACQ + tCONV l10 4 2 µs
tACQ Acquisition Time l2 1 0.5 µs
tCONV Conversion Time l8 3 1.5 µs
t1Minimum Positive CONV Pulse Width (Note 8) l8 3 1.5 µs
t2SCK↑ Setup Time After CONV↓(Note 8) l16 16 16 ns
t3SDO Enabled Time After CONV↓(Notes 8, 9) l16 16 16 ns
t4SDO Data Valid Access Time After SCK↓(Notes 8, 9, 10) l888ns
t5SCK Low Time (Note 11) l40% 40% 40% tSCK
t6SCK High Time (Note 11) l40% 40% 40% tSCK
t7SDO Data Valid Hold Time After SCK↓(Notes 8, 9, 10) l444 ns
t8SDO Into Hi-Z State Time After CONV↑(Notes 8, 9) 6 6 6 ns
Note 6: Linearity, offset and gain specifi cations apply for a single-ended
AIN input with respect to GND.
Note 7: Typical RMS noise at code transitions.
Note 8: Guaranteed by characterization. All input signals are specifi ed with
tr = tf = 2ns (10% to 90% of VDD) and timed from a voltage level of 1.6V.
Note 9: All timing specifi cations given are with a 10pF capacitance load.
With a capacitance load greater than this value, a digital buffer or latch
must be used.
Note 10: The time required for the output to cross the VIH or VIL voltage.
Note 11: Guaranteed by design, not subject to test.
Note 12: High temperatures degrade operating lifetimes. Operating lifetime
is derated at temperatures greater than 105°C.
LTC2360/LTC2361/LTC2362
6
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TYPICAL PERFORMANCE CHARACTERISTICS
Integral Nonlinearity
vs Output Code
Differential Nonlinearity
vs Output Code
Histogram for 16384 Conversions Supply Current vs Sample Rate
SINAD vs Input Frequency THD vs Input Frequency 48kHz Sine Wave 8192 FFT Plot
TA = 25°C, VDD = OVDD = VREF (LTC2360, Note 4)
OUTPUT CODE
0
0.6
0.8
3072 3584
236012 G01
–0.4
–0.2
0
0.2
0.4
–0.8
–0.6
512 1024 1536 2048 2560 4096
–1
INL (LSB)
1VDD = 3V
OUTPUT CODE
0
0.6
0.8
3072 3584
236012 G02
–0.4
–0.2
0
0.2
0.4
–0.8
–0.6
512 1024 1536 2048 2560 4096
–1
DNL (LSB)
1VDD = 3V
CODE
COUNT
10000
8000
4000
6000
2000
020472045 2049
236012 G04
20502046 2048
VDD = 3V
SAMPLING FREQUENCY (ksps)
0
SUPPLY CURRENT (µA)
500
400
200
300
100
04020 60 70
236012 G05
1003010 50
VDD = 3.6V
9080
INPUT FREQUENCY (kHz)
SINAD (dB)
236012 G07
74
73
72
70
71
69 1 10010
VDD = 3.6V
VDD = 2.35V
VDD = 3.0V
INPUT FREQUENCY (kHz)
THD (dB)
236012 G08
–78
–80
–82
–84
–90
–88
–86
–92 1 10010
VDD = 3.6V
VDD = 3.0V
VDD = 2.35V
INPUT FREQUENCY (kHz)
0
MAGNITUDE (dB)
0
–20
–60
–100
–40
–80
–120
–140 20 40
2306012 G09
503010
VDD = 3V
fSMPL = 100ksps
Integral and Differential Nonlinearity
vs Reference Voltage (TS8 Package)
REFERENCE VOLTAGE (V)
0.8
0.6
0.8
3.2
236012 G03
–0.4
–0.2
0
0.2
0.4
–0.8
–0.6
1.2 1.6 22.4 2.8 3.6
–1
NONLINEARITY ERROR (LSB)
1
VDD = 3.6V
MIN DNL
MAX DNL
MAX INL MIN INL
Reference Current vs Sample
Rate (TS8 Package)
SAMPLE RATE (ksps)
0
REFERENCE CURRENT (µA)
20.0
16.0
8.0
12.0
4.0
0.0 4020 60 70
236012 G06
1003010 50
VDD = 3.6V
9080
LTC2360/LTC2361/LTC2362
7
236012fa
Differential Nonlinearity
vs Output Code
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VDD = OVDD = VREF (LTC2361, Note 4)
Integral Nonlinearity
vs Output Code
Histogram for 16384 Conversions Supply Current vs Sample Rate
SINAD vs Input Frequency 124kHz Sine Wave 8192 FFT Plot
THD vs Input Frequency
CODE
COUNT
10000
8000
4000
6000
2000
020472045 2049
236012 G13
20502046 2048
VDD = 3V
SAMPLE RATE (ksps)
0
SUPPLY CURRENT (µA)
800
600
200
400
0200100
236012 G14
25015050
VDD = 3.6V
INPUT FREQUENCY (kHz)
SINAD (dB)
2306012 G16
74
72
73
70
71
69 1 100 100010
VDD = 3.6V
VDD = 2.35V
VDD = 3.0V
INPUT FREQUENCY (kHz)
THD (dB)
236012 G17
–71
–79
–77
–75
–73
–81
–83
–89
–87
–85
–91 VDD = 3.0V
1
VDD = 3.6V
100 1000
VDD = 2.35V
10
INPUT FREQUENCY (kHz)
0
MAGNITUDE (dB)
0
–20
–60
–100
–40
–80
–120
–140 50 100
2306012 G18
1257525
VDD = 3V
fSMPL = 250ksps
OUTPUT CODE
0
0.6
0.8
3072 3584
236012 G10
–0.4
–0.2
0
0.2
0.4
–0.8
–0.6
512 1024 1536 2048 2560 4096
–1
INL (LSB)
1VDD = 3V
OUTPUT CODE
0
0.6
0.8
3072 3584
236012 G11
–0.4
–0.2
0
0.2
0.4
–0.8
–0.6
512 1024 1536 2048 2560 4096
–1
DNL (LSB)
1VDD = 3V
Integral and Differential Nonlinearity
vs Reference Voltage (TS8 Package)
REFERENCE VOLTAGE (V)
0.8
0.6
0.8
3.2
236012 G12
–0.4
–0.2
0
0.2
0.4
–0.8
–0.6
1.2 1.6 22.4 2.8 3.6
–1
NONLINEARITY ERROR (LSB)
1
MIN DNL
MAX INL MIN INL
MAX DNL
VDD = 3.6V
Reference Current vs Sample
Rate (TS8 Package)
SAMPLE RATE (ksps)
0
REFERENCE CURRENT (µA)
50.0
40.0
20.0
30.0
10.0
0.0 100
236012 G15
25050
VDD = 3.6V
200150
LTC2360/LTC2361/LTC2362
8
236012fa
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VDD = OVDD = VREF (LTC2362, Note 4)
SINAD vs Input Frequency 248kHz Sine Wave 8192 FFT Plot
THD vs Input Frequency
INPUT FREQUENCY (kHz)
SINAD (dB)
2306012 G25
74
72
73
70
71
69 1 100 100010
VDD = 3.6V
VDD = 3.0V
VDD = 2.35V
INPUT FREQUENCY (kHz)
THD (dB)
2306012 G26
–67
–75
–71
–87
–79
–83
–91 1 100 100010
VDD = 3.6V
VDD = 3.0V
VDD = 2.35V
INPUT FREQUENCY (kHz)
0
MAGNITUDE (dB)
0
–20
–60
–100
–40
–80
–120
–140 100 200
2306012 G27
25015050
VDD = 3V
fSMPL = 500ksps
Differential Nonlinearity
vs Output Code
OUTPUT CODE
0
0.6
0.8
3072 3584
236012 G20
–0.4
–0.2
0
0.2
0.4
–0.8
–0.6
512 1024 1536 2048 2560 4096
–1
DNL (LSB)
1VDD = 3V
Histogram for 16384 Conversions Supply Current vs Sample Rate
CODE
COUNT
10000
8000
4000
6000
2000
020472045 2049
236012 G22
20502046 2048
VDD = 3V
SAMPLE RATE (ksps)
0
SUPPLY CURRENT (µA)
1200
600
800
1000
200
400
0400200
236012 G23
500300100
VDD = 3.6V
Integral Nonlinearity
vs Output Code
OUTPUT CODE
0
0.6
0.8
3072 3584
236012 G19
–0.4
–0.2
0
0.2
0.4
–0.8
–0.6
512 1024 1536 2048 2560 4096
–1
INL (LSB)
1VDD = 3V
Integral and Differential Nonlinearity
vs Reference Voltage (TS8 Package)
Reference Current vs Sample
Rate (TS8 Package)
REFERENCE VOLTAGE (V)
0.8
0.6
0.8
3.2
236012 G21
–0.4
–0.2
0
0.2
0.4
–0.8
–0.6
1.2 1.6 22.4 2.8 3.6
–1
NONLINEARITY ERROR (LSB)
1
VDD = 3.6V
MIN DNL
MAX INL MIN INL
MAX DNL
SAMPLE RATE (ksps)
0
REFERENCE CURRENT (µA)
80.0
60.0
20.0
40.0
0.0 100
236012 G24
50050
VDD = 3.6V
200 250 300 350 400 450150
LTC2360/LTC2361/LTC2362
9
236012fa
PIN FUNCTIONS
S6 Package
VDD (Pin 1): Positive Supply. The VDD range is 2.35V to
3.6V. VDD also defi nes the input span of the ADC, 0V to
VDD. Bypass to GND and to a solid ground plane with a
2.2F ceramic capacitor (or 2.2F tantalum in parallel
with 0.1F ceramic).
GND (Pin 2): Ground. The GND pin must be tied directly
to a solid ground plane.
AIN (Pin 3): Analog Input. AIN is a single-ended input with
respect to GND with a range from 0V to VDD.
SCK (Pin 4): Shift Clock Input. The SCK serial clock syn-
chronizes the serial data transfer. SDO data transitions on
the falling edge of SCK.
SDO (Pin 5): Three-State Serial Data Output. The A/D
conversion result is shifted out on SDO as a serial data
stream with MSB fi rst. The data stream consists of 12 bits
of conversion data followed by trailing zeros.
CONV (Pin 6): Convert Input. This active high signal starts
a conversion on the rising edge. The device automatically
powers down after conversion. A logic low on this input
enables the SDO pin, allowing the data to be shifted out.
TS8 Package
VDD (Pin 1): Positive Supply. The VDD range is 2.35V to
3.6V. Bypass to GND and to a solid ground plane with a
2.2F ceramic capacitor (or 2.2F tantalum in parallel
with 0.1F ceramic).
VREF (Pin 2): Reference Input. VREF defi nes the input
span of the ADC, 0V to VREF. The VREF range is 1.4V to
VDD. Bypass to GND and to a solid ground plane with a
2.2F ceramic capacitor (or 2.2F tantalum in parallel
with 0.1F ceramic).
GND (Pin 3): Ground. The GND pin must be tied directly
to a solid ground plane.
AIN (Pin 4): Analog Input. AIN is a single-ended input with
respect to GND with a range from 0V to VREF.
OVDD (Pin 5): Output Driver Supply for SDO. The OVDD
range is 1V to VDD. Bypass to GND and to a solid ground
plane with a 2.2F ceramic capacitor (or 2.2F tantalum in
parallel with 0.1F ceramic). OVDD can be driven separately
from VDD and OVDD can be higher than VDD.
SDO (Pin 6): Three-State Serial Data Output. The A/D
conversion result is shifted out on SDO as a serial data
stream with MSB fi rst. The data stream consists of 12 bits
of conversion data followed by trailing zeros.
SCK (Pin 7): Shift Clock Input. The SCK serial clock syn-
chronizes the serial data transfer. SDO data transitions on
the falling edge of SCK.
CONV (Pin 8): Convert Input. This active high signal starts
a conversion on the rising edge. The device automatically
powers down after conversion. A logic low on this input
enables the SDO pin, allowing the data to be shifted out.
LTC2360/LTC2361/LTC2362
10
236012fa
BLOCK DIAGRAM
236012 F01
t8
Hi-Z
1.6VCONV
SDO
Figure 1. SDO Into Hi-Z State After CONV Rising Edge Figure 2. SDO Data Valid Hold Time After SCK Falling Edge
Figure 3. SDO Data Valid Acess Time After SCK Falling Edge
VIH
236012 F02
VIL
t7
1.6VSCK
SDO
VIH
236012 F03
VIL
t4
1.6VSCK
SDO
TIMING DIAGRAMS
12-BIT ADC
VDD
AIN
S AND H
ANALOG
INPUT
RANGE
0V TO VREF
THREE-STATE
SERIAL
OUTPUT
PORT
TIMING
LOGIC
6
7
SDO
SCK
CONV
236012 BD
8
2.2µF
1
4
2
VREF
3
GND
OVDD
2.2µF
5
2.2µF
TS8 PACKAGE
++
LTC2360/LTC2361/LTC2362
11
236012fa
APPLICATIONS INFORMATION
DC PERFORMANCE
The noise of an ADC can be evaluated in two ways: sig-
nal-to-noise ratio (SNR) in the frequency domain and
histogram in the time domain. The LTC2360/LTC2361/
LTC2362 excel in both. Figure 5 demonstrates that the
LTC2360/LTC2361/LTC2362 have an SNR of over 73dB.
The noise in the time domain histogram is the transition
noise associated with a 12-bit resolution ADC which can
be measured with a fi xed DC signal applied to the input of
the ADC. The resulting output codes are collected over a
large number of conversions. The shape of the distribu-
tion of codes will give an indication of the magnitude of
the transition noise. In Figure 4, the distribution of output
codes is shown for a DC input that has been digitized
16384 times. The distribution is Gaussian and the RMS
code transition is about 0.32LSB. This corresponds to a
noise level of 73dB relative to a full scale of 3V.
DYNAMIC PERFORMANCE
The LTC2360/LTC2361/LTC2362 have excellent high speed
sampling capability. Fast fourier transform (FFT) test
techniques are used to test the ADCs’ frequency response,
distortion and noise at the rated throughput. By applying
a low distortion sine wave and analyzing the digital output
using an FFT algorithm, the ADCs’ spectral content can
be examined for frequencies outside the fundamental.
Figures 5 and 6 show typical LTC2361 and LTC2362 FFT
plots respectively.
Figure 4. Histogram for 16384 Conversions
Figure 5. LTC2361 FFT Plot Figure 6. LTC2362 FFT Plot
INPUT FREQUENCY (kHz)
0
MAGNITUDE (dB)
0
–20
–60
–100
–40
–80
–120
–140 50 100
236012 F05
12525 75
VDD = 3V
fSMPL = 250ksps
fIN = 124kHz
SINAD = 73dB
THD = –84dB
INPUT FREQUENCY (kHz)
0
MAGNITUDE (dB)
0
–20
–60
–100
–40
–80
–120
–140 100 200
236012 F06
25050 150
VDD = 3V
fSMPL = 500ksps
fIN = 248kHz
SINAD = 73dB
THD = –81dB
CODE
COUNT
10000
8000
4000
6000
2000
020472045 2049
236012 F04
20502046 2048
VDD = 3V
LTC2360/LTC2361/LTC2362
12
236012fa
APPLICATIONS INFORMATION
Signal-to-Noise plus Distortion Ratio
The signal-to-noise plus distortion ratio (SINAD) is the
ratio between the RMS amplitude of the fundamental
input frequency to the RMS amplitude of all other fre-
quency components at the A/D output. The output is band
limited to frequencies from above DC and below half the
sampling frequency. Figure 6 shows a typical FFT with a
500kHz sampling rate and a 248kHz input. The dynamic
performance is excellent for input frequencies up to and
beyond the Nyquist frequency of 250kHz.
Effective Number of Bits
The effective number of bits (ENOB) is a measurement of
the resolution of an ADC and is directly related to SINAD
by the equation:
ENOB =SINAD – 1.76
6.02
where ENOB is the effective number of bits of resolution
and SINAD is expressed in dB. At the maximum sampling
rate of 500kHz, the LTC2362 maintains ENOB above 11
bits up to the Nyquist input frequency of 250kHz (refer
to Figure 7).
Total Harmonic Distortion
The total harmonic distortion (THD) is the ratio of the RMS
sum of all harmonics of the input signal to the fundamental
itself. The out-of-band harmonics alias into the frequency
band between DC and half the sampling frequency. THD
is expressed as:
THD =20log V2
2+V3
2+V4
2+...Vn
2
V1
where V1 is the RMS amplitude of the fundamental
frequency and V2 through Vn are the amplitudes of the
second through nth harmonics. THD vs Input Frequency
is shown in Figure 8. The LTC2362 has excellent distortion
performance up to the Nyquist frequency and beyond.
Figure 7. LTC2362 ENOB and SINAD vs Input Frequency Figure 8. LTC2362 THD vs Input Frequency
INPUT FREQUENCY (kHz)
SINAD (dB)
ENOB
2306012 F07
74
72
73
70
71
12
67
69
68
11.67
11.34
11
1 100 100010
VDD = 3.6V
VDD = 3.0V
VDD = 2.35V
INPUT FREQUENCY (kHz)
THD (dB)
2306012 F08
–67
–75
–71
–87
–79
–83
–91 1 100 100010
VDD = 3.6V
VDD = 3.0V
VDD = 2.35V
LTC2360/LTC2361/LTC2362
13
236012fa
APPLICATIONS INFORMATION
Intermodulation Distortion
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce intermoduation distortion (IMD) in addition to
THD. IMD is the change in one sinusoidal input caused
by the presence of another sinusoidal input at a different
frequency.
If two pure sine waves of frequencies fa and fb are applied
to the ADC input, nonlinearities in the ADC transfer function
can create distortion products at the sum and difference
frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc.
For example, the 2nd order IMD terms include (fa ± fb).
If the two input sine waves are equal in magnitude, the
value (in decibels) of the 2nd order IMD products can be
expressed by the following formula:
IMD fa±fb
()
=20log Amplitude at fa±fb
()
Amplitude at fa
Peak Harmonic or Spurious Noise
The peak harmonic or spurious noise is the largest spectral
component excluding the input signal and DC. This value
is expressed in decibels relative to the RMS value of a
full-scale input signal.
Full-Power and Full-Linear Bandwidth
The full-power bandwidth is that input frequency at which
the amplitude of reconstructed fundamental is reduced by
3dB for full-scale input signal.
The full-linear bandwidth is the input frequency at which the
SINAD has dropped to 68dB (11 effective bits). The LTC2362
has been designed to optimize input bandwidth, allowing the
ADC to undersample input signals with frequencies above
the converter’s Nyquist frequency. The noise fl oor stays
very low at high frequencies; SINAD becomes dominated
by distortion at frequencies far beyond Nyquist.
Figure 9. LTC2362 Intermodulation Distortion Plot
INPUT FREQUENCY (kHz)
0
MAGNITUDE (dB)
0
–20
–60
–100
–40
–80
–120 100 200
236012 F09
25050 150
VDD = 3.6V
fSMPL = 500ksps
fa = 99kHz
fb = 101kHz
IMD = –76.5dB
LTC2360/LTC2361/LTC2362
14
236012fa
APPLICATIONS INFORMATION
OVERVIEW
The LTC2360/LTC2361/LTC2362 use a successive ap-
proximation algorithm and internal sample-and-hold circuit
to convert an analog signal to a 12-bit serial output. All
devices operate from a single 2.35V to 3.6V supply. The
conversion time of the devices is controlled by an internal
oscillator, which allows the LTC2360/LTC2361/LTC2362
to sample at a rate of 100ksps, 250ksps and 500ksps
respectively.
The LTC2360/LTC2361/LTC2362 contain a 12-bit, switched-
capacitor ADC, a sample-and-hold, a serial interface (see
Block Diagram) and are available in tiny 6- or 8-lead
TSOT-23 packages.
The S6 package of the LTC2360/LTC2361/LTC2362 uses
VDD as the reference and has an analog input range of 0V
to VDD. The ADC samples the analog input with respect to
GND and outputs the result through the serial interface.
The TS8 package provides two additional pins: a reference
pin, VREF, and an output supply pin, OVDD. The ADC can
operate with reduced spans down to 1.4V and achieve
342V resolution. OVDD controls the output swing of the
digital output pin, SDO, and allows the device to com-
municate with 1.8V, 2.5V or 3V digital systems.
SERIAL INTERFACE
The LTC2360/LTC2361/LTC2362 communicate with micro-
controllers, DSPs and other external circuitry via a 3-wire
interface. Figure 10 shows the operating sequence of the
serial interface.
Data Transfer
A rising CONV edge starts a conversion and disables SDO.
After the conversion, the ADC automatically goes into sleep
mode, drawing only leakage current.
CONV going low enables SDO and clocks out the MSB bit,
B11. SCK then synchronizes the data transfer with each
bit being transmitted on the falling SCK edge and can be
captured on the rising SCK edge. After completing the
data transfer, if further SCK clocks are applied with CONV
low, SDO will output zeros indefi nitely (see Figure 10). For
example, 16-clocks at SCK will produce the 12-bit data
and four trailing zeros on SDO.
SLEEP MODE
The LTC2360/LTC2361/LTC2362 enter sleep mode to save
power after each conversion if CONV remains high. In sleep
mode, all bias currents are shut down and only leakage
currents remain (about 0.1µA). The sample-and-hold is
in hold mode while the ADC is in sleep mode. The ADC
returns to sample mode after the falling edge of CONV
during power-up (see Figure 10).
Exiting Sleep Mode and Power-Up Time
By taking CONV low, the ADC powers up and acquires an
input signal completely after the aquisition time (tACQ).
After tACQ, the ADC can perform a conversion as described
in the Serial Interface section (see Figure 10).
1
RECOMMENDED HIGH OR LOW
Hi-Z STATE
234
t6
t5
t4t7t8
236012 F10
t3
9101112
B11
(MSB)
*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER SCK CLOCKS ARE
APPLIED WITH CONV LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY
BY TAKING CONV LOW, THE DEVICE POWERS UP
AND ACQUIRES AN INPUT ACCURATELY AFTER tACQ
SLEEP MODE
tCONV
CONV
SCK
SDO
t1tACQ
tTHROUGHPUT
t2
B10 B9 B3 B2 B1 B0*
Figure 10. LTC2360/LTC2361/LTC2362 Serial Interface Timing Diagram
LTC2360/LTC2361/LTC2362
15
236012fa
APPLICATIONS INFORMATION
ACHIEVING MICROPOWER PERFORMANCE
With typical operating currents of 0.5mA, 0.75mA and
1.1mA for the LTC2360/LTC2361/LTC2362 and automati-
cally entering sleep mode right after a conversion, these
devices achieve extremely low power consumption over
a wide range of sample rates (see Figure 11). The sleep
mode allows the supply current to drop with reduced
sample rate. Several things must be taken into account
to achieve such low power consumption.
Minimize Power Consumption in Sleep Mode
The LTC2360/LTC2361/LTC2362 enter sleep mode after
each conversion if CONV remains high and draw only
leakage current (see Figure 10). If the CONV input is not
running rail-to-rail, the input logic buffer will draw current.
This current may be large compared to the typical supply
current. To obtain the lowest supply current, bring the CONV
pin to GND when it is low and to VDD when it is high.
After the conversion with CONV staying high, the converter
is in sleep mode and draws only leakage current. The status
of the SCK input has no effect on supply current during
this time. For the best performance, hold SCK either high
or low while the ADC is converting.
Minimize the Device Active Time
In systems that have signifi cant time between conversions,
the ADC draws a minimal amount of power. Figures 12
and 13 show two ways to minimize the amount of time
the ADC draws power. In Figure 12, the ADC draws power
during tACQ and tCONV and is in sleep mode for the rest of
the time. The conversion results are available at the next
CONV falling edge. In Figure 13, the ADC draws twice the
power than that in Figure 12, but the conversion results
are available during tDATA. The user can use the fastest
SCK available in the system to shorten data transfer time,
tDATA as long as t4 and t7 are not violated.
SDO Loading
Capacitive loading on the digital output can increase power
consumption. A 100pF capacitor on the SDO pin can add
more than 50µA to the supply current at a 200kHz clock
frequency. An extra 50µA or so of current goes into charg-
ing and discharging the load capacitor. The same goes for
digital lines driven at a high frequency by any logic. The
C • V • f currents must be evaluated with the troublesome
ones minimized.
Figure 11. Supply Current vs Sample Rate
RECOMMENDED HIGH OR LOW
Hi-Z STATE
236012 F12
B11
CONV
SCK
SDO
12349101112
B10 B9 B3 B2 B1 B0
SAMPLING INPUT AND
TRANSFERRING DATA
EXECUTING A CONVERSION AND PUTTING
THE DEVICE INTO SLEEP MODE
tACQ tCONV SLEEP MODE
tTHROUGHPUT = tACQ + tCONV + tSLEEPMODE
Figure 12. Minimize the Time When the Device Draws Power, While the Conversion Results are Available After the Device Wakes Up
SAMPLE RATE (ksps)
SUPPLY CURRENT (µA)
236012 TA01b
1200
1000
800
400
600
200
01 100 100010
VDD = OVDD = VREF = 3.6V
TA = 25°C
LTC2361
LTC2362
LTC2360
LTC2360/LTC2361/LTC2362
16
236012fa
SINGLE-ENDED ANALOG INPUT
Driving the Analog Input
The analog input of the LTC2360/LTC2361/LTC2362 is
easy to drive. The input draws only one small current
spike while charging the sample-and-hold capacitor with
the ADC going into track mode. During the conversion,
the analog input draws only a small leakage current. If
the source impedance of the driving circuit is low, then
the input of the LTC2360/LTC2361/LTC2362 can be driven
directly. As source impedance increases, so will acquisi-
tion time. For minimum acquisition time with high source
impedance, a buffer amplifi er should be used. The main
requirement is that the amplifi er driving the analog input
must settle after the small current spike before the next
conversion starts (settling time must be less than tACQ
for full throughput rate). While choosing an input ampli-
fi er, also keep in mind the amount of noise and harmonic
distortion the amplifi er contributes.
Choosing an Input Amplifi er
Choosing an input amplifi er is easy if a few requirements
are taken into consideration. First, to limit the magnitude
of the voltage spike seen by the amplifi er from charging
the sampling capacitor, choose an amplifi er that has a low
output impedance (<100Ω) at the closed-loop bandwidth
frequency. For example, if an amplifi er is used in a gain
of 1 and has a unity-gain bandwidth of 10MHz, then the
output impedance at 10MHz must be less than 100Ω. The
second requirement is that the closed-loop bandwidth must
be greater than 8MHz to ensure adequate small-signal
settling for full throughput rate. If slower op amps are
used, more time for settling can be provided by increasing
the time between conversions. The best choice for an op
amp to drive the LTC2360/LTC2361/LTC2362 will depend
on the application. Generally, applications fall into two
categories: AC applications where dynamic specifi cations
are most critical and time domain applications where DC
accuracy and settling time are most critical. The follow-
ing list is a summary of the op amps that are suitable for
driving the LTC2360/LTC2361/LTC2362. (More detailed
information is available on the Linear Technology website at
www.linear.com.)
LTC1566-1: Low Noise 2.3MHz Continuous Time Low-
pass Filter.
LT
®
1630: Dual 30MHz Rail-to-Rail Voltage FB Amplifi er.
2.7V to ±15V supplies. Very high AVOL, 500µV offset and
520ns settling to 0.5LSB for a 4V swing. THD and noise
are –93dB to 40kHz and below 1LSB to 320kHz (AV =
1, 2VP-P into 1k, VS = 5V), making the part excellent for
AC applications (to 1/3 Nyquist) where rail-to-rail perfor-
mance is desired. Quad version is available as LT1631.
LTC6241: Dual 18MHz, Low Noise, Rail-to-Rail, CMOS
Voltage FB Amplifi er. 2.8V to 6V supplies. Very high AVOL
and 125µV offset. It is suitable for applications with a single
5V supply. Quad version is available as LTC6242.
LT1797: Unity-Gain Stable 10MHz, Rail-to-Rail Voltage
Feedback Amplifi er.
LT1801: 180MHz GBWP, –75dBc at 500kHz, 2mA/Ampli-
fi er, 8.5nV/√Hz.
LT6203: 100MHz GBWP, –80dBc Distortion at 1MHz, Unity-
Gain Stable, R-R In and Out, 3mA/Amplifi er, 1.9nV/√Hz.
APPLICATIONS INFORMATION
RECOMMENDED HIGH OR LOW
Hi-Z STATE
236012 F13
B11
CONV
SCK
SDO
12349101112
B10 B9 B3 B2 B1 B0
DATA TRANSFER
ACQUIRE
INPUT
EXECUTE CONVERSION EXECUTING A DUMMY CONVERSION AND
PUT THE DEVICE INTO SLEEP MODE
tDATA tCONV
tCONV
tACQ SLEEP MODE
tTHROUGHPUT = tACQ + 2 • tCONV + tDATA + tSLEEPMODE
RECOMMENDED HIGH OR LOW
Figure 13. Minimize the Time When the Device Draws Power, While the Conversion Results are Available Right After Conversion
LTC2360/LTC2361/LTC2362
17
236012fa
Input Filtering and Source Impedance
The noise and the distortion of the input amplifi er and
other circuitry must be considered since they will add to
the LTC2360/LTC2361/LTC2362 noise and distortion. The
small-signal bandwidth of the sample-and-hold circuit is
10MHz. Any noise or distortion products that are pres-
ent at the analog inputs will be summed over this entire
bandwidth. Noisy input circuitry should be fi ltered prior
to the analog inputs to minimize noise. A simple 1-pole
RC fi lter is suffi cient for many applications. For example,
Figure 14 shows a 220pF capacitor from AIN to ground
and a 51Ω source resistor to limit the input bandwidth
to 10MHz. The 220pF capacitor also acts as a charge
reservoir for the input sample-and-hold and isolates the
ADC input from sampling-glitch sensitive circuitry. High
quality capacitors and resistors should be used since these
components can add distortion. NPO and silvermica type
dielectric capacitors have excellent linearity. Carbon surface
mount resistors can generate distortion from self heating
and from damage that may occur during soldering. Metal
fi lm surface mount resistors are much less susceptible to
both problems. When high amplitude unwanted signals
are close in frequency to the desired signal frequency,
a multiple pole fi lter is required. High external source
resistance, combined with the 20pF of input capacitance,
will reduce the rated 10MHz bandwidth and increase
acquisition time beyond 500ns.
APPLICATIONS INFORMATION
Reference Input
On the TS8 package of the LTC2360/LTC2361/LTC2362,
the voltage on the VREF pin defi nes the full-scale range
of the ADC. The reference voltage can range from VDD
down to 1.4V.
Input Range
The analog input of the LTC2360/LTC2361/LTC2362 is
driven single-ended with respect to GND from a single
supply. The input may swing up to VDD for the S6 package
and to VREF for the TS8 package. The 0V to 2.5V range is
also ideally suited for single-ended input use with VDD or
VREF = 2.5V for single supply applications. If the difference
between the AIN input and GND exceeds VDD for the S6
package or VREF for the TS8 package, the output code will
stay fi xed at all ones, and if this difference goes below 0V,
the output code will stay fi xed at all zeros.
Figure 15 shows the ideal input/output characteristics for
the LTC2360/LTC2361/LTC2362. The code transitions oc-
cur midway between successive integer LSB values (i.e.,
0.5LSB, 1.5LSB, 2.5LSB, …, FS – 1.5LSB). The output
code is straight binary with 1LSB = VDD/4096 for the S6
package and 1LSB = VREF/4096 for the TS8 package.
VDD
GND
AIN
CONV
SDO
SCK
1
2
3
6
5
4
LTC2362
220pF
51
2.2µF
236012 F14
Figure 14. RC Input Filter
INPUT VOLTAGE (V)
0
1LSB
UNIPOLAR OUTPUT CODE
111...111
111...110
236012 F15
000...001
000...000
FS – 1LSB
Figure 15. Transfer Characteristics
LTC2360/LTC2361/LTC2362
18
236012fa
APPLICATIONS INFORMATION
BOARD LAYOUT AND BYPASSING
Wire wrap boards are not recommended for high resolution
and/or high speed A/D converters. To obtain the best per-
formance from the LTC2360/LTC2361/LTC2362, a printed
circuit board with ground plane is required. Layout for the
printed circuit board should ensure that digital and analog
signal lines are separated as much as possible. In particular,
care should be taken not to run any digital track alongside
an analog signal track or underneath the ADC. The analog
input should be screened by the ground plane.
High quality tantalum and ceramic bypass capacitors
should be used at the VDD pin as shown in the Block
Diagram on the fi rst page of this data sheet. For optimum
performance, a 2.2µF surface mount AVX capacitor with
a 0.1µF ceramic is recommended for the VDD and VREF
pins. Alternatively, 2.2µF ceramic chip capacitors such as
Murata GRM235Y5V106Z016 may be used. The capacitors
must be located as close to the pins as possible. The traces
connecting the pins and the bypass capacitors must be
kept short and should be made as wide as possible.
Figure 16 shows the recommended system ground con-
nections. All analog circuitry grounds should be terminated
at the LTC2360/LTC2361/LTC2362. The ground return
from the LTC2360/LTC2361/LTC2362 to the power supply
should be low impedance for noise free operation. Digital
circuitry grounds must be connected to the digital supply
common.
In applications where the ADC data outputs and control sig-
nals are connected to a continuously active microprocessor
bus, it is possible to get errors in the conversion results.
These errors are due to feedthrough from the micropro-
cessor to the successive approximation comparator. The
problem can be eliminated by forcing the microprocessor
into a wait state during conversion or by using three-state
buffers to isolate the ADC data bus.
Figure 16. Power Supply Ground Practice
236012 F16
GND
AIN
VDD
CAIN
CONV
SDO
SCK
CVDD
PIN 1
VIAS TO GROUND PLANE
+
2.2μF
LTC2360/LTC2361/LTC2362
19
236012fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
PACKAGE DESCRIPTION
S6 Package
6-Lead Plastic TSOT-23
(Reference LTC DWG # 05-08-1636)
1.50 – 1.75
(NOTE 4)
2.80 BSC
0.30 – 0.45
6 PLCS (NOTE 3)
DATUM ‘A’
0.09 – 0.20
(NOTE 3) S6 TSOT-23 0302 REV B
2.90 BSC
(NOTE 4)
0.95 BSC
1.90 BSC
0.80 – 0.90
1.00 MAX 0.01 – 0.10
0.20 BSC
0.30 – 0.50 REF
PIN ONE ID
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. JEDEC PACKAGE REFERENCE IS MO-193
3.85 MAX
0.62
MAX
0.95
REF
RECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
1.4 MIN
2.62 REF
1.22 REF
TS8 Package
8-Lead Plastic TSOT-23
(Reference LTC DWG # 05-08-1637)
1.50 – 1.75
(NOTE 4)
2.80 BSC
0.22 – 0.36
8 PLCS (NOTE 3)
DATUM ‘A’
0.09 – 0.20
(NOTE 3) TS8 TSOT-23 0802
2.90 BSC
(NOTE 4)
0.65 BSC
1.95 BSC
0.80 – 0.90
1.00 MAX 0.01 – 0.10
0.20 BSC
0.30 – 0.50 REF
PIN ONE ID
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. JEDEC PACKAGE REFERENCE IS MO-193
3.85 MAX
0.52
MAX
0.65
REF
RECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
1.4 MIN
2.62 REF
1.22 REF
LTC2360/LTC2361/LTC2362
20
236012fa
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2008
LT 0809 REV A • PRINTED IN USA
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ADCs
LTC1403/LTC1403A 12-/14-Bit, 2.8Msps Serial Sampling ADC 3V, Differential Input, 12mW, MSOP Package
LTC1407/LTC1407A 12-/14-Bit, 3Msps Simultaneous Sampling ADC 3V, 2-Channel Differential, 14mW, MSOP Package
LTC1860 12-Bit, 250ksps Serial ADC 5V Supply, 1-Channel, 4.3mW, MSOP-8 Package
LTC1860L 12-Bit, 150ksps Serial ADC 3V Supply, 1-Channel, 1.3mW, MSOP-8 Package
LTC1861 12-Bit, 250ksps Serial ADC 5V Supply, 2-Channel, 4.3mW, MSOP-8 Package
LTC1861L 12-Bit, 150ksps Serial ADC 3V Supply, 2-Channel, 1.3mW, MSOP-8 Package
LTC1863 12-Bit, 200ksps Serial ADC 8-Channel ADC 5V Supply, 6.5mW, SSOP-16 Package, Pin Compatible to LTC1863L,
LTC1867
LTC1863L 12-Bit, 250ksps Serial ADC 8-Channel ADC 5V Supply, 2.2mW, SSOP-16 Package, Pin Compatible to LTC1863,
LTC1867L
LTC1864/LTC1865 16-Bit, 250ksps Serial ADC 5V Supply, 1 and 2 Channel, 4.3mW, MSOP Package
LTC1867 16-Bit, 200ksps Serial ADC 8-Channel ADC 5V Supply, 6.5mW, SSOP-16 Package, Pin Compatible to LTC1863,
LTC1867L
LTC1867L 16-Bit, 175ksps Serial ADC 8-Channel ADC 3V Supply, 2.2mW, SSOP-16 Package, Pin Compatible to LTC1863L,
LTC1867
LTC2355/LTC2356 12-/14-Bit, 3.5Msps Serial ADCs 3.3V Supply, Differential Input, 18mW, MSOP Package
LTC2365/LTC2366 12-Bit, 1/3 Msps Serial ADCs in TSOT23 2.35V to 3.6V Supply, Pin and Software Compatible to
LTC2360/LTC2361/LTC2362
DACs
LTC1592 16-Bit, Serial SoftSpan™ IOUT DAC ±1LSB INL/DNL, Software Selectable Spans
LTC1666/LTC1667/LTC1668 12-/14-/16-Bit, 50Msps DACs 87dB SFDR, 20ns Settling Time
LTC2630 12-/10-/8-Bit Single VOUT DACs SC70 6-Pin Package, Internal Reference, ±1LSB INL (12 Bits)
References
LT1460-2.5 Micropower Series Voltage Reference 0.1% Initial Accuracy, 10ppm Drift
LT1461-2.5 Precision Voltage Reference 0.05% Initial Accuracy, 3ppm Drift
LT1790-2.5 Micropower Series Reference in SOT-23 0.05% Initial Accuracy, 10ppm Drift
LT6660 Ultra-Tiny Micropower Series Reference 2mm × 2mm DFN Package, 0.2% Initial Accuracy, 10ppm Drift
SoftSpan is a trademark of Linear Technology Corporation.
Recommended AC Test Circuitry for the LTC2362
4.7µF
±1.5V AC INPUT 50
5%
1k
1%
1k
1%
220pF
2200pF
236012 TA02
TO
MCU
LTC2362
CONV
SCK
SDO
AIN
VDD
3V
GND
4.7µF 2.2µF
+ +
