OBSOLETE 2, 4 MEG x 72 BUFFERED DRAM DIMMs DRAM MODULE MT9LD272(X), MT18LD472(F)(X) For the latest data sheet, please refer to the Micron Web site: www.micronsemi.com/datasheets/datasheet.html FEATURES PIN ASSIGNMENT (Front View) * JEDEC-standard ECC pinout in a 168-pin, dual inline memory module (DIMM) * 16MB (2 Meg x 72) and 32MB (4 Meg x 72) * High-performance CMOS silicon-gate process * Single +3.3V 0.3V power supply * All inputs, outputs and clocks are TTL-compatible * Refresh modes: RAS#-ONLY, CAS#-BEFORE- RAS# (CBR) and HIDDEN * All inputs are buffered except RAS# * 2,048 cycles (11 row, 11 column addresses) or 4,096 cycles (12 row, 10 column addresses) * FAST-PAGE-MODE (FPM) or Extended Data-Out (EDO) PAGE MODE access cycles OPTIONS 168-Pin DIMM PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 MARKING * Package 168-pin DIMM (gold) G * Timing 50ns access 60ns access -5* -6 * Access Cycles FAST PAGE MODE EDO PAGE MODE None X * Refresh 2,048 cycles across 32ms 4,096 cycles across 64ms (32MB only) None F * EDO version only KEY TIMING PARAMETERS EDO Operating Mode SPEED -5 -6 tRC 84ns 104ns tRAC 50ns 60ns tPC 20ns 25ns tAA 30ns 35ns tCAC tCAS 18ns 20ns 8ns 10ns FPM Operating Mode SPEED -6 NOTE: tRC tRAC tPC tAA tCAC tRP 110ns 60ns 35ns 35ns 20ns 40ns Pin symbols in parentheses are not used on these modules but may be used for other modules in this product family. They are for reference only. 2, 4 Meg x 72 Buffered DRAM DIMMs DM33.p65 - Rev. 2/99 1 SYMBOL VSS DQ0 DQ1 DQ2 DQ3 VDD DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VDD DQ14 DQ15 DQ16 DQ17 VSS NC NC VDD WE0# CAS0# RFU RAS0# OE0# VSS A0 A2 A4 A6 A8 A10 NC (A12) VDD RFU RFU PIN 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 SYMBOL VSS OE2# RAS2# CAS4# RFU WE2# VDD NC NC DQ18 DQ19 VSS DQ20 DQ21 DQ22 DQ23 VDD DQ24 RFU RFU RFU RFU DQ25 DQ26 DQ27 VSS DQ28 DQ29 DQ30 DQ31 VDD DQ32 DQ33 DQ34 DQ35 VSS PD1 PD3 PD5 PD7 ID0 VDD PIN 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 SYMBOL VSS DQ36 DQ37 DQ38 DQ39 VDD DQ40 DQ41 DQ42 DQ43 DQ44 VSS DQ45 DQ46 DQ47 DQ48 DQ49 VDD DQ50 DQ51 DQ52 DQ53 VSS NC NC VDD RFU NC RFU NC RFU VSS A1 A3 A5 A7 A9 A11 NC (A13) VDD RFU B0 PIN 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 SYMBOL VSS RFU NC NC RFU PDE# VDD NC NC DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 VDD DQ60 RFU RFU RFU RFU DQ61 DQ62 DQ63 VSS DQ64 DQ65 DQ66 DQ67 VDD DQ68 DQ69 DQ70 DQ71 VSS PD2 PD4 PD6 PD8 ID1 VDD Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc. OBSOLETE 2, 4 MEG x 72 BUFFERED DRAM DIMMs PART NUMBERS FAST PAGE MODE EDO Operating Mode FAST-PAGE-MODE operations allow faster data operations (READ or WRITE) within a row-addressdefined page boundary. The FAST-PAGE-MODE cycle is always initiated with a row address strobed in by RAS#, followed by a column address strobed in by CAS#. Additional columns may be accessed by providing valid column addresses, strobing CAS# and holding RAS# LOW, thus executing faster memory cycles. Returning RAS# HIGH terminates the FAST-PAGEMODE operation. PART NUMBER MT9LD272G-x X MT18LD472G-x X MT18LD472FG-x X x = speed CONFIGURATION 2 Meg x 72 ECC 4 Meg x 72 ECC 4 Meg x 72 ECC REFRESH 2K Refresh 2K Refresh 4K Refresh FPM Operating Mode PART NUMBER MT9LD272G-x MT18LD472G-x MT18LD472FG-x x = speed CONFIGURATION 2 Meg x 72 ECC 4 Meg x 72 ECC 4 Meg x 72 ECC REFRESH 2K Refresh 2K Refresh 4K Refresh EDO PAGE MODE EDO PAGE MODE, designated by the "X" version, is an accelerated FAST-PAGE-MODE cycle. The primary advantage of EDO is the availability of data-out even after CAS# goes back HIGH. EDO provides for CAS# precharge time (tCP) to occur without the output data going invalid. This elimination of CAS# output control provides for pipelined READs. FAST-PAGE-MODE modules have traditionally turned the output buffers off (High-Z) with the rising edge of CAS#. EDO-PAGE-MODE DRAMs operate like FAST-PAGE-MODE DRAMs, except data will remain valid or become valid after CAS# goes HIGH during READs, provided RAS# and OE# are held LOW. If OE# is pulsed while RAS# and CAS# are LOW, data will toggle from valid data to High-Z and back to the same valid data. If OE# is toggled or pulsed after CAS# goes HIGH while RAS# remains LOW, data will transition to and remain High-Z. During an application, if the DQ outputs are wire OR'd, OE# must be used to disable idle banks of DRAMs. Alternatively, pulsing WE# to the idle banks during CAS# HIGH time will also High-Z the outputs. Independent of OE# control, the outputs will disable after tOFF, which is referenced from the rising edge of RAS# or CAS#, whichever occurs last. (Refer to the 4 Meg x 4 [MT4LC4M4E8] DRAM data sheet for additional information on EDO functionality.) GENERAL DESCRIPTION The MT9LD272(X) and MT18LD472(F)(X) are randomly accessed 16MB and 32MB memories organized in a x72 configuration. They are specially processed to operate from 3V to 3.6V for low-voltage memory systems. During READ or WRITE cycles, each bit is uniquely addressed through the address bits. Two copies of address 0 (A0 and B0) are defined to allow maximum performance for four-byte applications which interleave between two four-byte banks. A0 is common to the DRAMs used for DQ0-DQ35, while B0 is common to the DRAMs used for DQ36-DQ71. RAS# is used to latch the first 11/12 bits and CAS# the latter 10/11 bits. READ and WRITE cycles are selected with the WE# input. A logic HIGH on WE# dictates read mode, while a logic LOW on WE# dictates write mode. During a WRITE cycle, data-in (D) is latched by the falling edge of WE# or CAS#, whichever occurs last. An EARLY WRITE occurs when WE# is taken LOW prior to CAS# falling. A LATE WRITE or READ-MODIFY-WRITE occurs when WE# falls after CAS# was taken LOW. During EARLY WRITE cycles, the data-outputs (Q) will remain High-Z regardless of the state of OE#. During LATE WRITE or READ-MODIFY-WRITE cycles, OE# must be taken HIGH to disable the data-outputs prior to applying input data. If a LATE WRITE or READMODIFY-WRITE is attempted while keeping OE# LOW, no WRITE will occur, and the data-outputs will drive read data from the accessed location. 2, 4 Meg x 72 Buffered DRAM DIMMs DM33.p65 - Rev. 2/99 REFRESH Returning RAS# and CAS# HIGH terminates a memory cycle and decreases chip current to a reduced standby level. Also, the chip is preconditioned for the next cycle during the RAS# HIGH time. Correct memory cell data is preserved by maintaining power and executing any RAS# cycle (READ, WRITE) or RAS# REFRESH cycle (RAS#-ONLY, CBR or HIDDEN) so that all combinations of RAS# addresses are executed at least every tREF, regardless of sequence. The CBR REFRESH cycle will invoke the internal refresh counter for automatic RAS# addressing. 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc. OBSOLETE 2, 4 MEG x 72 BUFFERED DRAM DIMMs FUNCTIONAL BLOCK DIAGRAM MT9LD272(X) (16MB) A0 D WE0# OE0# D DQ8-DQ15 A0 DQ0-DQ7 A0 DQ0-DQ7 A0 DQ0-DQ7 A0 DQ0-DQ7 A0 DQ0-DQ7 WE# WE# WE# WE# WE# OE# D RAS0# CAS0# DQ0-DQ7 D U1 DQ16-DQ23 U2 OE# OE# U3 DQ24-DQ31 OE# U4 DQ32-DQ39 OE# U5 RAS# RAS# RAS# RAS# RAS# CAS# A1A10 CAS# A1A10 CAS# A1A10 CAS# A1A10 CAS# A1A10 10 10 10 10 10 A10 A10-A1 D 10 A1 DQ40-DQ47 B0 D WE2# OE2# D RAS2# CAS4# D DQ56-DQ63 DQ64-DQ71 A0 DQ0-DQ7 A0 DQ0-DQ7 A0 DQ0-DQ7 A0 DQ0-DQ7 WE# WE# WE# WE# OE# D DQ48-DQ55 U6 U7 OE# OE# U8 OE# U9 RAS# RAS# RAS# RAS# CAS# A1A10 CAS# A1A10 CAS# A1A10 CAS# A1A10 10 10 10 PRESENCE DETECT U1-U9 = MT4LC2M8B1 FAST PAGE MODE PD1-PD8 VDD U1-U9, Buffers VSS U1-U9, Buffers U1-U9 = MT4LC2M8E7 EDO PAGE MODE GENERATOR E# 10 PDE# NOTE: 1. All inputs, with the exception of RAS#, are redriven. 2. D = line buffers. 2, 4 Meg x 72 Buffered DRAM DIMMs DM33.p65 - Rev. 2/99 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc. OBSOLETE 2, 4 MEG x 72 BUFFERED DRAM DIMMs FUNCTIONAL BLOCK DIAGRAM MT18LD472(F)(X) (32MB) A0 D WE0# D DQ0-DQ3 DQ4-DQ7 DQ8-DQ11 DQ12-DQ15 DQ16-DQ19 DQ20-DQ23 DQ24-DQ27 DQ28-DQ31 DQ32-DQ35 A0 DQ0-DQ3 A0 DQ0-DQ3 A0 DQ0-DQ3 A0 DQ0-DQ3 A0 DQ0-DQ3 A0 DQ0-DQ3 A0 DQ0-DQ3 A0 DQ0-DQ3 A0 DQ0-DQ3 WE# WE# WE# WE# WE# WE# WE# WE# WE# U1 OE0# D RAS0# CAS0# D U3 U2 U4 U5 U6 U7 U9 U8 OE# OE# OE# OE# OE# OE# OE# OE# OE# RAS# RAS# RAS# RAS# RAS# RAS# RAS# RAS# RAS# CAS# A1A11 CAS# A1A11 CAS# A1A11 CAS# A1A11 CAS# A1A11 CAS# A1A11 CAS# A1A11 CAS# A1A11 CAS# A1A11 DQ36-DQ39 DQ40-DQ43 DQ44-DQ47 DQ48-DQ51 DQ52-DQ55 DQ56-DQ59 DQ60-DQ63 DQ64-DQ67 DQ68-DQ71 A11 A11-A1 D A1 B0 A0 D WE2# D DQ0-DQ3 WE# A0 DQ0-DQ3 D RAS2# CAS4# D DQ0-DQ3 WE# WE# U10 OE2# A0 A0 DQ0-DQ3 WE# U12 U11 A0 DQ0-DQ3 WE# U13 A0 DQ0-DQ3 DQ0-DQ3 WE# WE# U14 A0 U15 A0 DQ0-DQ3 DQ0-DQ3 WE# WE# U16 A0 U17 U18 OE# OE# OE# OE# OE# OE# OE# OE# OE# RAS# RAS# RAS# RAS# RAS# RAS# RAS# RAS# RAS# CAS# A1A11 CAS# A1A11 CAS# A1A11 CAS# A1A11 CAS# A1A11 CAS# A1A11 CAS# A1A11 CAS# A1A11 CAS# A1A11 PRESENCEDETECT GENERATOR E# PDE# PD1-PD8 MT18LD472G (2K REFRESH) U1-U18 = MT4LC4M4B1 FAST PAGE MODE MT18LD472FG (4K REFRESH) U1-U18 = MT4LC4M4A1 FAST PAGE MODE MT18LD472G X (2K REFRESH) U1-U18 = MT4LC4M4E8 EDO PAGE MODE MT18LD472FG X (4K REFRESH) U1-U18 = MT4LC4M4E9 EDO PAGE MODE VDD U1-U18, Buffers VSS U1-U18, Buffers NOTE: 1. All inputs with the exception of RAS# are redriven. 2. D = line buffers. 2, 4 Meg x 72 Buffered DRAM DIMMs DM33.p65 - Rev. 2/99 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc. OBSOLETE 2, 4 MEG x 72 BUFFERED DRAM DIMMs PIN DESCRIPTIONS PIN NUMBERS 30, 45 SYMBOL RAS0#, RAS2# TYPE Input 28, 46 CAS0#, CAS4# Buffered Input 27, 48 WE0#, WE2# Buffered Input 31, 44 OE0#, OE2# Buffered Input 33-38, 117-122, 126 A0-A11, B0 Buffered Input 2-5, 7-11, 13-17, 19-22, 52-53, 55-58, 60, 65-67, 69-72, 74-77, 86-89, 91-95, 97-101, 103-106, 136-137, 139-142, 144, 149-151, 153-156, 158-161 79-82, 163-166 DQ0-DQ71 Input/ Output PD1-PD8 Buffered Output 29, 41-42, 47, 61-64, 111, 113, 115, 125, 128, 131, 145-148 6, 18, 26, 40, 49, 59, 73, 84, 90, 102, 110, 124, 133, 143, 157, 168 1, 12, 23, 32, 43, 54, 68, 78, 85, 96, 107, 116, 127, 138, 152, 162 83, 167 RFU - VDD Supply Power Supply: +3.3V 0.3V. VSS Supply Ground. ID0, ID1 Output 132 PDE# Input ID Bits: ID0 = DIMM type. ID1 = Refresh Mode. These pins will be either left floating (NC) or they will be grounded (VSS). Presence-Detect Enable: PDE# is the READ control for the buffered presence-detect pins. 2, 4 Meg x 72 Buffered DRAM DIMMs DM33.p65 - Rev. 2/99 DESCRIPTION Row-Address Strobe: RAS# is used to clock-in the rowaddress bits. Two RAS# inputs allow for one x72 bank or two x36 banks. Column-Address Strobe: CAS# is used to clock-in the column-address bits, enable the DRAM output buffers and strobe the data inputs on WRITE cycles. Write Enable: WE# is the READ/WRITE control for the DQ pins. WE0# controls DQ0-DQ35. WE2# controls DQ36-DQ71. If WE# is LOW prior to CAS# going LOW, the access is an EARLY WRITE cycle. If WE# is HIGH while CAS# is LOW, the access is a READ cycle, provided OE# is also LOW. If WE# goes LOW after CAS# goes LOW, then the cycle is a LATE WRITE cycle. A LATE WRITE cycle is generally used in conjunction with a READ cycle to form a READ-MODIFY-WRITE cycle. Output Enable: OE# is the input/output control for the DQ pins. OE0# controls DQ0-DQ35. OE2# controls DQ36-DQ71. These signals may be driven, allowing LATE WRITE cycles. Address Inputs: These inputs are multiplexed and clocked by RAS# and CAS#. A0 is common to the DRAMs used for DQ0-DQ35 while B0 is common to the DRAMs used for DQ36-DQ71 Data I/O: For WRITE cycles, DQ0-DQ71 act as inputs to the addressed DRAM location. For READ access cycles, DQ0-DQ71 act as outputs for the addressed DRAM location. Presence-Detect: These pins are read by the host system and tell the system the DIMM's personality. They will be either no connect (1), or they will be driven to VOL (0). Reserved for Future Use: These pins should be left unconnected. 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc. OBSOLETE 2, 4 MEG x 72 BUFFERED DRAM DIMMs PRESENCE-DETECT TRUTH TABLE CHARACTERISTICS PRESENCE-DETECT PIN (PDx) Module Density Module Configuration Row/Column Addresses 1 2 3 4 0MB No module installed X 1 1 1 1 8MB 1 Meg x 64/72 10/9 1 1 0 0 8MB 16MB 1 Meg x 64/72 2 Meg x 64/72 10/10 10/10 0 1 0 0 1 1 0 0 * 16MB 2 Meg x 64/72 4 Meg x 64/72 11/10 11/10 1 0 0 1 0 0 1 1 4 Meg x 64/72 8 Meg x 64/72 12*/11* 12*/11* 1 0 1 0 0 1 1 1 32MB * 32MB 64MB Page Mode Access Timing Refresh Control Data Width ID0 ID1 5 6 7 70ns 0 1 60ns 1 1 50ns 0 0 Fast Page Mode 0 EDO Page Mode 1 Standard 8 Vss x64, No Parity Vss 1 x72, ECC Vss 0 NOTE: VSS = Ground; VOL = 0; NC = 1. * This addressing includes a redundant address to allow mixing of 12/10 and 11/11 DRAMs with the same presence-detect setting. 2, 4 Meg x 72 Buffered DRAM DIMMs DM33.p65 - Rev. 2/99 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc. OBSOLETE 2, 4 MEG x 72 BUFFERED DRAM DIMMs ABSOLUTE MAXIMUM RATINGS* *Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Voltage on VDD Pin Relative to VSS ........ -1V to +4.6V Voltage on Inputs or I/O Pins Relative to VSS ..................................... -1V to +4.6V Operating Temperature, TA (ambient) .. 0C to +70C Storage Temperature (plastic) ........... -55C to +125C Power Dissipation ................................................... 9W DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (Notes: 1) (VDD = +3.3V 0.3V) PARAMETER/CONDITION SYMBOL MIN MAX SUPPLY VOLTAGE VDD 3 3.6 V INPUT HIGH VOLTAGE: Logic 1; All inputs VIH 2 VDD + 0.3 V 36 INPUT LOW VOLTAGE: Logic 0; All inputs VIL -0.5 0.8 V 36 CAS0#, CAS4#, A0-A11, B0, PDE#, WE0#, WE2#, OE0#, OE2# II1 -2 2 A RAS0#-RAS3# II2 -18 18 A DQ0-DQ71, PD1-PD8 IOZ -5 5 A VOH 2.4 - V VOL - 0.4 V INPUT LEAKAGE CURRENT: Any input 0V VIN VDD + 0.3V (All other pins not under test = 0V) OUTPUT LEAKAGE CURRENT: DQ is disabled; 0V VOUT VDD + 0.3V OUTPUT LEVELS: Output High Voltage (IOUT = -2mA) Output Low Voltage (IOUT = 2mA) 2, 4 Meg x 72 Buffered DRAM DIMMs DM33.p65 - Rev. 2/99 7 UNITS NOTES Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc. OBSOLETE 2, 4 MEG x 72 BUFFERED DRAM DIMMs 2,048-CYCLE REFRESH ICC OPERATING CONDITIONS AND MAXIMUM LIMITS (Notes: 1, 5, 6) (VDD = +3.3V 0.3V) MAX PARAMETER/CONDITION SYMBOL SIZE -5* -6 UNITS NOTES STANDBY CURRENT: TTL (RAS# = CAS# = VIH) ICC1 16MB 32MB 72 90 72 90 mA STANDBY CURRENT: CMOS (RAS# = CAS# = VDD - 0.2V) ICC2 16MB 32MB 9 9 9 9 mA OPERATING CURRENT: Random READ/WRITE Average power supply current (RAS#, CAS#, address cycling: tRC = tRC [MIN]) ICC3 16MB 32MB 990 1,980 900 1,800 mA 3, 29 OPERATING CURRENT: FAST PAGE MODE Average power supply current (RAS# = VIL, CAS#, address cycling: tPC = tPC [MIN]) ICC4 16MB 32MB - - 720 1,440 mA 3, 29 990 1,980 900 1,800 mA 3, 29 OPERATING CURRENT: EDO PAGE MODE ("X" version only) Average power supply current (RAS# = VIL, CAS#, address cycling: tPC = tPC [MIN]) 16MB ICC5 (X only) 32MB REFRESH CURRENT: RAS#-ONLY Average power supply current (RAS# cycling, CAS# = VIH: tRC = tRC [MIN]) ICC6 16MB 32MB 990 1,980 900 1,800 mA 3, 29 REFRESH CURRENT: CBR Average power supply current (RAS#, CAS#, address cycling: tRC = tRC [MIN]) ICC7 16MB 32MB 990 1,980 900 1,800 mA 3, 4 4,096-CYCLE REFRESH ICC OPERATING CONDITIONS AND MAXIMUM LIMITS (Notes: 1, 5, 6) (VDD = +3.3V 0.3V) MAX PARAMETER/CONDITION SYMBOL SIZE -5* -6 UNITS NOTES STANDBY CURRENT: TTL (RAS# = CAS# = VIH) ICC1 32MB 90 90 mA STANDBY CURRENT: CMOS (RAS# = CAS# = VDD - 0.2V) ICC2 32MB 9 9 mA OPERATING CURRENT: Random READ/WRITE Average power supply current (RAS#, CAS#, address cycling: tRC = tRC [MIN]) ICC3 32MB 1,620 1,440 mA 3, 29 OPERATING CURRENT: FAST PAGE MODE Average power supply current (RAS# = VIL, CAS#, address cycling: tPC = tPC [MIN]) ICC4 32MB - 1,260 mA 3, 29 1,800 1,620 mA 3, 29 OPERATING CURRENT: EDO PAGE MODE ("X" version only) Average power supply current (RAS# = VIL, CAS#, address cycling: tPC = tPC [MIN]) ICC5 (X only) 32MB REFRESH CURRENT: RAS#-ONLY Average power supply current (RAS# cycling, CAS# = VIH: tRC = tRC [MIN]) ICC6 32MB 1,620 1,440 mA 3, 29 REFRESH CURRENT: CBR Average power supply current (RAS#, CAS#, address cycling: tRC = tRC [MIN]) ICC7 32MB 1,620 1,440 mA 3, 4 * EDO version only 2, 4 Meg x 72 Buffered DRAM DIMMs DM33.p65 - Rev. 2/99 8 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc. OBSOLETE 2, 4 MEG x 72 BUFFERED DRAM DIMMs CAPACITANCE MAX PARAMETER SYMBOL 16MB 32MB UNITS NOTES Input Capacitance: A0-A11, B0, PDE#, OE0#, OE2# CI1 Input Capacitance: WE0#, WE2#, CAS0#, CAS4# CI2 Input Capacitance: RAS0#, RAS2# CI3 Input/Output Capacitance: DQ0-DQ71 CIO Output Capacitance: PD1-PD8 CO 9 9 pF 2 9 9 pF 2 39 67 pF 2 10 10 pF 2 10 10 pF 2 FAST PAGE MODE AC ELECTRICAL CHARACTERISTICS (Notes: 5, 6, 7, 8, 9, 12, 35) (VDD = +3.3V 0.3V) AC CHARACTERISTICS - FAST PAGE MODE OPTION PARAMETER Access time from column address Column-address hold time (referenced to RAS#) Column-address setup time Row-address setup time Column address to WE# delay time Access time from CAS# Column-address hold time CAS# pulse width CAS# hold time (CBR Refresh) CAS# to output in Low-Z CAS# precharge time Access time from CAS# precharge CAS# to RAS# precharge time CAS# hold time CAS# setup time (CBR Refresh) CAS# to WE# delay time WRITE command to CAS# lead time Data-in hold time Data-in setup time Output disable Output enable OE# hold time from WE# during READ-MODIFY-WRITE cycle Output buffer turn-off delay OE# setup prior to RAS# during HIDDEN REFRESH cycle FAST-PAGE-MODE READ or WRITE cycle time 2, 4 Meg x 72 Buffered DRAM DIMMs DM33.p65 - Rev. 2/99 -6 SYMBOL tAA tAR tASC tASR tAWD tCAC tCAH tCAS tCHR tCLZ tCP tCPA tCRP tCSH tCSR tCWD tCWL tDH tDS tOD tOE tOEH tOFF tORD tPC 9 MIN MAX 35 43 2 5 57 20 15 15 8 5 10 10,000 40 10 58 7 42 15 15 -2 3 13 5 0 35 15 15 20 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns NOTES 23 22 21 23 21, 28 14, 23 23 4, 22 21, 30 15 23 23 22 4, 21 21, 28 23, 27 22, 27 22, 26 19, 25, 33 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc. OBSOLETE 2, 4 MEG x 72 BUFFERED DRAM DIMMs FAST PAGE MODE AC ELECTRICAL CHARACTERISTICS (Notes: 5, 6, 7, 8, 9, 12, 35) (VDD = +3.3V 0.3V) AC CHARACTERISTICS - FAST PAGE MODE OPTION PARAMETER PDE# to valid presence-detect data PDE# inactive to presence-detects inactive FAST-PAGE-MODE READ-WRITE cycle time Access time from RAS# RAS# to column-address delay time Row-address hold time RAS# pulse width RAS# pulse width (FAST PAGE MODE) Random READ or WRITE cycle time RAS# to CAS# delay time READ command hold time (referenced to CAS#) READ command setup time Refresh period (2,048 cycles) (16MB) Refresh period (4,096 cycles) (32MB) RAS# precharge time RAS# to CAS# precharge time READ command hold time (referenced to RAS#) RAS# hold time READ-WRITE cycle time RAS# to WE# delay time WRITE command to RAS# lead time Transition time (rise or fall) WRITE command hold time WRITE command hold time (referenced to RAS#) WE# command setup time WRITE command pulse width WE# hold time (CBR Refresh) WE# setup time (CBR Refresh) 2, 4 Meg x 72 Buffered DRAM DIMMs DM33.p65 - Rev. 2/99 -6 SYMBOL tPD tPDOFF tPRWC tRAC tRAD tRAH tRAS tRASP tRC tRCD tRCH tRCS tREF tREF tRP tRPC tRRH tRSH tRWC tRWD tRWL tT tWCH tWCR tWCS tWP tWRH tWRP 10 MIN MAX 10 2 87 60 13 8 60 60 110 18 2 2 10,000 125,000 32 64 40 0 0 20 160 87 20 2 15 43 2 10 8 12 50 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ms ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns NOTES 32 31 21 13 17, 24 22 16, 24 18, 21 21 18 23 23 21, 28 23 23 22 21, 28 22 21 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc. OBSOLETE 2, 4 MEG x 72 BUFFERED DRAM DIMMs EDO PAGE MODE AC ELECTRICAL CHARACTERISTICS (Notes: 5, 6, 7, 8, 9, 12, 35) (VDD = +3.3V 0.3V) AC CHARACTERISTICS - EDO PAGE MODE OPTION PARAMETER Access time from column address Column-address setup to CAS# precharge Column-address hold time (referenced to RAS#) Column-address setup time Row-address setup time Column address to WE# delay time Access time from CAS# Column-address hold time CAS# pulse width CAS# hold time (CBR Refresh) CAS# to output in Low-Z Data output hold after next CAS# LOW CAS# precharge time Access time from CAS# precharge CAS# to RAS# precharge time CAS# hold time CAS# setup time (CBR Refresh) CAS# to WE# delay time WRITE command to CAS# lead time Data-in hold time Data-in setup time Output disable Output enable OE# hold time from WE# during READ-MODIFY-WRITE cycle OE# HIGH hold from CAS# HIGH OE# HIGH pulse width OE# LOW to CAS# HIGH setup time Output buffer turn-off delay 2, 4 Meg x 72 Buffered DRAM DIMMs DM33.p65 - Rev. 2/99 -5 SYMBOL tAA tACH tAR tASC tASR tAWD tCAC tCAH tCAS tCHR tCLZ tCOH tCP tCPA tCRP tCSH tCSR tCWD tCWL tDH tDS tOD tOE tOEH MIN 6 tOEHC 5 5 4 2 tOEP tOES tOFF 11 -6 MAX 30 12 36 2 5 44 MIN NOTES 23 8 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 10 5 5 2 ns ns ns ns 26 15 43 2 5 51 18 13 8 6 2 5 8 10,000 20 15 10 8 2 5 10 33 10 36 7 30 8 13 -2 0 MAX 35 12 12 17 10,000 40 10 43 7 37 10 15 -2 0 15 15 20 22 21 23 21, 28 14, 23 23 4, 22 21 21 15 23 23 22 4, 21 21, 28 23, 27 22, 27 22, 26 19, 25, 33 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc. OBSOLETE 2, 4 MEG x 72 BUFFERED DRAM DIMMs EDO PAGE MODE AC ELECTRICAL CHARACTERISTICS (Notes: 5, 6, 7, 8, 9, 12, 35) (VDD = +3.3V 0.3V) AC CHARACTERISTICS - EDO PAGE MODE OPTION PARAMETER OE# setup prior to RAS# during HIDDEN REFRESH cycle EDO-PAGE-MODE READ or WRITE cycle time PDE# to valid presence-detect data PDE# inactive to presence-detect inactive EDO-PAGE-MODE READ-WRITE cycle time Access time from RAS# RAS# to column-address delay time Row-address hold time RAS# pulse width RAS# pulse width (EDO PAGE MODE) Random READ or WRITE cycle time RAS# to CAS# delay time READ command hold time (referenced to CAS#) READ command setup time Refresh period (2,048 cycles) (16MB) Refresh period (4,096 cycles) (32MB) RAS# precharge time RAS# to CAS# precharge time READ command hold time (referenced to RAS#) RAS# hold time READ-ZWRITE cycle time RAS# to WE# delay time WRITE command to RAS# lead time Transition time (rise or fall) WRITE command hold time WRITE command hold time (referenced to RAS#) WE# command setup time Output disable delay from WE# WRITE command pulse width WE# pulse to disable at CAS# HIGH WE# hold time (CBR Refresh) WE# setup time (CBR Refresh) 2, 4 Meg x 72 Buffered DRAM DIMMs DM33.p65 - Rev. 2/99 -5 SYMBOL tORD MIN 0 tPC 20 tPD -6 MAX MIN 0 25 10 tPDOFF 2 49 tPRWC tRAC 10 2 58 50 tRAD 7 7 50 50 84 9 2 2 tRAH tRAS tRASP tRC tRCD tRCH tRCS tREF 10,000 125,000 60 10 8 60 60 104 12 2 2 32 64 tREF tRP 30 5 0 18 121 69 18 2 13 36 2 2 5 10 6 10 tRPC tRRH tRSH tRWC tRWD tRWL tT tWCH tWCR tWCS tWHZ tWP tWPZ tWRH tWRP 12 MAX 50 17 10,000 125,000 32 64 40 5 0 20 145 81 20 2 15 43 2 2 5 10 8 12 50 20 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns NOTES 32 31 21 13 17, 22 22 16, 24 18, 21 21 18 23 23 21, 28 23 23 22 21, 28 25 22 21 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc. OBSOLETE 2, 4 MEG x 72 BUFFERED DRAM DIMMs NOTES 19. tOFF (MAX) defines the time at which the output achieves the open circuit condition and is not referenced to VOH or VOL. 20.A HIDDEN REFRESH may also be performed after a WRITE cycle. In this case, WE# = LOW and OE# = HIGH. 21.A +2ns timing skew from the DRAM to the module resulted from the addition of line drivers. 22.A -2ns timing skew from the DRAM to the module resulted from the addition of line drivers. 23.A +5ns timing skew from the DRAM to the module resulted from the addition of line drivers. 24.A -2ns (MIN) and a -5ns (MAX) timing skew from the DRAM to the module resulted from the addition of line drivers. 25.A +2ns (MIN) and a +5ns (MAX) timing skew from the DRAM to the module resulted from the addition of line drivers. 26.LATE WRITE and READ-MODIFY-WRITE cycles must have both tOD and tOEH met (OE# HIGH during WRITE cycle) in order to ensure that the output buffers will be open during the WRITE cycle. The DQs will provide the previously read data if CAS# remains LOW and OE# is taken back LOW after tOEH is met. If CAS# goes HIGH prior to OE# going back LOW, the DQs will remain open. 27.These parameters are referenced to CAS# leading edge in EARLY WRITE cycles and WE# leading edge in LATE WRITE or READ-MODIFY-WRITE cycles. 28. tWCS, tRWD, tAWD and tCWD are not restrictive operating parameters. tWCS applies to EARLY WRITE cycles. tRWD, tAWD and tCWD apply to READ-MODIFY-WRITE cycles. If tWCS tWCS (MIN), the cycle is an EARLY WRITE cycle and the data output will remain an open circuit throughout the entire cycle. If tWCS < tWCS (MIN) and tRWD tRWD (MIN), tAWD tAWD (MIN) and tCWD tCWD (MIN), the cycle is a READMODIFY-WRITE and the data output will contain data read from the selected cell. If neither of the above conditions is met, the state of data-out is indeterminate. OE# held HIGH and WE# taken LOW after CAS# goes LOW result in a LATE WRITE (OE#-controlled) cycle. tWCS, tRWD, tCWD and tAWD are not applicable in a LATE WRITE cycle. 29.Column address changed once each cycle. 30.The 3ns minimum parameter guaranteed by design. 1. All voltages referenced to VSS. 2. This parameter is sampled. VDD = +3.3V; f = 1 MHz. 3. ICC is dependent on output loading. Specified values are obtained with minimum cycle time and the outputs open. 4. Enables on-chip refresh and address counters. 5. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range is ensured. 6. An initial pause of 100s is required after powerup, followed by eight RAS# REFRESH cycles (RAS#-ONLY or CBR with WE# HIGH), before proper device operation is ensured. The eight RAS# cycle wake-ups should be repeated any time the tREF refresh requirement is exceeded. 7. AC characteristics assume tT = 5ns for FPM and 2.5ns for EDO. 8. VIH (MIN) and VIL (MAX) are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL (or between VIL and VIH). 9. In addition to meeting the transition rate specification, all input signals must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. 10.If CAS# = VIH, data output is High-Z. 11.If CAS# = VIL, data output may contain data from the last valid READ cycle. 12.Measured with a load equivalent to two TTL gates and 100pF and VOL = 0.8V and VOH = 2V. 13.Requires that tAA and tCAC are not violated. 14.Requires that tAA and tRAC are not violated. 15.If CAS# is LOW at the falling edge of RAS#, Q will be maintained from the previous cycle. To initiate a new cycle and clear the data-out buffer, CAS# must be pulsed HIGH for tCP. 16.The tRCD (MAX) limit is no longer specified. tRCD (MAX) was specified as a reference point only. If tRCD was greater than the specified tRCD (MAX) limit, then access time was controlled exclusively by tCAC (tRAC [MIN] no longer applied). With or without the tRCD (MAX) limit, tAA and tCAC must always be met. 17.The tRAD (MAX) limit is no longer specified. tRAD (MAX) was specified as a reference point only. If tRAD was greater than the specified tRAD (MAX) limit, then access time was controlled exclusively by tAA (tRAC and tCAC no longer applied). With or without the tRAD (MAX) limit, tAA, tRAC and tCAC must always be met. 18.Either tRCH or tRRH must be satisfied for a READ cycle. 2, 4 Meg x 72 Buffered DRAM DIMMs DM33.p65 - Rev. 2/99 13 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc. OBSOLETE 2, 4 MEG x 72 BUFFERED DRAM DIMMs NOTES (continued) 31. tPDOFF MAX is determined by the pull-up resistor value. Care must be taken to ensure adequate recovery time prior to reading valid up-level on subsequent DIMM position. 32.Measured with specified current load and 100pF. 33.With the FPM option, tOFF is determined by the first RAS# or CAS# signal to transition HIGH. In comparison, tOFF on an EDO option is determined by the latter of the RAS# and CAS# signals to transition HIGH. 2, 4 Meg x 72 Buffered DRAM DIMMs DM33.p65 - Rev. 2/99 34.Applies to both FPM and EDO operating modes. 35.If OE# is tied permanently LOW, LATE WRITE or READ-MODIFY-WRITE operations are not possible. 36. VIH overshoot: VIH (MAX) = VDD + 2V for a pulse width 10ns, and the pulse width cannot be greater than one third of the cycle rate. VIL undershoot: VIL (MIN) = -2V for a pulse width 10ns, and the pulse width cannot be greater than one third of the cycle rate. 14 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc. OBSOLETE 2, 4 MEG x 72 BUFFERED DRAM DIMMs READ CYCLE 34 tRC tRAS RAS# tRP V IH V IL tCSH tRSH tRCD tCRP CAS# tRRH tCAS V IH V IL tAR tRAD tRAH tASR ADDR V IH V IL tASC ROW tCAH ROW COLUMN tRCH tRCS WE# V IH V IL tAA tRAC NOTE 1 tOFF tCAC tCLZ DQ V OH V OL OPEN OE# OPEN VALID DATA tOE tOD V IH V IL DON'T CARE UNDEFINED FAST PAGE MODE AND EDO PAGE MODE TIMING PARAMETERS -5* SYMBOL tAA tACH (EDO) tAR tASC tASR MIN -6 MIN 12 36 15 43 2 5 2 5 ns ns 18 tCAH tCAS (EDO) tCAS (FPM) tCLZ (EDO) tCLZ (FPM) tCRP tCSH (EDO) tCSH (FPM) 13 8 - 2 10,000 - - 10 36 tOD (EDO) - 0 tOD - (FPM) -5* UNITS ns ns ns tCAC MAX 30 tOE MAX 35 20 15 10 15 2 10,000 10,000 5 10 43 12 - 12 58 0 3 SYMBOL tOFF (EDO) tOFF (FPM) MAX MIN MAX UNITS 2 - 17 - 2 5 20 20 ns ns 60 ns ns ns ns 10,000 ns ns tRAC 50 tRAD 7 - 7 tRAS 50 84 (EDO) tRAD (FPM) tRAH ns ns ns tRC (EDO) tRC ns ns 10 13 8 10,000 60 104 (FPM) (EDO) tRCD (FPM) - 9 - 110 12 18 ns ns ns tRCH 2 2 2 2 ns ns tRCD ns ns ns -6 MIN tRCS ns ns tRP 15 tRRH 30 0 40 0 ns ns 15 15 ns ns tRSH 18 20 ns *EDO version only NOTE: 1. For EDO, tOFF is referenced from rising edge of RAS# or CAS#, whichever occurs last. For FPM, tOFF is referenced from rising edge of RAS# or CAS#, whichever occurs first. 2, 4 Meg x 72 Buffered DRAM DIMMs DM33.p65 - Rev. 2/99 15 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc. OBSOLETE 2, 4 MEG x 72 BUFFERED DRAM DIMMs EARLY WRITE CYCLE 34 tRC tRAS RAS# tRP V IH V IL tCSH tRSH tCRP CAS# tCAS tAR tASC tCAH V IH V IL tRAD tRAH tASR ADDR tRCD V IH V IL tACH ROW ROW COLUMN tCWL tRWL tWCR tWCH tWCS tWP WE# V IH V IL tDS V DQ V IOH IOL OE# tDH VALID DATA V IH V IL DON'T CARE UNDEFINED FAST PAGE MODE AND EDO PAGE MODE TIMING PARAMETERS -5* SYMBOL tACH (EDO) tAR tASC tASR tCAH tCAS (FPM) tCAS (EDO) tCRP MIN 12 36 -6 MAX MIN 15 43 -5* MAX UNITS ns ns SYMBOL tRAD 2 5 ns ns tRAS 13 - 8 15 15 10 ns ns ns tRC 10,000 10,000 (EDO) tRAH 2 5 - 10,000 MIN tRC (FPM) 10 7 50 - 8 60 110 10,000 ns ns ns ns ns tRCD 9 30 18 12 40 20 ns ns ns 18 13 20 15 ns ns 43 2 10 ns ns ns 5 ns (EDO) (FPM) (EDO) tCWL (FPM) tCWL (EDO) 36 - 8 43 15 10 ns ns ns tRWL tDH 13 15 ns tWCS -2 - -2 13 ns ns tWP (FPM) 36 2 - tWP (EDO) 5 (FPM) ns 104 18 tRP tRAD UNITS 84 - ns ns tDS 10,000 MAX (EDO) tRCD (FPM) 10 58 tCSH MIN 7 10 - tCSH -6 MAX tRSH tWCH tWCR *EDO version only 2, 4 Meg x 72 Buffered DRAM DIMMs DM33.p65 - Rev. 2/99 16 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc. OBSOLETE 2, 4 MEG x 72 BUFFERED DRAM DIMMs FAST-PAGE-MODE READ CYCLE tRC tRAS RAS tRP V IH V IL tCSH tRSH tRCD tCRP CAS tRRH tCAS V IH V IL tAR tRAD tRAH tASR ADDR V IH V IL tRAL tCAH tASC ROW ROW COLUMN tRCH tRCS WE V IH V IL tAA tRAC tOFF tCAC tCLZ DQ V IOH V IOL OPEN OE OPEN VALID DATA tOE tOD V IH V IL DON'T CARE UNDEFINED FAST PAGE MODE TIMING PARAMETERS -6 SYMBOL MIN tAA tAR tASC 43 2 tASR 5 tCAC tCAH tCLZ tCP 10 tCPA tCRP tCSH tOD 2, 4 Meg x 72 Buffered DRAM DIMMs DM33.p65 - Rev. 2/99 UNITS 35 ns ns ns 10 58 3 SYMBOL tOE tOFF tPC MIN 5 35 ns ns tRAC tRAD 13 ns ns ns tRAH 8 60 18 tRCH 40 ns ns tRP 15 ns ns ns 20 15 15 5 tCAS -6 MAX 10,000 tRASP tRCD tRCS tRRH tRSH 17 MAX 15 20 UNITS ns ns ns 60 ns ns 125,000 ns ns ns 2 2 ns ns 40 0 20 ns ns ns Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc. OBSOLETE 2, 4 MEG x 72 BUFFERED DRAM DIMMs EDO-PAGE-MODE READ CYCLE tRASP RAS# V IH V IL tCSH tCRP CAS# tRP tRCD tPC tCP tCAS tRSH tCAS tCP tCAS tCP V IH V IL tAR tRAD tRAH tASR ADDR V IH V IL ROW tACH tACH tACH tASC tCAH tASC COLUMN tCAH tASC COLUMN tCAH COLUMN ROW tRCS WE# tRCH V IH V IL tAA tRAC tAA tCPA tCAC tCAC DQ V OH V OL VALID DATA OPEN tOFF tOEHC VALID DATA tOE OE# tCAC tCLZ tCOH tCLZ VALID DATA OPEN tOE tOD tOES V IH V IL tRRH tAA tCPA tOD tOES tOEP DON'T CARE UNDEFINED EDO PAGE MODE TIMING PARAMETERS -5 SYMBOL tAA tACH MIN -6 MAX 30 MIN -5 MAX 35 UNITS ns SYMBOL tOEHC 15 43 2 ns ns ns tOEP tASC 12 36 2 tASR 5 5 ns ns tPC ns ns ns tRAD ns ns tRCD ns ns ns tRCS ns ns tAR tCAC tCAH tCAS tCLZ tCOH tCP 18 13 8 2 5 8 tCPA tCRP 10,000 20 15 10 2 5 10 33 tCSH 10 36 tOD 0 tOE 2, 4 Meg x 72 Buffered DRAM DIMMs DM33.p65 - Rev. 2/99 10,000 40 10 43 12 12 0 15 15 tOES tOFF MIN 5 5 4 2 tRASP MIN 10 5 5 2 125,000 10 8 60 UNITS ns 20 ns ns ns 60 ns ns 125,000 ns ns ns 25 50 7 7 50 MAX 9 2 12 2 ns ns tRRH 2 30 0 2 40 0 ns ns ns tRSH 18 20 ns tRCH tRP 18 17 20 tRAC tRAH -6 MAX Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc. OBSOLETE 2, 4 MEG x 72 BUFFERED DRAM DIMMs FAST/EDO-PAGE-MODE EARLY WRITE CYCLE 34 t RP t RASP V IH V IL RAS# t CSH t PC t CRP t RCD t CAS t RSH t CP t CAS t CP t CP t CAS V IH V IL CAS# t AR t RAD t ASR V IH V IL ADDR t RAH tACH t ASC ROW t ACH t CAH t ASC COLUMN t ASC COLUMN t CWL t WCS t ACH t CAH t CAH COLUMN t CWL t WCH t WCS t WCH t WP ROW t CWL t WCS t WCH t WP t WP V IH V IL WE# t RWL t DH t WCR t DS V DQ V IOH IOL t DH t DS VALID DATA t DH t DS VALID DATA VALID DATA DON'T CARE UNDEFINED FAST PAGE MODE AND EDO PAGE MODE TIMING PARAMETERS -5* SYMBOL tACH (EDO) MIN 12 -6 MAX MIN 15 -5* MAX UNITS ns SYMBOL tPC (FPM) MIN - -6 MAX MIN 35 MAX UNITS ns tAR 36 43 ns tRAD (EDO) 7 10 ns tASC 2 5 13 2 5 15 ns ns ns tRAD (FPM) - 7 50 13 8 60 ns ns ns ns ns tRCD (EDO) tRCD (FPM) 9 - 12 18 ns ns 30 18 18 40 20 20 ns ns ns 13 36 15 43 ns ns 2 5 - 2 5 10 ns ns ns tASR tCAH tCAS (EDO) tCAS (FPM) tCP 8 - 10,000 - 10 15 10,000 10,000 tRAH tRASP 10 10 43 ns ns ns tRP (EDO) 8 10 36 (FPM) tCWL (EDO) - 8 58 10 ns ns tWCH 15 15 -2 ns ns ns tWCS tDS - 13 -2 tPC (EDO) 20 25 ns tCRP tCSH tCSH tCWL (FPM) tDH tRSH tRWL tWCR tWP (EDO) tWP (FPM) 125,000 125,000 *EDO version only 2, 4 Meg x 72 Buffered DRAM DIMMs DM33.p65 - Rev. 2/99 19 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc. OBSOLETE 2, 4 MEG x 72 BUFFERED DRAM DIMMs READ-WRITE CYCLE 34 (LATE WRITE and READ-MODIFY-WRITE cycles) t RWC t RAS t RP V IH V IL RAS# t CSH t RSH t CRP t RCD t CAS V IH V IL CAS# t AR t RAD t ASR V IH V IL ADDR t ASC t CAH t ACH t RAH ROW COLUMN t RCS ROW t RWD t CWL t CWD t RWL t AWD t WP V IH V IL WE# t AA t RAC t CAC t DS t CLZ V DQ V IOH IOL VALID D OUT OPEN t OE t DH VALID D IN t OD OPEN t OEH V IH V IL OE# DON'T CARE FAST PAGE MODE AND EDO PAGE MODE TIMING PARAMETERS -5* SYMBOL tAA tACH (EDO) tAR tASC tASR tAWD (EDO) tAWD (FPM) MIN -6 MAX 30 12 36 2 5 42 - tCAC UNDEFINED MIN -5* MAX 35 15 43 2 5 49 57 UNITS ns ns ns ns ns ns ns SYMBOL tOD (EDO) tOD (FPM) tOE tOEH (EDO) tOEH (FPM) tRAC tRAD (EDO) ns ns tRAD ns ns ns tRAS 5 10 ns ns tRCS 36 - 30 43 58 37 ns ns ns tRSH - 8 42 10 ns ns tRWD - 13 15 15 ns ns tRWL tDH tDS -2 -2 ns 18 tCAH 13 tCAS (EDO) (FPM) tCLZ (EDO) 8 - 2 tCLZ (FPM) - 10 tCAS tCRP tCSH (EDO) (FPM) tCWD (EDO) tCSH tCWD (FPM) tCWL (EDO) tCWL (FPM) 20 15 10,000 - 10 15 2 10,000 10,000 (FPM) tRAH tRCD (EDO) tRCD (FPM) MIN 0 - -6 MAX 12 - 12 7 10 UNITS ns ns ns ns ns ns ns - 7 13 8 ns ns 6 - MIN 0 3 8 13 50 50 9 - MAX 15 15 15 10,000 60 60 12 18 10,000 ns ns ns 2 30 2 40 ns ns 18 121 - 20 145 160 ns ns ns 69 - 81 87 ns ns tWP (EDO) 18 5 20 5 ns ns tWP (FPM) - 10 ns tRP tRWC (EDO) tRWC (FPM) tRWD (EDO) (FPM) *EDO version only 2, 4 Meg x 72 Buffered DRAM DIMMs DM33.p65 - Rev. 2/99 20 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc. OBSOLETE 2, 4 MEG x 72 BUFFERED DRAM DIMMs FAST/EDO-PAGE-MODE READ-WRITE CYCLE 34 (LATE WRITE and READ-MODIFY-WRITE cycles) t RASP t RP V IH V IL RAS# t CSH t CRP t CAS t RSH t PRWC NOTE 1 t PC tRCD t CP t CAS t CP t CAS t CP V IH V IL CAS# t AR t RAD t ASR V IH V IL ADDR t RAH t ASC t CAH ROW t ASC COLUMN t CAH t ASC COLUMN t CAH COLUMN ROW t RWD t RCS t RWL t CWL t CWL t WP t AWD t WP t AWD t AWD t CWD t CWD t CWD t CWL t WP V IH V IL WE# t AA t AA t RAC t DH t CPA t DS t CAC t DS t CAC t CLZ VALID D OUT OPEN t DH tCPA t DS t CAC t CLZ V IOH V IOL DQ tAA t DH t CLZ VALID DIN VALID D OUT t OD VALID D IN VALID D OUT t OD tOE t OE VALID D IN OPEN t OD t OE t OEH V IH V IL OE# DON'T CARE FAST PAGE MODE AND EDO PAGE MODE TIMING PARAMETERS -5* SYMBOL tAA tAR tASC tASR tAWD (EDO) tAWD (FPM) tCAC tCAH tCAS MIN 18 tCLZ (FPM) - 8 tCPA (EDO) tCSH (FPM) tCWD (EDO) tCWD (FPM) tCWL (EDO) tCWL (FPM) tDH tDS tOD (EDO) -5* MAX 35 20 15 10,000 - 10 15 2 10,000 10,000 5 10 33 tCRP tCSH MIN 43 2 5 49 57 13 8 - 2 tCP -6 MAX 30 36 2 5 42 - (EDO) (FPM) tCLZ (EDO) tCAS UNDEFINED SYMBOL tOD (FPM) tOE tOEH (EDO) tOEH (FPM) tPC (EDO) tPC (FPM) tPRWC (EDO) tPRWC (FPM) tRAD 7 - ns ns tRAH 7 50 tRCD tRASP 10 43 - 30 58 37 ns ns tRP - 8 - 42 10 15 ns ns ns tRWD 13 -2 15 -2 ns ns tWP (EDO) 0 15 MIN 3 (EDO) (FPM) tRCS tRSH tRWD (EDO) (FPM) tRWL tWP (FPM) MAX 15 15 UNITS ns ns ns ns ns ns ns ns 60 ns ns ns 8 13 25 35 58 87 50 (EDO) tRAD (FPM) tRCD -6 MAX - 12 6 - 20 - 49 - tRAC 10 36 12 MIN - ns ns ns ns ns ns 0 40 UNITS ns ns ns ns ns ns ns ns 10 13 125,000 8 60 125,000 ns ns 9 - 2 12 18 2 ns ns ns 30 18 40 20 ns ns 69 - 18 81 87 20 ns ns ns 5 - 5 10 ns ns ns NOTE: 1. tPC is for LATE WRITE cycles only. *EDO version only 2, 4 Meg x 72 Buffered DRAM DIMMs DM33.p65 - Rev. 2/99 21 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc. OBSOLETE 2, 4 MEG x 72 BUFFERED DRAM DIMMs EDO-PAGE-MODE READ EARLY WRITE CYCLE (Pseudo READ-MODIFY-WRITE) t RP t RASP RAS# V IH V IL t CSH tPC tCRP CAS# t RCD tRSH tPC t CP t CAS t CP t CAS t CP t CAS V IH V IL tAR tRAD tASR ADDR V IH V IL t ACH tRAH tASC tCAH t ASC COLUMN (A) ROW t CAH COLUMN (B) V IH V IL ROW tWCS tWCH tAA tAA tCPA tRAC tCAC tCAC tCOH DQ V IOH V IOL t CAH COLUMN (N) tRCH tRCS WE# tASC OPEN t DS VALID DATA (B) VALID DATA (A) t DH t WHZ VALID DATA IN tOE OE# V IH V IL DON'T CARE UNDEFINED EDO PAGE MODE TIMING PARAMETERS -5 SYMBOL tAA tACH tAR tASC tASR MIN tCAS tCOH tCP tCSH tDH tDS -5 MAX 35 UNITS ns SYMBOL MIN tOE ns ns tPC 2 5 2 5 tRAD 7 tRAH 20 ns ns ns 7 50 ns ns tRCD 10,000 tRCS 40 ns ns ns 18 13 8 10,000 5 8 15 10 5 10 33 tRCH tRP tRSH 10 36 10 43 ns ns tWCH 13 -2 15 -2 ns ns tWHZ 2, 4 Meg x 72 Buffered DRAM DIMMs DM33.p65 - Rev. 2/99 20 tRAC tRASP tWCS 22 -6 MAX MIN 12 15 43 tCPA tCRP MIN 12 36 tCAC tCAH -6 MAX 30 MAX ns 60 ns ns ns 25 50 10 125,000 8 60 UNITS 15 125,000 ns ns 9 2 2 12 2 2 ns ns ns 30 18 40 20 ns ns 13 2 2 15 2 2 ns ns ns 17 20 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc. OBSOLETE 2, 4 MEG x 72 BUFFERED DRAM DIMMs FAST-PAGE-MODE READ EARLY WRITE CYCLE (Pseudo READ-MODIFY-WRITE) t RASP RAS# t RP V IH V IL t RSH t CSH t RCD t CRP CAS# t PC t CAS t CP t CAS t CP V IH V IL t AR t RAD t ASR ADDR V IH V IL t ASC t RAH ROW tASC t CAH COLUMN t CAH COLUMN ROW t CWL t RWL t WP t RCS t WCS WE# V IH V IL t CAC t CLZ DQ t WCH V OH V OL NOTE 1 t OFF t DS VALID DATA OPEN t DH VALID DATA t AA t RAC DON'T CARE UNDEFINED FAST PAGE MODE TIMING PARAMETERS -6 SYMBOL tAA tAR tASC tASR MIN -6 MAX 35 43 UNITS ns ns 2 5 ns ns tRAC tRAD 13 ns ns ns tRAH 8 60 18 5 10 ns ns tRCS 10 58 15 ns ns ns tRSH 15 -2 ns ns tWCS tCAC tCAH tCAS tCLZ tCP tCRP tCSH tCWL tDH tDS 20 15 15 10,000 SYMBOL tOFF tPC tRASP tRCD tRP tRWL tWCH tWP MIN 5 35 MAX 20 UNITS ns ns 60 ns ns 125,000 ns ns ns 2 40 ns ns 20 20 15 ns ns ns 2 10 ns ns NOTE: 1. Do not drive data prior to tristate. 2, 4 Meg x 72 Buffered DRAM DIMMs DM33.p65 - Rev. 2/99 23 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc. OBSOLETE 2, 4 MEG x 72 BUFFERED DRAM DIMMs EDO READ CYCLE (with WE#-controlled disable) RAS# V IH V IL tCSH tRCD tCRP CAS# tCAS tCP V IH V IL tAR tRAD tRAH tASR ADDR V IH V IL tASC ROW tCAH tASC COLUMN COLUMN tRCS WE# tRCH tWPZ tRCS V IH V IL tAA tRAC tCAC tCLZ DQ V OH V OL tWHZ OPEN VALID DATA tOE OE# tCLZ OPEN tOD V IH V IL DON'T CARE UNDEFINED EDO PAGE MODE TIMING PARAMETERS -5 SYMBOL tAA tAR tASC tASR MIN tCAS tCLZ MIN -5 MAX 35 UNITS ns tOD 43 ns tOE 2 5 2 5 tRAC 20 ns ns ns ns ns tRCD 10,000 tRCS 18 13 8 10,000 15 10 tCRP 2 8 10 2 10 10 ns ns ns tCSH 36 43 ns tCP SYMBOL 36 tCAC tCAH -6 MAX 30 2, 4 Meg x 72 Buffered DRAM DIMMs DM33.p65 - Rev. 2/99 tRAD tRAH tRCH tWHZ tWPZ 24 -6 MIN MAX MIN MAX UNITS 0 12 12 50 0 15 15 60 ns ns ns 7 7 10 8 ns ns 9 2 2 12 2 2 ns ns ns 2 10 17 2 10 20 ns ns Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc. OBSOLETE 2, 4 MEG x 72 BUFFERED DRAM DIMMs RAS#-ONLY REFRESH CYCLE 34 t RC t RAS RAS# t RP V IH V IL t RPC t CRP CAS# V IH V IL t ASR ADDR V IH V IL t RAH ROW ROW V DQ V OH OL WE# OPEN V IH V IL DON'T CARE UNDEFINED FAST PAGE MODE AND EDO PAGE MODE TIMING PARAMETERS -5* SYMBOL tASR tCRP tCSR tRAH tRAS MIN 5 10 7 7 50 -6 MAX 10,000 MIN 5 10 7 8 60 -5* MAX 10,000 UNITS ns ns ns ns ns SYMBOL tRC MIN (FPM) tRC (EDO) tRP tRPC (FPM) tRPC (EDO) - 84 30 - 5 -6 MAX MIN 110 104 40 0 5 MAX UNITS ns ns ns ns ns *EDO version only 2, 4 Meg x 72 Buffered DRAM DIMMs DM33.p65 - Rev. 2/99 25 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc. OBSOLETE 2, 4 MEG x 72 BUFFERED DRAM DIMMs CBR REFRESH CYCLE 34 (Addresses, OE# = DON'T CARE) t RP RAS# t RAS t RP NOTE 1 t RAS V IH V IL t RPC t CP CAS# V IH V IL DQ V OH V OL t CSR t CSR t CHR OPEN t WRP WE# t RPC t CHR t WRH t WRP t WRH V IH V IL PRESENCE-DETECT READ CYCLE 34 PDE# V IH V IL tPD PD1-PD8 tPDOFF V IH V IL VALID PRESENCE-DETECT DON'T CARE UNDEFINED FAST PAGE MODE AND EDO PAGE MODE TIMING PARAMETERS -5* SYMBOL tCHR tCP tCSR MIN 6 8 7 tPD tPDOFF tRAS -6 MAX MIN 8 10,000 2 60 UNITS ns SYMBOL tRP tRPC 10 ns ns ns 10,000 ns ns 10 7 10 2 50 -5* MAX MIN 30 (FPM) -6 MAX MIN 40 MAX UNITS ns tWRH - 5 6 0 5 8 ns ns ns tWRP 10 12 ns tRPC (EDO) *EDO version only NOTE: 1. PD pins must be pulled HIGH at next level of assembly. 2, 4 Meg x 72 Buffered DRAM DIMMs DM33.p65 - Rev. 2/99 26 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc. OBSOLETE 2, 4 MEG x 72 BUFFERED DRAM DIMMs HIDDEN REFRESH CYCLE 20, 34 (WE# = HIGH; OE# = LOW) tRC tRAS RAS# tRAS V IH V IL tCRP CAS# tRP tRSH tRCD tCHR V IH V IL tAR tRAD tASR ADDR V IH V IL tRAH tASC ROW tCAH COLUMN tAA tRAC tOFF tCAC tCLZ V DQ V IOH IOL OPEN VALID DATA OPEN DON'T CARE UNDEFINED FAST PAGE MODE AND EDO PAGE MODE TIMING PARAMETERS -5* SYMBOL tAA tAR MIN -6 MAX 30 MIN -5* MAX 35 SYMBOL tOFF (FPM) MIN - MAX - MIN 5 MAX 20 UNITS ns 2 0 17 2 0 20 ns ns 60 ns ns ns 36 2 43 2 ns ns tOFF (EDO) tASC tASR 5 5 tRAC tRAD - 7 7 50 tORD tCAH 13 15 ns ns ns tCHR 6 - 8 5 ns ns tRAH 2 10 3 15 ns ns ns tRCD (FPM) 2 10 - tOD (EDO) 0 15 15 ns ns tCAC tCLZ (FPM) tCLZ (EDO) tCRP tOD 18 tOE - 12 12 20 0 -6 UNITS ns 50 (FPM) tRAD (EDO) tRAS 10,000 8 60 10,000 ns ns tRP - 9 30 18 12 40 ns ns ns tRSH 18 20 ns tRCD (FPM) (EDO) 13 10 *EDO version only 2, 4 Meg x 72 Buffered DRAM DIMMs DM33.p65 - Rev. 2/99 27 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc. OBSOLETE 2, 4 MEG x 72 BUFFERED DRAM DIMMs 168-PIN DIMM DF-8 (16MB) FRONT VIEW 5.256 (133.50) 5.244 (133.20) .200 (5.08) MAX .079 (2.00) R (2X) 1.005 (25.53) .995 (25.27) .700 (17.78) TYP .118 (3.00) (2X) .118 (3.00) TYP .250 (6.35) TYP .118 (3.00) TYP 1.700 (43.18) .039 (1.00) R(2X) 2.625 (66.68) .128 (3.25) (2X) .118 (3.00) .039 (1.00) TYP .050 (1.27) TYP PIN 1 (PIN 85 on backside) .054 (1.37) .046 (1.17) PIN 84 (PIN 168 ON BACKSIDE) 4.550 (115.57) 168-PIN DIMM DF-7 (32MB) FRONT VIEW 5.256 (133.50) 5.244 (133.20) .350 (8.89) MAX .079 (2.00) R (2X) 1.005 (25.53) .995 (25.27) .118 (3.00) (2X) .700 (17.78) TYP .118 (3.00) TYP .054 (1.37) .046 (1.17) .250 (6.35) TYP .118 (3.00) TYP .039 (1.00) R(2X) PIN 1 .050 (1.27) TYP .039 (1.00) TYP PIN 84 4.550 (115.57) BACK VIEW .128 (3.25) (2X) .118 (3.00) 1.700 (43.18) 2.625 (66.68) PIN 168 PIN 85 NOTE: All dimensions in inches (millimeters) MAX or typical where noted. MIN 2, 4 Meg x 72 Buffered DRAM DIMMs DM33.p65 - Rev. 2/99 28 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc. OBSOLETE 2, 4 MEG x 72 BUFFERED DRAM DIMMs 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micronsemi.com, Internet: http://www.micronsemi.com, Customer Comment Line: 800-932-4992 Micron is a registered trademark of Micron Technology, Inc. 2, 4 Meg x 72 Buffered DRAM DIMMs DM33.p65 - Rev. 2/99 29 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc.