Virtex-E Extended Memory: Introduction and Ordering Information - Xilinx, Inc.

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DS025-1 (v1.4) April 2, 2001 www.xilinx.com Module 1 of 4

Preliminary Product Specification 1-800-255-7778 1

Features

• Fast, Extended Block RAM, 1.8 V FPGA Family

- 560 Kb and 1,120 Kb embedded block RAM

- 130 MHz internal performance (four LUT levels)

- PCI compliant 3.3 V, 32/64-bit, 33/66-MHz

• Sophisticated SelectRAM+™ Memory Hierarchy

- 294 Kb of internal configurable distributed RAM

- Up to 1,120 Kb of synchronous internal block RAM

- True Dual-Port™ block RAM

- Memory bandwidth up to 2.24 Tb/s (equivalent

bandwidth of over 100 RAMBUS channels)

- Designed for high-performance Interfaces to

external memories

·200 MHz ZBT* SRAMs

·200 Mb/s DDR SDRAMs

•Highly Flexible SelectIO +™ Technology

- Supports 20 high-performance interface standards

- Up to 556 singled-ended I/Os or up to 201

diff erential I/O pairs for an aggregate bandwidth of

>100 Gb/s

•Complete Industry-Standard Differential Signalling

Support

- LVDS (622 Mb/s), BLVDS (Bus LVDS), LVPECL

- Al I/O signals can be input, output, or bi-directional

- LVPECL and LVDS clock inputs for 300+ MHz

clocks

•Proprietary High-Performance SelectLink™

Technology

- 80 Gb/s chip-to-chip communication link

- Support for Double Data Rate (DDR) interface

- Web-based HDL generation methodology

•Eight Fully Digital Delay-Locked Loops (DLLs)

•IEEE 1149.1 boundary-scan logic

•Supported by Xilinx Foundation Series™ and Alliance

Series™ Devel op men t System s

- Inte rnet Team Design (Xili nx iTD™) tool ideal for

million-plus gate density designs

- Wide selection of PC or workstation platforms

•SRAM-based In-System Configuration

- Unlimited re-programmability

•Advanced Packaging Options

- 1.0 mm FG676 and FG900

-1.27mm BG560

•0.18

m 6-layer Metal Process with Copper

Interconnect

•100% Factory Tested

* ZBT is a trademark of Integrated Device Technology, Inc.

Introduction

The Virtex™-E Extended Memory (Virtex-EM) family of

FPGAs is an extension of the highly successful Virtex-E

fa mi ly ar ch itec tu re. The Vi rtex-EM fami ly (devices sh own in

Table 1) includes all of the features of Virtex-E, plus addi-

tional block RAM, useful for applications such as network

switches and high-performance video graphic systems.

Xilinx developed the Virtex-EM product family to enable

cust ome rs t o desig n s yste ms r eq uiring hi gh me mory ban d-

width, such as 160 Gb/s network switches. Unlike traditional

ASIC devices, this family also supports fast time-to-market

delivery, because the development engineering is already

completed. Just complete the design and program the

device. There is no NRE, no silicon production cycles, and no

additional delays for design re-work. In addition, designers

can update the design over a network at any time, providing

prod uc t up grades or upd at es to cu st om ers ev en so on er.

The Virte x-EM family is the result of more than fifteen years

of FPGA design e xperience. Xilinx has a history of support-

ing customer applications by providing the highest level of

logic, RAM, an d features available in the indust ry. The Vir-

tex-EM family, first FPGAs to deploy copper interconnect,

offers the performance and high memory bandwidth for

advanced system integration without the initial investment,

long de velopment cycles, and inventory risk expected in tra-

ditional ASIC development.

0Virtex™-E 1.8 V Extended Memory

Field Programmable Gate Arrays

DS025-1 (v1.4 ) Apri l 2, 2001 00Preliminary Product Specification

Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays R

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2 1-800-255-7778 Preliminary Pr odu ct Specifi cation

Virtex-E Compar ed to Virtex Devices

The Virtex-E f amily offers up to 43,200 logic cells in de vices

up to 30% faster than the Virtex family.

I/O performance is increased to 622 Mb/s using Source

Synchron ous da ta transm iss ion arch ite ctures and sy nchro-

nous system performance up to 240 MHz using sin-

gled-ended SelectI/O technology. Additional I/O standards

are suppor te d, notably LVPECL, LVDS, and BLVDS, which

use two pins per si gnal. Alm ost all signal pins can be used

fo r these new standa r ds.

Virtex-E devices have up to 640 Kb of faster (250MHz)

block SelectRAM, but the individual RAMs are the same

size and structure as in the Virtex family. They also have

eight DLLs instead of the four in Vir tex devices. Each indi-

vidual DLL is slightly improved with easier clock mirroring

and 4x frequency multiplication.

VCCINT, the supply voltage for the internal logic and mem-

ory, is 1.8 V, instead of 2.5 V for Vir tex devices. Advanced

processing and 0.18

m design rules have resulted in

smaller dice, faster speed, and lower power consumption.

I/O pins are 3 V tolerant, and can be 5 V tolerant with an

exter nal 100

resistor. P CI 5 V is not suppo r ted. With the

addition o f appropr iate exter nal re si s tors, any pin c an to ler -

ate any voltage desired.

Banking rules are different. With Virtex devices, all input

buffers are powered by VCCINT. With Vir tex-E devices, the

LVTTL, LVCMOS2, and PCI input buffers are powered by

the I/O supply voltage VCCO.

The Virtex-E family is not bitstream-compatible with the Vir-

tex family, but Vir tex designs can b e compiled i nto equiva-

lent Virtex-E devices.

The same dev ice in the same pa ckage fo r the Virt ex-E and

Virtex families are pin-compatible with some minor excep-

tions. See the data sheet pinout section for details.

General Description

The Virtex-E FPGA family delivers high-performance,

high-capacity programmable logic solutions. Dramatic

increases in silicon efficiency result from optimizing the new

architecture for place-and-route efficiency and exploiting an

aggressive 6-layer metal 0.18

m CMOS process. These

advances make Virtex-E FPGAs powerful and flexible alter-

natives to mask-programmed gate arrays. The Virtex-E fam-

ily includes the nine members in Table 1.

Buildi ng on exper ience ga ined from Vir tex FPGAs, the Vir-

tex-E family is an evolutionar y step forward in programma-

ble logic design. Combining a wide v ariety of programmable

system features, a rich hierarchy of fast, flexible intercon-

nect resour ces, and advanced proces s technol ogy, the Vir-

tex-E family delivers a high-speed and high-capacity

programmable logic solution that enhances design flexibility

while reducing time-to-market.

V i rtex -E A rchi tecture

Vir tex-E dev ices feature a flexible, regular archi tecture that

comprises an array of configurable logic blocks (CLBs) sur-

rounded by programmable input/output blocks (IOBs), all

interconnected by a rich hierarchy of fast, versatile routing

resources. The abundance of routing resources permits the

Vir tex-E family to acco mmodat e even the l argest and m ost

complex desig ns.

Vir tex-E FPGAs are SRAM-based, and are customized by

loading configu ration dat a into inte r nal memo r y cells. C on-

figuration data can be read from an external SPROM (mas-

ter serial mode), or can be written into the FPGA

(SelectMAP™, slave serial, and JTAG modes).

The standard Xilinx Foundation Series™ and Alliance

Series™ Development systems deliver complete design

support for Virtex-E, cove r in g every a sp ec t fr om b ehavioral

and schematic entry, through simulation, automatic design

translation and implementation, to the creation and down-

loading of a configuration bit stream.

Higher Performance

Vir tex-E devices provide better performance than previous

generations of FPGAs. Designs can achieve synchronous

system clock rates up to 240 MHz including I/O or 622 Mb/s

using Source Synchronous data transmission architech-

tures. Virtex-E I/Os comply fully with 3.3 V PCI specifica-

tions, and interfaces can be implemented that operate at

33 MHz or 66 MHz.

While performance is design-dependent, many designs

operate intern ally at spe eds in ex cess of 133 MHz an d can

achieve over 311 MHz. Table 2, page 3, shows perfor-

mance data for representative circuits, using worst-case

timing parameters.

Table 1: Virtex-E Extended M emory Field-Programmable Gate Array Family Members

Device Logic Gates CLB Array Logic

Cells Differential

I/O Pairs User I/O BlockRAM

Bits Distributed

RAM Bits

XCV405E 129,600 40 x 60 10,800 183 404 573,440 153,600

XCV812E 254,016 56 x 84 21,168 201 556 1,146,880 301,056

Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays

DS025-1 (v1.4) April 2, 2001 www.xilinx.com Module 1 of 4

Preliminary Product Specification 1-800-255-7778 3

Virtex-E Extended Memory Device/Pac kage Combinations and Maximum I/O

Virtex-E Extended Memory Ordering Information

Table 2: Performance f or Common Circuit Functions

Function Bits Virtex-E -7

Adder 16

64 4.3 ns

6.3 ns

Pipelined Mul tiplier 8 x 8

16 x 16 4.4 ns

5.1 ns

Address Decoder 16

64 3.8 ns

5.5 ns

16:1 Multiplex er 4.6 ns

Parity Tree 9

3.5 ns

4.3 ns

5.9 ns

Chip-to-Chip

HSTL Class IV

LVTTL,16mA, fast slew

LVDS

LVPECL

Table 3: Virtex-EM Family Maximum User I/O by Device/Package (Excluding Dedicated Clock Pins)

Package XCV405E XCV812E

BG560 404 404

FG676 404

FG900 556

Figure 1: Virtex Ordering Information

Example: XCV405E-6BG560C

De vice Type Temperature Range

C = Commercial (TJ = 0˚C to +85˚C)

I = Industrial (TJ = −40˚C to +100˚C)

Number of Pins

P ackage Type

BG = Ball Grid Array

FG = Fine Pitch Ball Grid Array

Speed Grade

(-6, -7, -8)

DS025_001_112000

Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays R

Module 1 of 4 www.xilinx.com DS025-1 (v1.4) April 2, 2001

4 1-800-255-7778 Preliminary Pr odu ct Specifi cation

Revision History

The following table sho ws the revision history for this document.

Virtex-E Extended Memory Data Sheet

The Virtex-E Extended Memory Data Sheet contains the following modules:

•DS025-1, Virtex-E 1.8V Extended Memory FPGAs:

Introduction and Ordering Information (Module 1)

•DS025-2, Virtex-E 1.8V Extended Memory FPGAs:

Functional Description (Module 2)

•DS025-3, Virtex-E 1.8V Extended Memory FPGAs:

DC and Switching Characteristics (Module 3)

•DS025-4, Virtex-E 1.8V Extended Memory FPGAs:

Pinout Tables (Module 4)

Date Version Revision

03/23/00 1.0 Initial Xilinx release.

08/01/00 1.1 Accumulated edits and fixes. Upgrade to Preliminary. Preview -8 numbers added.

Reformatted to adhere to corporate documentation style guidelines. Minor changes in

BG560 pin-out table.

09/19/00 1.2 •In Table 3 (Module 4), FG676 Fine-Pitch BGA — XCV405E, the following pins are no

longer labeled as VREF: B7, G16, G26, W26, AF20, AF8, Y1, H1.

•Min values added to Virtex-E Electrical Characteristics tables.

11/20/00 1.3 •Updated speed grade -8 numbers in Virtex-E Electrical Characteristics tables

(Module 3).

•Updated minimums in Table 11 (Module 2), and added notes to Table 12 (Module 2).

•Added to note 2 of Absolute Maximum Ratings (Module 3).

•Changed all minimum hold times to –0.4 for Global Clock Set-Up and Hold for LVTTL

Standard, with DLL (Module 3).

•Revised maximum TDLLPW in -6 speed grade for DLL Timing Parameters (Module 3).

04/02/01 1.4 •In Table 4, FG676 Fine-Pitc h BGA — XCV405E, pin B19 is no longer labeled as VREF,

and pin G16 is now labeled as VREF.

•Updated values in Virtex-E Switching Characteristics tables.

•Converted data sheet to modularized f ormat. See Virtex-E Extended Memory Data

Sheet, below.