LX27901
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Analog Mixed Signal Group
One Enterprise Aliso Viejo, CA 92656 USA
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D E S C R I P T I O N
K E Y F E A T U R E S
The LX27901 is an extremely
versatile high-performance
controller for driving LEDs from the
HVDC (output) rail of a standard
PFC front-end.
The controller allows the user to
utilize three different converter
drive schemes, LLC (resonant),
conventional PWM control, and
Microsemi’s proprietary
synchronous scheme, all selectable
by the multi-function ENABLE pin.
In non-resonant mode, the
controller provides two 180° phase-
shifted pulse-width modulated drive
signals for implementing various
two-switch DC-DC converter
topologies, such a half-bridge and
asymmetrical forward converter. It
can also be used for one-switch
topologies.
Direct PWM input dimming
operation can be realized by
inputting a suitable dimming pulse
train to the DIM pin. The LX27901
supports analog LED current control
utilizing the BRTA pin for setting the
analog LED current.
In addition, a proprietary dimming
algorithm ACU_BRITE® is
incorporated. The controller
integrates the pulsed LED current
and compares it with a reference for
very accurate brightness control
irrespective of duty cycle.
The LX27901 is designed to operate
with Microsemi’s proprietary
lossless (magnetic) current
balancing schemes.
The controller also provides a
proprietary synchronous regulation
function to allow the user to control
the LED current and dimming from
an unregulated switching power
supply source, to minimize the
number of power conversion stages
and the associated losses and
component costs.
A versatile set of system monitoring
and protection functions are
incorporated in the LX27901 design
to provide reliable protection of the
device and the system. These can
account for shorted and open LED
strings for example.
Three input pins, ISNS, VSNS and
UVS/SYN are assigned to support
regulation and protection. A
dedicated fault indication pin allows
the user to generate a direct fault
report to the system and configure
addition protection features with
simple external circuits.
The device is available in 16 lead
SOIC surface mount package in the
industrial temperature range.
Refer to the Application Note titled
“Some Proprietary LED Current
Balancing Techniques”.
LLC, PWM and proprietary
synchronous modes to drive the LED
strings
LED strings can be dimmed by PWM
or analog methods
Proprietary algorithm to provide
accurate brightness control at high
efficiency over wide dimming duty
cycle range
Accurate parallel LED strings current
matching using Microsemi’s patented
non-dissipative current-balancing
technology
Robust protection from open or
shorted LED conditions
Dedicated fault indication
0.8A Source & Sink Drive Capability
On Chip 5.25V Regulator
Direct connection to input voltage
rail up to 27V
LLC max operating frequency to 1
MHz, PWM to 150 kHz
Synchronous regulation function to
minimize power conversion stage
RoHS compliant & halogen Free
A P P L I C A T I O N S
LCD LED Backlight TV
LCD LED Backlight Monitors
Other LED Backlight Systems
LX27901
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Analog Mixed Signal Group
One Enterprise Aliso Viejo, CA 92656 USA
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IMPORTANT: For the most current data, consult MICROSEMI’s website: http://www.microsemi.com
PACKAGE ORDER INFO
T H E R M A L D A T A
TA (C)
D
Plastic SOIC 16 Pin
JA = 82.2 C/W
RoHS Compliant / Pb-free
THERMAL RESISTANCE-JUNCTION TO AMBIENT
-40 to +85
LX27901ID
Junction Temperature Calculation: TJ = TA + (PD x JA).
The JA numbers are guidelines for the thermal
performance of the device/pc-board system. All of the
above assume no ambient airflow. JA number above is
with 4-layer pcb board.
Note: Available in Tape & Reel. Append the letters “TR” to the part number.
(i.e. LX27901ID-TR)
AA B S O L U T E M A X I M U M R A T I N G S
P A C K A G E P I N O U T
Supply Input Voltage, VIN ............................................................................... 0.3V to 36V
Signal Outputs, VDD, AOUT, BOUT, C_OUT ..............................................-0.3V to 6.5V
Signal Inputs, C_R, BRTA .................................................................. -0.3V to VDD+0.3V
Signal Inputs, ENABLE, DIM, ISNS, VSNS, UVS/SYN ................... -0.3V to VDD+0.3V
Signal Outputs COMP, SST/BCOM, FAULT ............................................... -0.3V to VDD
Maximum Junction Temperature ............................................................................... 150°C
Storage Temperature Range ......................................................................... -65C to 150C
Peak Package Solder Reflow Temperature (40 seconds maximum exposure) ........... 260°C
Lead Temperature. (Soldering 10 seconds) ................................................................ 300°C
Notes: Exceeding these ratings could cause damage to the device. All voltages are with respect to
GND. Currents are positive into, negative out of specified terminal. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those
indicated under “Recommended Operating Conditions” are not implied. Exposure to
“Absolute Maximum Ratings” for extended periods may affect device reliability.
MSC
LX27901ID
xxxx
FAULT
C_R
DIM
BRTA
VIN
UVS/
SYN
ENABLE AOUT
VDD
C_OUT
BOUT
ISNS
COMP
GND
SST/
BCOM
VSNS
LX27901ID
D PACKAGE
(Top View)
RoHS / Pb-free Matte Tin Pin Finish
E L E C T R I C A L C H A R A C T E R I S T I C S
Unless otherwise listed, the following specifications apply over the operating ambient temperature of -40°C < Temp < 85°C, and VIN = 7.5V to 27V, except where
otherwise noted and the following test conditions: VIN = 12V, CC_R = 330pF, RC_R= 15K
Parameters
Symbol
Test Conditions/Comments
MIN
TYP
MAX
Units
Power
Controller Input Voltage
VIN
7.5
27
V
Controller Operating Voltage
VDD
1µF bypass cap on VDD pin,
IVDD = 0 to 5mA
5.0
5.25
5.5
V
Power Supply Input Current
IIN
AOUT, BOUT = no load, VDD = no load
7
10
mA
Sleep Mode Current
IDDSLEEP
VIN = 24V, VENABLE < 0.8V
200
400
µA
VDD Off Voltage
ENABLE < 0.8V
0.1
V
Enable
ENABLE On
ENH
1.7
V
LX27901
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E L E C T R I C A L C H A R A C T E R I S T I C S
Unless otherwise listed, the following specifications apply over the operating ambient temperature of -40°C < Temp < 85°C, and VIN = 7.5V to 27V, except where
otherwise noted and the following test conditions: VIN = 12V, CC_R = 330pF, RC_R= 15K
Parameters
Symbol
Test Conditions/Comments
MIN
TYP
MAX
Units
Shut Down
ENL
0.8
V
LLC Resonant Mode
Threshold
VLLCTH
LLC resonant drive mode, VDD = 5.25V
2
3
V
PWM Switching Mode
Threshold
VPWMTH
PWM switching drive mode, VDD = 5.25V
3
4
V
Synchronous LED Drive Mode
Threshold
VSYN
Synchronous LED drive mode, VDD = 5.25V
4
VDD
V
Input High Current
ENIIH
ENABLE = 2V
10
µA
Input Low Current
ENIIL
0V < VENABLE < 0.8V
5
µA
Under Voltage Lockout
VDD Startup Threshold
VDDUVLOR
Rising Threshold.
4.35
4.6
4.8
V
VDD UVLO Threshold
VDDUVLOF
Falling Threshold.
4.0
4.2
4.45
V
VDD UVLO Hysteresis
VDDUVLOH
0.4
V
Output
Output Resistance
RSINK
ISINK, AOUT and BOUT, TA = 25°C
5
6
Ω
Output Resistance
RSOURCE
ISOURCE, AOUT and BOUT, TA = 25°C
5
6
Ω
Dead Time
OUTDT
TA = 25°C, at full duty
250
330
410
ns
C_OUT Output Resistance
RC_OUT
Source and sink
15
20
Ω
Switching Frequency Oscillator
Switching Frequency
Tolerance
OSCINPWM
TA = 25°C, Frequency of AOUT, BOUT in PWM
mode, CC_R=330pF, RC_R = 15K.
128.8
140
151.2
kHz
Max Oscillator Frequency
OSCMAX_LLC
TA = 25°C, Frequency of AOUT, BOUT in LLC
mode, CC_R=330pF, RC_R = 15K.
1
MHz
LLC Frequency Control
Current Source
VENABLE < 2.8V
0
200
µA
Ramp Valley Voltage
OSCVV
0.5
V
Ramp Peak Voltage
OSCPV
2.5
V
Synchronization Range
Ratio of UVS/SYN input over C_R oscillator
free run frequency
1.05
3
Ratio
LED Dimming Control
ISNS Reference
ISNSREF
TA = 25°C, input, Corresponds to 2V after
4.75X internal amplifier.
414.6
421
426.4
mV
ISNS Linear Input Range
Linear operation range for internal circuit
800
mV
BRTA Input Range
4.75 times of ISNS signal. Input outside the
range is clamped at upper or lower limit
internally.
0.5
2.0
V
Pre-Amplifier Gain
KPRAMP
4.75
Error Amp Output Capacity
Source and Sink
100
µA
LX27901
PRELIMINARY DATASHEET
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One Enterprise Aliso Viejo, CA 92656 USA
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Multipurpose High Performance LED Controller
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E L E C T R I C A L C H A R A C T E R I S T I C S
Unless otherwise listed, the following specifications apply over the operating ambient temperature of -40°C < Temp < 85°C, and VIN = 7.5V to 27V, except where
otherwise noted and the following test conditions: VIN = 12V, CC_R = 330pF, RC_R= 15K
Parameters
Symbol
Test Conditions/Comments
MIN
TYP
MAX
Units
DIM Input Voltage Range
VDIM
Effective for duty from 0 to 100%
0.5
2.0
V
PWM Dimming Mode Control
Threshold
VPDMODETH
Voltage level of FAULT pin, in ACU_BRITE
PWM dimming mode when below threshold; in
conventional PWM dimming mode when
above threshold.
2.8
3.0
3.2
V
Fault Monitoring and Protection
VSNS Threshold
VSNSTH
Fault when above the threshold
1.8
2.0
2.2
V
VSNS Clamping Current
Source
ICLAMP
Pull down source at COMP pin
160
µA
UVS/SYN Threshold
UVS/SYNTH
Fault when below the threshold, positive and
negative input
0.35
0.4
0.45
V
UVS/SYN Input Range
VUVS/SYN
Functional operation range, positive and
negative input
-0.5
4
V
ISNS Fault Threshold
VISNSTH
Fault when below the threshold
85
100
115
mV
Over Current Threshold
OCTH
Upper threshold for ISNS input
550
600
650
mV
Short Circuit Threshold
SCTH
Upper threshold for ISNS input
870
930
990
mV
Fault Count
FC
At clock frequency of AOUT, BOUT
256
Count
Fault reset Interval
FRESET
Interval for resetting fault counter, At clock
frequency of AOUT, BOUT
32768
Count
Fault Output Sinking Capacity
FSINK
VFAULT ≤ 0.8V, TA = 25°C
4
6
mA
Fault Output Open Impedance
RF
When in open state
5
MΩ
Bias & References
Internal Master Reference
Voltage
VREF
1.2
V
Soft Start Charging Source
ISSC
C_B Charging source at start up
2
µA
Power-Up Sequencing
Power On Reset Time
TPOR
After UVLO of VDD released
50
µs
Start up Time Out
TSTART
After POR
32768
Count
F U N C T I O N A L P I N D E S C R I P T I O N
Name
Pin #
Description
VIN
1
Input voltage pin. A built-in regulator is connected to this pin to step down the input voltage to the internal
operating voltage VDD. This pin can accept input voltage from 10V to 27V to provide the flexibility of
interfacing with either 12V or 24V system supply. A low ESR decoupling capacitor of not less than 1µF
should be connected from this pin to GND with low impedance traces.
ENABLE
2
Enable pin to control the on/off operation of the controller. A logic low signal <0.8V on this pin sets the
LX27901
PRELIMINARY DATASHEET
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F U N C T I O N A L P I N D E S C R I P T I O N
Name
Pin #
Description
controller in sleep mode to save energy, and a signal > 2V activates the controller operation. The DC signal
level on this pin also sets the drive mode of the controller. When 2V<VENABLE<3V the AOUT, BOUT signals
are set in LLC resonant drive mode. When 3V<VENABLE<4V the controller drives the power converter in
normal PWM drive mode; and when VENABLE >4V the controller is set in synchronous LED drive mode.
C_R
3
Converter operating frequency programming terminal. A pull-up resistor from this pin to VDD and a
capacitor connected from this pin to ground determines the switching frequency of the inverter.
BRTA
4
Terminal for programming the analog LED current setting. An analog signal is accepted from this pin to set
the reference level for the LED current control loop.
DIM
5
PWM dimming control input. VDIM > 2V sets the dimming operation in continuous analog mode. A PWM
signal of low level <0.5V and high level > 2V will force the PWM dimming operation to follow the PWM
signal directly. Input level <0.5V will stop the controller output.
SST/BCOM
6
For PWM dimming brightness compensation and soft start. The elapsed dimming demand and the
accumulated LED current over the active dimming period are compared at this pin. The comparison result
is used to control the LED light output to exactly match the dimming demand with compensation for the
distortion of the LED current during dimming operation. At start up this pin is connected to a 2µA charging
current source to control the soft start process. An internal active pull down circuit is connected from this
pin to COMP to force the COMP voltage rise slowly with the charge of the capacitor at this pin. Soft start
completes when the voltage rises to 2.5V and the control enters normal operation mode. The 2µA charging
source and the COMP pull down circuit is disconnected then, and this pin is connected to the brightness
compensation circuit.
FAULT
7
Fault indication pin with open drain output. Internally pulled down when an open LED string, severely
shorted LED string, over voltage of the LED strings, or over current occurs. Once latched, the fault signal
can only be reset by ENABLE or power recycling. The voltage level at this pin during normal operation also
sets the operation mode of dimming control. When the voltage is above 3V the COMP signal is turned on
and off by the digital dimming control signal and AOUT, BOUT and C_OUT are turned on and off
accordingly by the COMP signal. When the voltage at the FAULT pin is below 3V the COMP signal is
turned on and off by the control signal from the ACU_BRITE dimming control algorithm, and AOUT, BOUT
and C_OUT are turned on and off accordingly by the COMP signal. The voltage level of this pin during
normal operation can be set by an external resistive divider.
UVS/SYN
8
Sense for under voltage conditions. A threshold of 0.4V is set internally to compare the sense feedback
signal to this pin when the LED strings are on. A fault will be declared if the sensed signal stays below the
threshold over certain counts set by the internal circuitry. LED string current and voltage sense signals can
be fed to this pin to detect open or short string conditions. When the controller is set in synchronous
regulation mode UVS/SYN will receive the synchronization signal from the power supply to synchronize the
switching frequency of AOUT and BOUT. An internal rectifier circuit is included to allow an AC input signal
to be connected to this pin directly.
VSNS
9
Voltage sense input pin. The voltage signal on this pin feeds the over voltage detection circuit. A threshold
of 2V is set internally for fault detection. When the voltage sense signal reaches the threshold of 2V, a
clamping current source will be activated to pull down COMP signal to limit the sensed voltage. In the
meanwhile, the fault monitoring circuit will start counting the accumulated fault duration and set up the fault
flag when the fault count reaches pre-determined counts.
ISNS
10
Current sense input pin. A full wave rectifier circuit is built in to allow AC input to this pin. The regulation
point at this pin is 421mV which is amplified by 4.75 times and then fed to the error amplifier to compare
with a reference signal of 2V to regulate the LED current. This signal is also used to detect open LED, over
current and short circuit conditions. The threshold for open LED is 100mV, the threshold of over current is
600mV, and the threshold for short circuit is 930mV. A fault flag will be declared if ISNS signal stays below
100mV or above 600mV over defined counts, and the operation will be cut off immediately when ISNS
signal goes above 930mV.
LX27901
PRELIMINARY DATASHEET
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F U N C T I O N A L P I N D E S C R I P T I O N
Name
Pin #
Description
COMP
11
Output of the error amplifier. The error amplifier is a GM type that provides robust control behavior and
simple compensation. The signal on this pin feeds to the PWM modulation circuit to control the drive output
to regulate the LED current. At start up the voltage of this pin is controlled by the soft start circuit.
C_OUT
12
Gate signal to drive an additional MOSFET for LED current regulation. The signal is synchronized with the
C_R oscillator frequency and is leading edge modulated by the output of the error amplifier in LLC and
synchronous regulation modes and trailing edge modulated in PWM half-bridge drive mode. This signal
can be used in combination with AOUT and BOUT to extend the regulation range in LLC operation mode or
provide additional driving capabilities in synchronous regulation mode.
AOUT
BOUT
15
13
Gate drive outputs. These driver outputs are capable of providing 0.8A source and sink current at nominal
operating voltage. Dead time is inserted to prevent possible shoot through at full duty cycle. Internal pull
down resistors of 20kΩ are provided at each of these pins. When the controller is in LLC mode AOUT and
BOUT are driven to maximum duty cycle (50%), and their switching frequency varies with the COMP signal
level. When the controller is in PWM mode these two outputs generate standard (non-resonant)
synchronous pulse-width modulated signals at fixed frequency. When the controller is in synchronous LED
drive mode, UVS/SYN receives the synchronization signal, AOUT outputs an N-channel FET drive signal
synchronized with the rising edge of the (UVS/SYN) sync input signal, and BOUT outputs a P-channel FET
drive signal synchronized with the falling edge cycle of the (UVS/SYN) sync input signal. Together they
drive the external power devices to control the LED current directly (synchronous topology). This is
different from the PWM mode, because the pulse-width of AOUT and BOUT signals is leading edge
modulated in the synchronous drive mode.
GND
14
Ground return of the on chip circuit. It is important to provide a low impedance ground plane to this pin and
the signal control circuitry in PCB layout, and not let the ground return current of the inverter power circuit
flow through the signal ground plane. Low ESR bypass capacitors for VDD and VDD should be connected
with lowest possible impedance to this pin through the signal ground plane.
VDD
16
The operating voltage of the IC. A built-in regulator supplies a regulated 5.25V derived from VIN supply to
this pin. A low ESR decoupling capacitor of not less than 1µF should be connected from this pin to GND
with low impedance traces.
LX27901
PRELIMINARY DATASHEET
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One Enterprise Aliso Viejo, CA 92656 USA
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F U N C T I O N A L B L O C K D I A G R A M
VIN
VDD
ENABLE
BRTA
SST/
BCOM
DIM
FREQUENCY
CONTROL
OSCILLATOR
CIRCUIT
FWR & 5X
AMP I_SNS
CONTROL
ACU_BRITE
SOFT START
CONTROL
INITIALAZATION
LOGIC
+
-
0.4V
PWM
MODULATION
DRIVER
BLOCK
AOUT
+
-
IS
+
-
FAULT
FAULT TIMING
CONTROL
UVS/
SYN
FULL WAVE
RECTIFIER
LX27901 GND
2.0V
+
-
3.0V
PWM
DIMMING
CONTROL
C_OUT
BOUT
VDD
REGULATOR
UVLO &
POR
LOGIC
MODE
SELECTION
LOGIC
START UP &
RESET TIMER
RESET
CLOCK
SYNC LOGIC
RAMP
GENERATION
SYNC POINT
DETECTION
Q
Q
SET
CLR
S
R
+
-
+
-
0.5V
4.65V
3.0V
ISNS
COMP
+
-
FAULT
POR
IS
VSNS
+
-
+
-
EA
C_R
0.5V
1.5V
POR
POR
CLOCK
D
Q
Q
_
V
SYNC
RESET
PHASE SIGNAL
PWM SIGNAL
SYNC
PWM DIMMING
CONTROL
Figure 1. LX27901 Functional Block Diagram.
LX27901
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T Y P I C A L P E R F O R M A N C E C H A R A C T E R I S T I C S
Figure 2
Figure 3
Figure 4
Figure 5
LX27901
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Figure 6
Figure 7
T Y P I C A L P E R F O R M A N C E C H A R A C T E R I S T I C S
S T A R T U P W I T H E N A B L E L L C M O D E
Figure 8
Channel 1: BOUT, Channel 2: I_LED
Channel 3: AOUT, Channel 4: ENABLE
O U T P U T T I M I N G S Y N C M O D E
Figure 9
Channel 1: AOUT, Channel 2: BOUT
Channel 3: COUT, Channel 4: UVS
D I M M I N G S Y N C M O D E
V S N S O V P R O T E C T I O N M O D E
LX27901
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Figure 10
Channel 1: AOUT, Channel 2: BOUT
Channel 3: COUT, Channel 4: UVS
Figure 11
Channel 1: AOUT, Channel 2: C_R
Channel 3: FAULT, Channel 4: VSNS
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T Y P I C A L P E R F O R M A N C E C H A R A C T E R I S T I C S
L L C D I M M I N G M O D E
Figure 12
Channel 1: AOUT, Channel 2: BOUT
Channel 3: COUT, Channel 4: C_R
P W M D I M M I N G M O D E
Figure 13
Channel 1: AOUT, Channel 2: BOUT
Channel 3: COUT, Channel 4: C_R
A C U _ B R I T E D I M M I N G M O DE
Figure 14
Channel 1: AOUT, Channel 2: BOUT
Channel 3: PWM_DIM, Channel 4: ILED
D I R E C T P W M D I M M I N G M O D E
Figure 15
Channel 1: AOUT, Channel 2: BOUT
Channel 3: PWM_DIM, Channel 4: ILED
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A C U _ B R I T E D I M M I N G M O DE
Figure 16
Channel 1: AOUT, Channel 2: BOUT
Channel 3: PWM_DIM, Channel 4: ILED
D I R E C T P W M D I M M I N G M O D E
Figure 17
Channel 1: AOUT, Channel 2: BOUT
Channel 3: PWM_DIM, Channel 4: ILED
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T Y P I C A L A P P L I C A T I O N S C H E M A T I C
1uF
R69
R184
BX2
1 4
3 5
R17R185
LED
LED1
LED
LED
LED2
LED
LED
LED3
LED
LED
LED4
LED
D8
R186
D1
C25
D7
C23
D2
C24
U1
LX27901
C_R
3
DIM
5
BRTA
4
SST/BCOM
6
FAULT
7ISNS 10
COMP 11
C_OUT 12
BOUT 13
GND 14
AOUT 15
ENABLE
2
VIN
1VDD 16
UVS/SYN
8VSNS 9
C26
C21
R24
C22
R25
BAV70
2
31
C10
10K
PGND
C7
C14
C6
2K
C40 1uF
5.1K
10K
TX1
15
3
2
4
C11
PWM_DIM
BX1
1 4
3 5
D1
ENABLE
51K
D2
+12V
C41 1uF VDD
C12
Q2
+C1
47u/450V
R2
2K
R1
R4
R5 R8
200K
2K
2K
R15
0.4R
3K
10K
BAS21
13
3K
2K
C13
4R7
2
4
9
10
6
7
Q1
BAS21
13
C2
C3 0.01U/450V
100p
4R7
C9
FAULT
1K
220p
0.01u 0.1u
VDC+
5.1K 1nF 1nF
5.1K
R3
0.01u
BAV70
2
31
1nF
D3 D4
R231
4.7n
R6
R232
R337
R338
A_DIM
10K
R7
Figure 18
LLC CONTROL MODE
(The component values are for reference only, modifications may be necessary for a particular application requirement.)
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20KR6
D3
D4
A_DIM
U1
LX27901
C_R
3
DIM
5
BRTA
4
SST/BCOM
6
FAULT
7ISNS 10
COMP 11
C_OUT 12
BOUT 13
GND 14
AOUT 15
ENABLE
2
VIN
1VDD 16
UVS/SYN
8VSNS 9
R24
R25
C10
C14
C7
C6
2K
C31 1uF
PWM_DIM
5.1K
10K C11
BX1
1 6
3 4
2 5
ENABLE
D1A
51K
+12V VDD
C32 1uF
C12
D5 BAV70
2
31
R4
1K
R5
R15
R8
0.4R
2K
C13
100p
FAULT
C9
0.1u
220p
C11
1nF
C12
1nF
5.1K
R3
R7 0.01u 1nF
4.7n Q3
10K
PGND
Q2
+C1
Q1
VDC+
C3
TX1
1
2
8
7
6
11
10
9
D1B
DRIVE CONTROL
FOR VDC1
D2A
D2B
VDC1
2K
100K
R92
R93
2K
100K
R95
R96
R100
LED1 LED2
Figure 19
SYNCHRONOUS REGULATION MODE
(The component values are for reference only, modifications may be necessary for a particular application requirement.)
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O O P E R A T I O N D O P E R A T I O N D E S C R I P T I O N E S C R I P T I O N
INTRODUCTION
This section describes the operation of LX27901 LED
drive controller. LX27901 is primarily designed for LIPS
power systems for LED backlit LCD TV and other large
screen CCFL backlight applications that addresses the
need to drive a half bridge or full bridge inverter stage
from the 400V PFC output across the safety isolation
barrier. It provides an optimized low cost solution for
such applications while providing a set of comprehensive
control features to fully satisfy the technical
requirements.
1. SYSTEM OVERVIEW
The system contains the following main function blocks:
Power and Start-Up Logic
Oscillator and Frequency Control Circuit
Regulation Control Circuit
Dimming Control Circuit
Drive Control Circuitry
Fault Detection and Protection Circuitry
The power and start-up logic provides regulated power
to the on chip circuitry and controls the start-up
sequencing, power on reset, and soft start operation etc.
The oscillator and frequency logic generates the clock
signals for the LLC and PWM operation and timing for
the operation and protection. The regulation and
dimming control logic handles the LED current
regulation and dimming control operation with
Microsemi’s proprietary ACU_BRITE technology to
provide accurate brightness control with non-dissipative
operation of the power devices. The drive control circuit
converts the PWM signal from the regulation and control
circuit to power drive signals to drive the external power
devices of the power supply and LED string control. The
fault detection and protection logic monitors the
operation of the internal and external circuits and
provides fault warning and protection for the system.
2. POWER CONTROL AND START UP
The LX27901 has a built in regulator to step down the
input voltage VIN to a regulated 5.25V supply VDD to
support the on chip circuitry. The regulator is controlled
by the ENABLE signal and is only activated when
ENABLE voltage goes above its logic threshold, thus
minimizing the power consumption at sleep mode. An
UVLO circuit is employed to monitor the VDD voltage.
The UVLO circuit releases the lock out function when
VDD reaches its rising threshold and initiates the Power
On Reset (POR) signal.
The POR signal initializes the whole control circuitry by
resetting the counters, registers, fault latch, setting the
analog signals such as the SST/BCOM and C_B voltage to
pre-determined initial values, while holding off the
output signals to pre-determined inactive states. After
the preset delay time the POR signal is released and the
controller operation starts.
3. OSCILLATOR AND FREQUENCY CONTROL
The system has a built in clock to control the switching
frequency. A resistor and a capacitor are required,
connected between VDD and C_R pin and from C_R pin to
ground respectively to set the oscillating frequency. A
controlled charging current source is also provided
internally to the C_R pin to adjust the oscillator
frequency when the ENABLE voltage level is set in LLC
resonance control mode. When the ENABLE voltage
level is set in PWM mode, the current source is
disconnected and the oscillator returns to the free run
frequency set by the external RC components.
4. REGULATION CONTROL
The regulation circuit controls the LED current through
closed loop regulation. The LED current is sensed and
fed to the ISNS pin as a feedback signal where it is
regulated by an internal transconductance error
amplifier to match the current reference threshold. This
controls the PWM drive of the external switching
MOSFETs of the power conversion circuit. The output of
the error amplifier, available on the COMP pin, allows the
user to adjust the control loop directly if desired. Three
power supply control modes are incorporated into the
controller operation
LLC Resonant control Mode: In LLC resonant mode the
PWM drive output signals AOUT and BOUT remain at full
duty cycle (50%), and the output signal from the error
amplifier controls the internal charging current source at
C_R pin to adjust the switching frequency of AOUT and
BOUT to regulate the LED current. Note that in this mode
the operating frequency of the drive signals should be
always higher than the resonance frequency.
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PWM control Mode: The internal current source at C_R
pin is disconnected and AOUT and BOUT signals remain
at the fixed frequency set by the RC components at C_R
pin, and the LED current is regulated by adjusting the
pulse width of the AOUT and BOUT signals.
Synchronous regulation Mode: The synchronization
signal from the power supply is received from UVS/SYN
pin and AOUT and BOUT output drive signals in
synchronous with the synchronization signal to drive
respective external switches in series with the LED
strings to control the LED current. In this mode AOUT
and BOUT are leading edge modulated PWM drive
signals controlled by the closed current loop from ISNS
feedback. The three control modes are selectable by the
voltage level of ENABLE signal. When 2V<VENABLE<3V the
controller is in LLC resonant drive mode; when
3V<VENABLE<4V the controller drives the power supply in
PWM drive mode; and when VENABLE>4V the controller
drives the external device in synchronous regulation
mode.
5. DIMMING CONTROL
The LX27901 supports external burst dimming and
analog dimming functions. In external digital dimming
mode a dimming pulse train is supplied to DIM pin and
the dimming operation follows the input pulse train
directly. It is recommended that the high state of the
pulse train should be higher than 2V and the low state
should be lower than 0.5V. This signal is compared with
an internal DC level of 1.5V to generate an internal PWM
pulse train to control the burst dimming operation.
A unique feature called ACU_BRITE is incorporated to
compensate the LED current error by digital dimming
duty adjustment. A capacitor from SST/BCOM pin to
ground provides an integration function for such control.
A controlled charging current source and a controlled
discharging current source are connected internally to
the SST/BCOM pin. The charging current source is
linearly proportional to the internal current regulation
reference and turned on and off by the internal digital
dimming signal. The discharging current source is
proportional to the ISNS signal at the same ratio as the
charging source to the internal reference. At power on
reset the SST/BCOM capacitor is discharged to zero and
the capacitor is used for soft start operation. When the
capacitor voltage reaches 2.5V it switches over to
ACU_BRITE dimming control function. The voltage of
SST/BCOM is fed to a comparator and compared with a
threshold level of 2.5V. When VSST/BCOM is greater than
2.5V, the LED current is turned on, and when VSST/BCOM is
lower than 2.5V, the LED current is turned off.
With such control mechanism the integration of the LED
current always matches the integration of its reference
over the digital dimming operation to yield an accurate
brightness control. This feature essentially enables the
control of dimming operation by turning on and off the
power supply directly without losing dimming accuracy,
instead of putting an additional control device in series
with the LED string to control the LED on/off. The LED
current distortion at the rising and falling edge of the
digital dimming operation is accurately compensated by
the dimming duty adjustment, the no load power supply
losses at LED off state are eliminated, and the serial
control device is removed.
6. DRIVE CONTROL CIRCUIT
The drive control circuit converts the PWM signal
from the regulation and control circuit to the drive
output signals AOUT, BOUT and C_OUT to drive the
external power devices for the power supply and LED
string control. The signals from AOUT and BOUT are
180° out of phase. When the controller is in LLC
resonant mode AOUT and BOUT remain at full duty, and
their switching frequency varies with the COMP signal
level to adjust the power supply output. When the
controller is in the PWM control mode AOUT and BOUT
remain at a fixed switching frequency but their duty
cycle varies with the COMP signal level. When in
synchronous regulation mode AOUT outputs a NFET
drive signal in synchronous with the positive cycle of the
synchronization signal from UVS/SYN pin, and BOUT
outputs a PFET drive signal in synchronous with the
negative cycle of the synchronization signal from
UVS/SYN to drive the external devices. In this mode the
AOUT and BOUT signal is a leading edge modulated
PWM signal with their falling edge in synchronous with
the zero crossing point of the synchronization signal to
minimize their turn off transient and their pulse width is
controlled by the closed current loop from ISNS
feedback. The driving capacity of AOUT and BOUT is
0.8A in both the sourcing and sinking mode.
The signal from C_OUT provides the user additional
control for LED current regulation. The signal is in
synchronous with the C_R oscillator frequency and is
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O P E R A T I O N D E S C R I P T I O N
leading edge modulated by the output of the error
amplifier in LLC and synchronous regulation modes, and
trailing edge modulated in PWM half bridge drive mode.
This signal can be used in combination with AOUT and
BOUT to extend regulation range in LLC operation mode
or provide additional driving capabilities in synchronous
regulation mode.
7. SOFT START
Soft start is accomplished by internal circuitry in
combination with the SST/BCOM capacitor charging
control. At power on the SST/BCOM capacitor is
discharged to zero during POR. When the operation
commences following POR the SST/BCOM pin is
disconnected from the dimming control circuit and a
small soft start current source of 2 µA is turned on to
charge the SST/BCOM capacitor slowly. The voltage of
the SST/BCOM capacitor pulls down the COMP signal
through the soft start circuit to force the VCOMP signal to
rise slowly together with it. During this course the
voltage amplitude of SST/BCOM is monitored. When the
SST/BCOM signal rises to 2.5V, the soft start current
source is turned off and the SST/BCOM pin switches over
to the internal dimming control circuit. The capacitor at
SST/BCOM is charged and discharged by the ACU_BRITE
brightness compensation circuit and its voltage is
compared with a 2.5V reference to turn on and off the
AOUT, BOUT and C_OUT signals while the COMP signal
resumes its role in the regulation function. During start
up a timer-counter circuit is also furnished to monitor
the system operation. If the ISNS signal does not reach
100mV after the counter reaches the full count of 32k
(15 bit) clock cycles, the start-up is considered failed and
a fault flag is raised by pulling down the FAULT pin
signal.
3. 8. FAULT DETECTION AND PROTECTION
The following system operating conditions are
monitored with fault reporting and protection:
Open LED string, Short LED string, Power supply failure,
Over voltage and Over current. The above fault
conditions are monitored from the ISNS, VSNS and
UVS/SYN inputs. The ISNS signal is used to monitor open
LED, power supply failure and over current conditions.
Open LED detection is disabled during start up until the 15
bit counter times out.
After the counter time out if ISNS signal is still below
100mV while the LED is on, it indicates an open LED or
power supply failure condition. A fault counter will start
to count the fault. When the counter reaches the full
count of 256, a fault condition is confirmed and the
FAULT pin is pulled to low state to indicate a fault
condition. The fault counter is incremented by a clock at
the same frequency as AOUT, BOUT and reset
periodically at an interval of 32768 clock pulses. In
addition, during the interval if there is any single
occurrence of ISNS>100mV it will reset the fault counter
and the fault counting has to start all over again. Such
reset mechanism guarantees reliable fault detection and
prevents noise triggered false fault reporting. The ISNS
signal is also used to monitor over current and short
circuit conditions. A typical threshold of 600mV is set
for over current detection and a typical threshold of
930mV is set for short circuit detection. The fault
counter will start counting when ISNS>600mV occurs
and reports a fault when the counter reaches full count
of 256. Periodical reset at every 32768 clock cycle
interval is also employed for the fault counter.
In addition, a time delay circuit, similar to a one shot, is
employed to hold the over current status for about 50µs.
The fault counter will be reset if the over current
condition does not persist when the elapsed holding
time is over. When ISNS signal exceeds 930mV typically
it will be recognized as a short circuit. The output signal
will be shut off immediately with a fault flag raised. The
short circuit detection is active all the time after POR
release.
The VSNS signal is used to limit and monitor over
voltage condition. When the voltage sense signal reaches
the threshold of 2V, a clamping current source will be
activated to pull down COMP signal to limit the sensed
voltage. In the meanwhile, the fault counter starts
counting and reports fault condition when the counter
reaches full count. Periodical reset at every 32768 clock
cycle interval also applies to the VSNS fault counting.
Similarly a time delay circuit is also employed to hold the
over voltage status for about 50µs. The fault counter will
be reset if the over voltage condition does not persist
when the elapsed holding time is over. In actual
applications, if a balancer network is deployed in the
drive system, the signals from the secondary winding
loop can also be fed to VSNS pin to detect open or short
LED fault. When a LED string is open or shorted, the
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voltage in the primary and secondary winding of the
associated balancer will rise dramatically, and such
distinctive signal change can be readily used for open or
short LED detection with VSNS circuit.
The UVS/SYN signal provides further means for fault
detection. A threshold of 0.4V is set internally for the
UVS/SYN signal. When UVS/SYN<0.4V occurs, the fault
counter also starts counting and reports a fault condition
when the counter reaches full count Periodical reset at
every 32k clock cycle interval also applies to the
UVS/SYN fault count. Similarly a time delay circuit is
also employed to hold the over voltage status for about
50µs. The fault counter will be reset if the over current
condition does not persist when the elapsed holding time
is over.
SETTING OPERATING FREQUENCY
The switching frequency of AOUT and BOUT is
programmed with the external capacitor and resistor,
RC_R and CC_R.
RCRC
SW CR
f
__
693000
fSW is the switching frequency in kHz, RC_R is in kohms,
and CC_R is in pF. For most applications, lamp free run
frequency is set at less than 150kHz. Normally CC_R can
be chosen from 220pF to 470pF, and the value of RC_R can
also be used to adjust the frequency control range in LLC
mode.
SETTING COMP PIN CAPACITOR
An external capacitor CCOMP is connected from this pin to
ground to adjust loop response of the inverter module.
The error amplifier is a GM type that provides robust
control behavior and simple compensation. The ideal
current error amplifier compensation depends on the
dimming mode operation range. If minimal dimming is
required by the application the loop response can be
slower, but for wide range digital dimming it must be
fast enough to allow the lamp current to get to full
amplitude within a few current cycles.
If value of CCOMP is small the gain will be increased and
may result in overshoot, and the loop could become
unstable. However as the capacitor value is increased it
will reduce the gain and the loop response may be too
slow. Therefore it is necessary to choose an optimal
value, typical recommended values range from 1nF to
10nF, but should be adjusted depending on the
application requirements.
VIN, VDD BYPASS CAPACITOR
The LX27901 has internal Low Dropout Regulator to
generate an accurate 5V supply for the internal control
circuitry. In order to have stable operation, it is required
to provide bypass capacitor with low ESR between both
VIN and VDD and ground. It is recommended to use a
capacitance of not less than 1F for VIN and 1uF for
VDD.
LAYOUT GUIDELINES
It is important to have a good PCB layout to achieve
stable operation. Especially, high voltage section and the
power switching section of the circuit layout require
particular attention. High voltage section layout also
needs to be planned carefully to meet Safety
requirement as well as proper isolation from the control
circuit. Following are guidelines for inverter PCB layout
1) Use a star-ground connection for analog and power
ground. Analog ground should be isolated from
power ground except one connection point, GND
pin.
2) Route high speed digital signal traces away from
sensitive analog signals.
3) Place decoupling cap as close to related pin as
possible.
4) Make shortest and direct connection from feedback
sources.
5) Keep short and wide for high current signal paths
especially ground.
6) Make trace as thick as possible
7) Route current sense and voltage divider traces away
from high voltage field.
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P A C K A G E D I M E N S I O N S
D
16-Pin Plastic Narrow Body SOIC
H
e
11 8
916
E
B
A
D
L
A1 c
A2
DIM
MILLIMETERS
INCHES
MIN
MAX
MIN
MAX
A
1.35
1.75
0.053
0.069
A1
0.10
0.25
0.004
0.010
A2
1.25
1.52
0.049
0.060
b
0.33
0.51
0.013
0.020
c
0.19
0.25
0.007
0.010
D
9.78
10.01
0.385
0.394
E
5.79
6.20
0.228
0.244
e
1.27 BSC
0.050 BSC
H
3.81
4.01
0.150
0.158
L
0.40
1.27
0.016
0.050
Θ
0
8
0
8
*LC
0.10
0.004
*Lead Coplanarity
Note:
1. Controlled dimensions are in mm, inches are for
reference only.
2. Dimensions do not include mold flash or protrusions;
these shall not exceed 0.155mm (.006”) on any side.
Lead dimension shall not include solder coverage.
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N O T E S
PRELIMINARY DATA – Information contained in this document is pre-production data
and is proprietary to Microsemi. It may not be modified in any way without the express
written consent of Microsemi. Product referred to herein is offered in pre-production form
only and may not have completed Microsemi’s Quality Assurance process for Release to
Production. Microsemi reserves the right to change or discontinue this proposed product
at any time.
