DC1369A-C - ANALOG DEVICES - Product.Network

QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 1369

12/14 BIT, 25 TO 150 MSPS ADC

1

LTC2261-14, LTC2261-12, LTC2260-14, LTC2260-12, LTC2259-14, LTC2259-12, LTC2258-14,

LTC2258-12, LTC2257-14, LTC2257-12, LTC2256-14, LTC2256-12, LTC2262-14, LTC2262-12

DESCRIPTION

Demonstration circuit 1369 supports a family of 14/12

BIT 125 MSPS ADCs. Each assembly features one of

the following devices: LTC2261-14, LTC2261-12,

LTC2260-14, LTC2260-12, LTC2259-14, LTC2259-12,

LTC2258-14, LTC2258-12, LTC2257-14, LTC2257-12,

LTC2256-14, LTC2256-12, LTC2262-14, or LTC2262-

12 high speed, high dynamic range ADCs.

Demonstration circuit 1369 supports the LTC2261 fam-

ily DDR LVDS output mode. This family of ADCs is

also supported by demonstration circuit 1370A, which

is compatible with CMOS and DDR CMOS output

modes.

Several versions of the 1369A demo board supporting

the LTC2261 12/14-BIT series of A/D converters are

listed in Table 1. Depending on the required resolution

and sample rate, the DC1369 is supplied with the ap-

propriate ADC. The circuitry on the analog inputs is

optimized for analog input frequencies from 5 MHz to

170MHz. Refer to the datasheet for proper input net-

works for different input frequencies.

Design files for this circuit board are available. Call

the LTC factory.

LTC is a trademark of Linear Technology Corporation

Table 1.

DC1369Variants

DC1369

VARIANTS

ADC PART

NUMBER

RESOLUTION* MAXIMUM SAMPLE

RATE

INPUT FREQUENCY

1369A-A

LTC2261-14 14-BIT 125 Msps 5MHz-170MHz

1369A-B

LTC2260-14 14-BIT 105 Msps 5MHz-170MHz

1369A-C

LTC2259-14 14-BIT 80 Msps 5MHz-170MHz

1369A-D

LTC2258-14 14-BIT 65 Msps 5MHz-170MHz

1369A-E

LTC2257-14 14-BIT 40 Msps 5MHz-170MHz

1369A-F

LTC2256-14 14-BIT 25 Msps 5MHz-170MHz

1369A-G

LTC2261-12 12-BIT 125 Msps 5MHz-170MHz

1369A-H

LTC2260-12 12-BIT 105 Msps 5MHz-170MHz

1369A-I

LTC2259-12 12-BIT 80 Msps 5MHz-170MHz

1369A-J

LTC2258-12 12-BIT 65 Msps 5MHz-170MHz

1369A-K

LTC2257-12 12-BIT 40 Msps 5MHz-170MHz

1369A-L

LTC2256-12 12-BIT 25 Msps 5MHz-170MHz

1369A-M

LTC2262-14 14-BIT 150Msps 5MHz-170MHz

1369A-N

LTC2262-12 12-BIT 150Msps 5MHz-170MHz

QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 1369

12/14 BIT, 25 TO 150 MSPS ADC

2

Table 2.

Performance Summary (TA = 25°C)

PARAMETER CONDITION VALUE

Supply Voltage – DC1369A Depending on sampling rate and the A/D converter

provided, this supply must provide up to 250mA.

Optimized for 3.6V

[3.5V 6.0V min/max]

Analog input range Depending on SENSE Pin Voltage 1 V

PP

to 2V

PP

Minimum Logic High 1.3V

Logic Input Voltages

Maximum Logic Low 0.6V

Nominal Logic levels (100Ω load, 3.5mA Mode) 350mV/1.25V com

mon mode

Logic Output Voltages (differential)

Minimum Logic levels (100Ω load, 3.5mA Mode) 247mV/1.25V common mode

Sampling Frequency (Convert Clock Fre-

quency)

See Table 1

Convert Clock Level Single ended Encode Mode (ENC- tied to GND) 0-3.6V

Convert Clock Level Differential Encode Mode (ENC- not tied to GND) 0.2V-3.6V

Resolution See Table 1

Input frequency range See Table 1

SFDR See Applicable Data Sheet

SNR See Applicable Data Sheet

QUICK START PROCEDURE

Demonstration circuit 1369 is easy to set up to

evaluate the performance of the LTC2261 A/D

converters. Refer to Figure 1 for proper meas-

urement equipment setup and follow the proce-

dure below:

SETUP

If a DC890 FastDAACS Data Acquisition and

Collection System was supplied with the DC1369

demonstration circuit, follow the DC890 Quick

Start Guide to install the required software and

for connecting the DC890 to the DC1369 and to

a PC running Windows98, 2000 or XP.

3

Figure 1. DC1369 Setup (zoom for detail)

DC1369 DEMONSTRATION CIRCUIT BOARD JUMPERS

The DC1369 demonstration circuit

board should have the following jumper

settings as default positions: (as per

Figure 1)

JP2: PAR/SER : Selects Parallel or Serial

programming mode. (Default - Serial)

JP3: Duty Cycle Stabilizer: Enables/ Disable

Duty Cycle Stabilizer. (Default - Enable)

JP4: SHDN: Enables and disables the

LTC2261. (Default - Enable)

3.5-6V

+

Analog Input

Single End

ed

Encode Clock

Parallel Data Output

To DC890

Jumpers are shown in

default positions.

Duty Cycle Stabilizer

SHDN

Parallel/Serial

Programming mode

4

APPLYING POWER AND SIGNALS TO THE

DC996 DEMONSTRATION CIRCUIT

If a DC890 is used to acquire data from the

DC1369, the DC890 must FIRST be con-

nected to a powered USB port or provided an

external 6-9V BEFORE applying +3.6V to

+6.0V across the pins marked “V+” and

“GND” on the DC1369. DC1369 requires 3.6V

for proper operation. Regulators on the board

produce the voltages required for the ADC.

The DC1369 demonstration circuit requires up

to 250mA depending on the sampling rate and

the A/D converter supplied.

The DC890 data collection board is powered

by the USB cable and does not require an ex-

ternal power supply unless it must be con-

nected to the PC through an un-powered hub,

in which case it must be supplied an external

6-9V on turrets G7(+) and G1(-) or the adja-

cent 2.1mm power jack.

ANALOG INPUT NETWORK

For optimal distortion and noise performance

the RC network on the analog inputs may

need to be optimized for different analog input

frequencies. For input frequencies above 170

MHz, refer to the LTC2261 datasheet for a

proper input network. Other input networks

may be more appropriate for input frequen-

cies less that 5MHz.

In almost all cases, filters will be required on

both analog input and encode clock to provide

data sheet SNR. In the case of the DC1369 a

band pass filter used for the clock should be

used prior to the DC1075A.

The filters should be located close to the in-

puts to avoid reflections from impedance dis-

continuities at the driven end of a long trans-

mission line. Most filters do not present 50Ω

outside the passband. In some cases, 3dB to

10dB pads may be required to obtain low dis-

tortion.

If your generator cannot deliver full scale sig-

nals without distortion, you may benefit from a

medium power amplifier based on a Gallium

Arsenide Gain block prior to the final filter.

This is particularly true at higher frequencies

where IC based operational amplifiers may be

unable to deliver the combination of low noise

figure and High IP3 point required. A high or-

der filter can be used prior to this final ampli-

fier, and a relatively lower Q filter used be-

tween the amplifier and the demo circuit.

ENCODE CLOCK

NOTE: Apply an encode clock to the SMA

connector on the DC1369 demonstration cir-

cuit board marked “J7”. As a default the

DC1369 is populated to have a single ended

input.

For the best noise performance, the ENCODE

INPUT must be driven with a very low jitter,

square wave source. The amplitude should be

large, up to 3V

P-P

or 13dBm. When using a

sinusoidal signal generator a squaring circuit

can be used. Linear Technology also pro-

vides demo board DC1075A that divides a

high frequency sine wave by four, producing a

low jitter square wave for best results with the

LTC2261.

Using band pass filters on the clock and the

analog input will improve the noise perform-

ance by reducing the wideband noise power

of the signals. In the case of the DC1369 a

band pass filter used for the clock should be

used prior to the DC1075A. Datasheet FFT

5

plots are taken with 10 pole LC filters made by

TTE (Los Angeles, CA) to suppress signal

generator harmonics, non-harmonically re-

lated spurs and broadband noise. Low phase

noise Agilent 8644B generators are used with

TTE band pass filters for both the Clock input

and the Analog input.

Apply the analog input signal of interest to the

SMA connectors on the DC1369 demonstra-

tion circuit board marked “J5 AIN+”. These

inputs are capacitive coupled to Balun trans-

formers ETC1-1-13.

An internally generated conversion clock out-

put is available on J1 which could be collected

via a logic analyzer, or other data collection

system if populated with a SAMTEC MEC8-

150 type connector or collected by the DC890

QuickEval-II Data Acquisition Board using

PScope software.

SOFTWARE

The DC890B is controlled by the PScope Sys-

tem Software provided or downloaded from

the Linear Technology website at

http://www.linear.com/software/. If a DC890B

was provided, follow the DC890 Quick Start

Guide and the instructions below.

To start the data collection software if

“PScope.exe”, is installed (by default) in

\Program Files\LTC\PScope\, double click the

PScope Icon or bring up the run window un-

der the start menu and browse to the PScope

directory and select PScope.

If the DC1369 demonstration circuit is prop-

erly connected to the DC890, PSCOPE

should automatically detect the DC1369, and

configure itself accordingly. If necessary the

procedure below explains how to manually

configure PSCOPE.

Under the “Configure” menu, go to “ADC

Configuration....” Check the “Config Manu-

ally” box and use the following configuration

options, see Figure 2:

Manual Configuration settings:

Bits: 14

Alignment: 14

FPGA Ld: DDR LVDS

Channs: 2

Bipolar: Checked

Positive-Edge Clk: Checked

Figure 2: ADC configuration

If everything is hooked up properly, powered

and a suitable convert clock is present, click-

ing the “Collect” button should result in time

and frequency plots displayed in the PScope

window. Additional information and help for

PScope is available in the DC890B Quick

Start Guide and in the online help available

within the PScope program itself.

6

SERIAL PROGRAMMING

PScope has the ability to program the DC1369

board serially through the DC890. There are

several options available in the LTC2261 family

that are only available through serially pro-

gramming. PScope allows all of these features

to be tested.

These options are available by first clicking on

the “Set Demo Bd Options” icon on the PScope

toolbar (Figure 3).

Figure 3: PScope Toolbar

This will bring up the menu shown in figure 4.

Figure 4: Demobd Configuration Options.

This menu allows any of the options available for

the LTC2261 family to be programmed serially.

The LTC2261 family has the following options:

Power Control

– Selects between normal op-

eration, nap, and sleep modes:

- Normal (Default) – Entire ADC is powered, and

active

- Nap – ADC core powers down while references

stay active.

- Shutdown – The entire ADC is powered down.

Clock Inversion

– Selects the polarity of the

CLKOUT signal:

- Normal (Default) – Normal CLKOUT polarity

- Inverted – CLKOUT polarity is inverted

Clock Delay

- Selects the phase delay of the

CLKOUT signal:

- None (Default) – No CLKOUT delay

- 45 deg – CLKOUT delayed by 45 degrees

- 90 deg – CLKOUT delayed by 90 degrees

- 135 deg – CLKOUT delayed by 135 degrees

Clock Duty Cycle

– Enable or disables Duty

Cycle Stabilizer

- Stabilizer off (Default) – Duty Cycle Stabilizer

Disabled

- Stabilizer on – Duty Cycle Stabilizer Enabled

Output Current

– Selects the LVDS output drive

current

- 1.75mA (Default) - LVDS output driver current

- 2.1mA - LVDS output driver current

- 2.5mA - LVDS output driver current

- 3.0mA - LVDS output driver current

- 3.5mA - LVDS output driver current

- 4.0mA - LVDS output driver current

- 4.5mA - LVDS output driver current

Internal Termination

– Enables LVDS internal

termination

7

- Off (Default) – Disables internal termination

- On – Enables internal termination

Outputs

– Enables Digital Outputs

- Enabled (Default) – Enables digital outputs

- Disabled – Disables digital outputs

Output Mode

– Selects Digital output mode

- Full Rate – Full rate CMOS output mode (This

mode is not supported by the DC1369A, please

use the DC1370)

- Double LVDS (Default) – double data rate

LVDS output mode

- Double CMOS – double data rate CMOS out-

put mode (This mode is not supported by the

DC1369A, please use the DC1370)

Test Pattern

– Selects Digital output test pat-

terns

- Off (Default) – ADC data presented at output

- All out =1 – All digital outputs are 1

- All out = 0 – All digital outputs are 0

- Checkerboard - OF, and D13-D0 Alternate be-

tween 101 0101 1010 0101 and 010 1010 0101

1010 on alternating samples.

- Alternating – Digital outputs alternate between

all 1’s and all 0’s on alternating samples.

Alternate Bit

– Alternate Bit Polarity (ABP)

Mode

- Off (Default) – Disables alternate bit polarity

- On – Enables alternate bit polarity (Before

enabling ABP, be sure the part is in offset binary

mode)

Randomizer

– Enables Data Output Random-

izer

- Off (Default) – Disables data output randomizer

- On – Enables data output randomizer

Two’s complement

– Enables two’s comple-

ment mode

- Off (Default) – Selects offset binary mode

- On – Selects two’s complement mode

Once the desired settings are selected hit OK

and PScope will automatically update the regis-

ter of the device on the DC1369 demo board.

8

VDD

-D8/D9

+D12/D13

SCK

R16

100

C9

8.2pF

C20

1uFC21

0.1uF

R7 10K 1%

SDI

PAR/SER

C26

0.1uF

R19

100

RN2 33

1

2

3

4

8

7

6

5

C15

0.1uF

C24

4.7uF

R1

301

1%

C2 0.01uF

VIN

R50 36nH

OX40

L2

BEAD

J8

2

4

6

8

10

12

14

1

3

5

7

9

11

13

5V

SCK/SCL

CS

GND

EEVCC

EEGND

NC

VUNREG

GND

MISO

MOSI/SDA

EESDA

EESCL

GND

SDI

R24

100K

OVDD

VDD

SD0

SDA

R26 4.99K 1%

+D4/D5

C34

0.1uF

OXA2

R40

1%

24.9

R49

OPT

TP2

V+

3.5V - 6V

L6

OPT

JP2

PAR

SER

PAR/SER

1

3

2

-D0/D0

VSS

R20

100

C36

0.1uF

U6 LT1763CDE

78

5

6

9

10 2

4

11 3

12

1

GNDSHDN

SENSE

BYP

NC

IN OUT

NC

IN OUT

NC

-D12/D13

C7

0.01uF

1 2

C10

8.2pF

C22

1uF

RN1 33

1

2

3

4

8

7

6

5

SD0

J9

ENC -

W

R17

100

R54 0

L1 56uH

R23

100

VCC_IN

R52

OPT

R10 0

R14

1K

-D6/D7

C56 0.1uF

W

-CLK

VCC_IN

C1

OPT

1 2

R5 OPT

ENABLE

-D2/D3

SDI

R39

1%

24.9

VDD

R35

1K

R44

86.6

1%

R57

0

R51

OPT

R55 OPT

U4 LT1763CDE-1.8

78

5

6

9

10 2

4

11 3

12

1

GNDSHDN

SENSE

BYP

NC

IN OUT

NC

IN OUT

NC

C31

0.1uF

C3

0.01uF

1 2

+D10/D11

U7 24LC32A-I/ST

1

2

3

4 5

6

7

8

A0

A1

A2

A3 SDA

SCL

WP

VCC

TP3

GND

C51

4.7pF

VOUT

SDA

CS

C38

0.01uF

R2

301

1%

VDD

C27 0.1uF

U2

LTC2261CUJ

32

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

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24

25

26

27

28

29

30

31

33

34

36

35

37

38

39

40

41

D10_11+

AIN+

AIN-

GND

REFH

REFL

PAR/SER

VDD

ENC +

ENC -

CS

SCK

SDI

SDO

D0_1-

D0_1+

D2_3-

D2_3+

D4_5-

D4_5+

D6_7-

D6_7+

OGND

OVDD

CLKOUT-

CLKOUT+

D8_9-

D8_9+

D10_11-

D12_13-

D12_13+

OF+

OF-

VCM

VREF

SENSE

VDD

GND

C14

1uF

R48 0

R6

10K

C23

1uF

VDD

SDA

U1 24LC025-I/ST

1

2

3

4 5

6

7

8

A0

A1

A2

A3 SDA

SCL

WP

VCC

C57

0

1 2

R9 0

VDD

PAR/SER

C19

0.1uF

JP4

SHD N

EN

DIS

1

3

2

C33

0.1uF

CS

J5

AIN+

J7

ENC +

TP4

R47 0

VOUT

-D10/D11

CS

VSS

R46 OPT

+D0/D1

SDA

R21

100

VDD

SCL

JP3

DUTY CYCLE STAB.

EN

DIS

1

3

2

C30

0.1uF

SCL

CS

VSS

C13

1uF

C17

1uF

C32

0.1uF

C55

22uF

ENABLE

VSS

SCL

D1

HSMS-2822

1 2

3

+CLK

SD0

TP5

GND

R56

OPT

R8 6.81K 1%

VCC_IN

R22

100

OVDD

SDA

FAST DAACS BOARD ID CIRCUITRY

VDD

C37

0.1uF

T1

MABA-007159-000000

C35

0.1uF

R18

100

R33

1K

VDD

+D8/D9

SDI

SCL

R4 OPT

TP1

EXT REF

P1 EDGE-CON-100

2

4

6

8

10

12

14

16

18

20

22

24

26

28

30

32

34

36

38

40

42

44

46

48

50

52

54

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58

60

62

64

66

68

70

72

74

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86

88

90

92

94

96

98

100

1

3

5

7

9

11

13

15

17

19

21

23

25

27

29

31

33

35

37

39

41

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53

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59

61

63

65

67

69

71

73

75

77

79

81

83

85

87

89

91

93

95

97

99

C18

0.1uF

R36

86.6

1%

VOUT

C39

0.01uF

R30

100

U3

FI N1108

32

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

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29

30

31

33

34

36

35

37

38

39

40

41

42

43

44

45

46

48

47

OUT6-

VE1

VE2

EN12

IN1-

IN1+

IN2+

IN2-

IN3-

IN3+

IN4+

IN4-

VC1

EN

IN5-

IN5+

IN6+

IN6-

IN7-

IN7+

IN8+

IN8-

EN34

VE3

VBB

VC2

VC3

EN56

OUT8-

OUT8+

OUT7+

OUT7-

OUT6+

OUT5+

VE4

OUT5-

VE5

OUT4-

OUR4+

OUT3+

OUT3-

OUT2-

OUT2+

OUT1+

OUT1-

EN78

VC5

VC4

VOUT

R29 4.99K 1%

VOUT

+D2/D3

C52

100pF

C59

0.01uF

1 2

SCL

SDA

R45 86.6 1%

C28

0.1uF

SCK

-D4/D5

C53

100pF

L4

BEAD

VCC_IN

SCL

R25 4.99K

1%

U5

PCF8574TS/3

10

11

12

144

16

17

19

20

15

2

1

5

6

7

9

8

3

13

18

P0

P1

P2

P3SDA

P4

P5

P6

P7

GND

SCL

INT

VDD

A0

A1

A2

NC

C54

22uF

C6

0.01uF

1 2

L3 BEAD

C12

0.1uF

T2

MABAES0060

C58

0

1 2

T3

WBC4-1WL

L5

BEAD

C29

0.1uF

OXA0

R34

1K

R53 OPT

C61

0.01uF

1 2

VOUT

+D6/D7

C60

0.01uF

1 2