QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 1369 12/14 BIT, 25 TO 150 MSPS ADC LTC2261-14, LTC2261-12, LTC2260-14, LTC2260-12, LTC2259-14, LTC2259-12, LTC2258-14, LTC2258-12, LTC2257-14, LTC2257-12, LTC2256-14, LTC2256-12, LTC2262-14, LTC2262-12 DESCRIPTION Demonstration circuit 1369 supports a family of 14/12 BIT 125 MSPS ADCs. Each assembly features one of the following devices: LTC2261-14, LTC2261-12, LTC2260-14, LTC2260-12, LTC2259-14, LTC2259-12, LTC2258-14, LTC2258-12, LTC2257-14, LTC2257-12, LTC2256-14, LTC2256-12, LTC2262-14, or LTC226212 high speed, high dynamic range ADCs. Demonstration circuit 1369 supports the LTC2261 family DDR LVDS output mode. This family of ADCs is also supported by demonstration circuit 1370A, which is compatible with CMOS and DDR CMOS output modes. Table 1. Several versions of the 1369A demo board supporting the LTC2261 12/14-BIT series of A/D converters are listed in Table 1. Depending on the required resolution and sample rate, the DC1369 is supplied with the appropriate ADC. The circuitry on the analog inputs is optimized for analog input frequencies from 5 MHz to 170MHz. Refer to the datasheet for proper input networks for different input frequencies. Design files for this circuit board are available. Call the LTC factory. LTC is a trademark of Linear Technology Corporation DC1369Variants DC1369 VARIANTS ADC PART NUMBER RESOLUTION* MAXIMUM SAMPLE RATE INPUT FREQUENCY 1369A-A LTC2261-14 14-BIT 125 Msps 5MHz-170MHz 1369A-B LTC2260-14 14-BIT 105 Msps 5MHz-170MHz 1369A-C LTC2259-14 14-BIT 80 Msps 5MHz-170MHz 1369A-D LTC2258-14 14-BIT 65 Msps 5MHz-170MHz 1369A-E LTC2257-14 14-BIT 40 Msps 5MHz-170MHz 1369A-F LTC2256-14 14-BIT 25 Msps 5MHz-170MHz 1369A-G LTC2261-12 12-BIT 125 Msps 5MHz-170MHz 1369A-H LTC2260-12 12-BIT 105 Msps 5MHz-170MHz 1369A-I LTC2259-12 12-BIT 80 Msps 5MHz-170MHz 1369A-J LTC2258-12 12-BIT 65 Msps 5MHz-170MHz 1369A-K LTC2257-12 12-BIT 40 Msps 5MHz-170MHz 1369A-L LTC2256-12 12-BIT 25 Msps 5MHz-170MHz 1369A-M LTC2262-14 14-BIT 150Msps 5MHz-170MHz 1369A-N LTC2262-12 12-BIT 150Msps 5MHz-170MHz 1 QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 1369 12/14 BIT, 25 TO 150 MSPS ADC Table 2. Performance Summary (TA = 25C) PARAMETER CONDITION VALUE Supply Voltage - DC1369A Depending on sampling rate and the A/D converter provided, this supply must provide up to 250mA. Optimized for 3.6V Analog input range Depending on SENSE Pin Voltage 1 VPP to 2VPP Minimum Logic High 1.3V Maximum Logic Low 0.6V Nominal Logic levels (100 load, 3.5mA Mode) 350mV/1.25V common mode Minimum Logic levels (100 load, 3.5mA Mode) 247mV/1.25V common mode Logic Input Voltages Logic Output Voltages (differential) [3.5V 6.0V min/max] Sampling Frequency (Convert Clock Frequency) See Table 1 Convert Clock Level Single ended Encode Mode (ENC- tied to GND) 0-3.6V Convert Clock Level Differential Encode Mode (ENC- not tied to GND) 0.2V-3.6V Resolution See Table 1 Input frequency range See Table 1 SFDR See Applicable Data Sheet SNR See Applicable Data Sheet QUICK START PROCEDURE Demonstration circuit 1369 is easy to set up to evaluate the performance of the LTC2261 A/D converters. Refer to Figure 1 for proper meas- urement equipment setup and follow the procedure below: SETUP If a DC890 FastDAACS Data Acquisition and Start Guide to install the required software and Collection System was supplied with the DC1369 for connecting the DC890 to the DC1369 and to demonstration circuit, follow the DC890 Quick a PC running Windows98, 2000 or XP. 2 3.5-6V Jumpers are shown in default positions. + Analog Input Parallel Data Output To DC890 Parallel/Serial Programming mode Duty Cycle Stabilizer SHDN Single Ended Encode Clock Figure 1. DC1369 Setup (zoom for detail) DC1369 DEMONSTRATION CIRCUIT BOARD JUMPERS JP2: PAR/SER : Selects Parallel or Serial The DC1369 demonstration circuit programming mode. (Default - Serial) board should have the following jumper JP3: Duty Cycle Stabilizer: Enables/ Disable settings as default positions: (as per Duty Cycle Stabilizer. (Default - Enable) Figure 1) JP4: SHDN: Enables and disables the LTC2261. (Default - Enable) 3 APPLYING POWER AND SIGNALS TO THE DC996 DEMONSTRATION CIRCUIT If a DC890 is used to acquire data from the DC1369, the DC890 must FIRST be connected to a powered USB port or provided an external 6-9V BEFORE applying +3.6V to +6.0V across the pins marked "V+" and "GND" on the DC1369. DC1369 requires 3.6V for proper operation. Regulators on the board produce the voltages required for the ADC. The DC1369 demonstration circuit requires up to 250mA depending on the sampling rate and the A/D converter supplied. The DC890 data collection board is powered by the USB cable and does not require an external power supply unless it must be connected to the PC through an un-powered hub, in which case it must be supplied an external 6-9V on turrets G7(+) and G1(-) or the adjacent 2.1mm power jack. ANALOG INPUT NETWORK For optimal distortion and noise performance the RC network on the analog inputs may need to be optimized for different analog input frequencies. For input frequencies above 170 MHz, refer to the LTC2261 datasheet for a proper input network. Other input networks may be more appropriate for input frequencies less that 5MHz. In almost all cases, filters will be required on both analog input and encode clock to provide data sheet SNR. In the case of the DC1369 a band pass filter used for the clock should be used prior to the DC1075A. unable to deliver the combination of low noise figure and High IP3 point required. A high order filter can be used prior to this final amplifier, and a relatively lower Q filter used between the amplifier and the demo circuit. ENCODE CLOCK NOTE: Apply an encode clock to the SMA connector on the DC1369 demonstration circuit board marked "J7". As a default the DC1369 is populated to have a single ended input. The filters should be located close to the inputs to avoid reflections from impedance discontinuities at the driven end of a long transmission line. Most filters do not present 50 outside the passband. In some cases, 3dB to 10dB pads may be required to obtain low distortion. For the best noise performance, the ENCODE INPUT must be driven with a very low jitter, square wave source. The amplitude should be large, up to 3VP-P or 13dBm. When using a sinusoidal signal generator a squaring circuit can be used. Linear Technology also provides demo board DC1075A that divides a high frequency sine wave by four, producing a low jitter square wave for best results with the LTC2261. If your generator cannot deliver full scale signals without distortion, you may benefit from a medium power amplifier based on a Gallium Arsenide Gain block prior to the final filter. This is particularly true at higher frequencies where IC based operational amplifiers may be Using band pass filters on the clock and the analog input will improve the noise performance by reducing the wideband noise power of the signals. In the case of the DC1369 a band pass filter used for the clock should be used prior to the DC1075A. Datasheet FFT 4 plots are taken with 10 pole LC filters made by TTE (Los Angeles, CA) to suppress signal generator harmonics, non-harmonically related spurs and broadband noise. Low phase noise Agilent 8644B generators are used with TTE band pass filters for both the Clock input and the Analog input. Apply the analog input signal of interest to the SMA connectors on the DC1369 demonstration circuit board marked "J5 AIN+". These inputs are capacitive coupled to Balun transformers ETC1-1-13. An internally generated conversion clock output is available on J1 which could be collected via a logic analyzer, or other data collection system if populated with a SAMTEC MEC8150 type connector or collected by the DC890 QuickEval-II Data Acquisition Board using PScope software. Under the "Configure" menu, go to "ADC Configuration...." Check the "Config Manually" box and use the following configuration options, see Figure 2: Manual Configuration settings: Bits: 14 Alignment: 14 FPGA Ld: DDR LVDS Channs: 2 Bipolar: Checked Positive-Edge Clk: Checked Figure 2: ADC configuration SOFTWARE The DC890B is controlled by the PScope System Software provided or downloaded from the Linear Technology website at http://www.linear.com/software/. If a DC890B was provided, follow the DC890 Quick Start Guide and the instructions below. To start the data collection software if "PScope.exe", is installed (by default) in \Program Files\LTC\PScope\, double click the PScope Icon or bring up the run window under the start menu and browse to the PScope directory and select PScope. If the DC1369 demonstration circuit is properly connected to the DC890, PSCOPE should automatically detect the DC1369, and configure itself accordingly. If necessary the procedure below explains how to manually configure PSCOPE. If everything is hooked up properly, powered and a suitable convert clock is present, clicking the "Collect" button should result in time and frequency plots displayed in the PScope window. Additional information and help for PScope is available in the DC890B Quick Start Guide and in the online help available within the PScope program itself. 5 SERIAL PROGRAMMING PScope has the ability to program the DC1369 board serially through the DC890. There are several options available in the LTC2261 family that are only available through serially programming. PScope allows all of these features to be tested. These options are available by first clicking on the "Set Demo Bd Options" icon on the PScope toolbar (Figure 3). - Nap - ADC core powers down while references stay active. - Shutdown - The entire ADC is powered down. Clock Inversion - Selects the polarity of the CLKOUT signal: - Normal (Default) - Normal CLKOUT polarity - Inverted - CLKOUT polarity is inverted Figure 3: PScope Toolbar Clock Delay - Selects the phase delay of the CLKOUT signal: - None (Default) - No CLKOUT delay - 45 deg - CLKOUT delayed by 45 degrees This will bring up the menu shown in figure 4. - 90 deg - CLKOUT delayed by 90 degrees - 135 deg - CLKOUT delayed by 135 degrees Clock Duty Cycle - Enable or disables Duty Cycle Stabilizer - Stabilizer off (Default) - Duty Cycle Stabilizer Disabled - Stabilizer on - Duty Cycle Stabilizer Enabled Output Current - Selects the LVDS output drive current - 1.75mA (Default) - LVDS output driver current - 2.1mA - LVDS output driver current Figure 4: Demobd Configuration Options. This menu allows any of the options available for the LTC2261 family to be programmed serially. The LTC2261 family has the following options: Power Control - Selects between normal operation, nap, and sleep modes: - Normal (Default) - Entire ADC is powered, and active - 2.5mA - LVDS output driver current - 3.0mA - LVDS output driver current - 3.5mA - LVDS output driver current - 4.0mA - LVDS output driver current - 4.5mA - LVDS output driver current Internal Termination - Enables LVDS internal termination 6 - Off (Default) - Disables internal termination - On - Enables internal termination Randomizer - Enables Data Output Randomizer - Off (Default) - Disables data output randomizer Outputs - Enables Digital Outputs - Enabled (Default) - Enables digital outputs - Disabled - Disables digital outputs - On - Enables data output randomizer Two's complement - Enables two's complement mode - Off (Default) - Selects offset binary mode - On - Selects two's complement mode Output Mode - Selects Digital output mode - Full Rate - Full rate CMOS output mode (This mode is not supported by the DC1369A, please use the DC1370) Once the desired settings are selected hit OK and PScope will automatically update the register of the device on the DC1369 demo board. - Double LVDS (Default) - double data rate LVDS output mode - Double CMOS - double data rate CMOS output mode (This mode is not supported by the DC1369A, please use the DC1370) Test Pattern - Selects Digital output test patterns - Off (Default) - ADC data presented at output - All out =1 - All digital outputs are 1 - All out = 0 - All digital outputs are 0 - Checkerboard - OF, and D13-D0 Alternate between 101 0101 1010 0101 and 010 1010 0101 1010 on alternating samples. - Alternating - Digital outputs alternate between all 1's and all 0's on alternating samples. Alternate Bit - Alternate Bit Polarity (ABP) Mode - Off (Default) - Disables alternate bit polarity - On - Enables alternate bit polarity (Before enabling ABP, be sure the part is in offset binary mode) 7 8 GND GND 2 C31 J9 TP5 TP3 4.7uF C24 OPT C1 1uF C22 1uF C14 VIN 0.01uF C60 OPT L6 0.1uF 0.1uF 0.1uF J7 C30 C29 C28 0.1uF C32 0.01uF C7 8 12 1 4 9 10 11 8 12 1 4 9 10 11 R57 0 OUT OUT GND BYP SENSE SHDN NC NC NC NC IN IN GND BYP SENSE OUT OUT U6 LT1763CDE SHDN NC NC NC NC IN IN U4 LT1763CDE-1.8 R53 OPT 2 7 6 5 2 3 7 6 5 2 3 C2 0.01uF R56 OPT 0.1uF 0.1uF 0.1uF 0.01uF C39 0.01uF C38 0.01uF C59 T3 WBC4-1WL VDD C36 C35 T2 MABAES0060 C34 D1 HSMS-2822 1 R50 36nH R47 0 0.1uF 0.1uF 0.1uF C33 C19 0.1uF 8.2pF C10 R44 86.6 1% 56uH C18 8.2pF C9 R36 86.6 1% L1 0.1uF TP2 3.5V - 6V V+ ENC- ENC+ GND TP4 C6 0.01uF 1 C26 VOUT VDD J5 T1 MABA-007159-000000 2 1 R2 301 1% 22uF C55 BEAD 0 W C58 0 W C57 R8 6.81K 1% 2 2 VDD VDD PAR/SER REFL REFL REFH VDD 1uF C13 REFH GND AIN- AIN+ 1uF C23 1uF C17 R55 OPT OPT R52 1 R51 OPT 1 OPT R49 C37 0.1uF VDD OVDD VOUT R7 10K 1% L3 BEAD BEAD L4 L2 R54 0 R4 OPT 0.01uF C3 R5 OPT R48 0 C61 0.01uF 10 9 8 7 6 5 4 3 2 1 EXT REF VDD 1uF C20 4.7pF C51 PAR/SER 0.1uF C21 0.1uF C15 R10 0 R40 24.9 1% R46 OPT R1 301 1% 22uF C54 BEAD L5 0.1uF C12 R39 24.9 1% R9 0 GND 41 AIN+ 2 1 3 TP1 11 R14 1K R16 100 37 38 3 2 1 6 7 9 2 4 3 8 1 R33 1K A0 A1 A2 SCL SDA NC NC INT D8_9- D8_9+ R18 100 3 2 1 CS R34 1K VDD 10 11 12 14 16 17 19 20 18 13 RN2 1 2 3 4 33 8 7 6 5 DUTY CYCLE STAB. DIS EN U2 OVDD R30 100 R19 100 LTC2261CUJ 21 22 23 24 25 26 27 28 29 30 JP3 D4_5- D4_5+ D6_7- D6_7+ OGND OVDD CLKOUT- CLKOUT+ P0 P1 P2 P3 P4 P5 P6 P7 NC NC VOUT PAR/SER U5 PCF8574TS/3 PAR/SER OX40 SCL SDA SER PAR JP2 34 VDD 100 R17 32 R45 86.6 1% 2 1 2 1 2 1 2 1 40 VDD ENC+ 39 SENSE 36 13 CS ENC12 VREF SCK CS 35 VCM 14 SCK 15 SDI OF+ SDI 16 SD0 OFSDO 31 D10_11- 33 D12_13+ D0_117 D12_1318 D10_11+ D2_319 D2_3+ 20 VDD CS SCK SDI SD0 DIS EN 3 2 1 10K R6 SHDN JP4 SDI R21 100 VOUT VDD R35 1K R20 100 R22 100 OXA2 R23 100 ENABLE VOUT VBB IN1IN1+ IN2+ IN2IN3IN3+ IN4+ IN4IN5IN5+ IN6+ IN6IN7IN7+ IN8+ IN8- EN12 EN34 EN56 EN78 EN OUT1OUT1+ OUT2+ OUT2OUT3OUT3+ OUR4+ OUT4OUT5OUT5+ OUT6+ OUT6OUT7OUT7+ OUT8+ OUT8- C56 0.1uF VUNREG 5V J8 NC EEVCC EESDA EESCL EEGND 14 10 9 11 12 6 4 7 5 1 2 U7 24LC32A-I/ST 8 A0 VCC 7 A1 WP 6 A2 SCL 5 A3 SDA CS SCK/SCL MOSI/SDA MISO 1 2 3 4 24 4 5 6 7 8 9 10 11 14 15 16 17 18 19 20 21 3 22 27 46 13 U3 FIN1108 GND GND GND 3 8 13 D0_1+ 5 VDD GND 15 12 25 26 47 48 VC1 VC2 VC3 VC4 VC5 VE1 VE2 VE3 VE4 VE5 1 2 23 36 37 RN1 1 2 3 4 33 8 7 6 5 +D12/D13 -D12/D13 +D10/D11 -D10/D11 +D8/D9 -D8/D9 +CLK -CLK +D6/D7 -D6/D7 +D4/D5 -D4/D5 +D2/D3 -D2/D3 +D0/D1 -D0/D0 VCC_IN VSS SCL SDA 45 44 43 42 41 40 39 38 35 34 33 32 31 30 29 28 OXA0 100pF 100pF VCC_IN SDA SCL VSS C53 C52 CS SCK SDI SD0 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 VCC_IN 1 2 3 4 U1 24LC025-I/ST 8 A0 VCC 7 A1 WP 6 A2 SCL 5 A3 SDA C27 0.1uF R24 100K R25 4.99K 1% VSS VOUT SDA SCL VCC_IN ENABLE R26 4.99K 1% SCL SDA SDA VSS SCL R29 4.99K 1% FAST DAACS BOARD ID CIRCUITRY 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 P1 EDGE-CON-100