ML4800CSX_NL - Fairchild Semiconductor

www.fairchildsemi.com

REV. 1.0.5 9/25/01

Features

• Internally synchronized leading-edge PFC and trailing-

edge PWM in one IC

• TriFault Detect™ for UL1950 compliance and enhanced

safety

• Slew rate enhanced transconductance error ampliﬁer for

ultra-fast PFC response

• Low power: 200µA startup current, 5.5mA operating

current

• Low total harmonic distortion, high PF

• Reduced ripple current in storage capacitor between PFC

and PWM sections

• Average current, continuous boost leading edge PFC

• PWM conﬁgurable for current-mode or voltage mode

operation

• Current fed gain modulator for improved noise immunity

• Overvoltage and brown-out protection, UVLO, and soft

start

General Description

The ML4800 is a controller for power factor corrected,

switched mode power supplies. Power Factor Correction

(PFC) allows the use of smaller, lower cost bulk capacitors,

reduces power line loading and stress on the switching FETs,

and results in a power supply that fully complies with

IEC1000-3-2 speciﬁcation. Intended as a BiCMOS version

of the industry-standard ML4824, the ML4800 includes

circuits for the implementation of leading edge, average

current, “boost” type power factor correction and a trailing

edge, pulse width modulator (PWM). It also includes a

TriFault Detect™ function to help ensure that no unsafe

conditions will result from single component failure in the

PFC. Gate-drivers with 1A capabilities minimize the need

for external driver circuits. Low power requirements improve

efﬁciency and reduce component costs.

An over-voltage comparator shuts down the PFC section in

the event of a sudden decrease in load. The PFC section also

includes peak current limiting and input voltage brownout

protection. The PWM section can be operated in current or

voltage mode, at up to 250kHz, and includes an accurate

50% duty cycle limit to prevent transformer saturation.

Block Diagram

VEAO IEAO

VFB

IAC

VRMS

ISENSE

RAMP 1 OSCILLATOR

OVP

PFC ILIMIT

UVLO

VREF

PULSE WIDTH MODULATOR

POWER FACTOR CORRECTOR

TRI-FAULT

2.5V

7.5V

REFERENCE 14

VCC

VEA

+IEA

-PFC OUT 12

2.75V

0.5V

-1V

RAMP 2

PWM OUT 11

VDC

DC ILIMIT

VCC

DUTY CYCLE

LIMIT

1.0V

2.45V

VFB

VREF

VIN OK

GAIN

MODULATOR

VCC

1.6kΩ

1.25V

25µA

DC ILIMIT

17V

ML4800

Power Factor Correction and PWM Controller

Combo

ML4800 PRODUCT SPECIFICATION

REV. 1.0.5 9/25/01

Pin Conﬁguration

Pin Description

Pin Name Function

1 IEAO Slew rate enhanced PFC transconductance error amplifier output

PFC AC line reference input to Gain Modulator

SENSE

Current sense input to the PFC Gain Modulator

RMS

PFC Gain Modulator RMS line voltage compensation input

5 SS Connection point for the PWM soft start capacitor

PWM voltage feedback input

7 RAMP 1 Oscillator timing node; timing set by R

8 RAMP 2 When in current mode, this pin functions as the current sense input; when in voltage mode,

it is the PWM modulation ramp input.

9 DC I

LIMIT

PWM cycle-by-cycle current limit comparator input

10 GND Ground

11 PWM OUT PWM driver output

12 PFC OUT PFC driver output

13 V

Positive supply

14 V

REF

Buffered output for the internal 7.5V reference

15 V

PFC transconductance voltage error amplifier input

16 VEAO PFC transconductance voltage error amplifier output

IEAO

IAC

ISENSE

VRMS

VDC

RAMP 1

RAMP 2

VEAO

VFB

VREF

VCC

PFC OUT

PWM OUT

GND

DC ILIMIT

TOP VIEW

ML4800

16-Pin PDIP (P16)

16-Pin Narrow SOIC (S16N)

PRODUCT SPECIFICATION ML4800

REV. 1.0.5 9/25/01

Abolute Maximum Ratings

Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum rat-

ings are stress ratings only and functional device operation is not implied.

Operating Conditions

Parameter Min. Max. Units

18 V

SENSE

Voltage -5 0.7 V

Voltage on Any Other Pin GND - 0.3 V

CCZ

+ 0.3 V

REF

10 mA

Input Current 10 mA

Peak PFC OUT Current, Source or Sink 1 A

Peak PWM OUT Current, Source or Sink 1 A

PFC OUT, PWM OUT Energy Per Cycle 1.5 µJ

Junction Temperature 150 °C

Storage Temperature Range -65 150 °C

Lead Temperature (Soldering, 10 sec) 260 °C

Thermal Resistance (

)

Plastic DIP

Plastic SOIC 80

105 °C/W

°C/W

Temperature Range Min .Max. Units

ML4800CX 0 70 °C

ML4800IX -40 85 °C

Electrical Characteristics

Unless otherwise speciﬁed, V

= 15V, R

= 52.3k

Ω

, C

= 470pF, T

= Operating Temperature Range (Note 1)

Symbol Parameter Conditions Min. Typ. Max. Units

Voltage Error Ampliﬁer

Input Voltage Range 0 5 V

Transconductance V

NON INV

= V

INV

, VEAO = 3.75V 30 65 90 µ

Ω

Feedback Reference Voltage 2.43 2.5 2.57 V

Input Bias Current Note 2 -0.5 -1.0 µA

Output High Voltage 6.0 6.7 V

Output Low Voltage 0.1 0.4 V

Source Current V

= ±0.5V, V

OUT

= 6V -40 -140 µA

Sink Current V

= ±0.5V, V

OUT

= 1.5V 40 140 µA

Open Loop Gain 50 60 dB

Power Supply Rejection Ratio 11V < V

< 16.5V 50 60 dB

Current Error Ampliﬁer

Input Voltage Range -1.5 2 V

Transconductance V

NON INV

= V

INV

, VEAO = 3.75V 50 100 150 µ

Ω

Input Offset Voltage 0 4 15 mV

Ω

ML4800 PRODUCT SPECIFICATION

REV. 1.0.5 9/25/01

Input Bias Current -0.5 -1.0 µA

Output High Voltage 6.0 6.7 V

Output Low Voltage 0.65 1.0 V

Source Current V

= ±0.5V, V

OUT

= 6V -40 -104 µA

Sink Current V

= ±0.5V, V

OUT

= 1.5V 40 160 µA

Open Loop Gain 60 70 dB

Power Supply Rejection Ratio 11V < V

< 16.5V 60 75 dB

OVP Comparator

Threshold Voltage 2.65 2.75 2.85 V

Hysteresis 175 250 325 mV

Tri-Fault Detect

Fault Detect HIGH 2.65 2.75 2.85 V

Time to Fault Detect HIGH V

= V

FAULT DETECT LOW

= OPEN. 470pF from V

GND

24ms

Fault Detect LOW 0.4 0.5 0.6 V

PFC I

LIMIT

Comparator

Threshold Voltage -0.9 -1.0 -1.1 V

(PFC I

LIMIT

- Gain

Modulator Output) 120 220 mV

Delay to Output 150 300 ns

DC I

LIMIT

Comparator

Threshold Voltage 0.95 1.0 1.05 V

Input Bias Current ±0.3 ±1 µA

Delay to Output 150 300 ns

OK Comparator

Threshold Voltage 2.35 2.45 2.55 V

Hysteresis 0.8 1.0 1.2 V

GAIN Modulator

Gain (Note 3) I

= 100µA, V

RMS

= V

= 0V 0.60 0.80 1.05

= 50µA, V

RMS

= 1.2V, V

= 0V 1.8 2.0 2.40

= 50µA, V

RMS

= 1.8V, V

= 0V 0.85 1.0 1.25

= 100µA, V

RMS

= 3.3V, V

= 0V 0.20 0.30 0.40

Bandwidth I

= 100µA 10 MHz

Output Voltage I

= 350µA, V

RMS

= 1V, V

= 0V 0.60 0.75 0.9 V

Oscillator

Initial Accuracy T

= 25°C 71 76 81 kHz

Voltage Stability 11V < V

< 16.5V 1 %

Temperature Stability 2 %

Total Variation Line, Temp 68 84 kHz

Ramp Valley to Peak Voltage 2.5 V

Electrical Characteristics

(Continued)

Unless otherwise speciﬁed, V

= 15V, R

= 52.3k

Ω

, C

= 470pF, T

= Operating Temperature Range (Note 1)

Symbol Parameter Conditions Min. Typ. Max. Units

PRODUCT SPECIFICATION ML4800

REV. 1.0.5 9/25/01

Notes

1. Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions.

2. Includes all bias currents to other circuits connected to the V

pin.

3. Gain = K x 5.3V; K = (I

GAINMOD

- I

OFFSET

) x [I

(VEAO - 0.625)]

-1

; VEAO

MAX

=5V.

PFC Dead Time 350 650 ns

Discharge Current V

RAMP 2

= 0V, V

RAMP 1 = 2.5V 3.5 5.5 7.5 mA

Reference

Output Voltage TA = 25°C, I(VREF) = 1mA 7.4 7.5 7.6 V

Line Regulation 11V <VCC <16.5V 10 25 mV

Load Regulation 0mA <I(VREF) < 10mA;

TA = 0°C to 70°C 10 20 mV

0mA < I(VREF) < 5mA;

TA = –40°C to 85°C 10 20 mV

Temperature Stability 0.4 %

Total Variation Line, Load, Temp 7.35 7.65 V

Long Term Stability TJ = 125°C, 1000 Hours 5 25 mV

PFC Minimum Duty Cycle VIEAO > 4.0V 0 %

Maximum Duty Cycle VIEAO < 1.2V 90 95 %

Output Low Voltage IOUT = -20mA 0.4 0.8 V

IOUT = -100mA 0.7 2.0 V

IOUT = 10mA, VCC = 9V 0.4 0.8 V

Output High Voltage IOUT = 20mA VCC - 0.8V V

IOUT = 100mA VCC - 2V V

Rise/Fall Time CL = 1000pF 50 ns

PWM Duty Cycle Range 0-44 0-47 0-49 %

Output Low Voltage IOUT = -20mA 0.4 0.8 V

IOUT = -100mA 0.7 2.0 V

IOUT = 10mA, VCC = 9V 0.4 0.8 V

Output High Voltage IOUT = 20mA VCC - 0.8V V

IOUT = 100mA VCC - 2V V

Rise/Fall Time CL = 1000pF 50 ns

Supply Start-up Current VCC = 12V, CL = 0 200 350 µA

Operating Current 14V, CL = 0 5.5 7 mA

Undervoltage Lockout

Threshold 12.4 13 13.6 V

Undervoltage Lockout

Hysteresis 2.5 2.8 3.1 V

Electrical Characteristics (Continued)

Unless otherwise speciﬁed, VCC = 15V, RT = 52.3kΩ, CT = 470pF, TA = Operating Temperature Range (Note 1)

Symbol Parameter Conditions Min. Typ. Max. Units

ML4800 PRODUCT SPECIFICATION

6REV. 1.0.5 9/25/01

Typical Performance Characteristics

VARIABLE GAIN BLOCK CONSTANT (K)

VRMS(V)

0245

480

420

360

300

240

180

120

180

160

140

120

100

TRANSCONDUCTANCE (µ )

VFB (V)

053142

Ω

180

160

140

120

100

TRANSCONDUCTANCE (µ )

IEA INPUT VOLTAGE (mV)

–500 5000

Ω

Voltage Error Amplifier (VEA) Transconductance (gm)

Current Error Amplifier (IEA) Transconductance (gm) Gain Modulator Transfer Characteristic (K)

KIGAINMOD 84µA–()

IAC 5 0.625–()×

-----------------------------------------------------mV 1–

PRODUCT SPECIFICATION ML4800

REV. 1.0.5 9/25/01 7

Functional Description

The ML4800 consists of an average current controlled,

continuous boost Power Factor Corrector (PFC) front end

and a synchronized Pulse Width Modulator (PWM) back

end. The PWM can be used in either current or voltage

mode. In voltage mode, feedforward from the PFC output

buss can be used to improve the PWM’s line regulation.

In either mode, the PWM stage uses conventional trailing-

edge duty cycle modulation, while the PFC uses leading-

edge modulation. This patented leading/trailing edge modu-

lation technique results in a higher usable PFC error ampli-

ﬁer bandwidth, and can signiﬁcantly reduce the size of the

PFC DC buss capacitor.

The synchronization of the PWM with the PFC simpliﬁes the

PWM compensation due to the controlled ripple on the PFC

output capacitor (the PWM input capacitor). The PWM sec-

tion of the ML4800 runs at the same frequency as the PFC.

In addition to power factor correction, a number of protec-

tion features have been built into the ML4800. These include

soft-start, PFC ov ervoltage protection, peak current limiting,

brownout protection, duty cycle limiting, and under-voltage

lockout.

Power Factor Correction

Power factor correction makes a nonlinear load look like a

resistive load to the AC line. For a resistor, the current drawn

from the line is in phase with and proportional to the line

voltage, so the power factor is unity (one). A common class

of nonlinear load is the input of most power supplies, which

use a bridge rectiﬁer and capacitive input ﬁlter fed from the

line. The peak-charging effect, which occurs on the input ﬁl-

ter capacitor in these supplies, causes brief high-amplitude

pulses of current to ﬂow from the power line, rather than a

sinusoidal current inphase with the line voltage. Such sup-

plies present a power factor to the line of less than one (i.e.

they cause signiﬁcant current harmonics of the power line

frequency to appear at their input). If the input current drawn

by such a supply (or any other nonlinear load) can be made

to follow the input voltage in instantaneous amplitude, it will

appear resistive to the AC line and a unity power factor will

be achieved.

To hold the input current draw of a device drawing power

from the AC line in phase with and proportional to the input

voltage, a way must be found to prevent that device from

loading the line except in proportion to the instantaneous line

voltage. The PFC section of the ML4800 uses a boost-mode

DC-DC converter to accomplish this. The input to the con-

verter is the full wave rectiﬁed AC line voltage. No bulk ﬁl-

tering is applied following the bridge rectiﬁer, so the input

voltage to the boost converter ranges (at twice line fre-

quency) from zero volts to the peak value of the AC input

and back to zero. By forcing the boost converter to meet two

simultaneous conditions, it is possible to ensure that the cur-

rent drawn from the power line is proportional to the input

line voltage. One of these conditions is that the output volt-

age of the boost converter must be set higher than the peak

value of the line voltage. A commonly used value is

385VDC, to allow for a high line of 270VACrms. The other

condition is that the current drawn from the line at any given

instant must be proportional to the line voltage. Establishing

a suitable voltage control loop for the converter, which in

turn drives a current error ampliﬁer and switching output

driver satisﬁes the ﬁrst of these requirements. The second

requirement is met by using the rectiﬁed AC line voltage to

modulate the output of the voltage control loop. Such

modulation causes the current error ampliﬁer to command a

power stage current that varies directly with the input

voltage. In order to prevent ripple, which will necessarily

appear at the output of the boost circuit (typically about

10VAC on a 385V DC level), from introducing distortion

back through the voltage error ampliﬁer, the bandwidth of

the voltage loop is deliberately kept low. A ﬁnal reﬁnement

is to adjust the overall gain of the PFC such to be propor-

tional to 1/VIN2, which linearizes the transfer function of the

system as the AC input voltage varies.

Since the boost converter topology in the ML4800 PFC is of

the current-averaging type, no slope compensation is

required.

PFC Section

Gain Modulator

Figure 1 shows a block diagram of the PFC section of the

ML4800. The gain modulator is the heart of the PFC, as it is

this circuit block which controls the response of the current

loop to line voltage waveform and frequency, rms line volt-

age, and PFC output voltage. There are three inputs to the

gain modulator. These are:

1. A current representing the instantaneous input voltage

(amplitude and waveshape) to the PFC. The rectified

AC input sine wave is converted to a proportional

current via a resistor and is then fed into the gain

modulator at IAC. Sampling current in this way

minimizes ground noise, as is required in high power

switching power conversion environments. The gain

modulator responds linearly to this current.

2. A voltage proportional to the long-term RMS AC line

voltage, derived from the rectified line voltage after

scaling and filtering. This signal is presented to the gain

modulator at VRMS. The gain modulator s output is

inversely proportional to VRMS2 (except at unusually

low values of VRMS where special gain contouring takes

over, to limit power dissipation of the circuit

components under heavy brownout conditions). The

relationship between VRMS and gain is called K, and is

illustrated in the Typical Performance Characteristics.

3. The output of the voltage error amplifier, VEAO. The

gain modulator responds linearly to variations in this

voltage.

ML4800 PRODUCT SPECIFICATION

8REV. 1.0.5 9/25/01

The output of the gain modulator is a current signal, in the

form of a full wave rectiﬁed sinusoid at twice the line fre-

quency. This current is applied to the virtual-ground (nega-

tive) input of the current error ampliﬁer. In this way the gain

modulator forms the reference for the current error loop, and

ultimately controls the instantaneous current draw of the

PFC from the power line. The general form for the output of

the gain modulator is:

More exactly, the output current of the gain modulator is

given by:

where K is in units of V-1.

Note that the output current of the gain modulator is limited

to 500µA.

Current Error Amplier

The current error ampliﬁer’s output controls the PFC duty

cycle to keep the average current through the boost inductor

a linear function of the line voltage. At the inverting input to

the current error ampliﬁer, the output current of the gain

modulator is summed with a current which results from a

negative voltage being impressed upon the ISENSE pin. The

negative voltage on ISENSE represents the sum of all currents

ﬂowing in the PFC circuit, and is typically derived from a

current sense resistor in series with the negative terminal of

the input bridge rectiﬁer. In higher power applications, two

current transformers are sometimes used, one to monitor the

ID of the boost MOSFET(s) and one to monitor the IF of the

boost diode. As stated above, the inverting input of the cur-

rent error ampliﬁer is a virtual ground. Given this fact, and

the arrangement of the duty cycle modulator polarities inter-

nal to the PFC, an increase in positive current from the gain

modulator will cause the output stage to increase its duty

cycle until the voltage on ISENSE is adequately negative to

cancel this increased current. Similarly, if the gain modula-

tor’s output decreases, the output duty cycle will decrease, to

achieve a less negative voltage on the ISENSE pin.

Cycle-By-Cycle Current Limiter

The ISENSE pin, as well as being a part of the current feed-

back loop, is a direct input to the cycle-by-cycle current

limiter for the PFC section. Should the input voltage at this

pin ever be more negative than -1V, the output of the PFC

will be disabled until the protection ﬂip-ﬂop is reset by the

clock pulse at the start of the next PFC power cycle.

TriFault DetectTM

To improve power supply reliability, reduce system compo-

nent count, and simplify compliance to UL 1950 safety

standards, the ML4800 includes TriFault Detect. This feature

monitors VFB (Pin 15) for certain PFC fault conditions.

In the case of a feedback path failure, the output of the PFC

could go out of safe operating limits. With such a failure,

VFB will go outside of its normal operating area. Should

VFB go too low, too high, or open, TriFault Detect senses the

error and terminates the PFC output drive.

TriFault detect is an entirely internal circuit. It requires no

external components to serve its protective function.

Overvoltage Protection

The OVP comparator serves to protect the power circuit

from being subjected to excessive voltages if the load should

suddenly change. A resistor divider from the high voltage

DC output of the PFC is fed to VFB. When the voltage on

VFB exceeds 2.75V, the PFC output driver is shut down.

The PWM section will continue to operate. The OVP

comparator has 250mV of hysteresis, and the PFC will not

restart until the voltage at VFB drops below 2.50V. The VFB

should be set at a level where the active and passiv e external

power components and the ML4800 are within their safe

operating voltages, but not so low as to interfere with the

boost voltage regulation loop.

IGAINMOD IAC VEAO×

VRMS2

−−−−−−−−−−−−−−−−−−−− 1V×=(1)

IGAINMOD K VEAO 0.625V–()×IAC

×=

Figure 1. PFC Section Block Diagram

VEAO IEAO

VFB

IAC

VRMS

ISENSE

RAMP 1 OSCILLATOR

OVP

PFC ILIMIT

TRI-FAULT

2.5V

–

VEA

–

IEA

–+

–PFC OUT 12

2.75V

–1V

–

0.5V

1.6kΩ

GAIN

MODULATOR

PRODUCT SPECIFICATION ML4800

REV. 1.0.5 9/25/01 9

Error Amplier Compensation

The PWM loading of the PFC can be modeled as a negative

resistor; an increase in input voltage to the PWM causes a

decrease in the input current. This response dictates the

proper compensation of the two transconductance error

ampliﬁers. Figure 2 shows the types of compensation

networks most commonly used for the voltage and current

error ampliﬁers, along with their respective return points.

The current loop compensation is returned to VREF to

produce a soft-start characteristic on the PFC: as the

reference voltage comes up from zero volts, it creates a

differentiated voltage on IEAO which prevents the PFC

from immediately demanding a full duty cycle on its boost

converter.

There are two major concerns when compensating the

voltage loop error ampliﬁer; stability and transient response.

Optimizing interaction between transient response and

stability requires that the error ampliﬁer’s open-loop cross-

over frequency should be 1/2 that of the line frequency, or

23Hz for a 47Hz line (lowest anticipated international power

frequency). The gain vs. input voltage of the ML4800’s

voltage error ampliﬁer has a specially shaped non-linearity

such that under steady-state operating conditions the

transconductance of the error ampliﬁer is at a local

minimum. Rapid perturbations in line or load conditions

will cause the input to the voltage error ampliﬁer (VFB) to

deviate from its 2.5V (nominal) value. If this happens, the

transconductance of the voltage error ampliﬁer will increase

signiﬁcantly, as shown in the Typical Performance Charac-

teristics. This raises the gain-bandwidth product of the

voltage loop, resulting in a much more rapid voltage loop

response to such perturbations than would occur with a

conventional linear gain characteristic.

The current ampliﬁer compensation is similar to that of the

voltage error ampliﬁer with the exception of the choice of

crossover frequency. The crossover frequency of the current

ampliﬁer should be at least 10 times that of the voltage

ampliﬁer, to prevent interaction with the voltage loop.

It should also be limited to less than 1/6th that of the

switching frequency, e.g. 16.7kHz for a 100kHz switching

frequency.

There is a modest degree of gain contouring applied to the

transfer characteristic of the current error ampliﬁer, to

increase its speed of response to current-loop perturbations.

However, the boost inductor will usually be the dominant

factor in overall current loop response. Therefore, this

contouring is signiﬁcantly less marked than that of the

voltage error ampliﬁer. This is illustrated in the Typical

Performance Characteristics.

For more information on compensating the current and

voltage control loops, see Application Notes 33 and 34.

Application Note 16 also contains valuable information for

the design of this class of PFC.

Figure 2. Compensation Network Connections for the

Voltage and Current Error Amplifiers Figure 3. External Component Connections to VCC

VEAO IEAO

VFB

IAC

VRMS

ISENSE

2.5V

–

VEA

–

IEA

–

VREF

PFC

OUTPUT

GAIN

MODULATOR

ML4800

VCC

GND

VBIAS

0.22µF

CERAMIC 15V

ZENER

RBIAS

ML4800 PRODUCT SPECIFICATION

10 REV. 1.0.5 9/25/01

Oscillator (RAMP 1)

The oscillator frequency is determined by the values of RT

and CT, which determine the ramp and off-time of the

oscillator output clock:

The dead time of the oscillator is derived from the following

equation:

at VREF = 7.5V:

The dead time of the oscillator may be determined using:

The dead time is so small (tRAMP >> tDEADTIME) that the

operating frequency can typically be approximated by:

EXAMPLE:

For the application circuit shown in the data sheet, with the

oscillator running at:

Solving for RT x CT yields 1.96 x 10-4. Selecting standard

components values, CT = 390pF, and RT = 51.1kΩ.

The dead time of the oscillator adds to the Maximum PWM

Duty Cycle (it is an input to the Duty Cycle Limiter). With

zero oscillator dead time, the Maximum PWM Duty Cycle is

typically 45%. In many applications, care should be taken

that CT not be made so large as to extend the Maximum Duty

Cycle beyond 50%. This can be accomplished by using a

stable 390pF capacitor for CT.

PWM SECTION

Pulse Width Modulator

The PWM section of the ML4800 is straightforward, but

there are several points which should be noted. Foremost

among these is its inherent synchronization to the PFC

section of the device, from which it also derives its basic

timing. The PWM is capable of current-mode or voltage

mode operation. In current-mode applications, the PWM

ramp (RAMP 2) is usually derived directly from a current

sensing resistor or current transformer in the primary of the

output stage, and is thereby representative of the current

ﬂowing in the converter’s output stage. DC ILIMIT, which

provides cycle-by-cycle current limiting, is typically con-

nected to RAMP 2 in such applications. For voltage-mode

operation or certain specialized applications, RAMP 2 can

be connected to a separate RC timing network to generate a

voltage ramp against which VDC will be compared. Under

these conditions, the use of voltage feedforward from the

PFC buss can assist in line regulation accuracy and response.

As in current mode operation, the DC ILIMIT input is used

for output stage overcurrent protection.

No voltage error ampliﬁer is included in the PWM stage of

the ML4800, as this function is generally performed on the

output side of the PWM’s isolation boundary. To facilitate

the design of optocoupler feedback circuitry, an offset has

been built into the PWM’s RAMP 2 input which allows VDC

to command a zero percent duty cycle for input voltages

below 1.25V.

PWM Current Limit

The DC ILIMIT pin is a direct input to the cycle-by-cycle

current limiter for the PWM section. Should the input

voltage at this pin ever exceed 1V, the output of the PWM

will be disabled until the output ﬂip-ﬂop is reset by the clock

pulse at the start of the next PWM power cycle.

VIN OK Comparator

The VIN OK comparator monitors the DC output of the PFC

and inhibits the PWM if this voltage on VFB is less than its

nominal 2.45V. Once this voltage reaches 2.45V, which

corresponds to the PFC output capacitor being charged to its

rated boost voltage, the soft-start begins.

PWM Control (RAMP 2)

When the PWM section is used in current mode, RAMP 2

is generally used as the sampling point for a voltage

representing the current in the primary of the PWM’s output

transformer, derived either by a current sensing resistor or a

current transformer. In voltage mode, it is the input for a

ramp voltage generated by a second set of timing compo-

nents (RRAMP2, CRAMP2), that will have a minimum value of

zero volts and should have a peak value of approximately 5V.

In voltage mode operation, feedforward from the PFC output

buss is an excellent way to derive the timing ramp for the

PWM stage.

Soft Start

Start-up of the PWM is controlled by the selection of the

external capacitor at SS. A current source of 25µA supplies

the charging current for the capacitor, and start-up of the

PWM begins at 1.25V. Start-up delay can be programmed by

the following equation:

fOSC 1

tRAMP tDEADTIME

----------------------------------------------------=(2)

tRAMP CTRT

×InVREF 1.25–

VREF 3.75–

------------------------------

×=(3)

tRAMP CTRT

×0.51×=

tDEADTIME 2.5V

5.5mA

-----------------CT

×450 CT

×== (4)

fOSC 1

tRAMP

----------------=(5)

fOSC 100kHz 1

tRAMP

----------------==

CSS tDELAY 25µA

1.25V

---------------

×=(6)

PRODUCT SPECIFICATION ML4800

REV. 1.0.5 9/25/01 11

where CSS is the required soft start capacitance, and tDELAY

is the desired start-up delay.

It is important that the time constant of the PWM soft-start

allow the PFC time to generate sufﬁcient output power for

the PWM section. The PWM start-up delay should be at least

5ms.

Solving for the minimum value of CSS:

Caution should be exercised when using this minimum soft

start capacitance value because premature charging of the SS

capacitor and activation of the PWM section can result if

VFB is in the hysteresis band of the VIN OK comparator at

start-up. The magnitude of VFB at start-up is related both to

line voltage and nominal PFC output voltage. Typically, a

1.0µF soft start capacitor will allow time for VFB and PFC

out to reach their nominal values prior to activation of the

PWM section at line voltages between 90Vrms and

265Vrms.

Generating VCC

The ML4800 is a voltage-fed part. It requires an external

15V, ±10% (or better) shunt voltage regulator, or some other

VCC regulator, to regulate the voltage supplied to the part at

15V nominal. This allows low power dissipation while at the

same time delivering 13V nominal gate drive at the PWM

OUT and PFC OUT outputs. If using a Zener diode for this

function, it is important to limit the current through the

Zener to avoid overheating or destroying it. This can be

easily done with a single resistor in series with the Vcc pin,

returned to a bias supply of typically 18V to 20V. The

resistor’s value must be chosen to meet the operating current

requirement of the ML4800 itself (8.5mA, max.) plus the

current required by the two gate driver outputs.

EXAMPLE:

With a VBIAS of 20V, a VCC of 15V and the ML4800 driving

a total gate charge of 90nC at 100kHz (e.g., 1 IRF840

MOSFET and 2 IRF820 MOSFETs), the gate driver current

required is:

Choose RBIAS = 240Ω.

The ML4800 should be locally bypassed with a 1.0µF

ceramic capacitor. In most applications, an electrolytic

capacitor of between 47µF and 220µF is also required across

the part, both for ﬁltering and as part of the start-up bootstrap

circuitry.

Css 5ms 25µA

1.25V

---------------

×100nF== (6a)

IGATEDRIVE 100kHz 90nC×9mA== (7)

RBIAS VBIAS VCC

–

ICC IGIZ

---------------------------------=(8)

RBIAS 20V 15V–

6mA 9mA 5mA++

-------------------------------------------------- 250 Ω==

Figure 4. Typical Trailing Edge Control Scheme

RAMP

VEAO

TIME

VSW1

TIME

REF EA

–

OSC

DFF

CLK

RAMP

CLK

SW2

SW1

I2 I3

VIN

ML4800 PRODUCT SPECIFICATION

12 REV. 1.0.5 9/25/01

Leading/Trailing Modulation

Conventional Pulse Width Modulation (PWM) techniques

employ trailing edge modulation in which the switch will

turn on right after the trailing edge of the system clock. The

error ampliﬁer output voltage is then compared with the

modulating ramp. When the modulating ramp reaches the

level of the error ampliﬁer output voltage, the switch will be

turned OFF. When the switch is ON, the inductor current will

ramp up. The effective duty cycle of the trailing edge modu-

lation is determined during the ON time of the switch. Figure

4 shows a typical trailing edge control scheme.

In the case of leading edge modulation, the switch is turned

OFF right at the leading edge of the system clock. When the

modulating ramp reaches the level of the error ampliﬁer out-

put voltage, the switch will be turned ON. The effective

duty-cycle of the leading edge modulation is determined dur-

ing the OFF time of the switch. Figure 5 shows a leading

edge control scheme.

One of the advantages of this control technique is that it

requires only one system clock. Switch 1 (SW1) turns off

and switch 2 (SW2) turns on at the same instant to minimize

the momentary “no-load” period, thus lowering ripple volt-

age generated by the switching action. With such synchro-

nized switching, the ripple voltage of the ﬁrst stage is

reduced. Calculation and evaluation have shown that the

120Hz component of the PFC’s output ripple voltage can be

reduced by as much as 30% using this method.

Typical Applications

Figure 6 is the application circuit for a complete 100W

power factor corrected power supply, designed using the

methods and general topology detailed in Application Note

33.

Figure 5. Typical Leading Edge Control Scheme

REF EA

–

OSC

DFF

CLK

RAMP

CLK

SW2

SW1

I2 I3

VIN

VEAO

CMP

RAMP

VEAO

TIME

VSW1

TIME

PRODUCT SPECIFICATION ML4800

REV. 1.0.5 9/25/01 13

Figure 6. 100W Power Factor Corrected Power Supply, Designed Using Micro Linear Application Note 33

ML4800

IEAO

IAC

ISENSE

VRMS

VDC

RAMP1

RAMP 2

VDC

VFB

VREF

VCC

PFC OUT

PWM OUT

GND

DC ILMIT

R12 68.1k C6 1.5nF

C7 150pF

0.22µF

C26

47µF

0.47µF

ISENSE

C11

220pF

C18

470pF

R16 10kΩ

R37 1kΩ

PRI GND

NOTE: D7, D8, D10; 1N966B

D3, D5, D6, D12; UF4005

D4; 1N4733A

D2; 1N4744A

D11; MBR2545CT

L1; PREMIER MAGNETICS TSD-1047

L2; PREMIER MAGNETICS VTP-05007

L3; PREMIER MAGNETICS TSD-904

T1; PREMIER MAGNETICS PMGD-03

T2; PREMIER MAGNETICS TSD-735

UNUSED DESIGNATORS; C14, C16, C17, C27, C29, C33, D3, D9, R42, R43, R36, R35

VDC

R38

42.2kΩ

R28

240Ω

REF

VFB

C22

10µF

C10

10µF

C23

10nF

C19

1.0µF

D15

1N914

D13

1N914

D14

1N914

RT/CT

VBUSS

D12

Q2G T2C

Q3G

VCC

C31

330pF

PWM

ILIMIT

5.1V

D10

TL431A

D11B

D11A

C28

220pF

R10

249kΩ

R20

22Ω

Q1G

FES16JT

15V

357kΩ

100kΩ

13.2kΩ

AC INPUT

85 TO 260V

0.47µF

3.15A BR1

4A, 600V

KBL06

1.2Ω

R25

10kΩ

R40

470Ω

R32

8.66kΩ

12V

RETURN

12V RET

R33

2.26kΩ

R29

1.2kΩ

R30

1.5kΩ

C30

1000µF

C32

0.47µF

C21

1500µF

R34

240Ω

C12

10µF

35V

100µF

4.7nF C25

0.1µF

16V

600V

R39

33Ω

R13

383kΩ

R19

33Ω

R14

383kΩ

600V

R18

33Ω

R21

2.2Ω

R17

3ΩR22

2.2Ω

12V, 100W

12V

C24

0.47µF

1.2Ω

R24

10kΩ

C20

0.47µF

R23

220Ω

T1A

R15

4.99kΩ

R26

10kΩ

R11

412kΩ

R31

10kΩ

R44

10kΩ

IRF840A

1N4744A

L2 L3

R27

82kΩ

T1B

C13

0.22µF

C15

1.0µFC8

150µFC9

15nF

IRF820A

MBR2545CT

2N3904

1N4733A

MOC8112

IRF820A

ML4800 PRODUCT SPECIFICATION

9/25/01 0.0m 001

Stock#DS30004800

 2001 Fairchild Semiconductor Corporation

DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY

PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY

LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER

DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES

OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR

CORPORATION. As used herein:

1. Life support devices or systems are devices or systems

which, (a) are intended for surgical implant into the body,

or (b) support or sustain life, or (c) whose failure to perform

when properly used in accordance with instructions for use

provided in the labeling, can be reasonably expected to

result in significant injury of the user.

2. A critical component is any component of a life support

device or system whose failure to perform can be

reasonably expected to cause the failure of the life support

device or system, or to affect its safety or effectiveness.

www.fairchildsemi.com

Ordering Information

Part Number Temperature Range Package

ML4800CP 0°C to 70°C 16-Pin PDIP (P16)

ML4800CS 0°C to 70°C 16-Pin Narrow SOIC (S16N)

ML4800IP -40°C to 85°C 16-Pin PDIP (P16)

ML4800IS -40°C to 85°C 16-Pin Narrow SOIC (S16N)