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Document Number: 70748
S09-0870-Rev. C, 18-May-09
Vishay Siliconix
Si4982DY
Notes:
a. For design aid only; not subject to production testing.
b. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
SPECIFICATIONS TJ = 25 °C, unless otherwise noted
Parameter Symbol Test Conditions Min. Typ.aMax. Unit
Static
Gate Threshold Voltage VGS(th) VDS = VGS, ID = 250 µA 2V
Gate-Body Leakage IGSS VDS = 0 V, VGS = ± 20 V ± 100 nA
Zero Gate Voltage Drain Current IDSS
VDS = 100 V, VGS = 0 V 1µA
VDS = 100 V, VGS = 0 V, TJ = 55 °C 20
On-State Drain CurrentbID(on) V
DS = 5 V, VGS = 10 V 15 A
Drain-Source On-State ResistancebRDS(on)
VGS = 10 V, ID = 2.6 A 0.130 0.150 Ω
VGS = 6 V, ID = 2.4 A 0.140 0.180
Forward Transconductancebgfs VDS = 15 V, ID = 2.6 A 11 S
Diode Forward VoltagebVSD IS = 1.7 A, VGS = 0 V 1.2 V
Dynamica
Gate Charge Qg
VDS = 50 V, VGS = 10 V, ID = 2.6 A
15 30
nCGate-Source Charge Qgs 2.7
Gate-Drain Charge Qgd 4.0
Gate Resistance Rg 14.4Ω
Tur n - O n D e l ay Time td(on)
VDD = 50 V, RL = 50 Ω
ID ≅ 1 A, VGEN = 10 V, Rg = 6 Ω
10 20
ns
Rise Time tr10 20
Turn-Off Delay Time td(off) 30 60
Fall Time tf10 20
Source-Drain Reverse Recovery Time trr IF = 1.7 A, dI/dt = 100 A/µs 60 90