LM49321, LM49321RLEVAL
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SNAS457C –SEPTEMBER 2008–REVISED MAY 2013
LM49321 Audio Sub-System with Stereo DAC, Mono Class
AB Loudspeaker Amplifier, OCL/SE Stereo Headphone Output and RF Suppression
Check for Samples: LM49321,LM49321RLEVAL
1FEATURES DESCRIPTION
The LM49321 is an integrated audio sub-system
2• 8-Bit Stereo DAC with up to 192kHz Sampling designed for mono voice, stereo music cell phones
Rate connecting to base band processors with mono
• Multiple Distinct Output Modes differential analog voice paths. Operating on a 3.3V
• Mono Class AB Speaker Amplifier supply, it combines a mono speaker amplifier
delivering 520mW into an 8Ωload, a stereo
• Stereo OCL/SE Headphone Amplifier headphone amplifier delivering 36mW per channel
• Mono Earpiece Amplifier into a 32Ωload, and a mono earpiece amplifier
• Differential Mono Analog Input delivering 55mW into a 32Ωload. The headphone
amplifier can be configured for output capacitor-less
• Single-Ended Analog Inputs (OCL) or single-ended (SE) mode. It integrates the
• Independent Loudspeaker, Headphone and audio amplifiers, volume control, mixer, and power
Mono Earpiece Volume controls management control all into a single package. In
• I2C/SPI (Selectable) Compatible Interface addition, the LM49321 routes and mixes the single-
ended stereo and differential mono inputs into
• Ultra Low Shutdown Current multiple distinct output modes. The LM49321 features
• Click and Pop Suppression Circuit an I2S serial interface for full range audio and an I2C
or SPI compatible interface for control. The full range
APPLICATIONS music path features an SNR of 85dB with up to
192kHz playback.
• Cell Phones
• PDAs Boomer audio power amplifiers are designed
specifically to provide high quality output power with a
• Laptop Computers minimal amount of external components.
• Portable Devices
KEY SPECIFICATIONS
• POUT LS, 8Ω, 3.3V, 1% THD+N: 520 mW (Typ)
• POUT HP, 32Ω, 3.3V, 1% THD+N: 36 mW (Typ)
• POUT Mono Earpiece, 32Ω, 1% THD+N: 55 mW
(Typ)
• Shutdown Current: 0.6 µA (Typ)
• SNR (DAC + Amplifier): 85 dB (Typ)
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2008–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Speaker
AMP
+Volume
HP
AMP
DIFF-
I2S_CLK
I2S_SDI
I2S_WS
Volume
Mono
Earpiece
(Receiver)
-
PLL
I2C/SPI
Interface
-56 dB to +5 dB
Volume
Volume
Volume
Mixer
and
Output
Mode
Select
DAC
Gain
-3 dB to 6 dB
-12 dB to +9 dB
I2C_VDD
I2S_SDATA
SCL/SCK
ADDR/ENB
MODE
STEREO
DAC
MCLK
PLL_IN
PLL_OUT
DIFF+
LIN
RIN
LS+
LS-
-56 dB to +5 dB
-56 dB to +5 dB
-56 dB to +5 dB
LHP
RHP
CHP
EP+
EP-
PLL_VDD
Analog Power and Bias Digital Power
Ci
Ci
0.22 µF
0.22 µF
Ci
0.22 µF
Ci
0.22 µF
+
CS
1 PF
AVDD
+CS
0.1 PF
AGND DGND
+
CS
1 PF
DVDD
+CS
0.1 PF
+
CS
1 PF
I/O_VDD
+CS
0.1 PF
+CB
2.2 PF
BYPASS
Audio
Differential
Input
Audio
Single-Ended
Inputs
Volume
-6 dB to +15 dB
Volume
-6 dB to +15 dB
PLL_GND
LM49321, LM49321RLEVAL
SNAS457C –SEPTEMBER 2008–REVISED MAY 2013
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Block Diagram
Figure 1. Typical Audio Amplifier Subsystem Application Circuit with Output Capacitor-Less (OCL)
Headphone Configuration
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6
5
4
3
2
1
A B C D E F
+Volume
DIFF-
I2S_CLK
I2S_SDI
I2S_WS
Volume
-
PLL
I2C/SPI
Interface
-56 dB to +5 dB
Volume
Volume
Volume
Mixer
and
Output
Mode
Select
DAC
Gain
-3 dB to 6 dB
-12 dB to +9 dB
I2C_VDD
SCL/SCK
ADDR/ENB
MODE
STEREO
DAC
MCLK
PLL_IN
PLL_OUT
DIFF+
LIN
RIN
LS+
LS-
-56 dB to +5 dB
-56 dB to +5 dB
-56 dB to +5 dB
LHP
RHP
CHP
EP+
EP-
PLL_VDD
Analog Power and Bias Digital Power
Ci
Ci
0.22 µF
0.22 µF
Ci
0.22 µF
Ci
0.22 µF
+
CS
1 PF
AVDD
+CS
0.1 PF
AGND DGND
+
CS
1 PF
DVDD
+CS
0.1 PF
+
CS
1 PF
I/O_VDD
+CS
0.1 PF
+CB
2.2 PF
BYPASS
Audio
Differential
Input
Audio
Single-Ended
Inputs
Volume
-6 dB to +15 dB
Volume
-6 dB to +15 dB
Speaker
AMP
HP
AMP
Mono
Earpiece
(Receiver)
220 PF
+
220 PF
+
PLL_GND
I2S_SDATA
LM49321, LM49321RLEVAL
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SNAS457C –SEPTEMBER 2008–REVISED MAY 2013
Figure 2. Typical Audio Amplifier Subsystem Application Circuit with Cap-Coupled Single-Ended (SE)
Headphone Configuration
Connection Diagram
Top View (Bump Side Down)
Figure 3. 36 - Bump DSBGA Package
See Package Number YPG0036LVA
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PIN DESCRIPTIONS
Digital
Pin Pin Name I/O, Power Description
/Analog
A1 DGND D P DIGITAL GND
A2 MCLK D I MASTER CLOCK
A3 I2S_WS D I/O I2S WORD SELECT
A4 SDA/SDI D I/O I2C SDA OR SPI SDI
A5 DVDD D P DIGITAL SUPPLY VOLTAGE
A6 I/O_VDD D P I/O SUPPLY VOLTAGE
B1 PLL_VDD D P PLL SUPPLY VOLTAGE
B2 I2S_SDATA D I I2S SERIAL DATA INPUT
B3 I2S_CLK D I/O I2S CLOCK SIGNAL
B4 GPIO D O TEST PIN (MUST BE LEFT FLOATING)
B5 I2C_VDD D P I2C SUPPLY VOLTAGE
B6 SDL/SCK D I I2C_SCL OR SPI_SCK
C1 PLL_GND D P PHASE LOCK LOOP GROUND
C2 PLL_OUT D O PHASE LOCK LOOP FILTER OUTPUT
C3 PLL_IN D I PLL FILTER INPUT
C4 ADDR/ENB D I I2C ADDRESS OR SPI ENB DEPENDING ON MODE
C5 BYPASS A I HALF-SUPPLY BYPASS
C6 AVDD A P ANALOG SUPPLY VOLTAGE
D1 AGND A P ANALOG GROUND
D2 AGND A P ANALOG GROUND
D3 NC NO CONNECT (MUST BE LEFT FLOATING)
D4 MODE D I SELECTS BETWEEN I2C OR SPI CONTROL
D5 RHP A O RIGHT HEADPHONE OUTPUT
D6 CHP A O HEADPHONE CENTER PIN OUTPUT (1/2 VDD or GND)
E1 DIFF- A I ANALOG NEGATIVE DIFFERENTIAL INPUT
E2 LIN A I ANALOG LEFT CHANNEL INPUT
E3 RIN A I ANALOG RIGHT CHANNEL INPUT
E4 NC NO CONNECT (MUST BE LEFT FLOATING)
E5 LHP A O LEFT HEADPHONE OUTPUT
E6 AGND A P ANALOG GROUND
F1 DIFF+ A I ANALOG POSITIVE DIFFERENTIAL INPUT
F2 EP- A O MONO EARPIECE- OUTPUT
F3 EP+ A O MONO EARPIECE+ OUTPUT
F4 LS- A O LOUDSPEAKER OUTPUT-
F5 AVDD A P ANALOG SUPPLY VOLTAGE
F6 LS+ A O LOUDSPEAKER OUTPUT+
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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SNAS457C –SEPTEMBER 2008–REVISED MAY 2013
Absolute Maximum Ratings(1)(2)(3)(4)
Analog Supply Voltage(1) 6.0V
Digital Supply Voltage(1) 6.0V
Storage Temperature -65°C to +150°C
Input Voltage -0.3V to VDD +0.3V
Power Dissipation(5) Internally Limited
ESD Ratings(6) 2000V
ESD Ratings(7) 200V
Junction Temperature (TJMAX) 150°C
Thermal Resistance θJA (RLA36) 100°C/W
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All
voltages are measured with respect to the ground pin, unless otherwise specified.
(2) The Electrical Characteristics tables list specified specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
(3) Soldering Information: See AN-1279 “Microfill Wafer Level Underfilled Chip Scale package" (Literature Number SNOA430)
(4) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
(5) Maximum allowable power dissipation is PDMAX = (TJMAX - TA) / θJA or the number given in Absolute Maximum Ratings, whichever is
lower.
(6) Human body model, applicable std. JESD22-A114C.
(7) Machine model, applicable std. JESD22-A115-A.
Operating Ratings(1)(2)
Temperature Range (TMIN ≤TA≤TMAX)−40°C ≤TA≤+85°C
2.7V ≤AVDD ≤5.5V
2.7V ≤DVDD ≤4.0V
Supply Voltage 1.7V ≤I2C_VDD ≤4.0V
1.7V ≤I/O_VDD ≤4.0V
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All
voltages are measured with respect to the ground pin, unless otherwise specified.
(2) The Electrical Characteristics tables list specified specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
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Audio Amplifier Electrical Characteristics AVDD = 3.0V, DVDD = 3.0V(1)(2)
The following specifications apply for the circuit shown in Figure 41 with all programmable gain set at 0dB, unless otherwise
specified. Limits apply for TA= 25°C. LM49321 Units
Parameter Test Conditions (Limits)
Typ(3) Limits(4)
VIN = 0, No Load 13 18 mA (max)
All Amps On + DAC, OCL(5)
Headphone Mode Only, OCL, DAC off 4.6 6.25 mA (max)
Headphone Mode Only, OCL, DAC Off
STEREO_OUTPUT_ONLY = 1, 4 5.5 mA
STEREO_INPUT_ONLY = 1
Headphone Mode only OCL, DAC On,
IDD Supply Current OSR = 64, DAC_INPUT_ONLY = 1 7.5 10 mA (max)
STEREO_OUTPUT_ONLY = 1
Mono Loudspeaker Mode Only 6.5 11.5 mA (max)
Mono Earpiece Speaker Mode Only
MONO_ONLY = 1 (register 01h) 3.7 5 mA (max)
MONO_ONLY = 0 3.3 mA
DAC Off, All Amps On (OCL)(5) 10 13.5 mA (max)
ISD Shutdown Current See(6) 0.6 1 μA (max)
Speaker; THD = 1%; f = 1kHz, 8ΩBTL 420 370 mW (min)
POOutput Power Headphone; THD = 1%; f = 1kHz, 32ΩSE 27 24 mW (min)
Earpiece; THD = 1%; f = 1kHz, 32ΩBTL 45 40 mW (min)
VFS DAC Full Scale DAC Output 2.4 VRMS
Speaker; PO= 200mW; f = 1kHz, 8ΩBTL 0.04 %
THD+N Total Harmonic Distortion+Noise Headphone; PO= 10mW; f = 1kHz, 32ΩSE 0.01 %
Earpiece; PO= 20mW; f = 1kHz, 32ΩBTL 0.04 %
Speaker 10 55 mV (max)
VOS Offset Voltage Earpiece 8 50 mV (max)
Headphone (OCL) 8 15 mV (max)
∈OOutput Noise A-weighted; 0dB gain Table 1
PSRR Power Supply Rejection Ratio f = 217Hz; VRIPPLE = 200mVP-P, CB= 2.2μFTable 2
XTALK Crosstalk Headphone; PO= 10mW, f = 1kHz; OCL –60 dB
CB= 2.2μF, CD_6 = 0 35 ms
TWU Wake-Up Time CB= 2.2μF, CD_6 = 1 85 ms
CMRR Common-Mode Rejection Ratio f = 217Hz, VRMS = 200mVPP 56 dB
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All
voltages are measured with respect to the ground pin, unless otherwise specified.
(2) The Electrical Characteristics tables list specified specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
(3) Typical values represent most likely parametric norms at TA= +25ºC, and at the Recommended Operation Conditions at the time of
product characterization and are not ensured.
(4) Datasheet min/max specification limits are ensured by test or statistical analysis.
(5) Enabling mono bit (MONO_ONLY in Output Control Register 01h) will save 400μA (typ) form specified current.
(6) Shutdown current is measured in a normal room environment.
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Audio Amplifier Electrical Characteristics AVDD = 5.0V, DVDD = 3.3V(1)(2)
The following specifications apply for the circuit shown in Figure 41 with all programmable gain set at 0dB, unless otherwise
specified. Limits apply for TA= 25°C. LM49321 Units
Parameter Test Conditions (Limits)
Typ(3) Limits(4)
VIN = 0, No Load 17.5 mA (max)
All Amps On + DAC, OCL(5)
Headphone Mode Only, OCL, DAC Off 5.8 mA (max)
Headphone Mode Only, OCL, DAC Off
STEREO_OUTPUT_ONLY = 1, 5.5 mA
STEREO_INPUT_ONLY = 1
IDD Supply Current Headphone Mode Only, OCL, DAC On,
OSR = 64, DAC_INPUT_ONLY = 1 9.5 mA
STEREO_OUTPUT_ONLY = 1
Mono Loudspeaker Mode Only(5) 11.6 mA
Mono Earpiece Mode Only(5) 5 mA
DAC Off, All Amps On (OCL)(5) 12.9 mA
ISD Shutdown Current See(6) 1.6 μA
Speaker; THD = 1%; f = 1kHz, 8ΩBTL 1.25 mW
POOutput Power Headphone; THD = 1%; f = 1kHz, 32ΩSE 80 mW
Earpiece; THD = 1%; f = 1kHz, 32ΩBTL 175 mW
VFS DAC Full Scale DAC Output 2.4 VRMS
Speaker; PO= 500mW; f = 1kHz, 8ΩBTL 0.03 %
THD+N Total Harmonic Distortion + Noise Headphone; PO= 30mW; f = 1kHz, 32ΩSE 0.01 %
Earpiece; PO= 40mW; f = 1kHz, 32ΩBTL 0.04 %
Speaker 10 mV
VOS Offset Voltage Earpiece 8 mV
HP (OCL) 8 mV
∈OOutput Noise A-weighted; 0dB gain; Table 1
PSRR Power Supply Rejection Ratio f = 217Hz; Vripple = 200mVP-P, CB= 2.2μFTable 3
XTALK Crosstalk Headphone; PO= 15mW, f = 1kHz; OCL –56 dB
CB= 2.2μF, CD_6 = 0 45 ms
TWU Wake-Up Time CB= 2.2μF, CD_6 = 1 130 ms
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All
voltages are measured with respect to the ground pin, unless otherwise specified.
(2) The Electrical Characteristics tables list specified specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
(3) Typical values represent most likely parametric norms at TA= +25ºC, and at the Recommended Operation Conditions at the time of
product characterization and are not ensured.
(4) Datasheet min/max specification limits are ensured by test or statistical analysis.
(5) Enabling mono bit (MONO_ONLY in Output Control Register 01h) will save 400μA (typ) form specified current.
(6) Shutdown current is measured in a normal room environment.
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Volume Control Electrical Characteristics(1)(2)
The following specifications apply for 3.0V ≤AVDD ≤5.0V and 2.7V ≤DVDD ≤4.0V, unless otherwise specified. Limits apply
for TA= 25°C. LM49321 Units
Parameter Test Conditions (Limits)
Typ(3) Limits(4)
–7 dB (min)
Minimum gain setting –6 –5 dB (max)
Stereo Analog Inputs Pre-Amp Gain
Setting Range 15.5 dB (max)
Maximum gain setting 15 14.5 dB (min)
PGR –13 dB (min)
Minimum gain setting –12 –11 dB (max)
Differential Mono Analog Input Pre-
Amp Gain Setting Range 9.5 dB (max)
Maximum gain setting 9 8.5 dB (min)
–59 dB (min)
Minimum gain setting –56
Output Volume Control for –53 dB (max)
VCR Loudspeaker, Headphone Output, or 4.5 dB (min)
Earpiece Output Maximum gain setting +5 5.5 dB (max)
Stereo Channel to Channel Gain
ΔACH-CH 0.3 dB
Mismatch VIN = 1VRMS, Gain = 0dB
AMUTE Mute Attenuation –90 dB
with load, Headphone 18 kΩ(min)
DIFF+, DIFF-, LIN and RIN Input
RINPUT 23
Impedance 28 kΩ(max)
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All
voltages are measured with respect to the ground pin, unless otherwise specified.
(2) The Electrical Characteristics tables list specified specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
(3) Typical values represent most likely parametric norms at TA= +25ºC, and at the Recommended Operation Conditions at the time of
product characterization and are not ensured.
(4) Datasheet min/max specification limits are ensured by test or statistical analysis.
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Digital Section Electrical Characteristics(1)(2)
The following specifications apply for 3.0V ≤AVDD ≤5.0V and 2.7V ≤DVDD ≤4.0V, unless otherwise specified. Limits apply
for TA= 25°C. LM49321 Units
Parameter Test Conditions (Limits)
Typ(3) Limits(4)
Mode 0, DVDD = 3.0V
DISD Digital Shutdown Current No MCLK 0.01 μA
fMCLK = 12MHz, DVDD = 3.0V
DIDD Digital Power Supply Current 5.3 6.5 mA (max)
ALL MODES EXCEPT 0
PLLIDD PLL Quiescent Current fMCLK = 12MHz, DVDD = 3.0V 4.8 6 mA (max)
Audio DAC (Typical numbers are with 6.144MHz audio clock and 48kHz sampling frequency
RDAC Audio DAC Ripple 20Hz - 20kHz through headphone output +/-0.1 dB
PBDAC Audio DAC Passband width -3dB point 22.6 kHz
SBADAC Audio DAC Stop band Attenuation Above 24kHz 76 dB
DRDAC Audio DAC Dynamic Range DC - 20kHz, –60dBFS; AES17 Standard Table 4 dB
Audio DAC-AMP Signal to Noise A-Weighted, Signal = VOat 0dBFS, f = 1kHz
SNR Table 4 dB
Ratio Noise = digital zero, A-weighted
SNRDAC Internal DAC SNR A-weighted(5) 95 dB
PLL
10
fIN Input Frequency on MCLK pin 12 MHz
26
SPI/I2C (1.7V ≤I2C_VDD ≤2.2V)
fSPI Maximum SPI Frequency 1000 kHz (max)
tSPISETD SPI Data Setup Time 250 ns (max)
tSPISETENB SPI ENB Setup Time 250 ns (max)
tSPIHOLDD SPI Data Hold Time 250 ns (max)
tSPIHOLDENB SPI ENB Hold Time 250 ns (max)
tSPICL SPI Clock Low Time 500 ns (max)
tSPICH SPI Clock High Time 500 ns (max)
fCLKI2C I2C_CLK Frequency 400 kHz (max)
tI2CHOLD I2C_DATA Hold Time 250 ns (max)
tI2CSET I2C_DATA Setup Time 250 ns (max)
0.7 x
VIH I2C/SPI Input High Voltage I2C_VDD V (min)
I2C_VDD
0.25 x
VIL I2C/SPI Input Low Voltage 0 V (max)
I2C_VDD
SPI/I2C (2.2V ≤I2C_VDD ≤4.0V)
fSPI Maximum SPI Frequency 4000 kHz (max)
tSPISETD SPI Data Setup Time 100 ns (max)
tSPISETENB SPI ENB Setup Time 100 ns (max)
tSPIHOLDD SPI Data Hold Time 100 ns (max)
tSPIHOLENB SPI ENB Hold Time 100 ns (max)
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All
voltages are measured with respect to the ground pin, unless otherwise specified.
(2) The Electrical Characteristics tables list specified specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
(3) Typical values represent most likely parametric norms at TA= +25ºC, and at the Recommended Operation Conditions at the time of
product characterization and are not ensured.
(4) Datasheet min/max specification limits are ensured by test or statistical analysis.
(5) Internal DAC only with DAC modes 00 and 01.
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Digital Section Electrical Characteristics(1)(2) (continued)
The following specifications apply for 3.0V ≤AVDD ≤5.0V and 2.7V ≤DVDD ≤4.0V, unless otherwise specified. Limits apply
for TA= 25°C. LM49321 Units
Parameter Test Conditions (Limits)
Typ(3) Limits(4)
tSPICL SPI Clock Low Time 125 ns (max)
tSPICH SPI Clock High Time 125 ns (max)
fCLKI2C I2C_CLK Frequency 400 kHz (max)
tI2CHOLD I2C_DATA Hold Time 100 ns (max)
tI2CSET I2C_DATA Setup Time 100 ns (max)
0.7 x
VIH I2C/SPI Input High Voltage I2C_VDD V (min)
I2C_VDD
0.3 x
VIL I2C/SPI Input Low Voltage 0 V (max)
I2C_VDD
I2S(1.7V ≤I/O_VDD ≤2.7V)
I2S_RESOLUTION = 1 1536 6144 kHz (max)
I2S_CLK Frequency I2S_RESOLUTION = 0 3072 12288 kHz (max)
fCLKI2S40 % (min)
I2S_WS Duty Cycle 50 60 % (max)
0.75
VIH Digital Input High Voltage V (min)
x I/O_VDD
0.25 x
VIL Digital Input Low Voltage V (max)
I/O_VDD
I2S(2.7V ≤I/O_VDD ≤4.0V)
1536 6144 kHz (max)
I2S_CLK Frequency I2S_RESOLUTION = 0 3072 12288 kHz (max)
fCLKI2S40 %
I2S_WS Duty Cycle I2S_RESOLUTION = 1 50 60 %
0.7 x
VIH Digital Input High Voltage V (min)
I/O_VDD
0.3 x
VIL Digital Input Low Voltage V (max)
I/O_VDD
Table 1. Output Noise AVDD = 5.0V and AVDD = 3.0V. All gains set to 0dB. Units in μV, A-weighted, Inputs
terminated to ground.
MODE EP LS HP OCL Units
1 22 22 8 μV
2 22 22 8 μV
3 22 22 8 μV
4 68 88 46 μV
5 38 48 24 μV
6 29 34 18 μV
7 38 48 24 μV
Table 2. VPSRR AVDD = 3.0V, fRIPPLE = 217Hz; VRIPPLE = 200mVP-P; CB= 2.2μF; All gains set to 0dB.
MODE EP(Typ) LS (Typ) LS (Limit) HP (Typ) HP (Limit) Units
1 69 76 72 dB
2 69 76 67 72 68 dB
3 69 76 72 dB
4 63 62 55 dB
5 69 68 61 dB
6 69 70 64 dB
7 69 68 61 dB
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ENB
SCK
SDI
TSPISETENB
TSPIHOLDD
TSPISETD
TSPICH
TSPIT
TSPICL
TSPIHOLDENB
Register Address Data
ENB
SCK
SDI 7 0 7 0
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Table 3. PSRR AVDD = 5.0V, fRIPPLE = 217Hz; VRIPPLE = 200mVP-P; CB= 2.2μF; All gains set to 0dB.
MODE EP (Typ) LS (Typ) HP (Typ) Units
1 68 72 71 dB
2 68 72 71 dB
3 68 72 71 dB
4 68 66 69 dB
5 68 69 70 dB
6 69 72 71 dB
7 68 69 70 dB
Table 4. Dynamic Range and SNR. 3.0V ≤AVDD ≤5.0V. All programmable gain set to 0dB. Units in dB.
DR (Typ) SNR (Typ) Units
LS 95 85 dB
HP 95 85 dB
EP 97 85 dB
System Control
The LM49321 is controlled via either a two wire I2C compatible interface or three wire SPI interface, selectable
with the MODE pin. This interface is used to configure the operating mode, interfaces, data converters, mixers
and amplifiers. The LM49321 is controlled by writing 8 bit data into a series of write-only registers, the device is
always a slave for both type of interfaces.
THREE WIRE, SPI INTERFACE (MODE = 1)
Three Wire Mode Write Bus Transaction
Three Wire Mode Write Bus Timing
Figure 4. Three Wire Mode Write Bus
When the part is configured as an SPI device and the enable (ENB) line is lowered the serial data on SDI is
clocked in on the rising edge of the SCK line. The protocol used is 16bit, MSB first. The upper 8 bits (15:8) are
used to select an address within the device, the lower 8 bits (7:0) contain the updated data for this register.
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Start
Condition Stop
Condition
Data ACK
SDA
SCL
TI2CSET
TI2CHOLD
TI2CSET TI2CSET
ACK ACK Data ACK
PS 6 - 0 7 - 1 0 7 - 1 0
W
Host
Address
Start
Condition
SDA
SCL
Register
Address Stop
Condition
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TWO WIRE I2C COMPATIBLE INTERFACE (MODE = 0)
Two Wire Mode Write Bus Transaction
Two Wire Mode Write Bus Timing
Figure 5. Two Wire Mode Write Bus
When the part is configured as an I2C device then the LM49321 will respond to one of two addresses, according
to the ADDR input. If ADDR is low then the address portion of the I2C transaction should be set to write to
0010000. When ADDR is high then the address input should be set to write to 1110000.
Table 5. Chip Address
A7 A6 A5 A4 A3 A2 A1 A0
Chip Address 0 EC EC 1 0 0 0 0
ADR = 0 0 0 0 1 0 0 0 0
ADR = 1 0 1 1 1 0 0 0 0
EC — Externally configured by ADR pin
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Table 6. Control Registers
Address Register D7 D6 D5 D4 D3 D2 D1 D0
00h MODE_CONTROL 0 CD_6 0 OCL MODE_CONTROL
OUTPUT_ STEREO_ MONO_ONLY DAC_INPUT_ STEREO_INPUT_ HP_R_ HP_L_ LS_ MONO_
01h CONTROL OUT_ONL ONLY ONLY OUTPUT OUTPUT OUTPUT OUTPUT
Y
02h EP_VOL 0 0 0 EP_VOL
03h LS_VOL 0 0 0 LS_VOL
04h RESERVED 0 0 0 0 0 0 0 0
05h HP_L_VOL 0 0 0 HP_L_VOL
06h HP_R_VOL 0 0 0 HP_R_VOL
07h ANALOG_INPUT 0 0 ANA_R_GAIN ANA_L_GAIN
_GAIN
08h ANALOG_DAC 0 DAC_R_GAIN DAC_L_GAIN MONO_L_GAIN
_GAIN PLL_ AUDIO FAST_
09h CLOCKS R_DIV PLL_INPUT
ENABLE _CLK_SEL CLOCK
0Ah PLL_M 0 PLL_M
0Bh PLL_N
0Ch PLL_N_MOD VCO_FAS DITHER_LEVEL DITHER_LEVEL PLL_N_MOD
T
0Dh PLL_P 0 0 0 0 PLL_P
0Eh DAC_SET UP 0 CUST_COMP DITHER_ALW_ON DITHER_OFF MUTE_R MUTE_L DAC_MODE
I2S_ I2S_MASTER_
0Fh INTERFACE 0 0 0 0 I2C_FAST I2S_MODE RESOLUTION SLAVE
10h COMPENSATION _C OEFF0_LSB
11h COMPENSATION _C OEFF0_MSB
12h COMPENSATION _C OEFF1_LSB
13h COMPENSATION _C OEFF1_MSB
14h COMPENSATION _C OEFF2_LSB
15h COMPENSATION _C OEFF2_MSB
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Mixer Control Registers
This register is used to control the different mixer modes that the LM49321 supports.
Table 7. Mode Control Register (00h)(1)
Bits Field Description
3:0 MODE This sets the different mixer output modes.
_CONTROL MODE_CONTROL Mode Mono Earpiece Loudspeaker Headphone Headphone
Left Right
0000 0 SD SD SD SD
1001 1 M M M M
1010 2 AL+AR AL+AR AL AR
1011 3 M+AL+AR M+AL+AR M+AL M+AR
1100 4 DL+DR DL+DR DL DR
1101 5 DL+DR+AL+AR DL+DR+AL+AR DL+AL DR+AR
1110 M+DL+DR+AL+AR M+DL+DR+AL+A
6 M+DL+AL M+DR+AR
R
1111 7 M+DL+DR M+DL+DR M+DL M+DR
4 OCL This sets the headphone output to use output capacitor-less configuration.
OCL Headphone output configuration
0 Cap-coupled Single-ended Mode (SE)
1 Output capacitor-less (OCL)
(1) SD — Shutdown
M — Mono Differential Input
AL — Analog Left Channel
AR — Analog Right Channel
DL — I2S DAC Left Channel
DR — I2S DAC Right Channel
Note: Power-On Default Mode is Mode 0
This register is used to control the different output configurations.
Table 8. Output Control (01h)
Bits Field Description
0 EP_OUTPUT This enables the Mono Earpiece output.
EP_OUTPUT Status
0 Mono earpice output off
1 Mono earpice output on
1 LS_OUTPUT This enables the Mono Loudspeaker output.
LS_OUTPUT Status
0 Loudspeaker output off
1 Loudspeaker output on
2 HP_L_OUTPUT This enables the Headphone left output.
HP_L_OUTPUT Status
0 Headphone left output off. If OCL=1, output is in mute.
1 Headphone left output on
3 HP_R_OUTPUT This enables the Headphone right output.
HP_R_OUTPUT Status
0 Headphone right output off. If OCL=1, output is in
mute.
1 Headphone right output on
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Table 8. Output Control (01h) (continued)
Bits Field Description
4 STEREO_INPUT_ONLY This enables the analog left (AL) and analog right (AR) and disables all other inputs.
STEREO_INPUT_ONLY Status
0 Normal
1 Enables AL and AR inputs only
5 DAC_INPUT_ONLY This enables the DAC left (DL) and analog right (DR) and disables all other inputs.
DAC_INPUT_ONLY Status
0 Normal
1 Enables DL and DR inputs only
6 MONO_ONLY This enables mono earpiece (EP) and loudspeaker (LS) outputs MUX and disables the
headphone outputs MUX. Enabling this mode can save up to 400µA of current.
MONO_ONLY Status
0 Normal
1 Enable mono earpiece and loudspeaker outputs MUX
7 STEREO_OUTPUT_ONLY This enables the headphone output MUX only and disables all other output MUX’s.
Enabling this mode can save up to 200µA of current.
STEREO_OUTPUT_ONLY Status
0 Normal
1 Enables the headphone output MUX
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Volume Control Registers
These registers are used to control output volume control levels for Earpiece, Loudspeaker and Headphone.
Table 9. Volume Control Register
EP_VOL (02h), LS_VOL (03h), HP_L_VOL (05h), HP_R_VOL (06h)
Bits Field Description
4:0 EP_VOL This programs the Earpiece, Loudspeaker and Headphone volume
LS_VOL level.
HP_L_VOL VOL Level (dB)
HP_R_VOL 00000 MUTE
00001 –56
00010 –52
00011 –48
00100 –45
00101 –42
00110 –39
00111 –36
01000 –33
01001 –30
01010 –28
01011 –26
01100 –24
01101 –22
01110 –20
01111 –18
10000 –16
10001 –14
10010 –12
10011 –10
10100 –8
10101 –6
10110 –4
10111 –3
11000 –2
11001 –1
11010 0
11011 1
11100 2
11101 3
11110 4
11111 5
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This register is used to control input gain for left and right analog inputs.
Table 10. Analog Left and Right Input Control (07h)
Bits Field Description
2:0 ANA_L_GAIN This program the analog left input gain.
ANA_L_GAIN Level (dB)
000 –6
001 –3
010 0
011 3
100 6
101 9
110 12
111 15
5:3 ANA_R_GAIN This program the analog Right input gain.
ANA_R_GAIN Level (dB)
000 –6
001 –3
010 0
011 3
100 6
101 9
110 12
111 15
This register is sued to control input gain for Mono, DAC left and right inputs.
Table 11. Mono and DAC Input Gain Control (08h)
Bits Field Description
2:0 MONO_IN_GAIN This program the mono input gain.
MONO_IN_GAIN Level (dB)
000 –12
001 –9
010 –6
011 –3
100 0
101 3
110 6
111 9
4:3 DAC_L_GAIN This program the DAC left input gain.
DAC_L_GAIN Level (dB)
00 –3
01 0
10 3
11 6
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Table 11. Mono and DAC Input Gain Control (08h) (continued)
Bits Field Description
6:5 DAC_R_GAIN This program the DAC Right input gain.
DAC_R_GAIN Level (dB)
00 –3
01 0
10 3
11 6
Clock Configuration Register
This register is used to control the multiplexers and clock R divider in the clock module.
Table 12. CLOCK (09h)
Bits Register Description
0 FAST_CLOCK If set master clock is divided by two.
FAST_CLOCK MCLK Frequency
0 Normal
1 Divided by 2
1 PLL_INPUT Programs the PLL input multiplexer to select:
PLL_INPUT PLL Input Source
0 MCLK
1 I2S Input Clock
2 AUDIO_CLK_SEL Selects which clock is passed to the audio sub-system
DAC_CLK_SEL DAC Sub-system
Input Source
0 PLL Input
1 PLL Output
3 PLL_ENABLE If set enables the PLL. (MODES 4–7 only)
7:4 R_DIV Programs the R divider
R_DIV Divide Value
0000 1
0001 1
0010 1.5
0011 2
0100 2.5
0101 3
0110 3.5
0111 4
1000 4.5
1001 5
1010 5.5
1011 6
1100 6.5
1101 7
1110 7.5
1111 8
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I2S_CLK
MCLK
pll_input
I2S_INT_CLK
PLL
I2S_INPUT_CLK
I2S
Interface Stereo DAC
125/128
I2S_OUTPUT_CLK
%2 1
00
1
fast_clock
DAC
Clock
Gen
%R
DSP CLK
0
1
audio_dk_sel
R Div input clock
PLL
output
clock
PLL input
clock Clock Gen
input clock
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By default the stereo DAC operates at 250*fs, i.e. 12.000MHz (at the clock generator input clock) for 48kHz data.
It is expected that the PLL be used to drive the audio system unless a 12.000MHz master clock is supplied. The
PLL can also use the I2S clock input as a source. In this case, the audio DAC uses the clock from the output of
the PLL.
Common Clock Settings for the DAC
The DAC can work in 4 modes, each with different oversampling rates, 125,128,64 and 32. In normal operation
125x oversampling provides for the simplest clocking solution as it will work from 12.000MHz (common in most
systems with Bluetooth or USB) at 48kHz exactly. The other modes are useful if data is being provided to the
DAC from an uncontrollable isochronous source (such as a CD player, DAB, or other external digital source)
rather than being decoded from memory. In this case the PLL can be used to derive a clock for the DAC from the
I2S clock.
The DAC oversampling rate can be changed to allow simpler clocking strategies, this is controlled in the DAC
SETUP register but the oversampling rates are as follows:
DAC MODE Over sampling Ratio Used
00 125
01 128
10 64
11 32
The following table describes the clock required at the clock generator input for various clock sample rates in the
different DAC modes:
Required CLock at DAC Clock Generator
Fs (kHz) DAC Oversampling Ratio Input (MHz)
8 125 2
8 128 2.048
11.025 125 2.75625
11.025 128 2.8224
12 125 3
12 128 3.072
16 125 4
16 128 4.096
22.05 125 5.5125
22.05 128 5.6448
24 125 6
24 128 6.144
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Required CLock at DAC Clock Generator
Fs (kHz) DAC Oversampling Ratio Input (MHz)
32 125 8
32 128 8.192
44.1 125 11.025
44.1 128 11.2896
48 125 12
48 128 12.288
88.2 64 11.2896
96 64 12.288
176.4 32 22.5792
192 32 24.576
Methods for producing these clock frequencies are described in the PLL section.
The R divider can be used when the master clock is exactly 12.00 MHz in order to generate different sample
rates. The Table below shows different sample rates supported from 12.00MHz by using only the R divider and
disabling the PLL. In this way we can save power and the clock jitter will be low.
DAC Clock Generator Input
R_DIV Divide Value Sample Rate Supported <KHz>
Frequency <MHz>
11 6 2 8
9 5 2.4 9.6
7 4 3 12
5 3 4 16
4 2.5 4.8 19.2
3 2 6 24
2 1.5 8 32
0 1 12 48
The R divider can also be used along with the P divider in order to create the clock needed to support low
sample rates.
PLL Configuration Registers
PLL M DIVIDER CONFIGURATION REGISTER
This register is used to control the input divider of the PLL.
Table 13. PLL_M (0Ah)(1)
Bits Register Description
6:0 PLL_M Programs the PLL input divider to select:
PLL_M Divide Ratio
0000000 Divider Off
0000001 1
0000010 1.5
0000011 2
0000100 2.5
... ...
1111110 63.5
(1) The M divider should be set such that the output of the divider is between 0.5 and 5MHz. See the PLL setup section for details.
The division of the M divider is derived from PLL_M as such:
M = (PLL_M+1) / 2
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PLL N DIVIDER CONFIGURATION REGISTER
This register is used to control PLL N divider.
Table 14. PLL_N (0Bh)(1)
Bits Register Description
7:0 PLL_N Programs the PLL feedback divider:
PLL_N Divide Ratio
00000000 Divider Off
00000001 →00001010 10
00001011 11
00001100 12
... ...
11111000 248
11111001 249
(1) The N divider should be set such that the output of the divider is between 0.5 and 5MHz. See the PLL setup section for details. The N
divider should never be set so that (Fin/M) * N > 55MHz (or 80MHz if FAST_VCO is set in the PLL_N_MOD register).
The non-sigma-delta division of the N divider is derived from the PLL_N as such:
N = PLL_N
Fin /M is often referred to as Fcomp (Frequency of Comparison) or Fref (Reference Frequency). In this document, Fcomp is used
PLL P DIVIDER CONFIGURATION REGISTER
This register is used to control the PLL's P divider.
Table 15. PLL_P(1)
Bits Register Description
3:0 PLL_P Programs the PLL input divider to select:
0000 Divider Off
0001 1
0010 1.5
0011 2
... –> 2.5
1101 7
1110 7.5
1111 8
(1) The output of this divider should be either 12 or 24MHz in USB mode or 11.2896MHz, 12.288MHz or 24.576MHz in non-USB modes.
The division of the P divider is derived from PLL_P as such:
P = (PLL_P+1) / 2
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PLL_N_MODPLL_N
8
8 5
6'M
% N
% PVCO
0
% M
PLL_M
0.5 - 26 MHz
PLL_P
40 to 80 MHz
Phase Comparator
and Charge Pump
0.5 < 5 MHz
256 x FS
OR
250 x FS
7
4
M = 0, 1 + 0/2 64
N = 0, 1, 2, .., 255
P = 0, 1 + 0/2 8
External Loop Filter
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PLL N MODULATOR AND DITHER SELECT CONFIGURATION REGISTER
This register is used to control the Fractional component of the PLL.
Table 16. PLL_N_MOD (0Ch)(1)
Bits Register Description
4:0 PLL_N_MOD This programs the PLL N Modulator's fractional component:
PLL_N_MOD Fractional Addition
00000 0/32
00001 1/32
00010 →11110 2/32 →30/32
6:5 DITHER_LEVEL Allows control over the dither used by the N Modulator
DITHER_LEVEL DAC Sub-system Input Source
00 Medium (32)
01 Small (16)
10 Large (48)
7 VCO_FAST If set the VCO maximum and minimum frequencies are raised:
VCO_FAST Maximum FVCO
0 40–55MHz
(1) The complete N divider is a fractional divider as such:
N = PLL_N + (PLL_N_MOD/32)
If the modulus input is zero, then the N divider is simply an integer N divider. The output from the PLL is determined by the following
formula:
Fout = (Fin * N) / (M * P)
Please see over for more details on the PLL and common settings.
Further Notes on PLL Programming
The sigma-delta PLL is designed to drive audio circuits requiring accurate clock frequencies of up to 25MHz with
frequency errors noise-shaped away from the audio band. The 5 bits of modulus control provide exact
synchronization of 48kHz and 44.1kHz sample rates from any common clock source when the oversampling rate
of the audio system is 125fs. In systems where 128x oversampling must be used (for example with an
isochronous I2S data stream) a clock synchronous to the sample rate should be used as input to the PLL
(typically the I2S clock). If no isochronous source is available then the PLL can be used to obtain a clock that is
accurate to within typical crystal tolerances of the real sample rate.
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Table 17. Example Of PLL Settings For 48Khz Sample Rates
fsamp f_out
f_in (MHz) M N P PLL_M PLL_N PLL_N_MOD PLL_P
(kHz) (MHz)
11 48 11 60 5 21 60 0 9 12
12 48 5 25 5 9 25 0 9 12
12.288 48 4 19.53125 5 7 19 17 9 12
13 48 13 60 5 25 60 0 9 12
14.4 48 9 37.5 5 17 37 16 9 12
16.2 48 27 100 5 53 100 0 9 12
16.8 48 14 50 5 27 50 0 9 12
19.2 48 13 40.625 5 25 40 20 9 12
19.44 48 27 100 6 53 100 0 11 12
19.68 48 20.5 62.5 5 40 62 16 9 12
19.8 48 16.5 50 5 32 50 0 9 12
Table 18. Example PLL Settings For 44.1Khz Sample Rates
fsamp f_out
f_in (MHz) M N P PLL_M PLL_N PLL_N_MOD PLL_P
(kHz) (MHz)
11 44.1 11 55.125 5 21 55 4 9 11.025000
11.2896 44.1 8 39.0625 5 15 39 2 9 11.025000
12 44.1 5 22.96875 5 9 22 31 9 11.025000
13 44.1 13 55.125 5 25 55 4 9 11.025000
14.4 44.1 12 45.9375 5 23 45 30 9 11.025000
16.2 44.1 9 30.625 5 17 30 20 9 11.025000
16.8 44.1 17 55.78125 5 33 55 25 9 11.025000
19.2 44.1 16 45.9375 5 31 45 30 9 11.025000
19.44 44.1 13.5 38.28125 5 26 38 9 9 11.025000
19.68 44.1 20.5 45.9375 4 40 45 30 7 11.025000
19.8 44.1 11 30.625 5 21 30 20 9 11.025000
These tables cover the most common applications, obtaining clocks for sample rates such as 22.05kHz and
192kHz should be done by changing the P divider value or the R divider in the clock configuration diagram.
If the user needs to obtain a clock unrelated to those described above, the following method is advised. An
example of obtaining 11.2896 from 12.000MHz is shown below.
Choose a small range of P so that the VCO frequency is swept between 45 and 55MHz (or 60-80MHz if
VCOFAST is used). Remembering that the P divider can divide by half integers. So for P = 4.0 →7.0 sweep the
M inputs from 2.5 →24. The most accurate N and N_MOD can be calculated by:
N = FLOOR(((Fout/Fin)*(P*M)),1)
N_MOD = ROUND(32*((((Fout)/Fin)*(P*M)-N),0)
This shows that setting M = 11.5, N = 75 N_MOD = 47 P = 7 gives a comparison frequency of just over 1MHz, a
VCO frequency of just under 80MHz (so VCO_FAST must be set) and an output frequency of 11.289596 which
gives a sample rate of 44.099985443kHz, or accurate to 0.33 ppm.
Care must be taken when synchronization of isochronous data is not possible, i.e. when the PLL has to be used
in the above mode. The I2S should be master on the LM49321 so that the data source can support appropriate
SRC as required. This method should only be used with data being read on demand to eliminate sample rate
mismatch problems.
Where a system clock exists at an integer multiple of the required DAC clock rate it is preferable to use this
rather than the PLL. The LM49321 is designed to work in 8,12,16,24,32, and 48kHz modes from a 12MHz clock
without the use of the PLL. This saves power and reduces clock jitter.
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DAC Setup Register
This register is used to configure the basic operation of the stereo DAC.
Table 19. DAC_SETUP (0Eh)
Bits Register Description
1:0 DAC_MODE The DAC used in the LM49321 can operate in one of 4 oversampling modes.
The modes are described as follows:
DAC_MODE Oversampling Rate Typical fSMCLK Required
00 125 48KHz 12.000MHz (USB Mode)
44.1KHz 11.2896MHz
01 128 48KHz 12.288MHz
10 64 96KHz 12.288MHz
11 32 192KHz 24.576MHz
2 MUTE_L Mutes the left DAC channel on the next zero crossing.
3 MUTE_R Mutes the right DAC channel on the next zero crossing.
4 DITHER_OFF If set the dither in DAC is disabled.
5 DITHER If set the dither in DAC is enabled all the time.
ALWAYS_ON
6 CUST_COMP If set the DAC frequency response can be programmed manually via a 5 tap FIR
“compensation” filter. This can be used to enhance the frequency response of small
loudspeakers or provide a crude tone control. The compensation Coefficients can be set by
using registers 10h to 15h.
Interface Control Register
This register is used to control the I2S and I2C compatible interface on the chip.
Table 20. INTERFACE (0Fh)(1)
Bits Field Description
0 I2S_MASTER_SLAVE This enables I2S in master or slave mode.
I2S_MASTER_SLAVE Comments
LM49321 acts as a slave
where both I2S clock and word
0select are configured as
inputs.
LM49321 acts as a master for
I2S, so both I2S clock and I2S
1word select are configured as
outputs.
1 I2S_RESOLUTION This set the I2S resolution and affects the I2S Interface in
master mode. In slave mode the I2S Interface can support any
I2S compatible resolution. In master mode the I2S resolution
also depends on the DAC mode as the note below explains.
I2S_RESOLUTION Comments
0 I2S resolution is set to 16 bits.
1 I2S resolution is set to 32 bits.
2 I2S_MODE This set the I2S mode timing.
I2S_MODE Comments
I2S interface is configured in
0normal I2S mode timing.
I2S is configured in left
1justified mode timing.
(1) The master I2S format depends on the DAC mode. In USB mode the number of bits per word is 25 (i.e. 2.4MHz for a 48kHz sample
rate). The duty cycle is 40/60. In non-USB modes the format is 32 or 16 bits per word, depending on I2S_RESOLUTION and the duty
cycle is always 50-50. In slave mode it will decode any I2S compatible data stream.
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I2S_CLK
31 n2 n-1 31 2 nn-1
I2S_SDO
I2S_WS
LEFT
CHANNEL
RIGHT
CHANNEL
MSB LSB MSB LSB
I2S_CLK
31 n2 n-1 31 2 nn-1
I2S_SDO
I2S_WS
LEFT
CHANNEL
RIGHT
CHANNEL
MSB LSB MSB LSB
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Table 20. INTERFACE (0Fh)(1) (continued)
Bits Field Description
3 I2C_FAST This set the I2C Clock speed.
I2C_FAST Comments
I2C speed gets its default
0 value of a maximum of
400kHz.
This enables the I2C to run in
1 fast mode with an I2C clock up
to 3.4MHz.
Figure 6. I2S Mode Timing
Figure 7. Left Justified Mode Timing
FIR Compensation Filter Configuration Registers
These registers are used to configure the DAC’s FIR compensation filter. Three 16 bit coefficients are required
and must be programmed via the I2C/SPI Interface in bytes as follows:
Table 21. COMP_COEFF (10h →15h)(1)
Address Register Description
10h COMP_COEFF0_LSB Bits [7:0] of the 1st and 5th FIR tap (C0 and C4)
11h COMP_COEFF0_MSB Bits [15:8] of the 1st and 5th FIR tap (C0 and C4)
12h COMP_COEFF1_LSB Bits [7:0] of the 2nd and 4th FIR tap (C1 and C3)
13h COMP_COEFF1_MSB Bits [15:8] of the 2nd and 4th FIR tap (C1 and C3)
14h COMP_COEFF2_LSB Bits [7:0] of the 3rd FIR tap (C2)
15h COMP_COEFF2_MSB Bits [15:8] of the 3rd FIR tap (C2)
(1) The filter must be phase linear to ensure the data keeps the correct stereo imaging so the second half of the FIR filter must be the
reverse of the 1st half.
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Z-1
C0
Z-1 Z-1 Z-1
C1 C2 C3 C4
LM49321, LM49321RLEVAL
SNAS457C –SEPTEMBER 2008–REVISED MAY 2013
www.ti.com
If the CUST_COMP option in register 0Eh is not set the FIR filter will use its default values for a linear response
from the DAC into the analog mixer, these values are:
DAC_OSR C0, C4 C1, C3 C2
00 434 –2291 26984
01, 10, 11 61 –371 25699
If using 96 or 192kHz data then the custom compensation may be required to obtain flat frequency responses
above 24kHz. The total power of any custom filter must not exceed that of the above examples or the filters
within the DAC will clip. The coefficient must be programmed in 2’s complement.
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20 100 1k 10k 20k
0.001
0.01
0.1
1
10
THD+N (%)
FREQUENCY (Hz)
20 100 1k 10k 20k
0.001
0.01
0.1
1
10
THD+N (%)
FREQUENCY (Hz)
20 100 1k 10k 20k
0.001
0.01
0.1
1
10
THD+N (%)
FREQUENCY (Hz)
20 100 1k 10k 20k
0.001
0.01
0.1
1
10
THD+N (%)
FREQUENCY (Hz)
20 100 1k 10k 20k
0.001
0.01
0.1
1
10
THD+N (%)
FREQUENCY (Hz)
20 100 1k 10k 20k
0.001
0.01
0.1
1
10
THD+N (%)
FREQUENCY (Hz)
LM49321, LM49321RLEVAL
www.ti.com
SNAS457C –SEPTEMBER 2008–REVISED MAY 2013
Typical Performance Characteristics
THD+N vs Frequency THD+N vs Frequency
AVDD = 3.0V, EP Out, RL= 32Ω, PO= 20mW AVDD = 3.0V, HP Out, RL= 16Ω, PO= 20mW
Figure 8. Figure 9.
THD+N vs Frequency THD+N vs Frequency
AVDD = 3.0V, LS Out, RL= 8Ω, PO= 200mW AVDD = 5.0V, EP, RL= 32Ω, PO= 40mW
Figure 10. Figure 11.
THD+N vs Frequency THD+N vs Frequency
AVDD = 5.0V, HP Out, RL= 16Ω, PO= 60mW AVDD = 5.0V, HP Out, RL= 32Ω, PO= 30mW
Figure 12. Figure 13.
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1m 50m 100m
0.001
0.01
0.1
1
10
THD+N (%)
OUTPUT POWER (W)
10m
10m 100m 500m
0.001
0.01
0.1
1
10
THD+N (%)
OUTPUT POWER (W)
1m 50m 100m
0.001
0.01
0.1
1
10
THD+N (%)
OUTPUT POWER (W)
10m
1m 50m 100m
0.001
0.01
0.1
1
10
THD+N (%)
OUTPUT POWER (W)
10m
20 100 1k 10k 20k
0.001
0.01
0.1
1
10
THD+N (%)
FREQUENCY (Hz)
1m 50m 100m
0.001
0.01
0.1
1
10
THD+N (%)
OUTPUT POWER (W)
10m
LM49321, LM49321RLEVAL
SNAS457C –SEPTEMBER 2008–REVISED MAY 2013
www.ti.com
Typical Performance Characteristics (continued)
THD+N vs Frequency THD+N vs Output Power
AVDD = 5.0V, LS Out, RL= 8Ω, PO= 500mW AVDD = 3.0V, EP Out, RL= 16Ω, f = 1kHz
Figure 14. Figure 15.
THD+N vs Output Power THD+N vs Output Power
AVDD = 3.0V, EP Out, RL= 32Ω, f = 1kHz AVDD = 3.0V, HP Out, RL= 16Ω, f = 1kHz
Figure 16. Figure 17.
THD+N vs Output Power THD+N vs Output Power
AVDD = 3.0V, HP Out, RL= 32Ω, f = 1kHz AVDD = 3.0V, LS Out, RL= 8Ω, f = 1kHz
Figure 18. Figure 19.
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1m 10m 100m 1
0.001
0.01
0.1
1
10
THD+N (%)
I2S INPUT LEVEL (FFS)
10m 100m 2
0.001
0.01
0.1
1
10
THD+N (%)
OUTPUT POWER (W)
1m 100m200m
0.001
0.01
0.1
1
10
THD+N (%)
OUTPUT POWER (W)
10m
1m 100m200m
0.001
0.01
0.1
1
10
THD+N (%)
OUTPUT POWER (W)
10m
1m 100m200m
0.001
0.01
0.1
1
10
THD+N (%)
OUTPUT POWER (W)
10m
1m 100m200m
0.001
0.01
0.1
1
10
THD+N (%)
OUTPUT POWER (W)
10m
LM49321, LM49321RLEVAL
www.ti.com
SNAS457C –SEPTEMBER 2008–REVISED MAY 2013
Typical Performance Characteristics (continued)
THD+N vs Output Power THD+N vs Output Power
AVDD = 5.0V, EP Out, RL= 16Ω, f = 1kHz AVDD = 5.0V, EP Out, RL= 32Ω, f = 1kHz
Figure 20. Figure 21.
THD+N vs Output Power THD+N vs Output Power
AVDD = 5.0V, HP Out, RL= 16Ω, f = 1kHz AVDD = 5.0V, HP Out, RL= 32Ω, f = 1kHz
Figure 22. Figure 23.
THD+N vs Output Power
AVDD = 5.0V, LS Out, RL= 8Ω, f = 1kHz THD+N vs I2S Level EP Out
Figure 24. Figure 25.
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20 100 1k 10k 100k
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
PSRR (dB)
FREQUENCY (Hz)
20 100 1k 10k 100k
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
PSRR (dB)
FREQUENCY (Hz)
20 100 1k 10k 100k
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
PSRR (dB)
FREQUENCY (Hz)
20 100 1k 10k 100k
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
PSRR (dB)
FREQUENCY (Hz)
1m 10m 100m 1
0.001
0.01
0.1
1
10
THD+N (%)
I2S INPUT LEVEL (FFS)
1m 10m 100m 1
0.001
0.01
0.1
1
10
THD+N (%)
I2S INPUT LEVEL (FFS)
LM49321, LM49321RLEVAL
SNAS457C –SEPTEMBER 2008–REVISED MAY 2013
www.ti.com
Typical Performance Characteristics (continued)
THD+N vs I2S Level HP Out THD+N vs I2S Level LS Out
Figure 26. Figure 27.
PSRR vs Frequency PSRR vs Frequency
AVDD = 3.0V, EP Out Mode 1 AVDD = 3.0V, EP Out Mode 4
Figure 28. Figure 29.
PSRR vs Frequency PSRR vs Frequency
AVDD = 3.0V, HP Out Mode 2 AVDD = 3.0V, HP Out Mode 4
Figure 30. Figure 31.
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20 100 1k 10k 100k
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
PSRR (dB)
FREQUENCY (Hz)
20 100 1k 10k 100k
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
PSRR (dB)
FREQUENCY (Hz)
20 100 1k 10k 100k
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
PSRR (dB)
FREQUENCY (Hz)
20 100 1k 10k 100k
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
PSRR (dB)
FREQUENCY (Hz)
20 100 1k 10k 100k
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
PSRR (dB)
FREQUENCY (Hz)
20 100 1k 10k 100k
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
PSRR (dB)
FREQUENCY (Hz)
LM49321, LM49321RLEVAL
www.ti.com
SNAS457C –SEPTEMBER 2008–REVISED MAY 2013
Typical Performance Characteristics (continued)
PSRR vs Frequency PSRR vs Frequency
AVDD = 3.0V, LS Out Mode 2 AVDD = 3.0V, LS Out Mode 4
Figure 32. Figure 33.
PSRR vs Frequency PSRR vs Frequency
AVDD = 5.0V, HP Out Mode 2 AVDD = 5.0V, HP Out Mode 4
Figure 34. Figure 35.
PSRR vs Frequency PSRR vs Frequency
AVDD = 5.0V, LS Out Mode 4 AVDD = 5.0V, LS Out Mode 2
Figure 36. Figure 37.
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2.7 3 3.5 4 5.5
0
200m
400m
600m
800m
1
1.2
1.4
1.6
1.8
2
OUTPUT POWER (W)
SUPPLY VOLTAGE (V)
4.5 5
2.7 3 3.5 4 5.5
0
40
80
120
160
200
240
280
OUTPUT POWER (mW)
SUPPLY VOLTAGE (V)
4.5 5
2.7 3 3.5 4 5.5
10
30
50
70
90
110
130
150
OUTPUT POWER (mW)
SUPPLY VOLTAGE (V)
4.5 5
LM49321, LM49321RLEVAL
SNAS457C –SEPTEMBER 2008–REVISED MAY 2013
www.ti.com
Typical Performance Characteristics (continued)
Output Power vs Supply Voltage Output Power vs Supply Voltage
EP Out , RL= 32Ω, 1% THD+N HP Out , RL= 32Ω, 1% THD+N
Figure 38. Figure 39.
Output Power vs Supply Voltage
LS Out , RL= 8Ω, 1% THD+N
Figure 40.
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SNAS457C –SEPTEMBER 2008–REVISED MAY 2013
APPLICATION INFORMATION
I2S
The LM49321 supports both master and slave I2S transmission at either 16 or 32 bits per word at clock rates up
to 3.072MHz (48kHz stereo, 32bit). The basic format is shown below:
Figure 41.
MONO ONLY SETTING
The LM49321 may be restricted to mono amplification only by setting MONO_ONLY in Output Control register
0x01h to 1. This may save an additional 400μA from IDD.
LM49321 DEMOBOARD OPERATION
BOARD LAYOUT
DIGITAL SUPPLIES
JP14 — Digital Power DVDD
JP10 — I/O Power IOVDD
JP13 — PLL Supply PLLVDD
JP16 — USB Board Supply BBVDD
JP15 — I2CVDD
All supplies may be set independently. All digital ground is common. Jumpers may be used to connect all the
digital supplies together.
S9 – connects VDD_PLL to VDD_D
S10 – connects VDD_D to VDD_IO
S11 – connects VDD_IO to VDD_I2C
S12 – connects VDD_I2C to Analog VDD
S17 – connects BB_VDD to USB3.3V (from USB board)
S19 – connects VDD_D to USB3.3V (from USB board)
S20 – connects VDD_D to SPDIF receiver chip
ANALOG SUPPLY
JP11 — Analog Supply
S12 — connects Analog VDD with Digital VDD (I2C_VDD)
S16 — connects Analog Ground with Digital Ground
S21 — connects Analog VDD to SPDIF receiver chip
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INPUTS
Analog Inputs
JP2 — Mono Differential Input
JP6 — Left Input
JP7 — Right Input
Digital Inputs
JP19 — Digital Interface
Pin 1 — MCLK
Pin 2 — I2S_CLK
Pin 3 — I2S_SDI
Pin 4 — I2S_WS
JP20 — Toslink SPDIF Input
JP21 — Coaxial SPDIF Input
Coaxial and Toslink inputs may be toggled between by use of S25. Only one may be used at a time. Must be
used in conjunction with on-board SPDIF receiver chip.
OUTPUTS
JP5 — BTL Loudspeaker Output
JP1 — Left Headphone Output (Single-Ended or OCL)
JP3 — Right Headphone Output (Single-Ended or OCL)
P1 — Stereo Headphone Jack (Same as JP1, JP2, Single-Ended or OCL)
JP12 — Mono BTL Earpiece Output
CONTROL INTERFACE
X1, X2 – USB Control Bus for I2C/SPI
X1
Pin 9 – Mode Select (SPI or I2C)
X2
Pin 1 – SDA
Pin 3 – SCL
Pin 15 – ADDR/END
Pin 14 – USB5V
Pin 16 – USB3.3V
Pin 16 – USB GND
MISCELLANEOUS
I2S BUS SELECT
S23, S24, S26, S27 – I2S Bus select. Toggles between on-board and external I2S (whether on-board SPDIF
receiver is used). All jumpers must be set the same. Jumpers on top two pins selects external bus (JP19).
Jumpers on bottom two pins selects on-board SPDIF receiver output.
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HEADPHONE OUTPUT CONFIGURATION
Jumpers S1, S2, S3, and S4 are used to configure the headphone outputs for either cap-coupled outputs or
output capacitorless (OCL) mode in addition to the register control internal to the LM49321 for this feature.
Jumpers S1 and S3 bypass the output DC blocking capacitors when OCL mode is required. S2 connects the
center amplifier HPCOUT to the headphone ring when in OCL mode. S4 connects the center ring to GND when
cap-coupled mode is desired. S4 must be removed for OCL mode to function properly. Jumper settings for each
mode:
OCL
S1 = ON
S2 = ON
S3 = ON
S4 = OFF
Cap-Coupled
S1 = OFF
S2 = OFF
S3 = OFF
S4 = ON
PLL FILTER CONFIGURATION
The LM49321 demo board comes with a simple filter setup by connecting jumpers S5 and S6. Removing these
and connecting jumpers S7 and S8 will allow for an alternate PLL filter configuration to be used at R2 and C23.
ON-BOARD SPDIF RECEIVER
The SPDIF receiver present on the LM49321 demo board allows quick demonstration of the capabilities of the
LM49321 by using the common SPDIF output found on most CD/DVD players today. There are some limitations
in its useage, as the receiver will not work with digital supplies of less than 3.0V and analog supplies of less than
4V. This means low analog supply voltage testing of the LM49321 must be done on the external digital bus.
The choice of using on-board or external digital bus is made using jumpers S23, S24, S26, and S27 as described
above.
S25 selects whether the Toslink or Coaxial SPDIF input is used. The top two pins connects the toslink, the
bottom two connect the coaxial input.
Power on the digital side is routed through S20 (connecting to the other digital supplies), while on the analog side
it is interrupted by S21. Both jumpers must be in place for the receiver to function. The part is already configured
for I2S standard outputs. Jumper S28 allows the DATA output to be pulled either high or low. Default is high
(jumper on right two pins).
It may be necessary to quickly toggle S29 to reset the receiver and start it working upon initial power up. A quick
short across S29 should clear this condition.
LM49321 I2C/SPI INTERFACE SOFTWARE
Convenient graphical user interface software is available for demonstration purposes of the LM49321. It allows
for either SPI or I2C control via either USB or parallel port connections to a Windows computer. Control options
include all mode and output settings, volume controls, PLL and DAC setup, FIR setting and on-the-fly adjustment
by an easy to use graphical interface. An advanced option is also present to allow direct, register-level
commands. Software is available from www.ti.com and is compatible with Windows operating systems of
Windows 98 or more (with USB support) with the latest .NET updates from Microsoft.
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1
2
JP12
1
2
JP14
1
2
JP13
1
2
JP15
VDD_D
VDD_PLL
VDD_PLL
VDD_A
VDD_A
R3
422
150 nF
C18
10 nF
C19
1 uF
C4
1 uF
C9
0.1 uF C8
S7 S8
S6 S5
R2
C23
S10
P1
Stereo Headphone
Jack
1 uF C5
0.1 uF
C3
1
2
JP5
1
2
JP2
1
2
JP6
1
2
JP7
2.2 uF
C17
220 uF
C12
220 uF
C13
S4
S2
S3
S1
1
2
JP9
VDD_IO
1 uF
C16
S9
1
2
JP11
S12
S16
VDD_I2C
0.22 uF
C10
0.22 uF
C11
0.22 uF
C14
VDD_I2C
1
2
JP1
1
2
JP3
0.22 uF
C30
HPLOUT E5
HPCOUT D6
HPROUT D5
AGRND D2
LSOUTP F6
AVDD
C6
LSLOUTM F4
AGRND E6
EPOUTP F3
EPOUTM F2
M_IN+
F1
L_IN
E2
R_IN
E3
PLL_IN
C3
PLL_OUT
C2
PLL_GND C1
PLL_VDD
B1
DGND A1
MCLK
A2
I2S_DATA
B2 I2S_CLK
B3
I2S_WS
A3
GPIO B4
MODE
D4
SDA/SDI
A4
ADDR/ENBL
C4
VDD_I/O A6
I2C_VDD
B5
SCL/SCK
B6
AVDD
F5
BP
C5
M_IN-
E1
DVDD
A5
NC D3
NC E4
U1
LM49321RL
VDD_D
0.1 uF
C2
1 uF
C1
1
2
JP10
S11
VDD_IO
DGND
Diiferential Mono
Input
L IN
R IN
PLL
FILTER
OUTPUT 1
GND 2
VCC 3
JP20
TOSLINK RECEIVER
R4
75
C20
0.1 uF
0.01 uF
C24
C25
0.01 uF 47k
R6
47k
R5
R7
47k
23
1
S28
R9
1.6k
C27
0.33 uF
4.7 nF
C26
VDD_D
0.1 uF
C21
0.1 uF
C22
S26 I2S WS
S24 MCLK
S27 I2S CLK
S23 I2S DATA
R12
5k
5k
R11
BBVDD
USB_SCL
USB_SDA
USB_CS
USB_SPIDO
2
3
1S25
S20
47 uH
L1
COPY 1
DVDD
2
EMPH
3
RXP
4
RXN
5
AVDD
6AGND 7
FILT
8RST
9
MCLK 10
RERR 11
RCBL 12
PRO 13
CHS
14
NVERR 15
I2S_CLK 16
I2S_WS 17
I2S_DOUT 18
AUDIO 19
DGND 20
DGND 21
DGND 22
DVDD
23
H/S
24
U25
C26
DVDD
27
ORIG
28 U2
CS8415A
R8
47k
R10
5k
S29
RESET SPDIF
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
X1
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
X2
USB INTERFACE
USB_3.3V
USB_5V
USB_SPIDO
USB_CS
USB_SDA
USB_SCL
S22
1
2
JP16
BB_VDD
BBVDD
VDD_D
S17
S19
USB_3.3V
VDD_A S18
USB_5V
1
2
3
4
5
6
7
8
9
10
11
12
13
14
JP19
DIGITAL INTERFACE
JP21
S/PDIF IN
USB_SPI_M
USB_SPI_M
S21
VDD_A
LM49321, LM49321RLEVAL
SNAS457C –SEPTEMBER 2008–REVISED MAY 2013
www.ti.com
Demonstration Board Schematic
Figure 42. Complete Board Schematic
36 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: LM49321 LM49321RLEVAL
1
2
JP2
1
2
JP6
1
2
JP7
0.22 uF
C10
0.22 uF
C11
0.22 uF
C14
OUTPUT 1
GND 2
VCC 3
JP20
TOSLINK RECEIVER
75
R4
0.1 uF
C20
0.01 uF
C24
0.01 uF
C25 47k
R6
47k
R5
47k
R7 23
1
S28
1.6k
R9
0.33 uF
C27
4.7 nF
C26
VDD_D
0.1 uF
C21
0.1 uF
C22
S26 I2S WS
S24 MCLK
S27 I2S CLK
S23 I2S DATA
5k
R12
5k
R11
BBVDD
USB_SCL
USB_SDA
USB_CS
USB_SPIDO
2
3
1S25
S20
47 uH
L1
COPY 1
DVDD
2
EMPH
3
RXP
4
RXN
5
AVDD
6AGND 7
FILT
8RST
9
MCLK 10
RERR 11
RCBL 12
PRO 13
CHS
14
NVERR 15
I2S_CLK 16
I2S_WS 17
I2S_DOUT 18
AUDIO 19
DGND 20
DGND 21
DGND 22
DVDD
23
H/S
24
U25
C26
DVDD
27
ORIG
28 U2
CS8415A
47k
R8
5k
R10
S29
RESET SPDIF
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
X1
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
X2
USB INTERFACE
USB_3.3V
USB_5V
USB_SPIDO
USB_CS
USB_SDA
USB_SCL
S22
1
2
JP16
BB_VDD
BBVDD
VDD_D
S17
S19
USB_3.3V
VDD_A S18
USB_5V
1
2
3
4
5
6
7
8
9
10
11
12
13
14
JP19
DIGITAL INTERFACE
JP21
S/PDIF IN
USB_SPI_M
USB_SPI_M
S21
VDD_A
0.22 uF
C30
Diiferential Mono
Input
L IN
R IN
LM49321, LM49321RLEVAL
www.ti.com
SNAS457C –SEPTEMBER 2008–REVISED MAY 2013
Figure 43. Enlarged Board Schematic Part 1 of 2
Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 37
Product Folder Links: LM49321 LM49321RLEVAL
1
2
JP12
1
2
JP14
1
2
JP13
1
2
JP15
VDD_D
VDD_PLL
VDD_PLL
VDD_A
VDD_A
R3
422
150 nF
C18
10 nF
C19
1 uF
C4
1 uF
C9
0.1 uF C8
S7 S8
S6 S5
R2
C23
S10
P1
Stereo Headphone Jack
1 uF C5
0.1 uF
C3
1
2
JP5
2.2 uF
C17
220 uF
C12
220 uF
C13
S4
S2
S3
S1
1
2
JP9
VDD_IO
1 uF
C16
S9
1
2
JP11
S12
S16
VDD_I2C
VDD_I2C
1
2
JP1
1
2
JP3
HPLOUT E5
HPCOUT D6
HPROUT D5
AGRND D2
LSOUTP F6
AVDD
C6
LSLOUTM F4
AGRND E6
EPOUTP F3
EPOUTM F2
M_IN+
F1
L_IN
E2
R_IN
E3
PLL_IN
C3
PLL_OUT
C2
PLL_GND C1
PLL_VDD
B1
DGND A1
MCLK
A2
I2S_DATA
B2 I2S_CLK
B3
I2S_WS
A3
GPIO B4
MODE
D4
SDA/SDI
A4
ADDR/ENBL
C4
VDD_I/O A6
I2C_VDD
B5
SCL/SCK
B6
AVDD
F5
BP
C5
M_IN-
E1
DVDD
A5
NC D3
NC E4
U1
LM49321RL
VDD_D
0.1 uF
C2
1 uF
C1
1
2
JP10
S11
VDD_IO
DGND
PLL
FILTER
LM49321, LM49321RLEVAL
SNAS457C –SEPTEMBER 2008–REVISED MAY 2013
www.ti.com
Figure 44. Enlarged Board Schematic Part 2 of 2
38 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: LM49321 LM49321RLEVAL
LM49321, LM49321RLEVAL
www.ti.com
SNAS457C –SEPTEMBER 2008–REVISED MAY 2013
Revision History
Rev Date Description
1.0 09/10/08 Initial release.
1.01 09/23/08 Text edits.
1.02 08/31/09 Edited the package drawing and the top markings.
C 05/03/13 Changed layout of National Data Sheet to TI format.
Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 39
Product Folder Links: LM49321 LM49321RLEVAL
PACKAGE OPTION ADDENDUM
www.ti.com 24-Sep-2015
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LM49321RL/NOPB ACTIVE DSBGA YPG 36 250 Green (RoHS
& no Sb/Br) SNAG Level-1-260C-UNLIM -40 to 85 GK9
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 24-Sep-2015
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LM49321RL/NOPB DSBGA YPG 36 250 178.0 12.4 3.43 3.59 0.76 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 2-Sep-2015
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM49321RL/NOPB DSBGA YPG 36 250 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 2-Sep-2015
Pack Materials-Page 2
MECHANICAL DATA
YPG0036xxx
www.ti.com
RLA36XXX (Rev A)
0.650±0.075
D
E
4214895/A 12/12
A
. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.
B. This drawing is subject to change without notice.
NOTES:
D: Max =
E: Max =
3.525 mm, Min =
3.268 mm, Min =
3.465 mm
3.208 mm
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