LM49321, LM49321RLEVAL www.ti.com SNAS457C - SEPTEMBER 2008 - REVISED MAY 2013 LM49321 Audio Sub-System with Stereo DAC, Mono Class AB Loudspeaker Amplifier, OCL/SE Stereo Headphone Output and RF Suppression Check for Samples: LM49321, LM49321RLEVAL FEATURES DESCRIPTION * The LM49321 is an integrated audio sub-system designed for mono voice, stereo music cell phones connecting to base band processors with mono differential analog voice paths. Operating on a 3.3V supply, it combines a mono speaker amplifier delivering 520mW into an 8 load, a stereo headphone amplifier delivering 36mW per channel into a 32 load, and a mono earpiece amplifier delivering 55mW into a 32 load. The headphone amplifier can be configured for output capacitor-less (OCL) or single-ended (SE) mode. It integrates the audio amplifiers, volume control, mixer, and power management control all into a single package. In addition, the LM49321 routes and mixes the singleended stereo and differential mono inputs into multiple distinct output modes. The LM49321 features an I2S serial interface for full range audio and an I2C or SPI compatible interface for control. The full range music path features an SNR of 85dB with up to 192kHz playback. 1 2 * * * * * * * * * * 8-Bit Stereo DAC with up to 192kHz Sampling Rate Multiple Distinct Output Modes Mono Class AB Speaker Amplifier Stereo OCL/SE Headphone Amplifier Mono Earpiece Amplifier Differential Mono Analog Input Single-Ended Analog Inputs Independent Loudspeaker, Headphone and Mono Earpiece Volume controls I2C/SPI (Selectable) Compatible Interface Ultra Low Shutdown Current Click and Pop Suppression Circuit APPLICATIONS * * * * Cell Phones PDAs Laptop Computers Portable Devices Boomer audio power amplifiers are designed specifically to provide high quality output power with a minimal amount of external components. KEY SPECIFICATIONS * * * * * POUT LS, 8, 3.3V, 1% THD+N: 520 mW (Typ) POUT HP, 32, 3.3V, 1% THD+N: 36 mW (Typ) POUT Mono Earpiece, 32, 1% THD+N: 55 mW (Typ) Shutdown Current: 0.6 A (Typ) SNR (DAC + Amplifier): 85 dB (Typ) 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2008-2013, Texas Instruments Incorporated LM49321, LM49321RLEVAL SNAS457C - SEPTEMBER 2008 - REVISED MAY 2013 www.ti.com Block Diagram AVDD + CB CS 0.1 PF 1 PF + + + CS I/O_VDD DVDD BYPASS CS 2.2 PF 1 PF + + CS CS 0.1 PF 1 PF + CS 0.1 PF MCLK PLL_IN Digital Power Analog Power and Bias PLL PLL_OUT PLL_VDD PLL_GND Ci 0.22 F DIFF+ Audio Differential Input DIFF- LS+ + Volume -56 dB to +5 dB Volume Speaker AMP LS- -12 dB to +9 dB - Ci Volume 0.22 F Mixer LIN and Volume Output -6 dB to +15 dB Ci 0.22 F Audio Single-Ended Inputs LHP -56 dB to +5 dB CHP Mode HP AMP Select RIN Volume -6 dB to +15 dB Volume Ci 0.22 F -56 dB to +5 dB 2 I S_CLK 2 I S_SDI STEREO DAC 2 I S_WS Volume DAC Gain -3 dB to 6 dB -56 dB to +5 dB RHP EP+ EP- Mono Earpiece (Receiver) 2 I C_VDD I2S_SDATA SCL/SCK ADDR/ENB MODE 2 I C/SPI Interface AGND DGND Figure 1. Typical Audio Amplifier Subsystem Application Circuit with Output Capacitor-Less (OCL) Headphone Configuration 2 Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LM49321 LM49321RLEVAL LM49321, LM49321RLEVAL www.ti.com SNAS457C - SEPTEMBER 2008 - REVISED MAY 2013 AVDD + + + CS CS 0.1 PF 1 PF I/O_VDD DVDD BYPASS + CB CS 2.2 PF 1 PF + + CS CS 0.1 PF 1 PF + CS 0.1 PF MCLK PLL_IN Ci 0.22 F DIFF+ DIFF- LS+ + Volume AMP LS- -12 dB to +9 dB - Ci 0.22 F 220 PF Volume Mixer LIN LHP -56 dB to +5 dB and Volume Output -6 dB to +15 dB Ci Audio Single-Ended Inputs Speaker Volume -56 dB to +5 dB + Audio Differential Input Digital Power Analog Power and Bias PLL PLL_OUT PLL_VDD PLL_GND CHP Mode 0.22 F HP AMP Select RIN Volume Volume -56 dB to +5 dB 2 I S_CLK 2 I S_SDI + 220 PF -6 dB to +15 dB Ci 0.22 F Volume DAC Gain -3 dB to 6 dB STEREO DAC 2 I S_WS -56 dB to +5 dB RHP EP+ EP- Mono Earpiece (Receiver) 2 I C_VDD 2 I S_SDATA SCL/SCK ADDR/ENB MODE 2 I C/SPI Interface AGND DGND Figure 2. Typical Audio Amplifier Subsystem Application Circuit with Cap-Coupled Single-Ended (SE) Headphone Configuration Connection Diagram Top View (Bump Side Down) 6 5 4 3 2 1 A B C D E F Figure 3. 36 - Bump DSBGA Package See Package Number YPG0036LVA Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LM49321 LM49321RLEVAL Submit Documentation Feedback 3 LM49321, LM49321RLEVAL SNAS457C - SEPTEMBER 2008 - REVISED MAY 2013 www.ti.com PIN DESCRIPTIONS Pin Pin Name Digital /Analog A1 DGND D P DIGITAL GND A2 MCLK D I MASTER CLOCK A3 I2S_WS D I/O I2S WORD SELECT A4 SDA/SDI D I/O I2C SDA OR SPI SDI A5 DVDD D P DIGITAL SUPPLY VOLTAGE A6 I/O_VDD D P I/O SUPPLY VOLTAGE B1 PLL_VDD D P PLL SUPPLY VOLTAGE B2 I2S_SDATA D I I2S SERIAL DATA INPUT B3 I2S_CLK D I/O I2S CLOCK SIGNAL B4 GPIO D O TEST PIN (MUST BE LEFT FLOATING) B5 I2C_VDD D P I2C SUPPLY VOLTAGE B6 SDL/SCK D I I2C_SCL OR SPI_SCK C1 PLL_GND D P PHASE LOCK LOOP GROUND C2 PLL_OUT D O PHASE LOCK LOOP FILTER OUTPUT C3 PLL_IN D I PLL FILTER INPUT C4 ADDR/ENB D I I2C ADDRESS OR SPI ENB DEPENDING ON MODE C5 BYPASS A I HALF-SUPPLY BYPASS C6 AVDD A P ANALOG SUPPLY VOLTAGE D1 AGND A P ANALOG GROUND D2 AGND A P D3 NC D4 MODE D I SELECTS BETWEEN I2C OR SPI CONTROL D5 RHP A O RIGHT HEADPHONE OUTPUT D6 CHP A O HEADPHONE CENTER PIN OUTPUT (1/2 VDD or GND) E1 DIFF- A I ANALOG NEGATIVE DIFFERENTIAL INPUT E2 LIN A I ANALOG LEFT CHANNEL INPUT E3 RIN A I E4 NC E5 LHP A O E6 AGND A P ANALOG GROUND F1 DIFF+ A I ANALOG POSITIVE DIFFERENTIAL INPUT F2 EP- A O MONO EARPIECE- OUTPUT F3 EP+ A O MONO EARPIECE+ OUTPUT F4 LS- A O LOUDSPEAKER OUTPUT- F5 AVDD A P ANALOG SUPPLY VOLTAGE F6 LS+ A O LOUDSPEAKER OUTPUT+ I/O, Power Description ANALOG GROUND NO CONNECT (MUST BE LEFT FLOATING) ANALOG RIGHT CHANNEL INPUT NO CONNECT (MUST BE LEFT FLOATING) LEFT HEADPHONE OUTPUT These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 4 Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LM49321 LM49321RLEVAL LM49321, LM49321RLEVAL www.ti.com SNAS457C - SEPTEMBER 2008 - REVISED MAY 2013 Absolute Maximum Ratings (1) (2) (3) (4) Analog Supply Voltage (1) 6.0V Digital Supply Voltage (1) 6.0V Storage Temperature -65C to +150C Input Voltage Power Dissipation -0.3V to VDD +0.3V (5) Internally Limited ESD Ratings (6) 2000V ESD Ratings (7) 200V Junction Temperature (TJMAX) 150C JA (RLA36) Thermal Resistance (1) (2) (3) (4) (5) (6) (7) 100C/W Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All voltages are measured with respect to the ground pin, unless otherwise specified. The Electrical Characteristics tables list specified specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not ensured. Soldering Information: See AN-1279 "Microfill Wafer Level Underfilled Chip Scale package" (Literature Number SNOA430) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications. Maximum allowable power dissipation is PDMAX = (TJMAX - TA) / JA or the number given in Absolute Maximum Ratings, whichever is lower. Human body model, applicable std. JESD22-A114C. Machine model, applicable std. JESD22-A115-A. Operating Ratings (1) (2) Temperature Range (TMIN TA TMAX) -40C TA +85C 2.7V AVDD 5.5V 2.7V DVDD 4.0V Supply Voltage 1.7V I2C_VDD 4.0V 1.7V I/O_VDD 4.0V (1) (2) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All voltages are measured with respect to the ground pin, unless otherwise specified. The Electrical Characteristics tables list specified specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not ensured. Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LM49321 LM49321RLEVAL Submit Documentation Feedback 5 LM49321, LM49321RLEVAL SNAS457C - SEPTEMBER 2008 - REVISED MAY 2013 www.ti.com Audio Amplifier Electrical Characteristics AVDD = 3.0V, DVDD = 3.0V (1) (2) The following specifications apply for the circuit shown in Figure 41 with all programmable gain set at 0dB, unless otherwise specified. Limits apply for TA = 25C. IDD LM49321 Typ (3) Limits (4) Units (Limits) VIN = 0, No Load All Amps On + DAC, OCL (5) 13 18 mA (max) Headphone Mode Only, OCL, DAC off 4.6 6.25 mA (max) Headphone Mode Only, OCL, DAC Off STEREO_OUTPUT_ONLY = 1, STEREO_INPUT_ONLY = 1 4 5.5 mA Headphone Mode only OCL, DAC On, OSR = 64, DAC_INPUT_ONLY = 1 STEREO_OUTPUT_ONLY = 1 7.5 10 mA (max) Mono Loudspeaker Mode Only 6.5 11.5 mA (max) 3.7 3.3 5 mA (max) mA DAC Off, All Amps On (OCL) (5) 10 13.5 mA (max) See (6) 0.6 1 A (max) Speaker; THD = 1%; f = 1kHz, 8 BTL 420 370 mW (min) Headphone; THD = 1%; f = 1kHz, 32 SE 27 24 mW (min) Earpiece; THD = 1%; f = 1kHz, 32 BTL 45 40 mW (min) 2.4 VRMS Speaker; PO = 200mW; f = 1kHz, 8 BTL 0.04 % Headphone; PO = 10mW; f = 1kHz, 32 SE 0.01 % Earpiece; PO = 20mW; f = 1kHz, 32 BTL 0.04 Parameter Test Conditions Supply Current Mono Earpiece Speaker Mode Only MONO_ONLY = 1 (register 01h) MONO_ONLY = 0 ISD Shutdown Current PO Output Power VFS DAC THD+N VOS Full Scale DAC Output Total Harmonic Distortion+Noise Offset Voltage % Speaker 10 55 mV (max) Earpiece 8 50 mV (max) Headphone (OCL) 8 15 mV (max) O Output Noise A-weighted; 0dB gain Table 1 PSRR Power Supply Rejection Ratio f = 217Hz; VRIPPLE = 200mVP-P, CB = 2.2F Table 2 XTALK Crosstalk Headphone; PO = 10mW, f = 1kHz; OCL -60 dB TWU Wake-Up Time CB = 2.2F, CD_6 = 0 35 ms CB = 2.2F, CD_6 = 1 85 ms CMRR Common-Mode Rejection Ratio f = 217Hz, VRMS = 200mVPP 56 dB (1) (2) (3) (4) (5) (6) 6 Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All voltages are measured with respect to the ground pin, unless otherwise specified. The Electrical Characteristics tables list specified specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not ensured. Typical values represent most likely parametric norms at TA = +25C, and at the Recommended Operation Conditions at the time of product characterization and are not ensured. Datasheet min/max specification limits are ensured by test or statistical analysis. Enabling mono bit (MONO_ONLY in Output Control Register 01h) will save 400A (typ) form specified current. Shutdown current is measured in a normal room environment. Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LM49321 LM49321RLEVAL LM49321, LM49321RLEVAL www.ti.com SNAS457C - SEPTEMBER 2008 - REVISED MAY 2013 Audio Amplifier Electrical Characteristics AVDD = 5.0V, DVDD = 3.3V (1) (2) The following specifications apply for the circuit shown in Figure 41 with all programmable gain set at 0dB, unless otherwise specified. Limits apply for TA = 25C. Parameter IDD Test Conditions Supply Current PO VFS Output Power DAC THD+N mA (max) Headphone Mode Only, OCL, DAC Off 5.8 mA (max) Headphone Mode Only, OCL, DAC Off STEREO_OUTPUT_ONLY = 1, STEREO_INPUT_ONLY = 1 5.5 mA Headphone Mode Only, OCL, DAC On, OSR = 64, DAC_INPUT_ONLY = 1 STEREO_OUTPUT_ONLY = 1 9.5 mA Mono Loudspeaker Mode Only (5) 11.6 mA 5 mA 12.9 mA VOS (5) See (6) 1.6 A Speaker; THD = 1%; f = 1kHz, 8 BTL 1.25 mW Headphone; THD = 1%; f = 1kHz, 32 SE 80 mW Earpiece; THD = 1%; f = 1kHz, 32 BTL 175 mW 2.4 VRMS Speaker; PO = 500mW; f = 1kHz, 8 BTL 0.03 % Headphone; PO = 30mW; f = 1kHz, 32 SE 0.01 % Earpiece; PO = 40mW; f = 1kHz, 32 BTL 0.04 % Speaker 10 mV Earpiece 8 mV HP (OCL) 8 mV Full Scale DAC Output Total Harmonic Distortion + Noise Offset Voltage Units (Limits) 17.5 DAC Off, All Amps On (OCL) Shutdown Current Limits (4) VIN = 0, No Load All Amps On + DAC, OCL (5) Mono Earpiece Mode Only (5) ISD LM49321 Typ (3) O Output Noise A-weighted; 0dB gain; Table 1 PSRR Power Supply Rejection Ratio f = 217Hz; Vripple = 200mVP-P, CB = 2.2F Table 3 XTALK Crosstalk Headphone; PO= 15mW, f = 1kHz; OCL -56 dB CB = 2.2F, CD_6 = 0 45 ms CB = 2.2F, CD_6 = 1 130 ms TWU (1) (2) (3) (4) (5) (6) Wake-Up Time Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All voltages are measured with respect to the ground pin, unless otherwise specified. The Electrical Characteristics tables list specified specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not ensured. Typical values represent most likely parametric norms at TA = +25C, and at the Recommended Operation Conditions at the time of product characterization and are not ensured. Datasheet min/max specification limits are ensured by test or statistical analysis. Enabling mono bit (MONO_ONLY in Output Control Register 01h) will save 400A (typ) form specified current. Shutdown current is measured in a normal room environment. Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LM49321 LM49321RLEVAL Submit Documentation Feedback 7 LM49321, LM49321RLEVAL SNAS457C - SEPTEMBER 2008 - REVISED MAY 2013 www.ti.com Volume Control Electrical Characteristics (1) (2) The following specifications apply for 3.0V AVDD 5.0V and 2.7V DVDD 4.0V, unless otherwise specified. Limits apply for TA = 25C. Parameter LM49321 Test Conditions Typ (3) Minimum gain setting -6 Maximum gain setting 15 Minimum gain setting -12 Maximum gain setting 9 Stereo Analog Inputs Pre-Amp Gain Setting Range PGR Differential Mono Analog Input PreAmp Gain Setting Range Output Volume Control for Loudspeaker, Headphone Output, or Earpiece Output VCR ACH-CH Stereo Channel to Channel Gain Mismatch AMUTE Mute Attenuation RINPUT DIFF+, DIFF-, LIN and RIN Input Impedance (1) (2) (3) (4) 8 Minimum gain setting -56 Maximum gain setting +5 VIN = 1VRMS, Gain = 0dB with load, Headphone Limits (4) Units (Limits) -7 dB (min) -5 dB (max) 15.5 dB (max) 14.5 dB (min) -13 dB (min) -11 dB (max) 9.5 dB (max) 8.5 dB (min) -59 dB (min) -53 dB (max) 4.5 dB (min) 5.5 dB (max) 0.3 dB -90 dB 23 18 k (min) 28 k (max) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All voltages are measured with respect to the ground pin, unless otherwise specified. The Electrical Characteristics tables list specified specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not ensured. Typical values represent most likely parametric norms at TA = +25C, and at the Recommended Operation Conditions at the time of product characterization and are not ensured. Datasheet min/max specification limits are ensured by test or statistical analysis. Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LM49321 LM49321RLEVAL LM49321, LM49321RLEVAL www.ti.com SNAS457C - SEPTEMBER 2008 - REVISED MAY 2013 Digital Section Electrical Characteristics (1) (2) The following specifications apply for 3.0V AVDD 5.0V and 2.7V DVDD 4.0V, unless otherwise specified. Limits apply for TA = 25C. Parameter DISD LM49321 Test Conditions Typ (3) Limits (4) Units (Limits) Mode 0, DVDD = 3.0V Digital Shutdown Current A No MCLK 0.01 5.3 6.5 mA (max) 4.8 6 mA (max) DIDD Digital Power Supply Current fMCLK = 12MHz, DVDD = 3.0V ALL MODES EXCEPT 0 PLLIDD PLL Quiescent Current fMCLK = 12MHz, DVDD = 3.0V Audio DAC (Typical numbers are with 6.144MHz audio clock and 48kHz sampling frequency RDAC Audio DAC Ripple 20Hz - 20kHz through headphone output PBDAC Audio DAC Passband width -3dB point SBADAC Audio DAC Stop band Attenuation Above 24kHz DRDAC Audio DAC Dynamic Range SNR Audio DAC-AMP Signal to Noise Ratio SNRDAC Internal DAC SNR +/-0.1 dB 22.6 kHz 76 dB DC - 20kHz, -60dBFS; AES17 Standard Table 4 dB A-Weighted, Signal = VO at 0dBFS, f = 1kHz Noise = digital zero, A-weighted Table 4 dB 95 dB A-weighted (5) PLL fIN Input Frequency on MCLK pin 12 10 26 MHz SPI/I2C (1.7V I2C_VDD 2.2V) fSPI Maximum SPI Frequency 1000 kHz (max) tSPISETD SPI Data Setup Time 250 ns (max) tSPISETENB SPI ENB Setup Time 250 ns (max) tSPIHOLDD SPI Data Hold Time 250 ns (max) tSPIHOLDENB SPI ENB Hold Time 250 ns (max) tSPICL SPI Clock Low Time 500 ns (max) tSPICH SPI Clock High Time 500 ns (max) 2 fCLKI2C I C_CLK Frequency 400 kHz (max) tI2CHOLD I2C_DATA Hold Time 250 ns (max) tI2CSET I2C_DATA Setup Time 250 ns (max) VIH I2C/SPI Input High Voltage I2C_VDD 0.7 x I2C_VDD V (min) VIL I2C/SPI Input Low Voltage 0 0.25 x I2C_VDD V (max) SPI/I2C (2.2V I2C_VDD 4.0V) fSPI Maximum SPI Frequency 4000 kHz (max) tSPISETD SPI Data Setup Time 100 ns (max) tSPISETENB SPI ENB Setup Time 100 ns (max) tSPIHOLDD SPI Data Hold Time 100 ns (max) tSPIHOLENB SPI ENB Hold Time 100 ns (max) (1) (2) (3) (4) (5) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All voltages are measured with respect to the ground pin, unless otherwise specified. The Electrical Characteristics tables list specified specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not ensured. Typical values represent most likely parametric norms at TA = +25C, and at the Recommended Operation Conditions at the time of product characterization and are not ensured. Datasheet min/max specification limits are ensured by test or statistical analysis. Internal DAC only with DAC modes 00 and 01. Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LM49321 LM49321RLEVAL Submit Documentation Feedback 9 LM49321, LM49321RLEVAL SNAS457C - SEPTEMBER 2008 - REVISED MAY 2013 www.ti.com Digital Section Electrical Characteristics(1)(2) (continued) The following specifications apply for 3.0V AVDD 5.0V and 2.7V DVDD 4.0V, unless otherwise specified. Limits apply for TA = 25C. Parameter LM49321 Test Conditions Typ (3) Limits (4) Units (Limits) ns (max) tSPICL SPI Clock Low Time 125 tSPICH SPI Clock High Time 125 ns (max) fCLKI2C I2C_CLK Frequency 400 kHz (max) tI2CHOLD I2C_DATA Hold Time 100 ns (max) 2 tI2CSET I C_DATA Setup Time 100 ns (max) V (min) VIH I C/SPI Input High Voltage I C_VDD 0.7 x I2C_VDD VIL I2C/SPI Input Low Voltage 0 0.3 x I2C_VDD V (max) 1536 3072 6144 12288 kHz (max) kHz (max) 50 40 60 % (min) % (max) 2 2 2 I S(1.7V I/O_VDD 2.7V) I2S_RESOLUTION = 1 I2S_RESOLUTION = 0 I2S_CLK Frequency fCLKI2S I2S_WS Duty Cycle VIH Digital Input High Voltage 0.75 x I/O_VDD V (min) VIL Digital Input Low Voltage 0.25 x I/O_VDD V (max) I2S(2.7V I/O_VDD 4.0V) I2S_CLK Frequency I2S_RESOLUTION = 0 1536 3072 6144 12288 kHz (max) kHz (max) I2S_WS Duty Cycle I2S_RESOLUTION = 1 50 40 60 % % fCLKI S 2 VIH Digital Input High Voltage 0.7 x I/O_VDD V (min) VIL Digital Input Low Voltage 0.3 x I/O_VDD V (max) Table 1. Output Noise AVDD = 5.0V and AVDD = 3.0V. All gains set to 0dB. Units in V, A-weighted, Inputs terminated to ground. MODE EP LS HP OCL Units 1 22 22 8 V 2 22 22 8 V 3 22 22 8 V 4 68 88 46 V 5 38 48 24 V 6 29 34 18 V 7 38 48 24 V Table 2. VPSRR AVDD = 3.0V, fRIPPLE = 217Hz; VRIPPLE = 200mVP-P; CB = 2.2F; All gains set to 0dB. 10 MODE EP(Typ) LS (Typ) 1 69 76 2 69 76 3 69 76 72 dB 4 63 62 55 dB 5 69 68 61 dB 6 69 70 64 dB 7 69 68 61 dB Submit Documentation Feedback LS (Limit) HP (Typ) HP (Limit) 72 67 Units dB 72 68 dB Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LM49321 LM49321RLEVAL LM49321, LM49321RLEVAL www.ti.com SNAS457C - SEPTEMBER 2008 - REVISED MAY 2013 Table 3. PSRR AVDD = 5.0V, fRIPPLE = 217Hz; VRIPPLE = 200mVP-P; CB = 2.2F; All gains set to 0dB. MODE EP (Typ) LS (Typ) HP (Typ) Units 1 68 72 71 dB 2 68 72 71 dB 3 68 72 71 dB 4 68 66 69 dB 5 68 69 70 dB 6 69 72 71 dB 7 68 69 70 dB Table 4. Dynamic Range and SNR. 3.0V AVDD 5.0V. All programmable gain set to 0dB. Units in dB. DR (Typ) SNR (Typ) Units LS 95 85 dB HP 95 85 dB EP 97 85 dB System Control The LM49321 is controlled via either a two wire I2C compatible interface or three wire SPI interface, selectable with the MODE pin. This interface is used to configure the operating mode, interfaces, data converters, mixers and amplifiers. The LM49321 is controlled by writing 8 bit data into a series of write-only registers, the device is always a slave for both type of interfaces. THREE WIRE, SPI INTERFACE (MODE = 1) Three Wire Mode Write Bus Transaction ENB SCK SDI 7 0 7 0 Register Address Data Three Wire Mode Write Bus Timing TSPISETENB TSPIHOLDENB ENB TSPICL TSPIT SCK TSPICH SDI TSPISETD TSPIHOLDD Figure 4. Three Wire Mode Write Bus When the part is configured as an SPI device and the enable (ENB) line is lowered the serial data on SDI is clocked in on the rising edge of the SCK line. The protocol used is 16bit, MSB first. The upper 8 bits (15:8) are used to select an address within the device, the lower 8 bits (7:0) contain the updated data for this register. Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LM49321 LM49321RLEVAL Submit Documentation Feedback 11 LM49321, LM49321RLEVAL SNAS457C - SEPTEMBER 2008 - REVISED MAY 2013 www.ti.com TWO WIRE I2C COMPATIBLE INTERFACE (MODE = 0) Two Wire Mode Write Bus Transaction SDA SCL 6-0 S Start Condition Host Address 7-1 W ACK 0 7-1 ACK Register Address 0 Data P ACK Stop Condition Two Wire Mode Write Bus Timing SDA TI2CSET TI2CSET TI2CHOLD TI2CSET SCL Start Condition Data ACK Stop Condition Figure 5. Two Wire Mode Write Bus When the part is configured as an I2C device then the LM49321 will respond to one of two addresses, according to the ADDR input. If ADDR is low then the address portion of the I2C transaction should be set to write to 0010000. When ADDR is high then the address input should be set to write to 1110000. Table 5. Chip Address A7 A6 A5 A4 A3 A2 A1 A0 Chip Address 0 EC EC 1 0 0 0 0 ADR = 0 0 0 0 1 0 0 0 0 ADR = 1 0 1 1 1 0 0 0 0 EC -- Externally configured by ADR pin 12 Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LM49321 LM49321RLEVAL LM49321, LM49321RLEVAL www.ti.com SNAS457C - SEPTEMBER 2008 - REVISED MAY 2013 Table 6. Control Registers Address Register D7 D6 0 D5 0 D3 D2 00h MODE_CONTROL 01h OUTPUT_ CONTROL 02h EP_VOL 0 0 0 03h LS_VOL 0 0 0 04h RESERVED 0 0 0 05h HP_L_VOL 0 0 0 HP_L_VOL 06h HP_R_VOL 0 0 0 HP_R_VOL 07h ANALOG_INPUT _GAIN 0 0 08h ANALOG_DAC _GAIN 09h CLOCKS 0Ah PLL_M STEREO_ OUT_ONL Y CD_6 D4 MONO_ONLY 0 OCL DAC_INPUT_ ONLY D1 D0 MODE_CONTROL STEREO_INPUT_ ONLY HP_R_ OUTPUT HP_L_ OUTPUT LS_ OUTPUT MONO_ OUTPUT 0 0 EP_VOL LS_VOL 0 0 0 ANA_R_GAIN DAC_R_GAIN ANA_L_GAIN DAC_L_GAIN PLL_ ENABLE R_DIV 0 MONO_L_GAIN AUDIO _CLK_SEL PLL_INPUT FAST_ CLOCK PLL_M 0Bh PLL_N 0Ch PLL_N_MOD VCO_FAS T 0Dh PLL_P 0 0Eh DAC_SET UP 0 0Fh INTERFACE 0 DITHER_LEVEL 0 CUST_COMP 0 DITHER_LEVEL 0 PLL_N_MOD 0 DITHER_ALW_ON DITHER_OFF 0 0 PLL_P MUTE_R MUTE_L DAC_MODE I2C_FAST I2S_MODE I2S_ RESOLUTION 10h COMPENSATION _C OEFF0_LSB 11h COMPENSATION _C OEFF0_MSB 12h COMPENSATION _C OEFF1_LSB 13h COMPENSATION _C OEFF1_MSB 14h COMPENSATION _C OEFF2_LSB 15h COMPENSATION _C OEFF2_MSB I2S_MASTER_ SLAVE Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LM49321 LM49321RLEVAL 13 LM49321, LM49321RLEVAL SNAS457C - SEPTEMBER 2008 - REVISED MAY 2013 www.ti.com Mixer Control Registers This register is used to control the different mixer modes that the LM49321 supports. Table 7. Mode Control Register (00h) (1) Bits Field 3:0 MODE _CONTROL Description This sets the different mixer output modes. MODE_CONTROL Mode Mono Earpiece Loudspeaker Headphone Left Headphone Right 0000 0 SD SD SD SD 1001 1 M M M M 1010 2 AL+AR AL+AR AL AR 1011 3 M+AL+AR M+AL+AR M+AL M+AR 1100 4 DL+DR DL+DR DL DR 1101 5 DL+DR+AL+AR DL+DR+AL+AR DL+AL DR+AR M+DL+AL M+DR+AR M+DL M+DR 1110 6 1111 4 (1) OCL 7 M+DL+DR+AL+AR M+DL+DR+AL+A R M+DL+DR M+DL+DR This sets the headphone output to use output capacitor-less configuration. OCL Headphone output configuration 0 Cap-coupled Single-ended Mode (SE) 1 Output capacitor-less (OCL) SD -- Shutdown M -- Mono Differential Input AL -- Analog Left Channel AR -- Analog Right Channel DL -- I2S DAC Left Channel DR -- I2S DAC Right Channel Note: Power-On Default Mode is Mode 0 This register is used to control the different output configurations. Table 8. Output Control (01h) Bits Field 0 EP_OUTPUT 1 2 3 14 LS_OUTPUT HP_L_OUTPUT HP_R_OUTPUT Submit Documentation Feedback Description This enables the Mono Earpiece output. EP_OUTPUT Status 0 Mono earpice output off 1 Mono earpice output on This enables the Mono Loudspeaker output. LS_OUTPUT Status 0 Loudspeaker output off 1 Loudspeaker output on This enables the Headphone left output. HP_L_OUTPUT Status 0 Headphone left output off. If OCL=1, output is in mute. 1 Headphone left output on This enables the Headphone right output. HP_R_OUTPUT Status 0 Headphone right output off. If OCL=1, output is in mute. 1 Headphone right output on Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LM49321 LM49321RLEVAL LM49321, LM49321RLEVAL www.ti.com SNAS457C - SEPTEMBER 2008 - REVISED MAY 2013 Table 8. Output Control (01h) (continued) Bits Field 4 STEREO_INPUT_ONLY 5 6 Description DAC_INPUT_ONLY MONO_ONLY This enables the analog left (AL) and analog right (AR) and disables all other inputs. STEREO_INPUT_ONLY Status 0 Normal 1 Enables AL and AR inputs only This enables the DAC left (DL) and analog right (DR) and disables all other inputs. DAC_INPUT_ONLY Status 0 Normal 1 Enables DL and DR inputs only This enables mono earpiece (EP) and loudspeaker (LS) outputs MUX and disables the headphone outputs MUX. Enabling this mode can save up to 400A of current. MONO_ONLY 7 STEREO_OUTPUT_ONLY Status 0 Normal 1 Enable mono earpiece and loudspeaker outputs MUX This enables the headphone output MUX only and disables all other output MUX's. Enabling this mode can save up to 200A of current. STEREO_OUTPUT_ONLY Status 0 Normal 1 Enables the headphone output MUX Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LM49321 LM49321RLEVAL Submit Documentation Feedback 15 LM49321, LM49321RLEVAL SNAS457C - SEPTEMBER 2008 - REVISED MAY 2013 www.ti.com Volume Control Registers These registers are used to control output volume control levels for Earpiece, Loudspeaker and Headphone. Table 9. Volume Control Register EP_VOL (02h), LS_VOL (03h), HP_L_VOL (05h), HP_R_VOL (06h) 16 Bits Field Description 4:0 EP_VOL LS_VOL HP_L_VOL HP_R_VOL This programs the Earpiece, Loudspeaker and Headphone volume level. Submit Documentation Feedback VOL Level (dB) 00000 MUTE 00001 -56 00010 -52 00011 -48 00100 -45 00101 -42 00110 -39 00111 -36 01000 -33 01001 -30 01010 -28 01011 -26 01100 -24 01101 -22 01110 -20 01111 -18 10000 -16 10001 -14 10010 -12 10011 -10 10100 -8 10101 -6 10110 -4 10111 -3 11000 -2 11001 -1 11010 0 11011 1 11100 2 11101 3 11110 4 11111 5 Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LM49321 LM49321RLEVAL LM49321, LM49321RLEVAL www.ti.com SNAS457C - SEPTEMBER 2008 - REVISED MAY 2013 This register is used to control input gain for left and right analog inputs. Table 10. Analog Left and Right Input Control (07h) Bits Field 2:0 ANA_L_GAIN 5:3 Description ANA_R_GAIN This program the analog left input gain. ANA_L_GAIN Level (dB) 000 -6 001 -3 010 0 011 3 100 6 101 9 110 12 111 15 This program the analog Right input gain. ANA_R_GAIN Level (dB) 000 -6 001 -3 010 0 011 3 100 6 101 9 110 12 111 15 This register is sued to control input gain for Mono, DAC left and right inputs. Table 11. Mono and DAC Input Gain Control (08h) Bits Field 2:0 MONO_IN_GAIN 4:3 DAC_L_GAIN Description This program the mono input gain. MONO_IN_GAIN Level (dB) 000 -12 001 -9 010 -6 011 -3 100 0 101 3 110 6 111 9 This program the DAC left input gain. DAC_L_GAIN Level (dB) 00 -3 01 0 10 3 11 6 Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LM49321 LM49321RLEVAL Submit Documentation Feedback 17 LM49321, LM49321RLEVAL SNAS457C - SEPTEMBER 2008 - REVISED MAY 2013 www.ti.com Table 11. Mono and DAC Input Gain Control (08h) (continued) Bits Field 6:5 DAC_R_GAIN Description This program the DAC Right input gain. DAC_R_GAIN Level (dB) 00 -3 01 0 10 3 11 6 Clock Configuration Register This register is used to control the multiplexers and clock R divider in the clock module. Table 12. CLOCK (09h) Bits Register 0 FAST_CLOCK Description If set master clock is divided by two. FAST_CLOCK 1 PLL_INPUT MCLK Frequency 0 Normal 1 Divided by 2 Programs the PLL input multiplexer to select: PLL_INPUT PLL Input Source 0 MCLK 2 1 2 AUDIO_CLK_SEL I S Input Clock Selects which clock is passed to the audio sub-system DAC_CLK_SEL 18 3 PLL_ENABLE 7:4 R_DIV Submit Documentation Feedback DAC Sub-system Input Source 0 PLL Input 1 PLL Output If set enables the PLL. (MODES 4-7 only) Programs the R divider R_DIV Divide Value 0000 1 0001 1 0010 1.5 0011 2 0100 2.5 0101 3 0110 3.5 0111 4 1000 4.5 1001 5 1010 5.5 1011 6 1100 6.5 1101 7 1110 7.5 1111 8 Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LM49321 LM49321RLEVAL LM49321, LM49321RLEVAL www.ti.com SNAS457C - SEPTEMBER 2008 - REVISED MAY 2013 fast_clock %2 MCLK audio_dk_sel pll_input 1 0 0 1 0 1 PLL PLL input clock PLL output clock I S_INT_CLK I2S_INPUT_CLK I S_CLK 2 I S Interface %R Clock Gen input clock DAC Clock Gen 2 2 R Div input clock Stereo DAC 125/128 DSP CLK 2 I S_OUTPUT_CLK By default the stereo DAC operates at 250*fs, i.e. 12.000MHz (at the clock generator input clock) for 48kHz data. It is expected that the PLL be used to drive the audio system unless a 12.000MHz master clock is supplied. The PLL can also use the I2S clock input as a source. In this case, the audio DAC uses the clock from the output of the PLL. Common Clock Settings for the DAC The DAC can work in 4 modes, each with different oversampling rates, 125,128,64 and 32. In normal operation 125x oversampling provides for the simplest clocking solution as it will work from 12.000MHz (common in most systems with Bluetooth or USB) at 48kHz exactly. The other modes are useful if data is being provided to the DAC from an uncontrollable isochronous source (such as a CD player, DAB, or other external digital source) rather than being decoded from memory. In this case the PLL can be used to derive a clock for the DAC from the I2S clock. The DAC oversampling rate can be changed to allow simpler clocking strategies, this is controlled in the DAC SETUP register but the oversampling rates are as follows: DAC MODE Over sampling Ratio Used 00 125 01 128 10 64 11 32 The following table describes the clock required at the clock generator input for various clock sample rates in the different DAC modes: Required CLock at DAC Clock Generator Input (MHz) Fs (kHz) DAC Oversampling Ratio 8 125 2 8 128 2.048 11.025 125 2.75625 11.025 128 2.8224 12 125 3 12 128 3.072 16 125 4 16 128 4.096 22.05 125 5.5125 22.05 128 5.6448 24 125 6 24 128 6.144 Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LM49321 LM49321RLEVAL Submit Documentation Feedback 19 LM49321, LM49321RLEVAL SNAS457C - SEPTEMBER 2008 - REVISED MAY 2013 www.ti.com Fs (kHz) DAC Oversampling Ratio Required CLock at DAC Clock Generator Input (MHz) 32 125 8 32 128 8.192 44.1 125 11.025 44.1 128 11.2896 48 125 12 48 128 12.288 88.2 64 11.2896 96 64 12.288 176.4 32 22.5792 192 32 24.576 Methods for producing these clock frequencies are described in the PLL section. The R divider can be used when the master clock is exactly 12.00 MHz in order to generate different sample rates. The Table below shows different sample rates supported from 12.00MHz by using only the R divider and disabling the PLL. In this way we can save power and the clock jitter will be low. DAC Clock Generator Input Frequency <MHz> R_DIV Divide Value Sample Rate Supported <KHz> 11 6 2 8 9 5 2.4 9.6 7 4 3 12 5 3 4 16 4 2.5 4.8 19.2 3 2 6 24 2 1.5 8 32 0 1 12 48 The R divider can also be used along with the P divider in order to create the clock needed to support low sample rates. PLL Configuration Registers PLL M DIVIDER CONFIGURATION REGISTER This register is used to control the input divider of the PLL. Table 13. PLL_M (0Ah) (1) Bits 6:0 (1) 20 Register PLL_M Description Programs the PLL input divider to select: PLL_M Divide Ratio 0000000 Divider Off 0000001 1 0000010 1.5 0000011 2 0000100 2.5 ... ... 1111110 63.5 The M divider should be set such that the output of the divider is between 0.5 and 5MHz. See the PLL setup section for details. The division of the M divider is derived from PLL_M as such: M = (PLL_M+1) / 2 Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LM49321 LM49321RLEVAL LM49321, LM49321RLEVAL www.ti.com SNAS457C - SEPTEMBER 2008 - REVISED MAY 2013 PLL N DIVIDER CONFIGURATION REGISTER This register is used to control PLL N divider. Table 14. PLL_N (0Bh) (1) (1) Bits Register 7:0 PLL_N Description Programs the PLL feedback divider: PLL_N Divide Ratio 00000000 Divider Off 00000001 00001010 10 00001011 11 00001100 12 ... ... 11111000 248 11111001 249 The N divider should be set such that the output of the divider is between 0.5 and 5MHz. See the PLL setup section for details. The N divider should never be set so that (Fin/M) * N > 55MHz (or 80MHz if FAST_VCO is set in the PLL_N_MOD register). The non-sigma-delta division of the N divider is derived from the PLL_N as such: N = PLL_N Fin /M is often referred to as Fcomp (Frequency of Comparison) or Fref (Reference Frequency). In this document, Fcomp is used PLL P DIVIDER CONFIGURATION REGISTER This register is used to control the PLL's P divider. Table 15. PLL_P (1) Bits Register 3:0 PLL_P Description Programs the PLL input divider to select: 0000 (1) Divider Off 0001 1 0010 1.5 0011 2 ... -> 2.5 1101 7 1110 7.5 1111 8 The output of this divider should be either 12 or 24MHz in USB mode or 11.2896MHz, 12.288MHz or 24.576MHz in non-USB modes. The division of the P divider is derived from PLL_P as such: P = (PLL_P+1) / 2 Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LM49321 LM49321RLEVAL Submit Documentation Feedback 21 LM49321, LM49321RLEVAL SNAS457C - SEPTEMBER 2008 - REVISED MAY 2013 www.ti.com PLL N MODULATOR AND DITHER SELECT CONFIGURATION REGISTER This register is used to control the Fractional component of the PLL. Table 16. PLL_N_MOD (0Ch) (1) Bits Register 4:0 PLL_N_MOD 6:5 DITHER_LEVEL 7 (1) Description This programs the PLL N Modulator's fractional component: PLL_N_MOD Fractional Addition 00000 0/32 00001 1/32 00010 11110 2/32 30/32 Allows control over the dither used by the N Modulator VCO_FAST DITHER_LEVEL DAC Sub-system Input Source 00 Medium (32) 01 Small (16) 10 Large (48) If set the VCO maximum and minimum frequencies are raised: VCO_FAST Maximum FVCO 0 40-55MHz The complete N divider is a fractional divider as such: N = PLL_N + (PLL_N_MOD/32) If the modulus input is zero, then the N divider is simply an integer N divider. The output from the PLL is determined by the following formula: Fout = (Fin * N) / (M * P) Please see over for more details on the PLL and common settings. Further Notes on PLL Programming The sigma-delta PLL is designed to drive audio circuits requiring accurate clock frequencies of up to 25MHz with frequency errors noise-shaped away from the audio band. The 5 bits of modulus control provide exact synchronization of 48kHz and 44.1kHz sample rates from any common clock source when the oversampling rate of the audio system is 125fs. In systems where 128x oversampling must be used (for example with an isochronous I2S data stream) a clock synchronous to the sample rate should be used as input to the PLL (typically the I2S clock). If no isochronous source is available then the PLL can be used to obtain a clock that is accurate to within typical crystal tolerances of the real sample rate. PLL_P M = 0, 1 + 0/2 0.5 - 26 MHz %M 4 64 Phase Comparator and Charge Pump VCO 0 256 x FS OR 250 x FS 40 to 80 MHz %P 0.5 < 5 MHz P = 0, 1 + 0/2 8 External Loop Filter 7 PLL_M %N 6'M 8 N = 0, 1, 2, .., 255 8 5 PLL_N PLL_N_MOD 22 Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LM49321 LM49321RLEVAL LM49321, LM49321RLEVAL www.ti.com SNAS457C - SEPTEMBER 2008 - REVISED MAY 2013 Table 17. Example Of PLL Settings For 48Khz Sample Rates f_in (MHz) fsamp (kHz) M N P PLL_M PLL_N PLL_N_MOD PLL_P f_out (MHz) 11 48 11 60 5 21 60 0 9 12 12 48 5 25 5 9 25 0 9 12 12.288 48 4 19.53125 5 7 19 17 9 12 13 48 13 60 5 25 60 0 9 12 14.4 48 9 37.5 5 17 37 16 9 12 16.2 48 27 100 5 53 100 0 9 12 16.8 48 14 50 5 27 50 0 9 12 19.2 48 13 40.625 5 25 40 20 9 12 19.44 48 27 100 6 53 100 0 11 12 19.68 48 20.5 62.5 5 40 62 16 9 12 19.8 48 16.5 50 5 32 50 0 9 12 Table 18. Example PLL Settings For 44.1Khz Sample Rates f_in (MHz) fsamp (kHz) M N P PLL_M PLL_N PLL_N_MOD PLL_P f_out (MHz) 11 44.1 11 55.125 5 21 55 4 9 11.025000 11.2896 44.1 8 39.0625 5 15 39 2 9 11.025000 12 44.1 5 22.96875 5 9 22 31 9 11.025000 13 44.1 13 55.125 5 25 55 4 9 11.025000 14.4 44.1 12 45.9375 5 23 45 30 9 11.025000 16.2 44.1 9 30.625 5 17 30 20 9 11.025000 16.8 44.1 17 55.78125 5 33 55 25 9 11.025000 19.2 44.1 16 45.9375 5 31 45 30 9 11.025000 19.44 44.1 13.5 38.28125 5 26 38 9 9 11.025000 19.68 44.1 20.5 45.9375 4 40 45 30 7 11.025000 19.8 44.1 11 30.625 5 21 30 20 9 11.025000 These tables cover the most common applications, obtaining clocks for sample rates such as 22.05kHz and 192kHz should be done by changing the P divider value or the R divider in the clock configuration diagram. If the user needs to obtain a clock unrelated to those described above, the following method is advised. An example of obtaining 11.2896 from 12.000MHz is shown below. Choose a small range of P so that the VCO frequency is swept between 45 and 55MHz (or 60-80MHz if VCOFAST is used). Remembering that the P divider can divide by half integers. So for P = 4.0 7.0 sweep the M inputs from 2.5 24. The most accurate N and N_MOD can be calculated by: N = FLOOR(((Fout/Fin)*(P*M)),1) N_MOD = ROUND(32*((((Fout)/Fin)*(P*M)-N),0) This shows that setting M = 11.5, N = 75 N_MOD = 47 P = 7 gives a comparison frequency of just over 1MHz, a VCO frequency of just under 80MHz (so VCO_FAST must be set) and an output frequency of 11.289596 which gives a sample rate of 44.099985443kHz, or accurate to 0.33 ppm. Care must be taken when synchronization of isochronous data is not possible, i.e. when the PLL has to be used in the above mode. The I2S should be master on the LM49321 so that the data source can support appropriate SRC as required. This method should only be used with data being read on demand to eliminate sample rate mismatch problems. Where a system clock exists at an integer multiple of the required DAC clock rate it is preferable to use this rather than the PLL. The LM49321 is designed to work in 8,12,16,24,32, and 48kHz modes from a 12MHz clock without the use of the PLL. This saves power and reduces clock jitter. Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LM49321 LM49321RLEVAL Submit Documentation Feedback 23 LM49321, LM49321RLEVAL SNAS457C - SEPTEMBER 2008 - REVISED MAY 2013 www.ti.com DAC Setup Register This register is used to configure the basic operation of the stereo DAC. Table 19. DAC_SETUP (0Eh) Bits Register 1:0 DAC_MODE Description The DAC used in the LM49321 can operate in one of 4 oversampling modes. The modes are described as follows: DAC_MODE Oversampling Rate Typical fS MCLK Required 00 125 48KHz 12.000MHz (USB Mode) 01 128 44.1KHz 48KHz 11.2896MHz 12.288MHz 10 64 96KHz 12.288MHz 11 32 192KHz 24.576MHz 2 MUTE_L Mutes the left DAC channel on the next zero crossing. 3 MUTE_R Mutes the right DAC channel on the next zero crossing. 4 DITHER_OFF If set the dither in DAC is disabled. 5 DITHER ALWAYS_ON If set the dither in DAC is enabled all the time. 6 CUST_COMP If set the DAC frequency response can be programmed manually via a 5 tap FIR "compensation" filter. This can be used to enhance the frequency response of small loudspeakers or provide a crude tone control. The compensation Coefficients can be set by using registers 10h to 15h. Interface Control Register This register is used to control the I2S and I2C compatible interface on the chip. Table 20. INTERFACE (0Fh) (1) Bits 0 1 2 Field I2S_MASTER_SLAVE I2S_RESOLUTION 2 I S_MODE Description This enables I2S in master or slave mode. I2S_MASTER_SLAVE Comments 0 LM49321 acts as a slave where both I2S clock and word select are configured as inputs. 1 LM49321 acts as a master for I2S, so both I2S clock and I2S word select are configured as outputs. This set the I2S resolution and affects the I2S Interface in master mode. In slave mode the I2S Interface can support any I2 S compatible resolution. In master mode the I2S resolution also depends on the DAC mode as the note below explains. I2S_RESOLUTION Comments 0 I2S resolution is set to 16 bits. 1 I2S resolution is set to 32 bits. 2 This set the I S mode timing. I2S_MODE Comments 2 (1) 24 0 I S interface is configured in normal I2S mode timing. 1 I2S is configured in left justified mode timing. The master I2S format depends on the DAC mode. In USB mode the number of bits per word is 25 (i.e. 2.4MHz for a 48kHz sample rate). The duty cycle is 40/60. In non-USB modes the format is 32 or 16 bits per word, depending on I2S_RESOLUTION and the duty cycle is always 50-50. In slave mode it will decode any I2S compatible data stream. Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LM49321 LM49321RLEVAL LM49321, LM49321RLEVAL www.ti.com SNAS457C - SEPTEMBER 2008 - REVISED MAY 2013 Table 20. INTERFACE (0Fh)(1) (continued) Bits Field Description I2C_FAST 3 This set the I2C Clock speed. I2C_FAST LEFT CHANNEL Comments 0 I2C speed gets its default value of a maximum of 400kHz. 1 This enables the I2C to run in fast mode with an I2C clock up to 3.4MHz. RIGHT CHANNEL 2 I S_WS 2 I S_CLK 2 1 I S_SDO 2 3 n-1 MSB n 1 LSB 2 3 n-1 MSB n LSB 2 Figure 6. I S Mode Timing LEFT CHANNEL RIGHT CHANNEL 2 I S_WS 2 I S_CLK 2 I S_SDO 1 2 3 MSB n-1 n 1 LSB MSB 2 3 n-1 n LSB Figure 7. Left Justified Mode Timing FIR Compensation Filter Configuration Registers These registers are used to configure the DAC's FIR compensation filter. Three 16 bit coefficients are required and must be programmed via the I2C/SPI Interface in bytes as follows: Table 21. COMP_COEFF (10h 15h) (1) (1) Address Register Description 10h COMP_COEFF0_LSB Bits [7:0] of the 1st and 5th FIR tap (C0 and C4) 11h COMP_COEFF0_MSB Bits [15:8] of the 1st and 5th FIR tap (C0 and C4) 12h COMP_COEFF1_LSB Bits [7:0] of the 2nd and 4th FIR tap (C1 and C3) 13h COMP_COEFF1_MSB Bits [15:8] of the 2nd and 4th FIR tap (C1 and C3) 14h COMP_COEFF2_LSB Bits [7:0] of the 3rd FIR tap (C2) 15h COMP_COEFF2_MSB Bits [15:8] of the 3rd FIR tap (C2) The filter must be phase linear to ensure the data keeps the correct stereo imaging so the second half of the FIR filter must be the reverse of the 1st half. Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LM49321 LM49321RLEVAL Submit Documentation Feedback 25 LM49321, LM49321RLEVAL SNAS457C - SEPTEMBER 2008 - REVISED MAY 2013 www.ti.com -1 -1 Z C0 -1 Z C1 -1 Z C2 Z C3 C4 If the CUST_COMP option in register 0Eh is not set the FIR filter will use its default values for a linear response from the DAC into the analog mixer, these values are: DAC_OSR C0, C4 C1, C3 C2 00 434 -2291 26984 01, 10, 11 61 -371 25699 If using 96 or 192kHz data then the custom compensation may be required to obtain flat frequency responses above 24kHz. The total power of any custom filter must not exceed that of the above examples or the filters within the DAC will clip. The coefficient must be programmed in 2's complement. 26 Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LM49321 LM49321RLEVAL LM49321, LM49321RLEVAL www.ti.com SNAS457C - SEPTEMBER 2008 - REVISED MAY 2013 Typical Performance Characteristics THD+N vs Frequency AVDD = 3.0V, EP Out, RL = 32, PO = 20mW THD+N vs Frequency AVDD = 3.0V, HP Out, RL = 16, PO = 20mW 10 10 1 THD+N (%) THD+N (%) 1 0.1 0.01 0.001 20 0.1 0.01 100 1k 0.001 20 10k 20k 100 FREQUENCY (Hz) Figure 8. 10 1 1 THD+N (%) THD+N (%) THD+N vs Frequency AVDD = 5.0V, EP, RL = 32, PO = 40mW 10 0.1 0.01 0.1 0.01 100 1k 0.001 20 10k 20k 100 FREQUENCY (Hz) 1k 10k 20k FREQUENCY (Hz) Figure 10. Figure 11. THD+N vs Frequency AVDD = 5.0V, HP Out, RL = 16, PO = 60mW THD+N vs Frequency AVDD = 5.0V, HP Out, RL = 32, PO = 30mW 10 10 1 THD+N (%) 1 THD+N (%) 10k 20k Figure 9. THD+N vs Frequency AVDD = 3.0V, LS Out, RL = 8, PO = 200mW 0.001 20 1k FREQUENCY (Hz) 0.1 0.01 0.001 20 0.1 0.01 100 1k 10k 20k 0.001 20 FREQUENCY (Hz) Figure 12. 100 1k 10k 20k FREQUENCY (Hz) Figure 13. Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LM49321 LM49321RLEVAL Submit Documentation Feedback 27 LM49321, LM49321RLEVAL SNAS457C - SEPTEMBER 2008 - REVISED MAY 2013 www.ti.com Typical Performance Characteristics (continued) THD+N vs Output Power AVDD = 3.0V, EP Out, RL = 16, f = 1kHz 10 10 1 1 THD+N (%) THD+N (%) THD+N vs Frequency AVDD = 5.0V, LS Out, RL = 8, PO = 500mW 0.1 0.01 0.001 20 0.1 0.01 100 1k 0.001 1m 10k 20k Figure 15. THD+N vs Output Power AVDD = 3.0V, EP Out, RL = 32, f = 1kHz THD+N vs Output Power AVDD = 3.0V, HP Out, RL = 16, f = 1kHz 10 10 1 1 0.1 0.001 1m 0.1 0.01 10m 0.001 1m 50m 100m OUTPUT POWER (W) 10m 50m 100m OUTPUT POWER (W) Figure 16. Figure 17. THD+N vs Output Power AVDD = 3.0V, HP Out, RL = 32, f = 1kHz THD+N vs Output Power AVDD = 3.0V, LS Out, RL = 8, f = 1kHz 10 10 1 1 THD+N (%) THD+N (%) 50m 100m Figure 14. 0.01 0.1 0.001 1m 0.1 0.01 0.01 10m 50m 100m 0.001 10m Figure 18. Submit Documentation Feedback 100m 500m OUTPUT POWER (W) OUTPUT POWER (W) 28 10m OUTPUT POWER (W) THD+N (%) THD+N (%) FREQUENCY (Hz) Figure 19. Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LM49321 LM49321RLEVAL LM49321, LM49321RLEVAL www.ti.com SNAS457C - SEPTEMBER 2008 - REVISED MAY 2013 Typical Performance Characteristics (continued) THD+N vs Output Power AVDD = 5.0V, EP Out, RL = 32, f = 1kHz 10 10 1 1 THD+N (%) THD+N (%) THD+N vs Output Power AVDD = 5.0V, EP Out, RL = 16, f = 1kHz 0.1 0.01 0.001 1m 0.1 0.01 10m 0.001 1m 100m 200m 10m Figure 20. Figure 21. THD+N vs Output Power AVDD = 5.0V, HP Out, RL = 16, f = 1kHz THD+N vs Output Power AVDD = 5.0V, HP Out, RL = 32, f = 1kHz 10 10 1 1 0.1 0.01 0.001 1m 0.1 0.01 10m 0.001 1m 100m 200m 10m OUTPUT POWER (W) Figure 23. THD+N vs Output Power AVDD = 5.0V, LS Out, RL = 8, f = 1kHz THD+N vs I2S Level EP Out 10 1 1 THD+N (%) 10 0.1 0.01 0.001 10m 100m 200m OUTPUT POWER (W) Figure 22. THD+N (%) 100m 200m OUTPUT POWER (W) THD+N (%) THD+N (%) OUTPUT POWER (W) 0.1 0.01 100m 2 0.001 1m OUTPUT POWER (W) Figure 24. 10m 100m 1 I2S INPUT LEVEL (FFS) Figure 25. Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LM49321 LM49321RLEVAL Submit Documentation Feedback 29 LM49321, LM49321RLEVAL SNAS457C - SEPTEMBER 2008 - REVISED MAY 2013 www.ti.com Typical Performance Characteristics (continued) 10 THD+N vs I2S Level HP Out THD+N vs I2S Level LS Out 10 1 THD+N (%) THD+N (%) 1 0.1 0.01 0.1 0.01 0.001 1m 10m 100m 0.001 1m 1 10m Figure 26. Figure 27. PSRR vs Frequency AVDD = 3.0V, EP Out Mode 1 PSRR vs Frequency AVDD = 3.0V, EP Out Mode 4 0 -10 -10 -20 -20 -30 -30 PSRR (dB) PSRR (dB) 0 -40 -50 -60 -50 -60 -70 -80 -80 -90 -90 100 1k 10k -100 20 100k 100 FREQUENCY (Hz) Figure 29. PSRR vs Frequency AVDD = 3.0V, HP Out Mode 2 PSRR vs Frequency AVDD = 3.0V, HP Out Mode 4 0 -10 -20 -20 -30 -30 -40 -50 -60 -50 -60 -70 -70 -80 -80 -90 -90 100 1k 10k 100k -100 20 100 1k 10k 100k FREQUENCY (Hz) Figure 30. Submit Documentation Feedback 100k -40 FREQUENCY (Hz) 30 10k Figure 28. -10 -100 20 1k FREQUENCY (Hz) PSRR (dB) PSRR (dB) 0 1 -40 -70 -100 20 100m I2S INPUT LEVEL (FFS) I2S INPUT LEVEL (FFS) Figure 31. Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LM49321 LM49321RLEVAL LM49321, LM49321RLEVAL www.ti.com SNAS457C - SEPTEMBER 2008 - REVISED MAY 2013 Typical Performance Characteristics (continued) 0 -10 -10 -20 -20 -30 -30 PSRR (dB) PSRR (dB) 0 PSRR vs Frequency AVDD = 3.0V, LS Out Mode 2 -40 -50 -60 -40 -50 -60 -70 -70 -80 -80 -90 -90 -100 20 -100 20 100 1k 10k 100k PSRR vs Frequency AVDD = 3.0V, LS Out Mode 4 100 FREQUENCY (Hz) Figure 33. PSRR vs Frequency AVDD = 5.0V, HP Out Mode 2 PSRR vs Frequency AVDD = 5.0V, HP Out Mode 4 0 -10 -10 -20 -20 -30 -30 -40 -50 -60 -50 -60 -70 -80 -80 -90 -90 100 1k 10k -100 20 100k 100 FREQUENCY (Hz) 10k Figure 34. Figure 35. PSRR vs Frequency AVDD = 5.0V, LS Out Mode 4 PSRR vs Frequency AVDD = 5.0V, LS Out Mode 2 0 -10 -10 -20 -20 -30 -30 -40 -50 -60 -50 -60 -70 -80 -80 -90 -90 100 1k 10k 100k -40 -70 -100 20 1k FREQUENCY (Hz) PSRR (dB) PSRR (dB) 0 100k -40 -70 -100 20 10k Figure 32. PSRR (dB) PSRR (dB) 0 1k FREQUENCY (Hz) 100k -100 20 100 FREQUENCY (Hz) Figure 36. 1k 10k 100k FREQUENCY (Hz) Figure 37. Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LM49321 LM49321RLEVAL Submit Documentation Feedback 31 LM49321, LM49321RLEVAL SNAS457C - SEPTEMBER 2008 - REVISED MAY 2013 www.ti.com Typical Performance Characteristics (continued) 280 Output Power vs Supply Voltage EP Out , RL = 32, 1% THD+N 150 130 OUTPUT POWER (mW) OUTPUT POWER (mW) 240 200 160 120 80 40 0 2.7 Output Power vs Supply Voltage HP Out , RL = 32, 1% THD+N 110 90 70 50 30 3 3.5 4 4.5 5 10 2.7 5.5 3 SUPPLY VOLTAGE (V) 3.5 4 4.5 5 5.5 SUPPLY VOLTAGE (V) Figure 38. Figure 39. 2 Output Power vs Supply Voltage LS Out , RL = 8, 1% THD+N 1.8 OUTPUT POWER (W) 1.6 1.4 1.2 1 800m 600m 400m 200m 0 2.7 3 3.5 4 4.5 5 5.5 SUPPLY VOLTAGE (V) Figure 40. 32 Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LM49321 LM49321RLEVAL LM49321, LM49321RLEVAL www.ti.com SNAS457C - SEPTEMBER 2008 - REVISED MAY 2013 APPLICATION INFORMATION I2S The LM49321 supports both master and slave I2S transmission at either 16 or 32 bits per word at clock rates up to 3.072MHz (48kHz stereo, 32bit). The basic format is shown below: Figure 41. MONO ONLY SETTING The LM49321 may be restricted to mono amplification only by setting MONO_ONLY in Output Control register 0x01h to 1. This may save an additional 400A from IDD. LM49321 DEMOBOARD OPERATION BOARD LAYOUT DIGITAL SUPPLIES JP14 -- Digital Power DVDD JP10 -- I/O Power IOVDD JP13 -- PLL Supply PLLVDD JP16 -- USB Board Supply BBVDD JP15 -- I2CVDD All supplies may be set independently. All digital ground is common. Jumpers may be used to connect all the digital supplies together. S9 - connects VDD_PLL to VDD_D S10 - connects VDD_D to VDD_IO S11 - connects VDD_IO to VDD_I2C S12 - connects VDD_I2C to Analog VDD S17 - connects BB_VDD to USB3.3V (from USB board) S19 - connects VDD_D to USB3.3V (from USB board) S20 - connects VDD_D to SPDIF receiver chip ANALOG SUPPLY JP11 -- Analog Supply S12 -- connects Analog VDD with Digital VDD (I2C_VDD) S16 -- connects Analog Ground with Digital Ground S21 -- connects Analog VDD to SPDIF receiver chip Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LM49321 LM49321RLEVAL Submit Documentation Feedback 33 LM49321, LM49321RLEVAL SNAS457C - SEPTEMBER 2008 - REVISED MAY 2013 www.ti.com INPUTS Analog Inputs JP2 -- Mono Differential Input JP6 -- Left Input JP7 -- Right Input Digital Inputs JP19 -- Digital Interface Pin 1 -- MCLK Pin 2 -- I2S_CLK Pin 3 -- I2S_SDI Pin 4 -- I2S_WS JP20 -- Toslink SPDIF Input JP21 -- Coaxial SPDIF Input Coaxial and Toslink inputs may be toggled between by use of S25. Only one may be used at a time. Must be used in conjunction with on-board SPDIF receiver chip. OUTPUTS JP5 -- BTL Loudspeaker Output JP1 -- Left Headphone Output (Single-Ended or OCL) JP3 -- Right Headphone Output (Single-Ended or OCL) P1 -- Stereo Headphone Jack (Same as JP1, JP2, Single-Ended or OCL) JP12 -- Mono BTL Earpiece Output CONTROL INTERFACE X1, X2 - USB Control Bus for I2C/SPI X1 Pin 9 - Mode Select (SPI or I2C) X2 Pin 1 - SDA Pin 3 - SCL Pin 15 - ADDR/END Pin 14 - USB5V Pin 16 - USB3.3V Pin 16 - USB GND MISCELLANEOUS I2S BUS SELECT S23, S24, S26, S27 - I2S Bus select. Toggles between on-board and external I2S (whether on-board SPDIF receiver is used). All jumpers must be set the same. Jumpers on top two pins selects external bus (JP19). Jumpers on bottom two pins selects on-board SPDIF receiver output. 34 Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LM49321 LM49321RLEVAL LM49321, LM49321RLEVAL www.ti.com SNAS457C - SEPTEMBER 2008 - REVISED MAY 2013 HEADPHONE OUTPUT CONFIGURATION Jumpers S1, S2, S3, and S4 are used to configure the headphone outputs for either cap-coupled outputs or output capacitorless (OCL) mode in addition to the register control internal to the LM49321 for this feature. Jumpers S1 and S3 bypass the output DC blocking capacitors when OCL mode is required. S2 connects the center amplifier HPCOUT to the headphone ring when in OCL mode. S4 connects the center ring to GND when cap-coupled mode is desired. S4 must be removed for OCL mode to function properly. Jumper settings for each mode: OCL S1 = ON S2 = ON S3 = ON S4 = OFF Cap-Coupled S1 = OFF S2 = OFF S3 = OFF S4 = ON PLL FILTER CONFIGURATION The LM49321 demo board comes with a simple filter setup by connecting jumpers S5 and S6. Removing these and connecting jumpers S7 and S8 will allow for an alternate PLL filter configuration to be used at R2 and C23. ON-BOARD SPDIF RECEIVER The SPDIF receiver present on the LM49321 demo board allows quick demonstration of the capabilities of the LM49321 by using the common SPDIF output found on most CD/DVD players today. There are some limitations in its useage, as the receiver will not work with digital supplies of less than 3.0V and analog supplies of less than 4V. This means low analog supply voltage testing of the LM49321 must be done on the external digital bus. The choice of using on-board or external digital bus is made using jumpers S23, S24, S26, and S27 as described above. S25 selects whether the Toslink or Coaxial SPDIF input is used. The top two pins connects the toslink, the bottom two connect the coaxial input. Power on the digital side is routed through S20 (connecting to the other digital supplies), while on the analog side it is interrupted by S21. Both jumpers must be in place for the receiver to function. The part is already configured for I2S standard outputs. Jumper S28 allows the DATA output to be pulled either high or low. Default is high (jumper on right two pins). It may be necessary to quickly toggle S29 to reset the receiver and start it working upon initial power up. A quick short across S29 should clear this condition. LM49321 I2C/SPI INTERFACE SOFTWARE Convenient graphical user interface software is available for demonstration purposes of the LM49321. It allows for either SPI or I2C control via either USB or parallel port connections to a Windows computer. Control options include all mode and output settings, volume controls, PLL and DAC setup, FIR setting and on-the-fly adjustment by an easy to use graphical interface. An advanced option is also present to allow direct, register-level commands. Software is available from www.ti.com and is compatible with Windows operating systems of Windows 98 or more (with USB support) with the latest .NET updates from Microsoft. Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LM49321 LM49321RLEVAL Submit Documentation Feedback 35 LM49321, LM49321RLEVAL SNAS457C - SEPTEMBER 2008 - REVISED MAY 2013 www.ti.com Demonstration Board Schematic VDD_D C1 1 uF C2 VDD_A 0.1 uF C3 VDD_I2C 0.1 uF C4 1 uF 0.1 uF 1 uF VDD_PLL C5 C9 C8 1 uF JP1 E2 E3 C14 JP16 VDD_A S17 BBVDD 1 2 0.22 uF B3 B2 A3 S18 A4 B6 C4 D4 USB_5V 2 1 BB_VDD USB_3.3V S19 JP19 C20 0.1 uF 1 OUTPUT S21 P1 220 uF JP12 F3 F2 Stereo Headphone Jack 1 2 S4 JP9 GPIO VDD_I/O B4 A6 1 2 VDD_IO C16 1 uF NC NC D3 E4 C18 150 nF C19 10 nF R3 422 S24 RXP 0.01 uF 5 R4 75 24 47k C25 0.01 uF 3 28 R5 14 R7 47k RXN ORIG CHS U2 CS8415A R8 47k R9 1.6k 4.7 nF C27 0.33 uF X1 1 3 5 7 9 11 13 15 2 4 6 8 10 12 14 16 X2 1 3 5 7 9 11 13 15 AUDIO C U NVERR PRO RCBL RERR COPY S26 10 17 16 18 19 26 25 15 13 12 11 1 S27 I2S CLK R6 47k S9 S11 S10 S12 3 2 S28 VDD_PLL JP13 1 1 2 VDD_D JP14 VDD_IO JP10 1 2 1 2 VDD_I2C JP15 VDD_A 1 2 JP11 1 2 BBVDD DGND R11 7 C26 AGND S29 RESET SPDIF RST FILT 22 DGND 21 DGND 20 DGND 9 8 MCLK I2S_WS I2S_CLK I2S_DOUT H/S EMPH I2S WS AVDD 4 DVDD DVDD DVDD C24 2 6 23 27 2 S25 3 USB_CS C12 220 uF C13 C23 1 JP21 USB_SDA USB_SCL 1 2 S2 0.1 uF 0.1 uF USB_SPI_M BP EPOUTP EPOUTM D5 D6 E5 MCLK DIGITAL INTERFACE C22 C21 TOSLINK RECEIVER S/PDIF IN PLL FILTER I2S DATA R2 2 GND S23 SDA/SDI SCL/SCK ADDR/ENBL MODE C17 2.2 uF S8 HPROUT HPCOUT HPLOUT S3 E6 AGRND D2 AGRND 3 VCC S5 S6 S7 I2S_CLK I2S_DATA I2S_WS A1 47 uH JP20 C5 7 6 5 4 3 2 1 R_IN C1 14 13 12 11 10 9 8 VDD_A L1 S20 U1 LM49321RL DGND VDD_D LSLOUTM LSOUTP L_IN PLL_GND VDD_D M_IN+ M_IN- F4 F6 0.22 uF JP7 R IN 1 2 S1 JP5 F1 E1 C11 1 2 L IN JP3 C30 0.22 uF JP6 F5 0.22 uF 1 2 AVDD AVDD 1 2 C6 C10 Diiferential Mono Input MCLK PLL_IN PLL_OUT A5 DVDD B5 I2C_VDD B1 PLL_VDD A2 C3 C2 JP2 5k R10 5k R12 5k S16 USB_SPIDO USB_SCL USB_SDA USB_CS USB_SPI_M S22 2 4 6 8 10 12 14 16 USB_5V USB_SPIDO USB_3.3V USB INTERFACE Figure 42. Complete Board Schematic 36 Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LM49321 LM49321RLEVAL LM49321, LM49321RLEVAL www.ti.com SNAS457C - SEPTEMBER 2008 - REVISED MAY 2013 JP2 C10 Diiferential Mono Input 1 2 0.22 uF C30 0.22 uF JP6 C11 1 2 L IN 0.22 uF JP7 C14 1 2 R IN JP16 BBVDD S17 VDD_A 0.22 uF S18 2 1 USB_5V BB_VDD USB_3.3V VDD_D S19 JP19 VDD_D S20 L1 14 13 12 11 10 9 8 VDD_A 47 uH JP20 VCC OUTPUT GND 3 1 C20 0.1 uF S21 2 7 6 5 4 3 2 1 S23 MCLK DIGITAL INTERFACE C21 C22 0.1 uF 0.1 uF I2S DATA S24 TOSLINK RECEIVER 4 5 S/PDIF IN RXP 0.01 uF R4 75 47k R5 C25 0.01 uF 24 3 28 R7 47k 14 AVDD C24 2 RXN H/S EMPH ORIG U2 CS8415A CHS 4.7 nF C27 0.33 uF X1 USB_SPI_M 1 3 5 7 9 11 13 15 2 4 6 8 10 12 14 16 USB_CS 1 3 5 7 9 11 13 15 17 16 18 S27 I2S CLK R6 AUDIO C U NVERR PRO RCBL RERR COPY 19 26 25 15 13 12 11 1 47k 3 2 S28 1 BBVDD R11 5k R10 5k R12 5k USB_SPIDO USB_SCL USB_SDA USB_CS USB_SPI_M X2 USB_SDA USB_SCL S26 10 7 C26 AGND S29 RESET SPDIF RST FILT 22 DGND 21 DGND 20 DGND 9 8 MCLK I2S_WS I2S_CLK I2S_DOUT R8 47k R9 1.6k I2S WS 6 S25 3 23 DVDD 27 DVDD 2 DVDD 1 JP21 S22 2 4 6 8 10 12 14 16 USB_5V USB_SPIDO USB_3.3V USB INTERFACE Figure 43. Enlarged Board Schematic Part 1 of 2 Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LM49321 LM49321RLEVAL 37 LM49321, LM49321RLEVAL SNAS457C - SEPTEMBER 2008 - REVISED MAY 2013 www.ti.com VDD_D C1 1 uF VDD_A C2 0.1 uF C3 VDD_I2C 0.1 uF C4 1 uF 1 uF VDD_PLL C5 C9 C8 0.1 uF 1 uF JP1 1 2 F5 C6 AVDD AVDD MCLK PLL_IN PLL_OUT A5 DVDD B5 I2C_VDD B1 PLL_VDD A2 C3 C2 JP3 1 2 S1 JP5 F1 E1 E2 E3 B3 B2 A3 A4 B6 C4 D4 I2S_CLK I2S_DATA I2S_WS R2 C13 P1 220 uF JP12 F3 F2 Stereo Headphone Jack 1 2 S4 B4 A6 1 2 VDD_IO C16 1 uF A1 C18 150 nF C19 10 nF C12 220 uF S2 JP9 GPIO VDD_I/O E6 AGRND D2 AGRND BP 1 2 D5 D6 E5 S3 C1 PLL FILTER EPOUTP EPOUTM SDA/SDI SCL/SCK ADDR/ENBL MODE C17 2.2 uF S8 HPROUT HPCOUT HPLOUT U1 LM49321RL R_IN DGND S5 S6 S7 LSLOUTM LSOUTP L_IN PLL_GND C5 M_IN+ M_IN- F4 F6 NC NC D3 E4 R3 422 C23 S9 S11 S10 VDD_PLL JP13 1 2 VDD_D JP14 VDD_IO JP10 1 2 1 2 S12 VDD_I2C JP15 VDD_A 1 2 JP11 1 2 DGND S16 Figure 44. Enlarged Board Schematic Part 2 of 2 38 Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LM49321 LM49321RLEVAL LM49321, LM49321RLEVAL www.ti.com SNAS457C - SEPTEMBER 2008 - REVISED MAY 2013 Revision History Rev Date Description 1.0 09/10/08 Initial release. 1.01 09/23/08 Text edits. 1.02 08/31/09 Edited the package drawing and the top markings. C 05/03/13 Changed layout of National Data Sheet to TI format. Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LM49321 LM49321RLEVAL Submit Documentation Feedback 39 PACKAGE OPTION ADDENDUM www.ti.com 24-Sep-2015 PACKAGING INFORMATION Orderable Device Status (1) LM49321RL/NOPB ACTIVE Package Type Package Pins Package Drawing Qty DSBGA YPG 36 250 Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Green (RoHS & no Sb/Br) SNAG Level-1-260C-UNLIM Op Temp (C) Device Marking (4/5) -40 to 85 GK9 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 24-Sep-2015 Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 2-Sep-2015 TAPE AND REEL INFORMATION *All dimensions are nominal Device LM49321RL/NOPB Package Package Pins Type Drawing SPQ DSBGA 250 YPG 36 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 178.0 12.4 Pack Materials-Page 1 3.43 B0 (mm) K0 (mm) P1 (mm) 3.59 0.76 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 2-Sep-2015 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM49321RL/NOPB DSBGA YPG 36 250 210.0 185.0 35.0 Pack Materials-Page 2 MECHANICAL DATA YPG0036xxx D 0.6500.075 E RLA36XXX (Rev A) D: Max = 3.525 mm, Min =3.465 mm E: Max = 3.268 mm, Min =3.208 mm 4214895/A NOTES: A. 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