SQFlash
H/S mSATA 630
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H/S mSATA 630
Datasheet
(SQF-SHMxx-xG-S9x)
SQFlash
H/S mSATA 630
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CONTENTS
1. Overview ............................................................................................ 4
2. Features ............................................................................................. 5
3. Specification Table ............................................................................ 6
4. General Description .......................................................................... 8
5. Pin Assignment and Description ................................................... 10
5.1 Half-size mSATA Interface Pin Assignments ................................................................. 10
6. Identify Device Data ........................................................................ 12
7. ATA Command Set .......................................................................... 16
8. System Power Consumption ......................................................... 22
8.1 Supply Voltage .............................................................................................................. 22
8.2 Power Consumption ...................................................................................................... 22
9. Physical Dimension ........................................................................ 23
Appendix: Part Number Table ........................................................... 24
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H/S mSATA 630
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Revision History
Rev.
Date
History
0.1
2014/4/3
1. 1st draft
0.2
2015/7/3
1. Add 128G / 256G MLC and 64G / 128G Ultra MLC
0.3
2015/11/2
1. Add description of Fragment Writing and Flush Manager
1.0
2016/4/1
1. MLC / UMLC update to 15nm
Advantech reserves the right to make changes without further notice to any products or data herein to improve reliability, function, or
design. Information furnished by Advantech is believed to be accurate and reliable. However, Advantech does not assure any liability
arising out of the application or use of this information, nor the application or use of any product or circuit described herein, neither
does it convey any license under its patent rights nor the rights of others.
Copyright © 1983-2010 Advantech Co., Ltd. All rights reserved.
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H/S mSATA 630
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1. Overview
Advantech SQFlash Half-size mSATA combines the advantages of flash disk technology with the Serial ATA III
interface, which electrically complies with the Serial ATA International Organization Standard. Half-size mSATA,
consisting of a Half-size Mini PCIe form factor with SATA signal pins, is designed to operate at a maximum
operating frequency of 300MHz with 40MHz external crystal. SQFlash Half-size mSATA comes with a wide range of
capacities from 1GB to 64GB for SLC, and 4GB to up to 256GB for MLC, and delivers the read / write performance
up to 250MB/s and 150MB/s, respectively based on Toshiba 19nm toggle MLC Flash IC. Given the features of the
low power consumption, small form factor, and high shock-resistance, Half-size mSATA are deemed to be widely
adopted storage device for embedded solutions, and will be an attractive solution to replace the conventional
[PATA-interfaced] CompactFlash card in industrial applications.
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H/S mSATA 630
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2. Features
Standard SATA interface
– Support SATA 1.5 Gbps, 3.0 Gbps, and 6.0 Gbps interface
– SATA Revision 3.0 compliant
– Power management supported
Operating Voltage：3.3V
Support 72 bit ECC correct per 1K Byte data
TRIM、AHCI supported
Temperature Ranges
– Commercial Temperature
● 0℃ to 70℃ for operating
● -40℃ to 85℃ for storage
– Industrial Temperature
● -40℃ to 85℃ for operating
● -40℃ to 85℃ for storage
Mechanical Specification
– Shock：1,500G / 0.5ms
– Vibration：20G / 80~2,000Hz
Humidty
– Humidity：5% ~ 95% under 55℃
Endurance : > 2,000,000 program/erase cycles
– This is a test result of the whole SQFlash drive. The test is to keep writing a fixed logical block address (LBA)
and see if any bad blocks occur after 2M cycles. With wear-levelling mechanism, although the disk was kept
writing the same LBA but the physical block changes per block writing. So this test also proves that
wear-leveling is really working, or the block would be wearout after its designated life cycles.
Data Retention
– 10 years
Acquired RoHS、WHQL、CE、FCC Certificate
Acoustic：0 dB
Dimension：26.88 mm x 29.85 mm x 4.0 mm
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3. Specification Table
Performance
Sequential Performance (MB/sec)
Read
Write
Read
Write
SLC
1 GB
33.83
21.16
6,994
2,533
2 GB
67.44
41.19
13,652
4,531
4 GB
68.66
52.41
12,608
8,837
8 GB
66.78
56.49
12,705
11,684
16 GB
67.47
58.80
13,304
12,826
32 GB
67.45
59.48
12,618
12,726
Ultra
MLC
2 GB
121.90
57.17
64,444
12,025
4 GB
243.70
113.50
44,514
21,069
8 GB
321.50
185.00
39,105
29,754
16 GB
260.80
157.90
36,018
28,428
32 GB
523.40
187.30
44,434
25,054
64 GB
523.90
193.20
40,700
24,094
128 GB
526.40
179.50
40,820
24,084
MLC
4 GB
119.40
56.74
64,586
10,409
8 GB
236.90
113.10
45,339
20,926
16 GB
302.70
178.40
44,867
27,601
32 GB
250.70
151.40
42,784
24,905
64 GB
511.30
185.30
45,903
27,637
128 GB
506.60
193.60
33,821
23,900
256 GB
506.20
187.50
33,787
23,551
* All performance above are tested with AHCI mode.
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Endurance
According to JEDEC subcommittee JC-64.8, the actual endurance of flash storage can be presented by
Terabyte Write (TBW), which is measured by NAND Flash physical endurance, Wear-leveling Efficiency
(WLE) and Write Amplification Factor (WAF) of specific capacities with following formula.
TBW = [(NAND Flash Physical Endurance) x Capacity x WLE] / WAF
TBW of sequential writing
WLE
WAF
TBW
SLC
Ultra MLC
MLC
1 GB
0.9130
1.1013
80
--
--
2 GB
0.9130
1.1017
161
32
--
4 GB
0.9130
1.1025
323
64
9
8 GB
0.9120
1.1026
646
129
19
16 GB
0.9120
1.1031
1291
258
38
32 GB
0.9120
1.1029
2584
516
77
128 GB
0.9110
1.1039
5100
1300
153
256 GB
0.9100
1.1041
--
2603
309
128 GB
0.9110
1.1039
--
--
618
TBW of random writing
WLE
WAF
TBW
SLC
Ultra MLC
MLC
1 GB
0.9130
1.2176
73
--
--
2 GB
0.9130
1.2837
138
27
--
4 GB
0.9130
1.3034
273
54
8
8 GB
0.9120
1.3278
536
107
16
16 GB
0.9120
2.2323
638
127
19
32 GB
0.9120
2.3535
1210
242
36
64 GB
0.9110
2.4396
2333
466
70
128 GB
0.9110
2.3141
--
984
147
256 GB
0.9100
2.2614
--
--
301
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4. General Description
Advanced NAND Flash Controller
Advantech SQFlash Half-size mSATA includes Bad Block Management Algorithm, Wear Leveling Algorithm
and Error Detection / Correction Code (EDC/ECC) Algorithm, Fragment Writing Technology, and
GuaranteedFlush Technology.
Bad Block Management
Bad blocks are blocks that contain one or more invalid bits of which the reliability is not guaranteed. Bad
blocks may be representing when flash is shipped and may developed during life time of the device.
Advantech SQFlash Half-size mSATA implement an efficient bad block management algorithm to detect the
factory produced bad blocks and manages any bad blocks that may develop over the life time of the device.
This process is completely transparent to the user, user will not aware of the existence of the bad blocks
during operation.
Wear Leveling
NAND Type flash have individually erasable blocks, each of which can be put through a finite number of
erase cycles before becoming unreliable. It means after certain cycles for any given block, errors can be
occurred in a much higher rate compared with typical situation. Unfortunately, in the most of cases, the flash
media will not been used evenly. For certain area, like file system, the data gets updated much frequently
than other area. Flash media will rapidly wear out in place without any rotation.
Wear leveling attempts to work around these limitations by arranging data so that erasures and re-writes are
distributed evenly across the full medium. In this way, no single sector prematurely fails due to a high
concentration of program/erase cycles.
Advantech SQFlash Half-size mSATA provides advanced wear leveling algorithm, which can efficiently
spread out the flash usage through the whole flash media area. By implement both dynamic and static wear
leveling algorithms, the life expectancy of the flash media can be improved significantly.
Error Detection / Correction
Advantech SQFlash Half-size mSATA utilizes BCH ECC Algorithm which offers one of the most powerful ECC
algorithms in the industry. This algorithm can support 44 bit ECC correct per 1K Byte data.
Sophisticate Product Management Systems
Since industrial application require much more reliable devices compare with consumer product, a more
sophisticated product management system become necessary for industrial customer requirement. The key
to providing reliable devices is product traceability and failure analysis system. By implement such systems
end customer can expect much more reliable product.
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Block Diagram
LBA、Cylinders、Heads、Sectors value
Density
LBA
1 GB
1,974,672
2 GB
3,928,176
4 GB
7,835,184
8 GB
15,649,200
16 GB
31,277,232
32 GB
62,533,296
64 GB
125,045,424
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5. Pin Assignment and Description
5.1 Half-size mSATA Interface Pin Assignments
Pin #
Function
Description
1
NC
No Connect
2
+3.3V
3.3V Source
3
NC
No Connect
4
DGND
Digital GND
5
NC
No Connect
6
NC
No Connect
7
NC
No Connect
8
NC
No Connect
9
DGND
Digital GND
10
NC
No Connect
11
NC
No Connect
12
NC
No Connect
13
NC
No Connect
14
NC
No Connect
15
DGND
Digital GND
16
NC
No Connect
17
NC
No Connect
18
DGND
Digital GND
19
NC
No Connect
20
NC
No Connect
21
SATA GND
SATA Ground Return Pin
22
NC
No Connect
23
B+
Host Receiver Differential Signal Pair
24
+3.3V
3.3V Source
25
B-
Host Receiver Differential Signal Pair
26
SATA GND
SATA Ground Return Pin
27
SATA GND
SATA Ground Return Pin
28
NC
No Connect
29
SATA GND
SATA Ground Return Pin
30
NC
No Connect
31
A-
Host Transmitter Differential Signal Pair
32
NC
No Connect
33
A+
Host Transmitter Differential Signal Pair
34
DGND
Digital GND
35
SATA GND
SATA Ground Return Pin
36
NC
No Connect
37
SATA GND
SATA Ground Return Pin
38
NC
No Connect
39
+3.3V
3.3V Source
40
DGND
Digital GND
41
+3.3V
3.3V Source
42
NC
No Connect
43
NC
No Connect
44
DEVSLP
Enter/Exit DevSleep
45
NC
Reserved pin
46
NC
No Connect
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47
NC
Reserved pin
48
NC
No Connect
49
DA/DSS
Device Activity Signal
50
DGND
Digital GND
51
GND
Default connect to GND
52
+3.3V
3.3V Source
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6. Identify Device Data
The Identity Device Data enables Host to receive parameter information from the device. The parameter
words in the buffer have the arrangement and meanings defined in below table. All reserve bits or words
are zero
Word
Address
Default
Value
Data Field Type Information
0
0040h
General configuration bit-significant information
1
*1
Obsolete – Number of logical cylinders
2
C837h
Specific configuration
3
0010h
Obsolete – Number of logical heads (16)
4-5
0000h
Retired
6
003Fh
Obsolete – Number of logical sectors per logical track (63)
7-8
0000h
Reserved for assignment by the Compact Flash Association
9
0000h
Retired
10-19
Varies
Serial number (20 ASCII characters)
20-21
0000h
Retired
22
0000h
Obsolete
23-26
Varies
Firmware revision (8 ASCII characters)
27-46
Varies
Model number (xxxxxxxx)
47
8010h
7:0- Maximum number of sectors transferred per interrupt on
MULTIPLE commands
48
4000h
Trusted Computing feature set options(not support)
49
2F00h
Capabilities
50
4000h
Capabilities
51-52
00000h
Obsolete
53
0007h
Words 88 and 70:64 valid
54
*1
Obsolete – Number of logical cylinders
55
0010h
Obsolete – Number of logical heads (16)
56
003Fh
Obsolete – Number of logical sectors per track (63)
57-58
*2
Obsolete – Current capacity in sectors
59
0110h
Number of sectors transferred per interrupt on MULTIPLE commands
60-61
*3
Maximum number of sector ( 28bit LBA mode)
62
0000h
Obsolete
63
0407h
Multi-word DMA modes supported/selected
64
0003h
PIO modes supported
65
0078h
Minimum Multiword DMA transfer cycle time per word
66
0078h
Manufacturer’s recommended Multiword DMA transfer cycle time
67
0078h
Minimum PIO transfer cycle time without flow control
68
0078h
Minimum PIO transfer cycle time with IORDY flow control
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69
0100h
Additional Supported (support download microcode DMA)
70
0000h
Reserved
71-74
0000h
Reserved for the IDENTIFY PACKET DEVICE command
75
001Fh
Queue depth
76
670eh
Serial SATA capabilities
77
0084h
Serial ATA Additional Capabilities
78
014Ch
Serial ATA features supported
79
0040h
Serial ATA features enabled
80
07F8h
Major Version Number
81
0000h
Minor Version Number
82
346bh
Command set supported
83
7d09h
Command set supported
84
6063h
Command set/feature supported extension
85
3469h
Command set/feature enabled
86
bc01h
Command set/feature enabled
87
6063h
Command set/feature default
88
003Fh
Ultra DMA Modes
89
0001h
Time required for security erase unit completion
90
001Eh
Time required for Enhanced security erase completion
91
0000h
Current advanced power management value
92
FFFEh
Master Password Revision Code
93
0000h
Hardware reset result. The contents of the bits (12:0) of this word can
be changed only during the execution of hardware reset.
94
0000h
Vendor’s recommended and actual acoustic management value
95
0000h
Stream Minimum Request Size
96
0000h
Streaming Transfer Time – DMA
97
0000h
Streaming Access Latency – DMA and PIO
98-99
0000h
Streaming Performance Granularity
100-103
*4
Maximum user LBA for 48 bit Address feature set
104
0000h
Streaming Transfer Time – PIO
105
0008h
Maximum number of 512-byte blocks per DATA SET MANAGEMENT
command
106
4000h
Physical sector size/Logical sector size
107
0000h
Inter-seek delay for ISO-7779 acoustic testing in microseconds
108-111
0000h
Unique ID
112-116
0000h
Reserved
117-118
0000h
Words per logical Sector
119
4014h
Supported settings
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120
4014h
Command set/Feature Enabled/Supported
121-126
0000h
Reserved
127
0000h
Removable Media Status Notification feature set support
128
0021h
Security status
129-140
0000h
Vendor specific
141
0001h
Vendor specific
142-159
0000h
Vendor specific
160
0000h
Compact Flash Association (CFA) power mode 1
161-167
0000h
Reserved for assignment by the CFA
168
3h 2.5 inch
4h 1.8 inch
5h Less
than 1.8 inch
Device Nominal Form Factor
169
0001h
DATA SET MANAGEMENT command is supported
170-173
0000h
Additional Product Identifier
174-175
0000h
Reserve
176-205
0000h
Current media serial number
206
0000h
SCT Command Transport
207-208
0000h
Reserved
209
4000h
Alignment of logical blocks within a physical block
210-211
0000h
Write-Read-Verify Sector Count Mode 3 (not support)
212-213
0000h
Write-Read-Verify Sector Count Mode 2 (not support)
214-216
0000h
NV Cache relate (not support)
217
0001h
Non-rotating media device
218
0000h
Reserved
219
0000h
NV Cache relate (not support)
220
0000h
Write read verify feature set current mode
221
0000h
Reserved
222
107Fh
Transport major version number
223
0000h
Transport minor version number
224-229
0000h
reserved
230-233
0000h
Extend number of user addressable sectors
234
0001h
Minimum number of 512-byte data blocks per DOWNLOAD
MICROCODE command for mode 03h
235
0080h
Maximum number of 512-byte data blocks per DOWNLOAD
MICROCODE command for mode 03h
236-254
0000h
Reserved
255
XXA5h
XX is
variable
Integrity word (Checksum and Signature)
Capacity (GB)
*1 (Word 1 / 54)
*2 (Word 57 - 58)
*3 (Word 60 - 61)
*4 (Word 100 – 103)
1
7A7h
1E2190h
1E2190h
1E2190h
2
F39h
3BF070h
3BF070h
3BF070h
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4
1E5Dh
778E30h
778E30h
778E30h
8
3CA5h
EEC9B0h
EEC9B0h
EEC9B0h
16
3FFFh
FBFC10h
1DD40B0h
1DD40B0h
32
3FFFh
FBFC10h
3BA2EB0h
3BA2EB0h
64
3FFFh
FBFC10h
7740AB0h
7740AB0h
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7. ATA Command Set
[Command Set List]
Op-Code
Command Description
06h
Data Set Management
10h-1Fh
Recalibrate
20h
Read Sectors
21h
Read Sectors without Retry
24h
Read Sectors EXT
25h
Read DMA EXT
27h
Read Native Max Address EXT
29h
Read Multiple EXT
2Fh
Read Log EXT
30h
Write Sectors
31h
Write Sectors without Retry
34h
Write Sectors EXT
35h
Write DMA EXT
37h
Set Native Max Address EXT
39h
Write Multiple EXT
3Dh
Write DMA FUA EXT
3Fh
Write Long EXT
40h
Read Verify Sectors
41h
Read Verify Sectors without Retry
42h
Read Verify Sectors EXT
60h
Read FPDMA Queued
61h
Write FPDMA Queued
70h
Seek
90h
Execute Device Diagnostic
91h
Initialize Device Parameters
92h
Download Microcode
B0h
SMART
C4h
Read Multiple
C5h
Write Multiple
C6h
Set Multiple Mode
C8h
Read DMA
C9h
Read DMA without Retry
CAh
Write DMA
CBh
Write DMA without Retry
CEh
Write Multiple FUA EXT
E0h
Standby Immediate
E1h
Idle Immediate
E2h
Standby
E3h
Idle
E4h
Read Buffer
E5h
Check Power Mode
E6h
Sleep
E7h
Flush Cache
E8h
Write Buffer
EAh
Flush Cache EXT
ECh
Identify Device
EFh
Set Features
F1h
Security Set Password
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F2h
Security Unlock
F3h
Security Erase Prepare
F4h
Security Erase Unit
F5h
Security Freeze Lock
F6h
Security Disable Password
F8h
Read Native Max Address
F9h
Set Max Address
[Command Set Descriptions]
1. CHECK POWER MODE (code: E5h);
This command allow host to determine the current power mode of the device.
2. DOWNLOAD MICROCODE (code: 92h);
This command enable the host to alter the device’s microcode. The data transferred using the
DOWNLOAD MICROCODE command is vendor specific.
All transfers shall be an integer multiple of the sector size. The size of the data transfer is determined by
the content of the LBA Low register and the Sector Count register.
This allows transfer sizes from 0 bytes to 33,553,920 bytes, in 512bytes increments.
3. EXECUTE DEVICE DIAGNOSTIC (code: 90h);
This command performs the internal diagnostic tests implemented by the module.
4. FLUSH CACHE (code: E7h);
This command used by the host to request the device to flush the write cache.
5. FLUSH CACHE EXT (code: EAh);
This command is used by the host to request the device to flush the write cache. If there is data in the
write cache, that data shall be written to the media.
6. IDENTIFY DEVICE (code: ECh);
The IDENTIFY DEVICE command enables the host to receive parameter information from the module.
7. IDLE (code: 97h or E3h);
This command allows the host to place the module in the IDLE mode and also set the Standby timer.
INTRQ may be asserted even through the module may not have fully transitioned to IDLE mode. If the
Sector Count register is non-”0”, then the Standby timer shall be enabled. The value in the Sector Count
register shall be used to determine the time programmed into the Standby timer. If the Sector Count
register is “0” then the Standby timer is disabled.
8. IDLE IMMEDIATE (code: E1h);
This command causes the module to set BSY, enter the Idle (Read) mode, clear BSY and generate an
interrupt.
9. INITIALIZE DEVICE PARAMETERS (code: 91h);
This command enables the host to set the number of sectors per track and the number of heads per
cylinder.
10. NOP (code: 00h);
If this command is issued, the module respond with command aborted.
11. READ BUFFER (code: E4h);
This command enables the host to read the current contents of the module's sector buffer.
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12. READ DMA (code: C8h or C9h);
This command reads from “1” to “256” sectors as specified in the Sector Count register using the DMA
data transfer protocol. A sector count of “0” requests “256” sectors transfer. The transfer begins at the
sector specified in the Sector Number register.
13. READ DMA Ext (code: 25h);
This command allows the host to read data using the DMA data transfer protocol.
14. READ MULTIPLE (code: C4h);
This command performs similarly to the READ SECTORS command. Interrupts are not generated on
each sector, but on the transfer of a block which contains the number of sector per block is defined by the
content of word 59 in the IDENTIFY DEVICE response.
15. READ MULTIPLE EXT (code: 29h);
This command performs similarly to the READ SECTORS command. The number of sectors per block is
defined by a successful SET MULTIPLE command. If no successful SET MULTIPLE command has been
issued, the block is defined by the device’s default value for number of sectors per block as defined in bits
(7:0) in word 47 in the IDENTIFY DEVICE information.
16. READ NATIVE MAX ADDRESS (code: F8h);
This command returns the native maximum address. The native maximum address is the highest address
accepted by the device in the factory default condition.
17. READ NATIVE MAX ADDRESS EXT (code: 27h);
This command returns the native maximum address.
18. READ SECTOR(S) (code: 20h or 21h);
This command reads from “1” to “256” sectors as specified in the Sector Count register. A sector count of
“0” requests “256” sectors transfer. The transfer begins at the sector specified in the Sector Number
register.
19. READ SECTOR(S) EXT (code: 24h);
This command reads from “1” to “65536” sectors as specified in the Sector Count register. A sector count
of “0” requests “65536” sectors transfer. The transfer begins at the sector specified in the Sector Number
register.
20. READ VERIFY SECTOR(S) (code: 40h or 41h);
This command is identical to the READ SECTORS command, except that DRQ is never set and no data is
transferred to the host.
21. READ VERIFY SECTOR(S) EXT (code: 42h);
This command is identical to the READ SECTORS command, except that DRQ is never set and no data is
transferred to the host.
22. RECALIBRATE (code: 1Xh);
This command return value is select address mode by the host request.
23. SECURITY DISABLE PASSWORD (code: F6h);
This command transfers 512 bytes of data from the host. Table defines the content of this information. If
the password selected by word 0 match the password previously saved by the device, the device shall
disable the Lock mode. This command shall not change the Master password. The Master password shall
be reactivated when a User password is set.
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24. SECURITY ERASE PREPARE (code: F3h);
This command shall be issued immediately before the SECURITY ERASE UNIT command to enable
device eraseing and unlocking.
25. SECURITY ERASE UNIT (code: F4h);
This command transfer 512 bytes of data from the host. Table## defines the content of this information. If
the password does not match the password previously saved by the device, the device shall reject the
command with command aborted.
The SECURITY ERASE PREPARE command shall be completed immediately prior to the SECURITY
ERASE UNIT command.
26. SECURITY FREEZE LOCK (code: F5h);
This command shall set the device to frozen mode. After command completion any other commands that
update the device Lock mode shall be command aborted. Frozen shall be disabled by power-off or
hardware reset.
If SECURITY FREEZE LOCK is issued when the drive is in frozen mode, the drive executes the command
and remains in frozen mode.
27. SECURITY SET PASSWORD (code: F1h);
This command transfer 512 bytes of data from the host. Table defines the content of this information. The
data transferred controls the function of this command. Table defines the interaction of the identifier and
security level bits.
28. SECURITY UNLOCK (code: F2h);
This command transfer 512 bytes of data from the host. Table (as Disable Password) defines the content
of this information.
If the Identifier bit is set to Master and the device is in high security level, then the password supplied shall
be compared with the stored Master password. If the device is in maximum security level then the unlock
shall be rejected.
If the identifier bit is set to user then the device shall compare the supplied password with the stored User
password.
If the password compare fails then the device shall return command aborted to the host and decrements
the unlock counter. This counter shall be initially set to five and shall be decremented for each password
mismatch when SECURITY UNLOCK is issued and the device is locked. When this counter reachs zero
then SECURITY UNLOCK and SECURITY ERASE UNIT command shall be aborted unitl a power-on or a
hardware reset.
29. SEEK (code: 7Xh);
This command performs address range check.
30. SET MAX ADDRESS (code: F9h);
After successful command completion, all read and write access attempts to address greater than
specified by the successful SET MAX ADDRESS command shall be rejected with an IDNF error.
IDENTIFY DEVICE response words (61:60) shall reflect the maximum address set with this command.
31. SET MAX ADDRESS EXT (code: 37h);
After successful command completion, all read and write access attempts to address greater than
specified by the successful SET MAX ADDRESS command shall be rejected with an IDNF error.
IDENTIFY DEVICE response words (61:60) shall reflect the maximum address set with this command.
32. SET FEATURE (code: EFh);
This command is used by the host to establish parameters that affect the execution of certain device
features.
33. SET MULTIPLE MODE (code: C6h);
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This command enables the device to perform READ and Write Multiple operations and establishes the
block count for these commands.
34. SLEEP (code: 99h or E6h);
This command causes the module to set BSY, enter the Sleep mode, clear BSY and generate an interrupt.
35. SMART READ DATA (code: B0h with Feature register value of D0h);
This command returns the Device SMART data structure to the host.
36. SMART ENABLE/DISABLE AUTO SAVE (code: B0h with Feature register value of D2h);
This command enables and disables the optional attribute autosave feature of the device.
37. SMART EXECUTE OFF_LINE (code: B0h with Feature register value of D4h);
This command cause the device to immediately initiate the optional set of activities that collect SMART
data in an off-line mode and then save this data to the device’s non-volatile memory, or execute a
self-diagnostic test routine in either captive or off-line mode.
38. SMART READ LOG (code: B0h with Feature register value of D5h);
This command returns the specified log data to the host.
39. SMART ENABLE OPERATION (code: B0h with Feature register value of D8h);
This command enables access to all SMART capabilities within the device. Prior to receipt of this
command SMART data are neither monitored nor saved by the device.
40. SMART DISABLE OPERATION (code: B0h with Feature register value of D9h);
This command disables all SMART capabilities within the device including any and all timer and event
count functions related exclusively to this feature. After command acceptance the device shall disable all
SMART operations.
After receipt of this command by the device, all other SMART commands including SMART DISABLE
OPERATION commands, with exception of SMART ENABLE OPERATIONS, are disabled and invalid and
shall be command aborted by the device.
41. SMART RETURN STATUS (code: B0h with Feature register value of DAh);
This command cause the device to communicate the reliability status of the device to the host.
42. STANDBY (code: E2h);
This command causes the module to set BSY, enter the Standby mode, clear BSY and return the interrupt
immediately.
43. STANDBY IMMEDIATE (code: E0h);
This command causes the module to set BSY, enter the Standby mode, clear BSY and return the interrupt
immediately.
44. WRITE BUFFER (code: E8h);
This command enables the host to overwrite contents of the module’s sector buffer with any data pattern
desired.
45. WRITR DMA (code: CAh or CBh);
This command writes from “1” to “256” sectors as specified in the Sector Count register using the DMA
data transfer protocol. A sector count of “0” requests “256” sectors transfer. The transfer begins at the
sector specified in the Sector Number register.
46. WRITR DMA EXT (code: 35h);
This command writes from “1” to “65536” sectors as specified in the Sector Count register using the DMA
data transfer protocol. A sector count of “0” requests “65536” sectors transfer. The transfer begins at the
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REV 0.4 Page 21 of 26 Apr. 1, 2016
sector specified in the Sector Number register.
47. WRITE MULTIPLE (code: C5h);
This command is similar to the WRITE SECTORS command. Interrupts are not presented on each sector,
but on the transfer of a block which contains the number of sectors defined by Set Multiple command.
48. WRITE MULTIPLE EXT (code: 39h);
This command is similar to the WRITE SECTORS command. Interrupts are not presented on each sector,
but on the transfer of a block which contains the number of sectors defined by Set Multiple command.
49. WRITE SECTOR(S) (code: 30h);
This command writes from “1” to “256” sectors as specified in the Sector Count register. A sector count of
“0” requests “256” sectors transfer. The transfer begins at the sector specified in the Sector Number
register.
50. WRITE SECTOR(S) EXT (code: 34h);
This command writes from “1” to “65536” sectors as specified in the Sector Count register. A sector count
of “0” requests “65536” sectors transfer. The transfer begins at the sector specified in the Sector Number
register.
51. WRITE SECTOR(S) W/O ERASE (code: 38h);
This command writes from “1” to “256” sectors as specified in the Sector Count register. A sector count of
“0” requests “256” sectors transfer. The transfer begins at the sector specified in the Sector Number
register.
52. WRITE VERIFY (code: 3Ch);
This command is similar to the WRITE SECTOR(S) command, except that each sector is verified before
the command is completed.
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REV 0.4 Page 22 of 26 Apr. 1, 2016
8. System Power Consumption
8.1 Supply Voltage
Parameter
Rating
Operating Voltage
3.3V +/- 5%
8.2 Power Consumption
mA
Read
Write
Idle
Slumber
SLC
1 GB
158.79
167.88
77.27
10.00
2 GB
185.16
208.79
78.48
10.00
4 GB
191.82
239.70
78.79
10.00
8 GB
182.73
221.21
78.79
10.00
16 GB
184.85
222.73
79.09
10.00
32 GB
190.91
227.27
80.30
10.00
Ultra
MLC
2 GB
260.61
227.28
84.85
10.00
4 GB
363.64
266.67
84.85
10.00
8 GB
287.88
257.58
84.85
10.00
16 GB
409.10
378.79
87.88
10.00
32 GB
469.70
393.94
90.91
10.00
MLC
4 GB
260.61
218.19
84.85
10.00
8 GB
350.00
268.19
84.85
10.00
16 GB
284.85
254.55
84.85
10.00
32 GB
409.10
366.67
87.88
10.00
64 GB
475.76
384.85
90.91
10.00
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REV 0.4 Page 23 of 26 Apr. 1, 2016
9. Physical Dimension
Half-size mSATA (Unit: mm)
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REV 0.4 Page 24 of 26 Apr. 1, 2016
Appendix: Part Number Table
SLC
Product
Advantech PN
SQF HS mSATA 630 1G SLC (0~70°C)
SQF-SHMS1-1G-S9C
SQF HS mSATA 630 2G SLC (0~70°C)
SQF-SHMS2-2G-S9C
SQF HS mSATA 630 4G SLC (0~70°C)
SQF-SHMS2-4G-S9C
SQF HS mSATA 630 8G SLC (0~70°C)
SQF-SHMS2-8G-S9C
SQF HS mSATA 630 16G SLC (0~70°C)
SQF-SHMS2-16G-S9C
SQF HS mSATA 630 32G SLC (0~70°C)
SQF-SHMS2-32G-S9C
SQF HS mSATA 630 1G SLC (-40~85°C)
SQF-SHMS1-1G-S9E
SQF HS mSATA 630 2G SLC (-40~85°C)
SQF-SHMS2-2G-S9E
SQF HS mSATA 630 4G SLC (-40~85°C)
SQF-SHMS2-4G-S9E
SQF HS mSATA 630 8G SLC (-40~85°C)
SQF-SHMS2-8G-S9E
SQF HS mSATA 630 16G SLC (-40~85°C)
SQF-SHMS2-16G-S9E
SQF HS mSATA 630 32G SLC (-40~85°C)
SQF-SHMS2-32G-S9E
SQFlash
H/S mSATA 630
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REV 0.4 Page 25 of 26 Apr. 1, 2016
Ultra MLC
Product
Advantech PN
SQF HS mSATA 630 2G U-MLC (0~70°C)
SQF-SHMU1-2G-S9C
SQF HS mSATA 630 4G U-MLC (0~70°C)
SQF-SHMU2-4G-S9C
SQF HS mSATA 630 8G U-MLC (0~70°C)
SQF-SHMU2-8G-S9C
SQF HS mSATA 630 16G U-MLC (0~70°C)
SQF-SHMU2-16G-S9C
SQF HS mSATA 630 32G U-MLC (0~70°C)
SQF-SHMU2-32G-S9C
SQF HS mSATA 630 64G U-MLC (0~70°C)
SQF-SHMU2-64G-S9C
SQF HS mSATA 630 128G U-MLC (0~70°C)
SQF-SHMU2-128G-S9C
SQF HS mSATA 630 2G U-MLC (-40~85°C)
SQF-SHMU1-2G-S9E
SQF HS mSATA 630 4G U-MLC (-40~85°C)
SQF-SHMU2-4G-S9E
SQF HS mSATA 630 8G U-MLC (-40~85°C)
SQF-SHMU2-8G-S9E
SQF HS mSATA 630 16G U-MLC (-40~85°C)
SQF-SHMU2-16G-S9E
SQF HS mSATA 630 32G U-MLC (-40~85°C)
SQF-SHMU2-32G-S9E
SQF HS mSATA 630 64G U-MLC (-40~85°C)
SQF-SHMU2-64G-S9E
SQF HS mSATA 630 128G U-MLC (-40~85°C)
SQF-SHMU2-128G-S9E
SQFlash
H/S mSATA 630
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REV 0.4 Page 26 of 26 Apr. 1, 2016
MLC
Product
Advantech PN
SQF HS mSATA 630 4G MLC (0~70°C)
SQF-SHMM1-4G-S9C
SQF HS mSATA 630 8G MLC (0~70°C)
SQF-SHMM2-8G-S9C
SQF HS mSATA 630 16G MLC (0~70°C)
SQF-SHMM2-16G-S9C
SQF HS mSATA 630 32G MLC (0~70°C)
SQF-SHMM2-32G-S9C
SQF HS mSATA 630 64G MLC (0~70°C)
SQF-SHMM2-64G-S9C
SQF HS mSATA 630 128G MLC (0~70°C)
SQF-SHMM2-128G-S9C
SQF HS mSATA 630 256G MLC (0~70°C)
SQF-SHMM2-256G-S9C
SQF HS mSATA 630 4G MLC (-40~85°C)
SQF-SHMM1-4G-S9E
SQF HS mSATA 630 8G MLC (-40~85°C)
SQF-SHMM2-8G-S9E
SQF HS mSATA 630 16G MLC (-40~85°C)
SQF-SHMM2-16G-S9E
SQF HS mSATA 630 32G MLC (-40~85°C)
SQF-SHMM2-32G-S9E
SQF HS mSATA 630 64G MLC (-40~85°C)
SQF-SHMM2-64G-S9E
SQF HS mSATA 630 128G MLC (-40~85°C)
SQF-SHMM2-128G-S9E
SQF HS mSATA 630 256G MLC (-40~85°C)
SQF-SHMM2-256G-S9E