Dual, 256-Position, SPI
Digital Potentiometer
AD5162
Rev. C
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FEATURES
2-channel, 256-position potentiometer
End-to-end resistance: 2.5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ
Compact 10-lead MSOP (3 mm × 4.9 mm) package
Fast settling time: tS = 5 µs typical on power-up
Full read/write of wiper register
Power-on preset to midscale
Computer software replaces microcontroller in factory
programming applications
Single supply: 2.7 V to 5.5 V
Low temperature coefficient: 35 ppm/°C
Low power: IDD = 6 µA maximum
Wide operating temperature: −40°C to +125°C
Evaluation board available
Qualified for automotive applications
APPLICATIONS
Systems calibrations
Electronics level settings
Mechanical trimmers replacement in new designs
Permanent factory PCB setting
Transducer adjustment of pressure, temperature, position,
chemical, and optical sensors
RF amplifier biasing
Automotive electronics adjustment
Gain control and offset adjustment
FUNCTIONAL BLOCK DIAGRAM
A1
A = 0 A = 1
VDD
GND
SDI
CLK
CS
W1
WIPER
REGISTER 1
SPI INTERFACE
AD5162
04108-0-001
B1 W2
WIPER
REGISTER 2
B2
Figure 1.
GENERAL DESCRIPTION
The AD5162 provides a compact 3 mm × 4.9 mm packaged
solution for dual, 256-position adjustment applications. This
device performs the same electronic adjustment function as a
3-terminal mechanical potentiometer. Available in four end-to-
end resistance values (2.5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ), this low
temperature coefficient device is ideal for high accuracy and
stability-variable resistance adjustments. The wiper settings are
controllable through an SPI digital interface. The resistance
between the wiper and either endpoint of the fixed resistor
varies linearly with respect to the digital code transferred into
the RDAC latch.1
Operating from a 2.7 V to 5.5 V power supply and consuming
less than 6 µA allows the AD5162 to be used in portable battery-
operated applications.
For applications that program the AD5162 at the factory,
Analog Devices offers device programming software running
on Windows® NT/2000/XP operating systems. This software
effectively replaces the need for external SPI controllers, which
in turn enhances the time to market of systems. An AD5162
evaluation kit and software are available. The kit includes a
cable and instruction manual.
1 The terms digital potentiometer, VR, and RDAC are used interchangeably.
AD5162
Rev. C | Page 2 of 20
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Electrical Characteristics: 2.5 kΩ Version ................................. 3
Electrical Characteristics: 10 kΩ, 50 kΩ, and 100 kΩ Versions
......................................................................................................... 4
Timing Characteristics: All Versions ......................................... 5
Absolute Maximum Ratings ............................................................ 6
ESD Caution .................................................................................. 6
Pin Configuration and Function Descriptions ............................. 7
Typical Performance Characteristics ............................................. 8
Test Circuits ..................................................................................... 12
Theory of Operation ...................................................................... 13
Programming the Variable Resistor and Voltage ................... 13
Programming the Potentiometer Divider ............................... 14
ESD Protection ........................................................................... 14
Terminal Voltage Operating Range ......................................... 14
Power-Up Sequence ................................................................... 14
Layout and Power Supply Bypassing ....................................... 15
Constant Bias to Retain Resistance Setting ............................. 15
Evaluation Board ........................................................................ 15
SPI Interface .................................................................................... 16
SPI-Compatible, 3-Wire Serial Bus .......................................... 16
Outline Dimensions ....................................................................... 17
Ordering Guide .......................................................................... 17
Automotive Products ................................................................. 17
REVISION HISTORY
12/10—Rev. B to Rev.C
Added Automotive Parts to Features Section ............................... 1
Added Automotive Products Paragraph...................................... 17
4/09—Rev. A to Rev. B
Changes to Features Section............................................................ 1
Changes to DC Characteristics—Rheostat Mode Parameter and
to DC Characteristics—Potentiometer Divider Mode Parameter,
Table 1 ................................................................................................ 3
Updated Outline Dimensions ....................................................... 17
Changes to Ordering Guide .......................................................... 17
11/03—Rev. 0 to Rev. A
Changes to Electrical Characteristics ............................................ 3
11/03—Revision 0: Initial Version
AD5162
Rev. C | Page 3 of 20
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS: 2.5 kΩ VERSION
VDD = 5 V ± 10%, or 3 V ± 10%; VA = VDD; VB = 0 V; −40°C < TA < +125°C; unless otherwise noted.
Table 1.
Parameter Symbol Conditions Min Typ 1Max Unit
DC CHARACTERISTICS—RHEOSTAT MODE
Resistor Differential Nonlinearity2 R-DNL R
WB
, V
A
= no connect −2 ±0.1 +2 LSB
Resistor Integral Nonlinearity2 R-INL RWB, VA = no connect −14 ±2 +14 LSB
Nominal Resistor Tolerance3 ∆RAB TA = 25°C −20 +55 %
Resistance Temperature Coefficient (∆RAB/RAB )/∆T VAB = VDD, wiper = no connect 35 ppm/°C
Wiper Resistance RWB Code = 0x00, VDD = 5 V 160 200 Ω
DC CHARACTERISTICS—POTENTIOMETER
DIVIDER MODE4
Differential Nonlinearity5 DNL −1.5 ±0.1 +1.5 LSB
Integral Nonlinearity5 INL −2 ±0.6 +2 LSB
Voltage Divider Temperature
Coefficient
(∆VW/VW)/∆T Code = 0x80 15 ppm/°C
Full-Scale Error VWFSE Code = 0xFF −14 −5.5 0 LSB
Zero-Scale Error VWZSE Code = 0x00 0 4.5 12 LSB
RESISTOR TERMINALS
Voltage Range6 VA, VB, VW GND VDD V
Capacitance A, B7 CA, CB f = 1 MHz, measured to GND,
code = 0x80
45 pF
Capacitance W7 CW f = 1 MHz, measured to GND,
code = 0x80
60 pF
Common-Mode Leakage ICM VA = VB = VDD/2 1 nA
DIGITAL INPUTS AND OUTPUTS
Input Logic High VIH VDD = 5 V 2.4 V
Input Logic Low VIL VDD = 5 V 0.8 V
Input Logic High VIH VDD = 3 V 2.1 V
Input Logic Low VIL VDD = 3 V 0.6 V
Input Current I
IL
V
IN
= 0 V or 5 V ±1 µA
Input Capacitance7 CIL 5 pF
POWER SUPPLIES
Power Supply Range V
DD RANGE
2.7 5.5 V
Supply Current IDD VIH = 5 V or VIL = 0 V 3.5 6 µA
Power Dissipation8 PDISS VIH = 5 V or VIL = 0 V, VDD = 5 V 30 µW
Power Supply Sensitivity PSS VDD = 5 V ± 10%, code = midscale ±0.02 ±0.08 %/%
DYNAMIC CHARACTERISTICS9
Bandwidth, −3 dB BW Code = 0x80 4.8 MHz
Total Harmonic Distortion THDW VA = 1 V rms, VB = 0 V, f = 1 kHz 0.1 %
VW Settling Time tS VA = 5 V, VB = 0 V, ±1 LSB error band 1 µs
Resistor Noise Voltage Density e
N_WB
R
WB
= 1.25 kΩ, R
S
= 0 3.2 nV/√Hz
1 Typical specifications represent average readings at 25°C and VDD = 5 V.
2 Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from the ideal between successive tap positions. Parts are guaranteed monotonic.
3 VA = VDD, VB = 0 V, wiper (VW) = no connect.
4 Specifications apply to all VRs.
5 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V.
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
6 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other.
7 Guaranteed by design, but not subject to production test.
8 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
9 All dynamic characteristics use VDD = 5 V.
AD5162
Rev. C | Page 4 of 20
ELECTRICAL CHARACTERISTICS: 10 kΩ, 50 kΩ, AND 100 kΩ VERSIONS
VDD = 5 V ± 10%, or 3 V ± 10%; VA = VDD; VB = 0 V; −40°C < TA < 125°C; unless otherwise noted.
Table 2.
Parameter Symbol Conditions Min Typ1 Max Unit
DC CHARACTERISTICS—RHEOSTAT MODE
Resistor Differential Nonlinearity2 R-DNL RWB, VA = no connect −1 ±0.1 +1 LSB
Resistor Integral Nonlinearity2 R-INL RWB, VA = no connect −2.5 ±0.25 +2.5 LSB
Nominal Resistor Tolerance3 ∆RAB TA = 25°C −20 +20 %
Resistance Temperature Coefficient (∆RAB/RAB )/∆T VAB = VDD, wiper = no connect 35 ppm/°C
Wiper Resistance RWB Code = 0x00, VDD = 5 V 160 200 Ω
DC CHARACTERISTICS—POTENTIOMETER
DIVIDER MODE4
Differential Nonlinearity5 DNL −1 ±0.1 +1 LSB
Integral Nonlinearity5 INL −1 ±0.3 +1 LSB
Voltage Divider Temperature Coefficient (∆VW/VW)/∆T Code = 0x80 15 ppm/°C
Full-Scale Error VWFSE Code = 0xFF −2.5 −1 0 LSB
Zero-Scale Error V
WZSE
Code = 0x00 0 1 2.5 LSB
RESISTOR TERMINALS
Voltage Range6 VA, VB, VW GND VDD V
Capacitance A, B7 CA, CB f = 1 MHz, measured to GND,
code = 0x80
45 pF
Capacitance W7 CW f = 1 MHz, measured to GND,
code = 0x80
60 pF
Common-Mode Leakage ICM VA = VB = VDD/2 1 nA
DIGITAL INPUTS AND OUTPUTS
Input Logic High VIH VDD = 5 V 2.4 V
Input Logic Low VIL VDD = 5 V 0.8 V
Input Logic High V
IH
V
DD
= 3 V 2.1 V
Input Logic Low VIL VDD = 3 V 0.6 V
Input Current IIL VIN = 0 V or 5 V ±1 µA
Input Capacitance CIL 5 pF
POWER SUPPLIES
Power Supply Range VDD RANGE 2.7 5.5 V
Supply Current IDD VIH = 5 V or VIL = 0 V 3.5 6 µA
Power Dissipation PDISS VIH = 5 V or VIL = 0 V, VDD = 5 V 30 µW
Power Supply Sensitivity PSS V
DD
= 5 V ± 10%, code = midscale ±0.02 ±0.08 %/%
DYNAMIC CHARACTERISTICS
Bandwidth, −3 dB BW RAB = 10 kΩ/50 kΩ/100 kΩ,
code = 0x80
600/100/40 kHz
Total Harmonic Distortion THDW VA = 1 V rms, VB = 0 V,
f = 1 kHz, RAB = 10 kΩ
0.1 %
VW Settling Time tS VA = 5 V, VB = 0 V,
±1 LSB error band
2 µs
Resistor Noise Voltage Density eN_WB RWB = 5 kΩ, RS = 0 9 nV/√Hz
1 Typical specifications represent average readings at 25°C and VDD = 5 V.
2 Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from the ideal between successive tap positions. Parts are guaranteed monotonic.
3 VA = VDD, VB = 0 V, wiper (VW) = no connect.
4 Specifications apply to all VRs.
5 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V.
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
6 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other.
7 Guaranteed by design, but not subject to production test.
AD5162
Rev. C | Page 5 of 20
TIMING CHARACTERISTICS: ALL VERSIONS
VDD = 5 V ± 10%, or 3 V ± 10%; VA = VDD; VB = 0 V; −40°C < TA < +125°C; unless otherwise noted.
Table 3.
Parameter Symbol Conditions Min Typ Max Unit
SPI INTERFACE TIMING CHARACTERISTICS1
Clock Frequency fCLK 25 MHz
Input Clock Pulse Width tCH, tCL Clock level high or low 20 ns
Data Setup Time t
DS
5 ns
Data Hold Time tDH 5 ns
CS tCSS Setup Time 15 ns
CS tCSW High Pulse Width 40 ns
CLK Fall to CS tCSH0 Fall Hold Time 0 ns
CLK Fall to CS tCSH1 Rise Hold Time 0 ns
CS tCS1 Rise to Clock Rise Setup 10 ns
1 See the timing diagrams for the locations of measured values (that is, see Figure 42 and Figure 43).
AD5162
Rev. C | Page 6 of 20
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 4.
Parameter Rating
VDD to GND –0.3 V to +7 V
VA, VB, VW to GND VDD
Terminal Current, Ax to Bx, Ax to Wx, Bx to Wx1
Pulsed ±20 mA
Continuous ±5 mA
Digital Inputs and Output Voltage to GND 0 V to 7 V
Operating Temperature Range –40°C to +125°C
Maximum Junction Temperature (TJMAX) 150°C
Storage Temperature –65°C to +150°C
Lead Temperature (Soldering, 10 sec) 300°C
Thermal Resistance, θ
for 10-Lead MSOP2 230°C/W
1 The maximum terminal current is bound by the maximum current handling
of the switches, the maximum power dissipation of the package, and the
maximum applied voltage across any two of the A, B, and W terminals at a
given resistance.
2 The package power dissipation is (TJMAX − TA)/θJA.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
AD5162
Rev. C | Page 7 of 20
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
10
9
8
7
1
2
3
4
B1
A1
W2
W1
B2
CS
SDIGND
6
5CLKVDD
TOP VIEW
AD5162
04108-0-002
Figure 2.
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1 B1 B1 Terminal.
2 A1 A1 Terminal.
3 W2 W2 Terminal.
4 GND Digital Ground.
5 VDD Positive Power Supply.
6 CLK Serial Clock Input. Positive-edge triggered.
7 SDI Serial Data Input.
8 CS Chip Select Input, Active Low. When CS returns high, data is loaded into the DAC register.
9 B2 B2 Terminal.
10 W1 W1 Terminal.
AD5162
Rev. C | Page 8 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
–2.0
–1.5
–1.0
–0.5
0
0.5
RHEOSTAT MODE INL (LSB)
1.0
1.5
2.0
1289632 640 160 192 224 256
CODE (DECIMAL)
04108-0-003
V
DD
= 5.5V
T
A
= 25°C
R
AB
= 10kΩ
V
DD
= 2.7V
Figure 3. R-INL vs. Code vs. Supply Voltages
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
RHEOSTAT MODE DNL (LSB)
1289632 640 160 192 224 256
CODE (DECIMAL)
04108-0-004
T
A
= 25°C
R
AB
= 10kΩ
V
DD
= 2.7V
V
DD
= 5.5V
Figure 4. R-DNL vs. Code vs. Supply Voltages
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
POTENTIOMETER MODE INL (LSB)
1289632 640 160 192 224 256
CODE (DECIMAL)
04108-0-005
R
AB
= 10kΩ
V
DD
= 2.7V
T
A
= –40°C, +25°C, +85°C, +125°C
V
DD
= 5.5V
T
A
= –40°C, +25°C, +85°C, +125°C
Figure 5. INL vs. Code vs. Temperature
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
POTENTIOMETER MODE DNL (LSB)
1289632 640 160 192 224 256
CODE (DECIMAL)
04108-0-006
V
DD
= 2.7V; T
A
= –40°C, +25°C, +85°C, +125°C
R
AB
= 10kΩ
Figure 6. DNL vs. Code vs. Temperature
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
1.0
POTENTIOMETER MODE INL (LSB)
1289632 640 160 192 224 256
CODE (DECIMAL)
04108-0-007
T
A
= 25°C
R
AB
= 10kΩ
V
DD
= 2.7V
V
DD
= 5.5V
Figure 7. INL vs. Code vs. Supply Voltages
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
POTENTIOMETER MODE DNL (LSB)
1289632 640 160 192 224 256
CODE (DECIMAL)
04108-0-008
T
A
= 25°C
R
AB
= 10kΩ
V
DD
= 2.7V
V
DD
= 5.5V
Figure 8. DNL vs. Code vs. Supply Voltages
AD5162
Rev. C | Page 9 of 20
–2.0
–1.5
–1.0
–0.5
0
0.5
RHEOSTAT MODE INL (LSB)
1.0
1.5
2.0
1289632 640 160 192 224 256
CODE (DECIMAL)
04108-0-009
R
AB
= 10kΩ
V
DD
= 2.7V
T
A
= –40°C, +25°C, +85°C, +125°C
V
DD
= 5.5V
T
A
= –40°C, +25°C, +85°C, +125°C
Figure 9. R-INL vs. Code vs. Temperature
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
RHEOSTAT MODE DNL (LSB)
1289632 640 160 192 224 256
CODE (DECIMAL)
04108-0-010
V
DD
= 2.7V, 5.5V; T
A
= –40°C, +25°C, +85°C, +125°C
R
AB
= 10kΩ
Figure 10. R-DNL vs. Code vs. Temperature
–2.0
–1.5
–1.0
–0.5
0
0.5
FSE, FULL-SCALE ERROR (LSB)
1.0
1.5
2.0
TEMPERATURE (°C)
–40 –25 –10 5 20 35 50 65 80 95 110 125
04108-0-011
V
DD
= 5.5V, V
A
= 5.0V
R
AB
= 10kΩ
V
DD
= 2.7V, V
A
= 2.7V
Figure 11. Full-Scale Error vs. Temperature
0
0.75
1.50
2.25
3.00
3.75
4.50
ZSE, ZERO-SCALE ERROR (LSB)
TEMPERATURE (°C)
–40 –25 –10 5 20 35 50 65 80 95 110 125
04108-0-012
V
DD
= 5.5V, V
A
= 5.0V
R
AB
= 10kΩ
V
DD
= 2.7V, V
A
= 2.7V
Figure 12. Zero-Scale Error vs. Temperature
I
DD
, SUPPLY CURRENT (µA)
0.1
1
10
–40 –7 26 59 92 125
TEMPERATURE (°C)
04108-0-013
V
DD
= 5V
V
DD
= 3V
Figure 13. Supply Current vs. Temperature
–20
0
20
40
60
80
100
120
RHEOSTAT MODE TEMPCO (ppm/°C)
1289632 640 160 192 224 256
CODE (DECIMAL)
04108-0-014
R
AB
= 10kΩ
V
DD
= 2.7V
T
A
= –40°C TO +85°C, –40°C TO +125°C
V
DD
= 5.5V
T
A
= –40°C TO +85°C, –40°C TO +125°C
Figure 14. Rheostat Mode Tempco ΔRWB/ΔT vs. Code
AD5162
Rev. C | Page 10 of 20
–30
–20
–10
0
10
20
POTENTIOMETER MODE TEMPCO (ppm/°C)
30
40
50
1289632 640 160 192 224 256
CODE (DECIMAL)
04108-0-015
R
AB
= 10kΩ
V
DD
= 2.7V
T
A
= –40°C TO +85°C, –40°C TO +125°C
V
DD
= 5.5V
T
A
= –40°C TO +85°C, –40°C TO +125°C
Figure 15. Potentiometer Mode Tempco ΔVWB/ΔT vs. Code
–60
–54
–48
–42
–36
–30
–24
–18
–12
–6
0
GAIN (dB)
FREQUENCY (Hz)
10k 1M100k 10M
04108-0-016
0x80
0x40
0x20
0x10
0x08
0x04
0x010x02
Figure 16. Gain vs. Frequency vs. Code, RAB = 2.5 kΩ
–60
–54
–48
–42
–36
–30
–24
–18
–12
–6
0
GAIN (dB)
FREQUENCY (Hz)
1k 100k10k 1M
04108-0-017
0x80
0x40
0x20
0x10
0x08
0x04
0x01
0x02
Figure 17. Gain vs. Frequency vs. Code, RAB = 10 kΩ
–60
–54
–48
–42
–36
–30
–24
–18
–12
–6
0
GAIN (dB)
FREQUENCY (Hz)
1k 100k10k 1M
04108-0-018
0x80
0x40
0x20
0x10
0x08
0x04
0x01
0x02
Figure 18. Gain vs. Frequency vs. Code, RAB = 50 kΩ
–60
–54
–48
–42
–36
–30
–24
–18
–12
–6
0
GAIN (dB)
FREQUENCY (Hz)
1k 100k10k 1M
04108-0-019
0x80
0x40
0x20
0x10
0x08
0x04
0x01
0x02
Figure 19. Gain vs. Frequency vs. Code, RAB = 100 kΩ
–60
–54
–48
–42
–36
–30
–24
–18
–12
–6
0
GAIN (dB)
FREQUENCY (Hz)
10k1k 100k 1M 10M
04108-0-020
100kΩ
60kHz 50kΩ
120kHz 10kΩ
570kHz
2.5kΩ
2.2MHz
Figure 20. −3 dB Bandwidth at Code = 0x80
AD5162
Rev. C | Page 11 of 20
I
DD
, SUPPLY CURRENT (mA)
0.01
1
0.1
10
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
DIGITAL INPUT VOLTAGE (V)
04108-0-025
T
A
= 25°C
V
DD
= 2.7V
V
DD
= 5.5V
Figure 21. Supply Current vs. Digital Input Voltage
04108-0-021
V
W
CLK
Figure 22. Digital Feedthrough
04108-0-022
V
W2
V
W1
Figure 23. Digital Crosstalk
04108-0-024
V
W2
V
W1
Figure 24. Analog Crosstalk
04108-0-026
V
W
Figure 25. Midscale Glitch, Code 0x80 to Code 0x7F
04108-0-023
V
W
CS
Figure 26. Large-Signal Settling Time
AD5162
Rev. C | Page 12 of 20
TEST CIRCUITS
Figure 27 through Figure 32 illustrate the test circuits that define the test conditions used in the product specification tables (see Table 1
and Table 2).
04108-0-027
V
MS
AW
B
DUT
V+
V+ = V
DD
1LSB = V+/2
N
Figure 27. Test Circuit for Potentiometer Divider Nonlinearity Error
(INL, DNL)
04108-0-028
NO CONNECT
IW
VMS
AW
B
DUT
Figure 28. Test Circuit for Resistor Position Nonlinearity Error
(Rheostat Operation: R-INL, R-DNL)
04108-0-029
V
MS2
V
MS1
V
W
AW
B
DUT
IW = VDD/RNOMINAL
RW = [VMS1 – VMS2]/IW
Figure 29. Test Circuit for Wiper Resistance
04108-0-030
∆V
MS
%
DUT
( )
AW
B
V+ ∆V
DD
%
∆V
MS
∆V
DD
∆V
DD
V
A
V
MS
V+ = V
DD
± 10%
PSRR (dB) = 20 LOG
PSS (%/%) =
Figure 30. Test Circuit for Power Supply Sensitivity
(PSS, PSSR)
04108-0-031
+15V
–15V
W
A
2.5V
BV
OUT
OFFSET
GND
DUT
AD8610
V
IN
Figure 31. Test Circuit for Gain vs. Frequency
W
BV
CM
I
CM
A
NC
GND
NC
V
DD
DUT
NC = NO CONNECT
04108-0-033
Figure 32. Test Circuit for Common-Mode Leakage Current
AD5162
Rev. C | Page 13 of 20
THEORY OF OPERATION
The AD5162 is a 256-position, digitally controlled variable
resistor (VR) device.
An internal power-on preset places the wiper at midscale
during power-on, which simplifies the fault condition recovery
at power-up.
PROGRAMMING THE VARIABLE RESISTOR AND
VOLTAGE
Rheostat Operation
The nominal resistance of the RDAC between Terminal A and
Terminal B is available in 2.5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ.
The nominal resistance (RAB) of the VR has 256 contact points
accessed by the wiper terminal and the B terminal contact. The
8-bit data in the RDAC latch is decoded to select one of the
256 possible settings.
A
W
B
A
W
B
A
W
B
04108-0-034
Figure 33. Rheostat Mode Configuration
Assuming that a 10 kΩ part is used, the first connection of the
wiper starts at the B terminal for Data 0x00. Because there is
a 50 Ω wiper contact resistance, such a connection yields a
minimum of 100 Ω (2 × 50 Ω) resistance between Terminal W
and Terminal B. The second connection is the first tap point,
which corresponds to 139 Ω (RWB = RAB/256 + 2 × RW = 39 Ω +
2 × 50 Ω) for Data 0x01. The third connection is the next tap
point, representing 178 Ω (2 × 39 Ω + 2 × 50 Ω) for Data 0x02,
and so on. Each LSB data value increase moves the wiper up the
resistor ladder until the last tap point is reached at 10,100 Ω
(RAB + 2 × RW).
D5
D4
D3
D7
D6
D2
D1
D0
RDAC
LATCH
AND
DECODER
RS
RS
RS
RS
A
W
B
04108-0-035
Figure 34. AD5162 Equivalent RDAC Circuit
The general equation determining the digitally programmed
output resistance between W and B is
W
AB
WB
RR
D
DR ×+×= 2
256
)(
(1)
where:
D is the decimal equivalent of the binary code loaded in the
8-bit RDAC register.
RAB is the end-to-end resistance.
RW is the wiper resistance contributed by the on resistance of
the internal switch.
In summary, if RAB is 10 kΩ and the A terminal is open
circuited, the output resistance, RWB, is set according to the
RDAC latch codes, as listed in Table 6.
Table 6. Codes and Corresponding RWB Resistance
D (Dec) RWB (Ω) Output State
255 9961 Full scale (RAB − 1 LSB + RW)
128 5060 Midscale
1 139 1 LSB
0 100 Zero scale (wiper contact resistance)
Note that in the zero-scale condition, a finite wiper resistance of
100 Ω is present. Care should be taken to limit the current flow
between W and B in this state to a maximum pulse current of
no more than 20 mA. Otherwise, degradation or possible
destruction of the internal switch contact may occur.
Similar to the mechanical potentiometer, the resistance of the
RDAC between Wiper W and Terminal A also produces a
digitally controlled complementary resistance, RWA . When these
terminals are used, the B terminal can be opened. Setting the
resistance value for RWA starts at a maximum value of resistance
and decreases as the data loaded in the latch increases in value.
The general equation for this operation is
W
ABWA RR
D
DR ×+×
−
=2
256
256
)(
(2)
When RAB is 10 kΩ and the B terminal is open circuited, the
output resistance, RWA , is set according to the RDAC latch
codes, as listed in Table 7.
Table 7. Codes and Corresponding RWA Resistance
D (Dec) RWA (Ω) Output State
255 139 Full scale
128 5060 Midscale
1 9961 1 LSB
0 10,060 Zero scale
Typical device-to-device matching is process-lot dependent and
may vary by up to ±30%. Because the resistance element is
processed in thin-film technology, the change in RAB with tem-
perature has a very low temperature coefficient of 35 ppm/°C.
AD5162
Rev. C | Page 14 of 20
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates a voltage divider at
wiper to B and wiper to A, proportional to the input voltage at
A to B. Unlike the polarity of VDD to GND, which must be
positive, voltage across A to B, W to A, and W to B can be at
either polarity.
A
VI
W
B
VO
04108-0-036
Figure 35. Potentiometer Mode Configuration
If ignoring the effect of the wiper resistance for approximation,
connecting the A terminal to 5 V and the B terminal to ground
produces an output voltage at the wiper to B, starting at 0 V up
to 1 LSB less than 5 V. Each LSB of voltage is equal to the voltage
applied across the A and B terminals divided by the 256 positions
of the potentiometer divider. The general equation defining the
output voltage at VW with respect to ground for any valid input
voltage applied to Terminal A and Terminal B is
B
A
WV
D
V
D
DV
256
256
256
)( −
+=
(3)
A more accurate calculation, which includes the effect of wiper
resistance, VW, is
B
AB
WA
A
AB
WB
WV
R
DR
V
R
DR
DV )(
)(
)( +=
(4)
Operation of the digital potentiometer in the divider mode
results in more accurate operation over temperature. Unlike in
the rheostat mode, the output voltage is dependent mainly on
the ratio of the internal resistors RWA and RWB, not on the absolute
values. Therefore, the temperature drift reduces to 15 ppm/°C.
ESD PROTECTION
All digital inputs are protected with a series of input resistors
and parallel Zener ESD structures, as shown in Figure 36 and
Figure 37. This applies to the SDI, CLK, and CS
LOGIC
340Ω
GND
04108-0-037
digital input pins.
Figure 36. ESD Protection of Digital Pins
A, B, W
GND
04108-0-038
Figure 37. ESD Protection of Resistor Terminals
TERMINAL VOLTAGE OPERATING RANGE
The AD5162 VDD and GND power supply defines the boundary
conditions for proper 3-terminal digital potentiometer opera-
tion. Supply signals present on the A, B, and W terminals that
exceed VDD or GND are clamped by the internal forward-biased
diodes (see Figure 38).
GND
A
W
B
VDD
04108-0-039
Figure 38. Maximum Terminal Voltages Set by VDD and GND
POWER-UP SEQUENCE
Because the ESD protection diodes limit the voltage compliance
at the A, B, and W terminals (see Figure 38), it is important to
power VDD/GND before applying voltage to the A, B, and W
terminals; otherwise, the diode is forward-biased such that VDD
is powered unintentionally and may affect the rest of the user’s
circuit. The ideal power-up sequence is in the following order:
GND, VDD, digital inputs, and then VA, VB, VW. The relative
order of powering VA, VB, VW, and the digital inputs is not
important, as long as they are powered after VDD/GND.
AD5162
Rev. C | Page 15 of 20
LAYOUT AND POWER SUPPLY BYPASSING
It is good practice to employ compact, minimum lead length
layout design. The leads to the inputs should be as direct as
possible with a minimum conductor length. Ground paths
should have low resistance and low inductance.
Similarly, it is also good practice to bypass the power supplies with
quality capacitors for optimum stability. Supply leads to the device
should be bypassed with disc or chip ceramic capacitors of 0.01 μF
to 0.1 μF. Low ESR 1 μF to 10 μF tantalum or electrolytic capacitors
should also be applied at the supplies to minimize any transient
disturbance and low frequency ripple (see Figure 39). In addition,
note that the digital ground should be joined remotely to the
analog ground at one point to minimize the ground bounce.
VDD
GND
VDD C3
10FC1
0.1F
AD5162
+
04108-0-040
Figure 39. Power Supply Bypassing
CONSTANT BIAS TO RETAIN RESISTANCE SETTING
For users who desire nonvolatility but cannot justify the additional
cost of the EEMEM, the AD5162 can be considered a low cost
alternative by maintaining a constant bias to retain the wiper
setting. The AD5162 is designed specifically for low power
applications, allowing low power consumption even in battery-
operated systems. The graph in Figure 40 demonstrates the
power consumption from a 3.4 V, 450 mAhr Li-Ion cell phone
battery connected to the AD5162. The measurement over time
shows that the device draws approximately 1.3 μA and consumes
negligible power. Over a course of 30 days, the battery is depleted
by less than 2%, the majority of which is due to the intrinsic
leakage current of the battery itself.
This demonstrates that constantly biasing the potentiometer can be
a practical approach. Most portable devices do not require the
removal of batteries for the purpose of charging. Although the
resistance setting of the AD5162 is lost when the battery needs
replacement, such events occur rather infrequently such that
this inconvenience is justified by the lower cost and smaller size
offered by the AD5162. If total power is lost, the user should be
provided with a means to adjust the setting accordingly.
DAYS
BATTERY LIF E DE PLETED ( %)
0
90
92
94
96
51015
98
100
102
104
106
108
110
20 25 30
04108-0-041
TA= 25°C
Figure 40. Battery Operating Life Depletion
EVALUATION BOARD
An evaluation board, along with all necessary software, is
available to program the AD5162 from any PC running
Windows® 98/2000/XP. The graphical user interface, as shown
in Figure 41, is straightforward and easy to use. More detailed
information is available in the user manual, which is supplied
with the board.
04108-0-044
Figure 41. AD5162 Evaluation Board Software
The AD5162 starts at midscale upon power-up. To increment or
decrement the resistance, simply move the scrollbars in the left of
the software window (see Figure 41). To write a specific value,
use the bit pattern in the upper part of the SDI Write Bit Control
(Hit Run) box and then click Run. The format of writing data
to the device is shown in Table 8.
AD5162
Rev. C | Page 16 of 20
SPI INTERFACE
SPI-COMPATIBLE, 3-WIRE SERIAL BUS
The AD5162 contains a 3-wire, SPI-compatible digital interface
(SDI, CS, and CLK). The 9-bit serial word must be loaded MSB
first. The format of the word is shown in Table 8.
The positive-edge sensitive CLK input requires clean transitions
to avoid clocking incorrect data into the serial input register.
Standard logic families work well. If mechanical switches are
used for product evaluation, they should be debounced by a
flip-flop or another suitable means. When CS is low, the clock
loads data into the serial register on each positive clock edge
(see Figure 42).
The data setup and data hold times in Table 3 determine the
valid timing requirements. The AD5162 uses a 9-bit serial input
data register word that is transferred to the internal RDAC
register when the CS line returns to logic high. Extra MSB bits
are ignored.
Table 8. Serial Data-Word Format1
MSB LSB
B8 B7 B6 B5 B4 B3 B2 B1 B0
A0 D7 D6 D5 D4 D3 D2 D1 D0
(28) (27) (2
0)
1 The values of bits are shown in parentheses.
SDI
CLK
CS
VOUT
RDAC REGISTER LOAD
A0 D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
1
0
0
1
1
04108-0-042
Figure 42. SPI Interface Timing Diagram
(VA = 5 V, VB = 0 V, VW = VOUT)
t
CSH0
t
CSS
t
CL
t
CH
t
DS
t
CSW
t
S
t
CS1
t
CSH1
t
CH
CLK
CS
VOUT
1
0
1
0
1
0
VDD
0
±1LSB
SDI
(DATA IN) Dx Dx
04108-0-043
Figure 43. SPI Interface Detailed Timing Diagram (VA = 5 V, VB = 0 V, VW = VOUT)
AD5162
Rev. C | Page 17 of 20
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-187-BA
091709-A
6°
0°
0.70
0.55
0.40
5
10
1
6
0.50 BSC
0.30
0.15
1.10 MAX
3.10
3.00
2.90
COPLANARITY
0.10
0.23
0.13
3.10
3.00
2.90
5.15
4.90
4.65
PIN 1
IDENTIFIER
15° MAX
0.95
0.85
0.75
0.15
0.05
Figure 44. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
ORDERING GUIDE
Model1, 2, 3 RAB (kΩ) Temperature Package Description Package Option Branding
AD5162BRM2.5 2.5 –40°C to +125°C 10-Lead MSOP RM-10 D0Q
AD5162BRM2.5-RL7 2.5 –40°C to +125°C 10-Lead MSOP RM-10 D0Q
AD5162BRM10 10 –40°C to +125°C 10-Lead MSOP RM-10 D0R
AD5162BRM50 50 –40°C to +125°C 10-Lead MSOP RM-10 D0S
AD5162BRM50-RL7 50 –40°C to +125°C 10-Lead MSOP RM-10 D0S
AD5162BRM100 100 –40°C to +125°C 10-Lead MSOP RM-10 D0T
AD5162BRM100-RL7 100 –40°C to +125°C 10-Lead MSOP RM-10 D0T
AD5162BRMZ2.5 2.5 –40°C to +125°C 10-Lead MSOP RM-10 D74
AD5162BRMZ2.5-RL7 2.5 –40°C to +125°C 10-Lead MSOP RM-10 D74
AD5162BRMZ10 10 –40°C to +125°C 10-Lead MSOP RM-10 D9K
AD5162BRMZ10-RL7 10 –40°C to +125°C 10-Lead MSOP RM-10 D9K
AD5162BRMZ50 50 –40°C to +125°C 10-Lead MSOP RM-10 D0S#
AD5162BRMZ50-RL7 50 –40°C to +125°C 10-Lead MSOP RM-10 D0S#
AD5162BRMZ100 100 –40°C to +125°C 10-Lead MSOP RM-10 D0T#
AD5162BRMZ100-RL7 100 –40°C to +125°C 10-Lead MSOP RM-10 D0T#
AD5162WBRMZ100-RL7 100 –40°C to +125°C 10-Lead MSOP RM-10 D0T#
AD5162EVAL Evaluation Board
1 Z = RoHS Compliant Part.
2 W = Qualified for Automotive Applications.
3 The evaluation board is shipped with the 10 k Ω R
AB resistor option; however, the board is compatible with all available resistor value options.
AUTOMOTIVE PRODUCTS
The AD5162W model is available with controlled manufacturing to support the quality and reliability requirements of automotive
applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers
should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in
automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to
obtain the specific Automotive Reliability reports for these models.
AD5162
Rev. C | Page 18 of 20
NOTES
AD5162
Rev. C | Page 19 of 20
NOTES
AD5162
Rev. C | Page 20 of 20
NOTES
©2003–2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04108-0-12/10(C)