© 2006 Microchip Technology Inc. DS22026A-page 1
MCP1725
Features
• 500 mA Output Current Capability
• Input Operating Voltage Range: 2.3V to 6.0V
• Adjustable Output Voltage Range: 0.8V to 5.0V
• Standard Fixed Output Voltages:
- 0.8V, 1.2V, 1.8V, 2.5V, 3.0V, 3.3V, 5.0V
• Other Fixed Output Voltage Options Available
Upon Request
• Low Dropout Voltage: 210 mV Typical at 500 mA
• Typical Output Voltage Tolerance: 0.5%
• Stable with 1.0 µF Ceramic Output Capacitor
• Fast response to Load Transients
• Low Supply Current: 120 µA (typ)
• Low Shutdown Supply Current: 0.1 µA (typ)
• Adjustable Delay on Power Good Output
• Short Circuit Current Limiting and
Overtemperature Protection
• 2x3 DFN-8 and SOIC-8 Package Options
Applications
• High-Speed Driver Chipset Power
• Networking Backplane Cards
• Notebook Computers
• Network Interface Cards
• Palmtop Computers
• Video Graphics Adapters
• 2.5V to 1.XV Regulators
Description
The MCP1725 is a 500 mA Low Dropout (LDO) linear
regulator that provides high current and low output
voltages in a very small package. The MCP1725
comes in a fixed (or adjustable) output voltage version,
with an output voltage range of 0.8V to 5.0V. The
500 mA output current capability, combined with the
low output voltage capability, make the MCP1725 a
good choice for new sub-1.8V output voltage LDO
applications that have high current demands.
The MCP1725 is stable using ceramic output
capacitors that inherently provide lower output noise
and reduce the size and cost of the entire regulator
solution. Only 1 µF of output capacitance is needed to
stabilize the LDO.
Using CMOS construction, the quiescent current
consumed by the MCP1725 is typically less than
120 µA over the entire input voltage range, making it
attractive for portable computing applications that
demand high output current. When shut down, the
quiescent current is reduced to less than 0.1 µA.
The scaled-down output voltage is internally monitored
and a power good (PWRGD) output is provided when
the output is within 92% of regulation (typical). An
external capacitor can be used on the CDELAY pin to
adjust the delay from 200 µs to 300 ms.
The overtemperature and short circuit current-limiting
provide additional protection for the LDO during system
fault conditions.
Package Types
VIN
VIN
SHDN
GND PWRGD
CDELAY
Sense
VOUT
VIN
VIN
SHDN
GND PWRGD
CDELAY
ADJ
VOUT
Adjustable (SOIC-8) Fixed (SOIC-8)
VIN
VIN
SHDN
GND PWRGD
CDELAY
Sense
VOUT
11
22
33
44
55
66
77
88
Fixed (2x3 DFN)
VIN
VIN
SHDN
GND PWRGD
CDELAY
VOUT
Adjustable (2x3 DFN)
ADJ
1
2
3
45
6
7
81
2
3
45
6
7
8
Note: DFN tab is at ground potential.
500 mA, Low Voltage, Low Quiescent Current LDO Regulator
MCP1725
DS22026A-page 2 © 2006 Microchip Technology Inc.
Typical Application
MCP1725 Adjustable Output Voltage
VIN
SHDN
GND PWRGD
CDELAY
ADJ
VOUT
1
2
3
45
6
7
8
1µF
PWRGD
VOUT = 1.2V @ 500 mA
100 kΩ
4.7 µF
VIN = 2.3V to 2.8V
On
Off
VIN
20 kΩ
40 kΩ
R1
R2
C1C2
R3
1000 pF
C3
MCP1725 Fixed Output Voltage
VIN
SHDN
GND PWRGD
CDELAY
Sense
VOUT
1
2
3
45
6
7
8
PWRGD
VOUT = 1.8V @ 500 mA
VIN = 2.3V to 2.8V
On
Off
VIN
1µF
100 kΩ
4.7 µF
C1C2
R1
1000 pF
C3
© 2006 Microchip Technology Inc. DS22026A-page 3
MCP1725
Functional Block Diagram - Adjustable Output
EA
+
–
VOUT
PMOS
Rf
Cf
ISNS
Overtemperature
VREF
Comp
92% of VREF
TDELAY
PWRGD
CDELAY
VIN
Driver w/limit
and SHDN
GND
Soft-Start
ADJ
Undervoltage
Lock Out
VIN
Reference
SHDN
SHDN
SHDN
Sensing
(UVLO)
MCP1725
DS22026A-page 4 © 2006 Microchip Technology Inc.
Functional Block Diagram - Fixed Output
EA
+
–
VOUT
PMOS
Rf
Cf
ISNS
Overtemperature
VREF
Comp
92% of VREF
TDELAY
PWRGD
CDELAY
VIN
Driver w/limit
and SHDN
GND
Soft-Start
Sense
Undervoltage
Lock Out
VIN
Reference
SHDN
SHDN
SHDN
Sensing
(UVLO)
© 2006 Microchip Technology Inc. DS22026A-page 5
MCP1725
1.0 ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings †
VIN....................................................................................6.5V
Maximum Voltage on Any Pin ... (GND – 0.3V) to (VIN + 0.3)V
Maximum Power Dissipation......... Internally-Limited (Note 6)
Output Short Circuit Duration ................................ Continuous
Storage temperature .....................................-65°C to +150°C
Maximum Junction Temperature, TJ........................... +150°C
ESD protection on all pins (HBM/MM).............. ≥ 2kV; ≥ 200V
† Notice: Stresses above those listed under “Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of
the device at those or any other conditions above those
indicated in the operational listings of this specification
is not implied. Exposure to maximum rating conditions
for extended periods may affect device reliability.
AC/DC CHARACTERISTICS
Electrical Specifications: Unless otherwise noted, VIN = VOUT(MAX) + VDROPOUT(MAX) (Note 1), VR = 1.8V for Adjustable Output,
IOUT = 1 mA, CIN = COUT = 4.7 µF (X7R Ceramic), TA = +25°C.
Boldface type applies for junction temperatures, TJ (Note 7) of -40°C to +125°C
Parameters Sym Min Typ Max Units Conditions
Input Operating Voltage VIN 2.3 6.0 VNote 1
Input Quiescent Current Iq— 120 220 µA IL = 0 mA, VIN = Note 1,
VOUT = 0.8V to 5.0V
Input Quiescent Current for
SHDN Mode
ISHDN —0.1 3µA SHDN = GND
Maximum Output Current IOUT 500 ——mAV
IN = 2.3V to 6.0V
VR = 0.8V to 5.0V, Note 1
Line Regulation ΔVOUT/
(VOUT x ΔVIN)
— ±0.05 ±0.16 %/V (Note 1) ≤ VIN ≤ 6V
Load Regulation ΔVOUT/VOUT -1.0 ±0.5 1.0 %I
OUT = 1 mA to 500 mA,
(Note 4)
Output Short Circuit Current IOUT_SC —1.2—AR
LOAD <0.1Ω, Peak Current
Adjust Pin Characteristics (Adjustable Output Only)
Adjust Pin Reference Voltage VADJ 0.402 0.410 0.418 VV
IN = 2.3V to VIN =6.0V,
IOUT = 1 mA
Adjust Pin Leakage Current IADJ -10 ±0.01 +10 nA VIN = 6.0V, VADJ =0Vto6V
Adjust Temperature Coefficient TCVOUT — 40 — ppm/°C Note 3
Fixed-Output Characteristics (Fixed Output Only)
Voltage Regulation VOUT VR - 2.5% VR ±0.5% VR + 2.5% VNote 2
Note 1: The minimum VIN must meet two conditions: VIN ≥ 2.3V and VIN ≥ VOUT(MAX) + VDROPOUT(MAX).
2: VR is the nominal regulator output voltage for the fixed cases. VR = 1.2V, 1.8V, etc. VR is the desired set point output
voltage for the adjustable cases. VR = VADJ * ((R1/R2)+1). Figure 4-1.
3: TCVOUT = (VOUT-HIGH – VOUT-LOW) *106 / (VR * ΔTemperature). VOUT-HIGH is the highest voltage measured over the
temperature range. VOUT-LOW is the lowest voltage measured over the temperature range.
4: Load regulation is measured at a constant junction temperature using low duty-cycle pulse testing. Load regulation is
tested over a load range from 1 mA to the maximum specified output current.
5: Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its
nominal value that was measured with an input voltage of VOUT = VR + VDROPOUT(MAX).
6: The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction
temperature and the thermal resistance from junction to air. (i.e., TA, TJ, θJA). Exceeding the maximum allowable power
dissipation will cause the device operating junction temperature to exceed the maximum +150°C rating. Sustained
junction temperatures above +150°C can impact device reliability.
7: The junction temperature is approximated by soaking the device under test at an ambient temperature equal to the
desired junction temperature. The test time is small enough such that the rise in the junction temperature over the
ambient temperature is not significant.
MCP1725
DS22026A-page 6 © 2006 Microchip Technology Inc.
Dropout Characteristics
Dropout Voltage VIN-VOUT — 210 350 mV IOUT = 500 mA, (Note 5)
VIN(MIN) =2.3V
Power Good Characteristics
PWRGD Input Voltage Operat-
ing Range
VPWRGD_VIN 1.0 — 6.0 V TA = +25°C
1.2 —6.0 TA = -40°C to +125°C
For VIN < 2.3V, ISINK = 100 µA
PWRGD Threshold Voltage
(Referenced to VOUT)
VPWRGD_TH ———%V
OUT Falling Edge
89 92 95 VOUT < 2.5V Fixed, VOUT =
Adj.
90 92 94 VOUT >= 2.5V Fixed
PWRGD Threshold Hysteresis VPWRGD_HYS 1.0 2.0 3.0 %VOUT
PWRGD Output Voltage Low VPWRGD_L —0.20.4 VI
PWRGD SINK = 1.2 mA,
ADJ = 0V, SENSE = 0V
PWRGD Leakage PWRGD_LK —1—nAV
PWRGD = VIN = 6.0V
PWRGD Time Delay TPG Rising Edge
RPULLUP = 10 kΩ
ICDELAY = 140 nA (Typ)
— 200 — µs CDELAY = OPEN
10 30 55 ms CDELAY =0.01µF
— 300 — ms CDELAY =0.1µF
Detect Threshold to PWRGD
Active Time Delay
TVDET-PWRGD — 200 — µs VADJ or VSENSE =
VPWRGD_TH + 20 mV to
VPWRGD_TH - 20 mV
Shutdown Input
Logic High Input VSHDN-HIGH 45 ——%V
IN VIN = 2.3V to 6.0V
Logic Low Input VSHDN-LOW ——15 %VIN VIN = 2.3V to 6.0V
SHDN Input Leakage Current SHDNILK -0.1 ±0.001 +0.1 µA VIN =6V, SHDN =VIN,
SHDN = GND
AC/DC CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise noted, VIN = VOUT(MAX) + VDROPOUT(MAX) (Note 1), VR = 1.8V for Adjustable Output,
IOUT = 1 mA, CIN = COUT = 4.7 µF (X7R Ceramic), TA = +25°C.
Boldface type applies for junction temperatures, TJ (Note 7) of -40°C to +125°C
Parameters Sym Min Typ Max Units Conditions
Note 1: The minimum VIN must meet two conditions: VIN ≥ 2.3V and VIN ≥ VOUT(MAX) + VDROPOUT(MAX).
2: VR is the nominal regulator output voltage for the fixed cases. VR = 1.2V, 1.8V, etc. VR is the desired set point output
voltage for the adjustable cases. VR = VADJ * ((R1/R2)+1). Figure 4-1.
3: TCVOUT = (VOUT-HIGH – VOUT-LOW) *106 / (VR * ΔTemperature). VOUT-HIGH is the highest voltage measured over the
temperature range. VOUT-LOW is the lowest voltage measured over the temperature range.
4: Load regulation is measured at a constant junction temperature using low duty-cycle pulse testing. Load regulation is
tested over a load range from 1 mA to the maximum specified output current.
5: Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its
nominal value that was measured with an input voltage of VOUT = VR + VDROPOUT(MAX).
6: The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction
temperature and the thermal resistance from junction to air. (i.e., TA, TJ, θJA). Exceeding the maximum allowable power
dissipation will cause the device operating junction temperature to exceed the maximum +150°C rating. Sustained
junction temperatures above +150°C can impact device reliability.
7: The junction temperature is approximated by soaking the device under test at an ambient temperature equal to the
desired junction temperature. The test time is small enough such that the rise in the junction temperature over the
ambient temperature is not significant.
© 2006 Microchip Technology Inc. DS22026A-page 7
MCP1725
TEMPERATURE SPECIFICATIONS
AC Performance
Output Delay From SHDN TOR — 100 — µs SHDN = GND to VIN
VOUT = GND to 95% VR
Output Noise eN—2.0—µV/√Hz IOUT = 200 mA, f = 1 kHz,
COUT = 10 µF (X7R Ceramic),
VOUT = 2.5V
Power Supply Ripple Rejection
Ratio
PSRR — 60 — dB f = 100 Hz, COUT = 10 µF,
IOUT = 10 mA,
VINAC = 30 mV pk-pk,
CIN = 0 µF
Thermal Shutdown Temperature TSD — 150 — °C IOUT = 100 µA, VOUT = 1.8V,
VIN = 2.8V
Thermal Shutdown Hysteresis ΔTSD —10—°CI
OUT = 100 µA, VOUT = 1.8V,
VIN = 2.8V
Electrical Specifications: Unless otherwise indicated, all limits apply for VIN = 2.3V to 6.0V.
Parameters Sym Min Typ Max Units Conditions
Temperature Ranges
Operating Junction Temperature Range TJ-40 — +125 °C Steady State
Maximum Junction Temperature TJ— — +150 °C Transient
Storage Temperature Range TA-65 — +150 °C
Thermal Package Resistances
Thermal Resistance, 8LD 2x3 DFN θJA — 52 — °C/W 4-Layer JC51-7
Standard Board with
vias
Thermal Resistance, 8LD SOIC θJA — 150 — °C/W 4-Layer JC51-7
Standard Board
AC/DC CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise noted, VIN = VOUT(MAX) + VDROPOUT(MAX) (Note 1), VR = 1.8V for Adjustable Output,
IOUT = 1 mA, CIN = COUT = 4.7 µF (X7R Ceramic), TA = +25°C.
Boldface type applies for junction temperatures, TJ (Note 7) of -40°C to +125°C
Parameters Sym Min Typ Max Units Conditions
Note 1: The minimum VIN must meet two conditions: VIN ≥ 2.3V and VIN ≥ VOUT(MAX) + VDROPOUT(MAX).
2: VR is the nominal regulator output voltage for the fixed cases. VR = 1.2V, 1.8V, etc. VR is the desired set point output
voltage for the adjustable cases. VR = VADJ * ((R1/R2)+1). Figure 4-1.
3: TCVOUT = (VOUT-HIGH – VOUT-LOW) *106 / (VR * ΔTemperature). VOUT-HIGH is the highest voltage measured over the
temperature range. VOUT-LOW is the lowest voltage measured over the temperature range.
4: Load regulation is measured at a constant junction temperature using low duty-cycle pulse testing. Load regulation is
tested over a load range from 1 mA to the maximum specified output current.
5: Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its
nominal value that was measured with an input voltage of VOUT = VR + VDROPOUT(MAX).
6: The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction
temperature and the thermal resistance from junction to air. (i.e., TA, TJ, θJA). Exceeding the maximum allowable power
dissipation will cause the device operating junction temperature to exceed the maximum +150°C rating. Sustained
junction temperatures above +150°C can impact device reliability.
7: The junction temperature is approximated by soaking the device under test at an ambient temperature equal to the
desired junction temperature. The test time is small enough such that the rise in the junction temperature over the
ambient temperature is not significant.
MCP1725
DS22026A-page 8 © 2006 Microchip Technology Inc.
2.0 TYPICAL PERFORMANCE CURVES
Note: Unless otherwise indicated, VIN = VOUT + 0.5V or VIN = 2.3V (whichever is greater), IOUT = 1 mA, CIN = COUT = 4.7 µF Ceramic
(X7R), SHDN = VIN, CDELAY = Open, Fixed Output Version, and TA = +25°C.
Note: Junction Temperature (TJ) is approximated by soaking the device under test to an ambient temperature equal to the desired
junction temperature. The test time is small enough such that the rise in Junction Temperature over the Ambient temperature is not
significant.
FIGURE 2-1: Quiescent Current vs. Input
Voltage (1.8V Adjustable).
FIGURE 2-2: Ground Current vs. Load
Current (1.2V Adjustable).
FIGURE 2-3: Quiescent Current vs.
Junction Temperature (1.8V Adjustable).
FIGURE 2-4: Line Regulation vs.
Temperature (1.8V Adjustable).
FIGURE 2-5: Load Regulation vs.
Temperature (Adjustable Version).
FIGURE 2-6: Adjust Pin Voltage vs.
Temperature.
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and
are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed.
In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power
supply range) and therefore outside the warranted range.
80
90
100
110
120
130
140
150
23456
Input Voltage (V)
Quiescent Current (µA)
-45°C
0°C +25°C
+90°C
+130°C
IOUT = 0 mA
120
130
140
150
160
170
180
190
200
210
0 100 200 300 400 500
Load Current (mA)
Ground Current (µA)
VIN = 5.0V
VIN = 3.3V
VIN = 2.5V
VOUT = 1.2V Adj
80
90
100
110
120
130
140
150
-45 -20 5 30 55 80 105 130
Temperature (°C)
Quiescent Current (µA)
VIN = 5.0V
VIN = 2.3V
VIN = 3.3V
VIN = 6.0V
IOUT = 0 mA
0.00
0.02
0.04
0.06
0.08
0.10
0.12
-45 -20 5 30 55 80 105 130
Temperature (°C)
Line Regulation (%/V)
IOUT = 1 mA
IOUT = 50 mA
IOUT = 250 mA
IOUT = 100 mA
IOUT = 500 mA
VIN = 2.3V to 6.0V
0.00
0.02
0.04
0.06
0.08
0.10
0.12
0.14
0.16
0.18
0.20
-45 -20 5 30 55 80 105 130
Temperature (°C)
Load Regulation (%)
VOUT = 5V
VOUT = 3.3V
VOUT = 1.8V VOUT = 0.8V
IOUT = 1.0 mA to 500 mA
0.408
0.409
0.410
0.411
0.412
-45 -20 5 30 55 80 105 130
Temperature (°C)
Adjust Pin Voltage (V)
VIN = 5.0V
VIN = 6.0V
VIN = 2.3V, 3.0V, 4.0V
IOUT = 1 mA
© 2006 Microchip Technology Inc. DS22026A-page 9
MCP1725
Note: Unless otherwise indicated, VIN = VOUT + 0.5V or VIN = 2.3V (whichever is greater), IOUT = 1 mA,
CIN = COUT = 4.7 µF Ceramic (X7R), SHDN = VIN, CDELAY = Open, Fixed Output Version, and TA = +25°C.
FIGURE 2-7: Dropout Voltage vs. Load
Current (Adjustable Version).
FIGURE 2-8: Dropout Voltage vs.
Temperature (Adjustable Version).
FIGURE 2-9: Power Good (PWRGD)
Time Delay vs. Temperature (Adjustable
Version).
FIGURE 2-10: Quiescent Current vs. Input
Voltage (0.8V Fixed).
FIGURE 2-11: Quiescent Current vs. Input
Voltage (2.5V Fixed).
FIGURE 2-12: Ground Current vs. Load
Current.
0.00
0.05
0.10
0.15
0.20
0.25
0 100 200 300 400 500
Load Current (mA)
Dropout Voltage (V)
VOUT = 2.5V
VOUT = 5.0V
0.16
0.18
0.20
0.22
0.24
0.26
0.28
-45 -20 5 30 55 80 105 130
Temperature (°C)
Dropout Voltage (V)
VOUT = 2.5V
VOUT = 5.0V VOUT = 3.3V
IOUT = 500 mA
25
26
27
28
29
30
31
32
33
34
35
-45 -20 5 30 55 80 105 130
Temperature (°C)
Power Good Time Delay (ms)
VIN = 2.3V
VIN = 3.0V
VIN = 5.0V
CDELAY = 0.01 µF
IOUT = 0 mA
80
90
100
110
120
130
140
150
23456
Input Voltage (V)
Quiescent Current (µA)
-45°C
+130°C
+90°C
+25°C
0°C
IOUT = 0 mA
90
100
110
120
130
140
150
3 3.5 4 4.5 5 5.5 6
Input Voltage (V)
Quiescent Current (µA)
-45°C 0°C +25°C +90°C
+135°C
IOUT = 0 mA
110
130
150
170
190
210
0 100 200 300 400 500
Load Current (mA)
Ground Current (µA)
VOUT = 5.0V
VOUT = 2.5V
MCP1725
DS22026A-page 10 © 2006 Microchip Technology Inc.
Note: Unless otherwise indicated, VIN = VOUT + 0.5V or VIN = 2.3V (whichever is greater), IOUT = 1 mA,
CIN = COUT = 4.7 µF Ceramic (X7R), SHDN = VIN, CDELAY = Open, Fixed Output Version, and TA = +25°C.
FIGURE 2-13: Quiescent Current vs.
Junction Temperature.
FIGURE 2-14: ISHDN vs. Temperature.
FIGURE 2-15: Line Regulation vs.
Temperature (0.8V Fixed).
FIGURE 2-16: Line Regulation vs.
Temperature (2.5V Fixed).
FIGURE 2-17: Load Regulation vs.
Temperature (VOUT < 2.5V Fixed).
FIGURE 2-18: Load Regulation vs.
Temperature (VOUT
≥
2.5V Fixed).
80
90
100
110
120
130
140
-45 -20 5 30 55 80 105 130
Junction Temperature (°C)
Quiescent Current (µA)
VOUT = 0.8V
VOUT = 2.5V
IOUT = 0 mA
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
-45 -20 5 30 55 80 105 130
Temperature (°C)
ISHDN (µA)
VIN = 2.3V
VIN = 6.0V
VIN = 3.3V
VOUT = 0.8V
0.00
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
0.10
-45 -20 5 30 55 80 105 130
Temperature (°C)
Line Regulation (%/V)
IOUT = 1 mA
IOUT = 500 mA
IOUT = 250 mA
IOUT = 100 mA
IOUT = 50 mA
VIN = 2.3V to 6.0
V
VOUT = 0.8
V
0.010
0.015
0.020
0.025
0.030
0.035
0.040
0.045
0.050
-45 -20 5 30 55 80 105 130
Temperature (°C)
Line Regulation (%/V)
IOUT = 1 mA
IOUT = 250 mA IOUT = 500 mA
IOUT = 100 mA
IOUT = 50 mA
VOUT = 2.5
V
VIN = 3.0V to 6.0
V
0.02
0.04
0.06
0.08
0.10
0.12
0.14
0.16
0.18
0.20
-45 -20 5 30 55 80 105 130
Temperature (°C)
Load Regulation (%)
VOUT = 1.2V
IOUT = 1.0 mA to 500 mA
VOUT = 0.8V
-0.35
-0.30
-0.25
-0.20
-0.15
-0.10
-0.05
0.00
-45 -20 5 30 55 80 105 130
Temperature (°C)
Load Regulation (%)
VOUT = 2.5V
VOUT = 5.0V
IOUT = 1.0 mA to 500 mA
© 2006 Microchip Technology Inc. DS22026A-page 11
MCP1725
Note: Unless otherwise indicated, VIN = VOUT + 0.5V or VIN = 2.3V (whichever is greater), IOUT = 1 mA,
CIN = COUT = 4.7 µF Ceramic (X7R), SHDN = VIN, CDELAY = Open, Fixed Output Version, and TA = +25°C.
FIGURE 2-19: Dropout Voltage vs. Load
Current.
FIGURE 2-20: Dropout Voltage vs.
Temperature.
FIGURE 2-21: Short Circuit Current vs.
Input Voltage.
FIGURE 2-22: Output Noise Voltage
Density vs. Frequency.
FIGURE 2-23: Power Supply Ripple
Rejection (PSRR) vs. Frequency (VOUT = 1.2V
Adj.).
FIGURE 2-24: Power Supply Ripple
Rejection (PSRR) vs. Frequency (VOUT = 1.2V
Adj.).
0.00
0.05
0.10
0.15
0.20
0.25
0 100 200 300 400 500
Load Current (mA)
Dropout Voltage (V)
VOUT = 5.0V
VOUT = 2.5V
0.10
0.12
0.14
0.16
0.18
0.20
0.22
0.24
0.26
0.28
-45 -20 5 30 55 80 105 130
Temperature (°C)
Dropout Voltage (V)
VOUT = 5.0V
VOUT = 2.5V
ILOAD = 500 mA
0.50
0.60
0.70
0.80
0.90
1.00
1.10
1.20
3.03.54.04.55.05.56.0
Input Voltage (V)
Short Circuit Current (A)
ISTEADY STATE
IPEAK
VOUT = 2.5V Fixed
CIN = 3000 µF
0.001
0.01
0.1
1
10
0.01 0.1 1 10 100 1000
Frequency (kHz)
Noise (μV/¥Hz)
VIN = 3.3V
VOUT = 2.5V
VIN = 2.3V
VOUT = 0.8V
ILOAD = 200 mA
COUT = 1 μF
CIN = 10 μF
-80
-70
-60
-50
-40
-30
-20
-10
0
0.01 0.1 1 10 100 1000
Frequency (kHz)
PSRR (dB)
VR=1.2V Adj
COUT=4.7 μF ceramic X7R
VIN=2.5V
CIN=0 μF
IOUT=10 mA
-80
-70
-60
-50
-40
-30
-20
-10
0
0.01 0.1 1 10 100 1000
Frequency (kHz)
PSRR (dB)
VR=1.2V Adj
COUT=22 μF ceramic X7R
VIN=2.5V
CIN=0 μF
IOUT=10 mA
MCP1725
DS22026A-page 12 © 2006 Microchip Technology Inc.
Note: Unless otherwise indicated, VIN = VOUT + 0.5V or VIN = 2.3V (whichever is greater), IOUT = 1 mA,
CIN = COUT = 4.7 µF Ceramic (X7R), SHDN = VIN, CDELAY = Open, Fixed Output Version, and TA = +25°C.
FIGURE 2-25: Power Supply Ripple
Rejection (PSRR) vs. Frequency (VOUT = 2.5V
Fixed).
FIGURE 2-26: Power Supply Ripple
Rejection (PSRR) vs. Frequency (VOUT = 2.5V
Fixed).
FIGURE 2-27: 2.5V (Adj.) Startup from VIN.
FIGURE 2-28: 2.5V (Adj.) Startup from
Shutdown.
FIGURE 2-29: Power Good (PWRGD)
Timing with Cdelay of 1000 pF (2.5V Fixed).
FIGURE 2-30: Power Good (PWRGD)
Timing with CDELAY of 0.01 µF (2.5V Fixed).
-80
-70
-60
-50
-40
-30
-20
-10
0
0.01 0.1 1 10 100 1000
Frequency (KHz)
PSRR (dB)
VR=2.5V Fixed
COUT=4.7 μF ceramic X7R
VIN=3.3V
CIN=0 μF
IOUT=10 mA
-80
-70
-60
-50
-40
-30
-20
-10
0
0.01 0.1 1 10 100 1000
Frequency (KHz)
PSRR (dB)
VR=2.5V Fixed
COUT=22 μF ceramic X7R
VIN=3.3V
CIN=0 μF
IOUT=10 mA
© 2006 Microchip Technology Inc. DS22026A-page 13
MCP1725
Note: Unless otherwise indicated, VIN = VOUT + 0.5V or VIN = 2.3V (whichever is greater), IOUT = 1 mA,
CIN = COUT = 4.7 µF Ceramic (X7R), SHDN = VIN, CDELAY = Open, Fixed Output Version, and TA = +25°C.
FIGURE 2-31: Dynamic Line Response
(5.0V Fixed).
FIGURE 2-32: Dynamic Line Response
(2.5V Fixed).
FIGURE 2-33: Dynamic Load Response
(2.5V Fixed, 1 mA to 500 mA).
FIGURE 2-34: Dynamic Load Response
(2.5V Fixed, 10 mA to 500 mA).
MCP1725
DS22026A-page 14 © 2006 Microchip Technology Inc.
3.0 PIN DESCRIPTION
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1: PIN FUNCTION TABLE
3.1 Input Voltage Supply (VIN)
Connect the unregulated or regulated input voltage
source to VIN. If the input voltage source is located
several inches away from the LDO, or the input source
is a battery, it is recommended that an input capacitor
be used. A typical input capacitance value of 1 µF to
10 µF should be sufficient for most applications.
3.2 Shutdown Control Input (SHDN)
The SHDN input is used to turn the LDO output voltage
on and off. When the SHDN input is at a logic-high
level, the LDO output voltage is enabled. When the
SHDN input is pulled to a logic-low level, the LDO
output voltage is disabled. When the SHDN input is
pulled low, the PWRGD output also goes low and the
LDO enters a low quiescent current shutdown state
where the typical quiescent current is 0.1 µA.
3.3 Ground (GND)
Connect the GND pin of the LDO to a quiet circuit
ground. This will help the LDO power supply rejection
ratio and noise performance. The ground pin of the
LDO only conducts the quiescent current of the LDO
(typically 120 µA), so a heavy trace is not required.
For applications have switching or noisy inputs tie the
GND pin to the return of the output capacitor. Ground
planes help lower inductance and voltage spikes
caused by fast transient load currents and are
recommended for applications that are subjected to
fast load transients.
3.4 Power Good Output (PWRGD)
The PWRGD output is an open-drain output used to
indicate when the LDO output voltage is within 92%
(typically) of its nominal regulation value. The PWRGD
threshold has a typical hysteresis value of 2%. The
PWRGD output is typically delayed by 200 µs (typical,
no capacitance on CDELAY pin) from the time the LDO
output is within 92% + 3% (max hysteresis) of the
regulated output value on power-up. This delay time is
controlled by the CDELAY pin.
3.5 Power Good Delay Set-Point Input
(CDELAY)
The CDELAY input sets the power-up delay time for the
PWRGD output. By connecting an external capacitor
from the CDELAY pin to ground, the typical delay times
for the PWRGD output can be adjusted from 200 µs (no
capacitance) to 300 ms (0.1 µF capacitor). This allows
for the optimal setting of the system reset time.
Fixed Output Adjustable
Output Name Description
11V
IN Input Voltage Supply
22V
IN Input Voltage Supply
3 3 SHDN Shutdown Control Input (active-low)
4 4 GND Ground
5 5 PWRGD Power Good Output (open-drain)
66C
DELAY Power Good Delay Set-Point Input
—7 ADJ Voltage Sense Input (adjustable version)
7—Sense Voltage Sense Input (fixed voltage version)
88V
OUT Regulated Output Voltage
Exposed Pad Exposed Pad EP Exposed Pad of the DFN Package (ground potential)
© 2006 Microchip Technology Inc. DS22026A-page 15
MCP1725
3.6 Output Voltage Sense/Adjust
Input (ADJ/Sense)
3.6.1 ADJ
For adjustable applications, the output voltage is
connected to the ADJ input through a resistor divider
that sets the output voltage regulation value. This
provides the user the capability to set the output
voltage to any value they desire within the 0.8V to 5.0V
range of the device.
3.6.2 Sense
For fixed output voltage versions of the device, the
SENSE input is used to provide output voltage
feedback to the internal circuitry of the MCP1725. The
SENSE pin typically improves load regulation by
allowing the device to compensate for voltage drops
due to packaging and circuit board layout.
3.7 Regulated Output Voltage (VOUT)
The VOUT pin(s) is the regulated output voltage of the
LDO. A minimum output capacitance of 1.0 µF is
required for LDO stability. The MCP1725 is stable with
ceramic, tantalum and aluminum-electrolytic
capacitors. See Section 4.3 “Output Capacitor” for
output capacitor selection guidance.
3.8 Exposed Pad (EP)
The 2x3 DFN package has an exposed pad on the
bottom of the package. This pad should be soldered to
the Printed Circuit Board (PCB) to aid in the removal of
heat from the package during operation. The exposed
pad is at the ground potential of the LDO.
MCP1725
DS22026A-page 16 © 2006 Microchip Technology Inc.
4.0 DEVICE OVERVIEW
The MCP1725 is a high output current, Low Dropout
(LDO) voltage regulator with an adjustable delay
power-good output and shutdown control input. The
low dropout voltage of 210 mV typical at 0.5A of current
makes it ideal for battery-powered applications. Unlike
other high output current LDOs, the MCP1725 only
draws a maximum of 220 µA of quiescent current.
4.1 LDO Output Voltage
The MCP1725 LDO is available with either a fixed
output voltage or an adjustable output voltage. The
output voltage range is 0.8V to 5.0V for both versions.
4.1.1 ADJUST INPUT
The adjustable version of the MCP1725 uses the ADJ
pin (pin 7) to get the output voltage feedback for output
voltage regulation. This allows the user to set the
output voltage of the device with two external resistors.
The nominal voltage for ADJ is 0.41V.
Figure 4-1 shows the adjustable version of the
MCP1725. Resistors R1 and R2 form the resistor
divider network necessary to set the output voltage.
With this configuration, the equation for setting VOUT is:
EQUATION 4-1:
FIGURE 4-1: Typical adjustable output
voltage application circuit.
The allowable resistance value range for resistor R2 is
from 10 kΩ to 200 kΩ. Solving the equation for R1
yields the following equation:
EQUATION 4-2:
4.2 Output Current and Current
Limiting
The MCP1725 LDO is tested and ensured to supply a
minimum of 0.5A of output current. The MCP1725 has
no minimum output load, so the output load current can
go to 0 mA and the LDO will continue to regulate the
output voltage to within tolerance.
The MCP1725 also incorporates an output current limit.
If the output voltage falls below 0.7V due to an overload
condition (usually represents a shorted load condition),
the output current is limited to 1.2A (typical). If the
overload condition is a soft overload, the MCP1725 will
supply higher load currents of up to 1A. The MCP1725
should not be operated in this condition continuously as
it may result in failure of the device. However, this does
allow for device usage in applications that have higher
pulsed load currents having an average output current
value of 0.5A or less.
Output overload conditions may also result in an over-
temperature shutdown of the device. If the junction
temperature rises above 150°C, the LDO will shut
down the output voltage. See Section 4.9
“Overtemperature Protection” for more information
on overtemperature shutdown.
4.3 Output Capacitor
The MCP1725 requires a minimum output capacitance
of 1 µF for output voltage stability. Ceramic capacitors
are recommended because of their size, cost and
environmental robustness qualities.
Aluminum-electrolytic and tantalum capacitors can be
used on the LDO output as well. The Equivalent Series
Resistance (ESR) of the electrolytic output capacitor
must be no greater than 1 ohm. The output capacitor
should be located as close to the LDO output as is
practical. Ceramic materials X7R and X5R have low
temperature coefficients and are well within the
acceptable ESR range required. A typical 1 µF X7R
0805 capacitor has an ESR of 50 milli-ohms.
Larger LDO output capacitors can be used with the
MCP1725 to improve dynamic performance and power
supply ripple rejection performance. A maximum of
22 µF is recommended. Aluminum-electrolytic
capacitors are not recommended for low-temperature
applications of < -25°C.
VOUT VADJ
R1R2
+
R2
------------------
⎝⎠
⎛⎞
=
Where:
VOUT = LDO Output Voltage
VADJ =ADJ Pin Voltage
(typically 0.41V)
VIN
SHDN
GND PWRGD
CDELAY
ADJ
VOUT
1
2
3
45
6
7
8
1µF
VOUT
4.7 µF
VIN
On
Off
VIN R1
R2
C1
C2
1000 pF
C3
MCP1725-ADJ
R1R2
VOUT VADJ
–
VADJ
--------------------------------
⎝⎠
⎛⎞
=
Where:
VOUT = LDO Output Voltage
VADJ =ADJ Pin Voltage
(typically 0.41V)
© 2006 Microchip Technology Inc. DS22026A-page 17
MCP1725
4.4 Input Capacitor
Low input source impedance is necessary for the LDO
output to operate properly. When operating from
batteries, or in applications with long lead length
(> 10 inches) between the input source and the LDO,
some input capacitance is recommended. A minimum
of 1.0 µF to 4.7 µF is recommended for most
applications.
For applications that have output step load
requirements, the input capacitance of the LDO is very
important. The input capacitance provides the LDO
with a good local low-impedance source to pull the
transient currents from in order to respond quickly to
the output load step. For good step response
performance, the input capacitor should be of
equivalent (or higher) value than the output capacitor.
The capacitor should be placed as close to the input of
the LDO as is practical. Larger input capacitors will also
help reduce any high-frequency noise on the input and
output of the LDO and reduce the effects of any
inductance that exists between the input source
voltage and the input capacitance of the LDO.
4.5 Power Good Output (PWRGD)
The PWRGD output is used to indicate when the output
voltage of the LDO is within 92% (typical value, see
Section 1.0 “Electrical Characteristics” for Minimum
and Maximum specifications) of its nominal regulation
value.
As the output voltage of the LDO rises, the PWRGD
output will be held low until the output voltage has
exceeded the power good threshold plus the hysteresis
value. Once this threshold has been exceeded, the
power good time delay is started (shown as TPG in
Section 1.0 “Electrical Characteristics”). The power
good time delay is adjustable via the CDELAY pin of the
LDO (see Section 4.6 “CDELAY Input”). By placing a
capacitor from the CDELAY pin to ground, the power
good time delay can be adjusted from 200 µs (no
capacitance) to 300 ms (0.1 µF capacitor). After the
time delay period, the PWRGD output will go high,
indicating that the output voltage is stable and within
regulation limits.
If the output voltage of the LDO falls below the power
good threshold, the power good output will transition
low. The power good circuitry has a 170 µs delay when
detecting a falling output voltage, which helps to
increase noise immunity of the power good output and
avoid false triggering of the power good output during
fast output transients. See Figure 4-2 for power good
timing characteristics.
When the LDO is put into Shutdown mode using the
SHDN input, the power good output is pulled low
immediately, indicating that the output voltage will be
out of regulation. The timing diagram for the power
good output when using the shutdown input is shown in
Figure 4-3.
The power good output is an open-drain output that can
be pulled up to any voltage that is equal to or less than
the LDO input voltage. This output is capable of sinking
1.2 mA (VPWRGD < 0.4V maximum).
FIGURE 4-2: Power Good Timing.
FIGURE 4-3: Power Good Timing from
Shutdown.
TPG
TVDET_PWRGD
VPWRGD_TH
VOUT
PWRGD
VOL
VOH
VIN
SHDN
VOUT
30 µs 70 µs
TOR
PWRGD
TPG
MCP1725
DS22026A-page 18 © 2006 Microchip Technology Inc.
4.6 CDELAY Input
The CDELAY input is used to provide the power-up
delay timing for the power good output, as discussed in
the previous section. By adding a capacitor from the
CDELAY pin to ground, the PWRGD power-up time
delay can be adjusted from 200 µs (no capacitance on
CDELAY) to 300 ms (0.1 µF of capacitance on CDELAY).
See Section 1.0 “Electrical Characteristics” for
CDELAY timing tolerances.
Once the power good threshold (rising) has been
reached, the CDELAY pin charges the external capacitor
to VIN. The charging current is 140 nA (typical). The
PWRGD output will transition high when the CDELAY
pin voltage has charged to 0.42V. If the output falls
below the power good threshold limit during the
charging time between 0.0V and 0.42V on the CDELAY
pin, the CDELAY pin voltage will be pulled to ground,
thus resetting the timer. The CDELAY pin will be held low
until the output voltage of the LDO has once again risen
above the power good rising threshold. A timing
diagram showing CDELAY
, PWRGD and VOUT is shown
in Figure 4-4.
FIGURE 4-4: CDELAY and PWRGD Timing
Diagram.
4.7 Shutdown Input (SHDN)
The SHDN input is an active-low input signal that turns
the LDO on and off. The SHDN threshold is a
percentage of the input voltage. The typical value of
this shutdown threshold is 30% of VIN, with minimum
and maximum limits over the entire operating
temperature range of 45% and 15%, respectively.
The SHDN input will ignore low-going pulses (pulses
meant to shut down the LDO) that are up to 400 ns in
pulse width. If the shutdown input is pulled low for more
than 400 ns, the LDO will enter Shutdown mode. This
small bit of filtering helps to reject any system noise
spikes on the shutdown input signal.
On the rising edge of the SHDN input, the shutdown
circuitry has a 30 µs delay before allowing the LDO
output to turn on. This delay helps to reject any false
turn-on signals or noise on the SHDN input signal. After
the 30 µs delay, the LDO output enters its soft-start
period as it rises from 0V to its final regulation value. If
the SHDN input signal is pulled low during the 30 µs
delay period, the timer will be reset and the delay time
will start over again on the next rising edge of the
SHDN input. The total time from the SHDN input going
high (turn-on) to the LDO output being in regulation is
typically 100 µs. See Figure 4-5 for a timing diagram of
the SHDN input.
FIGURE 4-5: Shutdown Input Timing
Diagram.
VOUT
TPG
VPWRGD_TH
CDELAY
CDELAY Threshold (0.42V)
PWRGD
0V
VIN (typ)
SHDN
VOUT
30 µs 70 µs
TOR
400 ns (typ)
© 2006 Microchip Technology Inc. DS22026A-page 19
MCP1725
4.8 Dropout Voltage and
Undervoltage Lockout
Dropout voltage is defined as the input-to-output
voltage differential at which the output voltage drops
2% below the nominal value that was measured with a
VR + 0.6V differential applied. The MCP1725 LDO has
a very low dropout voltage specification of 210 mV
(typical) at 0.5A of output current. See Section 1.0
“Electrical Characteristics” for maximum dropout
voltage specifications.
The MCP1725 LDO operates across an input voltage
range of 2.3V to 6.0V and incorporates input
Undervoltage Lockout (UVLO) circuitry that keeps the
LDO output voltage off until the input voltage reaches a
minimum of 2.18V (typical) on the rising edge of the
input voltage. As the input voltage falls, the LDO output
will remain on until the input voltage level reaches
2.04V (typical).
Since the MCP1725 LDO undervoltage lockout
activates at 2.04V as the input voltage is falling, the
dropout voltage specification does not apply for output
voltages that are less than 1.9V.
For high-current applications, voltage drops across the
PCB traces must be taken into account. The trace
resistances can cause significant voltage drops
between the input voltage source and the LDO. For
applications with input voltages near 2.3V, these PCB
trace voltage drops can sometimes lower the input
voltage enough to trigger a shutdown due to
undervoltage lockout.
4.9 Overtemperature Protection
The MCP1725 LDO has temperature-sensing circuitry
to prevent the junction temperature from exceeding
approximately 150°C. If the LDO junction temperature
does reach 150°C, the LDO output will be turned off
until the junction temperature cools to approximately
140°C, at which point the LDO output will automatically
resume normal operation. If the internal power
dissipation continues to be excessive, the device will
again shut off. The junction temperature of the die is a
function of power dissipation, ambient temperature and
package thermal resistance. See Section 5.0
“Application Circuits/Issues” for more information
on LDO power dissipation and junction temperature.
MCP1725
DS22026A-page 20 © 2006 Microchip Technology Inc.
5.0 APPLICATION CIRCUITS/
ISSUES
5.1 Typical Application
The MCP1725 is used for applications that require high
LDO output current and a power good output.
FIGURE 5-1: Typical Application Circuit.
5.1.1 APPLICATION CONDITIONS
5.2 Power Calculations
5.2.1 POWER DISSIPATION
The internal power dissipation within the MCP1725 is a
function of input voltage, output voltage, output current
and quiescent current. Equation 5-1 can be used to
calculate the internal power dissipation for the LDO.
EQUATION 5-1:
In addition to the LDO pass element power dissipation,
there is power dissipation within the MCP1725 as a
result of quiescent or ground current. The power
dissipation as a result of the ground current can be
calculated using the following equation:
EQUATION 5-2:
The total power dissipated within the MCP1725 is the
sum of the power dissipated in the LDO pass device
and the P(IGND) term. Because of the CMOS
construction, the typical IGND for the MCP1725 is
120 µA. Operating at 3.465V results in a power
dissipation of 0.42 milli-Watts. For most applications,
this is small compared to the LDO pass device power
dissipation and can be neglected.
The maximum continuous operating junction
temperature specified for the MCP1725 is +125°C. To
estimate the internal junction temperature of the
MCP1725, the total internal power dissipation is
multiplied by the thermal resistance from junction to
ambient (RθJA) of the device. The thermal resistance
from junction to ambient for the 2x3 DFN package is
estimated at 76°C/W.
EQUATION 5-3:
Package Type = 2x3 DFN8
Input Voltage Range = 3.3V ± 5%
VIN maximum = 3.465V
VIN minimum = 3.135V
VDROPOUT (max) = 0.350V
VOUT (typical) = 2.5V
IOUT = 0.5A maximum
PDISS (typical) = 0.4W
Temperature Rise = 30.4°C
VIN
SHDN
GND PWRGD
CDELAY
Sense
VOUT
1
2
3
45
6
7
8
10 µF
VOUT = 2.5V @ 0.5A
10 µF
VIN = 3.3V
On
Off
VIN R1
C1
C2
1000 pF
C3
MCP1725-2.5
10kΩ
PWRGD
PLDO VIN MAX)()
VOUT MIN()
–()IOUT MAX)()
×=
Where:
PLDO = LDO Pass device internal
power dissipation
VIN(MAX) = Maximum input voltage
VOUT(MIN) = LDO minimum output voltage
PIGND()
VIN MAX()
IVIN
×=
Where:
PI(GND = Power dissipation due to the
quiescent current of the LDO
VIN(MAX) = Maximum input voltage
IVIN = Current flowing in the VIN pin
with no LDO output current
(LDO quiescent current)
TJMAX()
PTOTAL RθJA
×TAMAX
+=
TJ(MAX) = Maximum continuous junction
temperature
PTOTAL = Total device power dissipation
RθJA = Thermal resistance from junction to
ambient
TAMAX = Maximum ambient temperature
© 2006 Microchip Technology Inc. DS22026A-page 21
MCP1725
The maximum power dissipation capability for a
package can be calculated given the junction-to-
ambient thermal resistance and the maximum ambient
temperature for the application. Equation 5-4 can be
used to determine the package maximum internal
power dissipation.
EQUATION 5-4:
EQUATION 5-5:
EQUATION 5-6:
5.3 Typical Application
Internal power dissipation, junction temperature rise,
junction temperature and maximum power dissipation
is calculated in the following example. The power
dissipation as a result of ground current is small
enough to be neglected.
EXAMPLE 5-1: POWER DISSIPATION
EXAMPLE
5.3.1 DEVICE JUNCTION TEMPERATURE
RISE
The internal junction temperature rise is a function of
internal power dissipation and the thermal resistance
from junction-to-ambient for the application. The
thermal resistance from junction-to-ambient (RθJA) is
derived from an EIA/JEDEC standard for measuring
thermal resistance for small surface-mount packages.
The EIA/JEDEC specification is JESD51-7 “High
Effective Thermal Conductivity Test Board for Leaded
Surface-Mount Packages”. The standard describes the
test method and board specifications for measuring the
thermal resistance from junction to ambient. The actual
thermal resistance for a particular application can vary
depending on many factors such as copper area and
thickness. Refer to AN792, “A Method to Determine
How Much Power a SOT23 Can Dissipate in an
Application” (DS00792), for more information regarding
this subject.
PDMAX()
TJMAX()
TAMAX()
–()
RθJA
---------------------------------------------------=
PD(MAX) = Maximum device power dissipation
TJ(MAX) = maximum continuous junction
temperature
TA(MAX) = maximum ambient temperature
RθJA = Thermal resistance from junction to
ambient
TJRISE()
PDMAX()
RθJA
×=
TJ(RISE) = Rise in device junction temperature
over the ambient temperature
PD(MAX) = Maximum device power dissipation
RθJA = Thermal resistance from junction to
ambient
TJTJRISE()
TA
+=
TJ= Junction temperature
TJ(RISE) = Rise in device junction temperature
over the ambient temperature
TA= Ambient temperature
Package
Package
Type
= 2x3 DFN
Input Voltage
VIN =3.3V ± 5%
LDO Output Voltage and Current
VOUT =2.5V
IOUT =0.5A
Maximum Ambient Temperature
TA(MAX) = 60°C
Internal Power Dissipation
PLDO(MAX) =(V
IN(MAX) – VOUT(MIN)) x
IOUT(MAX)
PLDO = ((3.3V x 1.05) – (2.5V x 0.975))
x 0.5A
PLDO = 0.51 Watts
TJ(RISE) =P
TOTAL x RθJA
TJRISE = 0.51 W x 76.0° C/W
TJRISE =38.8°C
MCP1725
DS22026A-page 22 © 2006 Microchip Technology Inc.
5.3.2 JUNCTION TEMPERATURE
ESTIMATE
To estimate the internal junction temperature, the
calculated temperature rise is added to the ambient or
offset temperature. For this example, the worst-case
junction temperature is estimated below:
As you can see from the result, this application will be
operating near around a junction temperature of
100°C. The PCB layout for this application is very
important as it has a significant impact on the junction-
to-ambient thermal resistance (RθJA) of the 2x3 DFN
package, which is very important in this application.
5.3.3 MAXIMUM PACKAGE POWER
DISSIPATION AT 60°C AMBIENT
TEMPERATURE
From this table, you can see the difference in maximum
allowable power dissipation between the 2x3 DFN
package and the 8-pin SOIC package. This difference
is due to the exposed metal tab on the bottom of the
DFN package. The exposed tab of the DFN package
provides a very good thermal path from the die of the
LDO to the PCB. The PCB then acts like a heatsink,
providing more area to distribute the heat generated by
the LDO.
5.4 CDELAY Calculations (typical)
TJ =T
JRISE + TA(MAX)
TJ = 38.8°C + 60.0°C
TJ = 98.8°C
2x3 DFN (76° C/W RθJA):
PD(MAX) = (125°C – 60°C) / 76° C/W
PD(MAX) = 0.855W
SOIC8 (163°C/Watt RθJA):
PD(MAX) = (125°C – 60°C)/ 163° C/W
PD(MAX) = 0.399W
CI
ΔT
ΔV
-------
•=
Where:
C=C
DELAY Capacitor
I=C
DELAY charging current,
140 nA typical.
ΔT = time delay
ΔV=C
DELAY threshold voltage,
0.42V typical
CI
ΔT
ΔV
-------
•140nA ΔT•()
0.42V
---------------------------------- 333.3 09–
×10 ΔT•== =
For a delay of 300ms,
C = 333.3E-09 *.300
C = 100E-09 µF (0.1 µF)
© 2006 Microchip Technology Inc. DS22026A-page 23
MCP1725
6.0 PACKAGING INFORMATION
6.1 Package Marking Information
8-Lead SOIC (150 mil) Example:
XXXXXXXX
XXXXYYWW
NNN
250802E
SN^^0649
256
8-Lead DFN (2x3) Example:
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
3
e
ABL
649
25
XXXX
XYWW
NN
Standard
Extended Temp
Code Voltage
Options * Code Voltage
Options *
ABL 0.8 ABR 3.0
ABM 1.2 ABS 3.3
ABP 1.8 ABT 5.0
ABQ 2.5 ABU ADJ
* Custom output voltages available upon request.
Contact your local Microchip sales office for more
information.
MCP1725
DS22026A-page 24 © 2006 Microchip Technology Inc.
8-Lead Plastic Dual Flat No Lead Package (MC) 2x3 Body (DFN) – Saw Singulated
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Number of Pins
Pitch
Overall Height
Standoff
Contact Thickness
Overall Length
Overall Width
Exposed Pad Length
Exposed Pad Width
Contact Width
Contact Length §
Contact-to-Exposed Pad §
Units
Dimension Limits
N
e
A
A1
A3
D
E
D2
E2
b
L
K
0.80
0.00
1.30
1.50
0.18
0.30
0.20
8
0.50 BSC
0.90
0.02
0.20 REF
2.00 BSC
3.00 BSC
—
—
0.25
0.40
—
1.00
0.05
1.75
1.90
0.30
0.50
—
MIN NOM MAX
MILLIMETERS
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package may have one or more exposed tie bars at ends.
3. § Significant Characteristic
4. Package is saw singulated
5. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing No. C04–123, Sept. 8, 2006
A3A1 NOTE 2
NOTE 1
NOTE 1
E2
D2
BOTTOM VIEW
EXPOSED PAD
K
L
1
2
N
e
b
TOP VIEW
2
1
N
D
E
A
© 2006 Microchip Technology Inc. DS22026A-page 25
MCP1725
8-Lead Plastic Small Outline (SN) – Narrow, 150 mil Body (SOIC)
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Foot Angle φ048048
1512015120
β
Mold Draft Angle Bottom
1512015120
α
Mold Draft Angle Top
0.510.420.33.020.017.013BLead Width
0.250.230.20.010.009.008
c
Lead Thickness
0.760.620.48.030.025.019LFoot Length
0.510.380.25.020.015.010hChamfer Distance
5.004.904.80.197.193.189DOverall Length
3.993.913.71.157.154.146E1Molded Package Width
6.206.025.79.244.237.228EOverall Width
0.250.180.10.010.007.004A1Standoff §
1.551.421.32.061.056.052
A2
Molded Package Thickness
1.751.551.35.069.061.053AOverall Height
1.27
.050
p
Pitch
88
n
Number of Pins
MAXNOMMINMAXNOMMINDimension Limits
MILLIMETERSINCHES*Units
2
1
D
n
p
B
E
E1
h
L
β
c
45°
φ
A2
α
A
A1
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-057
§ Significant Characteristic
MCP1725
DS22026A-page 26 © 2006 Microchip Technology Inc.
NOTES:
© 2006 Microchip Technology Inc. DS22026A-page 27
MCP1725
APPENDIX A: REVISION HISTORY
Revision A (December 2006)
• Original Release of this Document.
MCP1725
DS22026A-page 28 © 2006 Microchip Technology Inc.
NOTES:
© 2006 Microchip Technology Inc. DS22026A-page 29
MCP1725
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Device: MCP1725: 500 mA Low Dropout Regulator
MCP1725T: 500 mA Low Dropout Regulator
Tape and Reel
Output Voltage *: 08 = 0.8V “Standard”
12 = 1.2V “Standard”
18 = 1.8V “Standard”
25 = 2.5V “Standard”
30 = 3.0V “Standard”
33 = 3.3V “Standard”
50 = 5.0V “Standard”
*Contact factory for other output voltage options
Extra Feature Code: 0 = Fixed
Tolerance: 2 = 2.0% (Standard)
Temperature: E = -40°C to +125°C
Package Type: MC = Plastic Dual Flat No Lead (DFN) (2x3 Body), 8-lead
SN = Plastic Small Outline (150 mil Body), 8-lead
PART NO. XXX
Output Feature
Code
Device
Voltage
X
Tolerance
X/
Temp.
XX
Package
Examples:
a) MCP1725-0802E/MC: 0.8V Low Dropout
Regulator,
8LD DFN pkg.
b) MCP1725T-1202E/MC: Tape and Reel,
1.2V Low Dropout
Regulator,
8LD DFN pkg.
c) MCP1725-1802E/MC: 1.8V Low Dropout
Voltage Regulator,
8LD DFN pkg.
d) MCP1725T-2502E/MC: Tape and Reel,
2.5V Low Dropout
Voltage Regulator,
8LD DFN pkg.
e) MCP1725-3002E/MC: 3.0V Low Dropout
Voltage Regulator,
8LD DFN pkg.
f) MCP1725-3302E/MC: 3.3V Low Dropout
Voltage Regulator,
8LD DFN pkg.
g) MCP1725T-5002E/MC: Tape and Reel,
5.0V Low Dropout
Voltage Regulator,
8LD DFN pkg.
h) MCP1725-ADJE/MC: ADJ Low Dropout
Voltage Regulator,
8LD DFN pkg.
i) MCP1725T-0802E/SN: Tape and Reel,
0.8V Low Dropout
Voltage Regulator,
8LD SOIC pkg.
j) MCP1725-1202E/SN: 1.2V Low Dropout
Voltage Regulator,
8LD SOIC pkg.
k) MCP1725T-1802E/SN: Tape and Reel,
1.8V Low Dropout
Voltage Regulator,
8LD SOIC pkg.
l) MCP1725-2502E/SN: 2.5V Low Dropout
Voltage Regulator,
8LD SOIC pkg.
m) MCP1725-3002E/SN: 3.0V Low Dropout
Voltage Regulator,
8LD SOIC pkg.
n) MCP1725-3302E/SN: 3.3V Low Dropout
Voltage Regulator,
8LD SOIC pkg.
o) MCP1725T-5002E/SN: Tape and Reel,
5.0V Low Dropout
Voltage Regulator,
8LD SOIC pkg.
p) MCP1725T-ADJE/SN: Tape and Reel,
ADJ Low Dropout
Voltage Regulator,
8LD SOIC pkg.
MCP1725
DS22026A-page 30 © 2006 Microchip Technology Inc.
NOTES:
© 2006 Microchip Technology Inc. DS22026A-page 31
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro,
PICSTART, PRO MATE, PowerSmart, rfPIC, and
SmartShunt are registered trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB,
SEEVAL, SmartSensor and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, ECAN,
ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active
Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PICkit,
PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,
PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB,
rfPICDEM, Select Mode, Smart Serial, SmartTel, Total
Endurance, UNI/O, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2006, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona, Gresham, Oregon and Mountain View, California. The
Company’s quality system processes and procedures are for its PIC®
8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs,
microperipherals, nonvolatile memory and analog products. In
addition, Microchip’s quality system for the design and manufacture of
development systems is ISO 9001:2000 certified.
DS22026A-page 32 © 2006 Microchip Technology Inc.
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12/08/06