MR28F010-12 - Intel - Product.Network

January 1996 Order Number: 271111-005

M28F010

1024K (128K x 8) CMOS FLASH MEMORY

YFlash Electrical Chip-Erase

Ð 5 Second Typical

YQuick-Pulse Programming Algorithm

Ð10 ms Typical Byte-Program

Ð 2 Second Typical Chip-Program

YSingle High Voltage for Writing and

Erasing

YCMOS Low Power Consumption

Ð 30 mA Maximum Active Current

Ð 100 mA Maximum Standby Current

YCommand Register Architecture for

Microprocessor/Microcontroller

Compatible Write Interface

YNoise Immunity Features

Ðg10% VCC Tolerance

Ð Maximum Latch-Up Immunity

through EPI Processing

YETOX-III Flash-Memory Technology

Ð EPROM-Compatible Process Base

Ð High-Volume Manufacturing

Experience

YCompatible with JEDEC-Standard

Byte-Wide EPROM Pinouts

Y10,000 Program/Erase Cycles Minimum

YAvailable in Three Product Grades:

Ð QML: b55§Ctoa

125§C(T

)

Ð SE2: b40§Ctoa

125§C(T

)

Ð SE3: b40§Ctoa

110§C(T

)

Intel’s M28F010 is a 1024-Kbit byte-wide, in-system re-writable, CMOS nonvolatile flash memory. It is orga-

nized as 131,072 bytes of 8 bits and is available in a 32-pin hermetic CERDIP package. The M28F010 is also

available in 32-contact leadless chip carrier, J-lead, and Flatpack surface mount packages. It offers the most

cost-effective and reliable alternative for updatable nonvolatile memory. The M28F010 adds electrical chip-

erasure and reprogramming to EPROM technology. Memory contents of the M28F010 can be erased and

reprogrammed 1) in a socket; 2) in a PROM programmer socket; 3) on-board during subassembly test; 4) in-

system during final test; and 5) in-system after-sale.

The M28F010 increases memory flexibility while contributing to time- and cost-savings. It is targeted for

alterable code-, data-storage applications where traditional EEPROM functionality (byte erasure) is either not

required or is not cost-effective. Use of the M28F010 is also appropriate where EPROM ultraviolet erasure is

impractical or too time consuming.

271111–1

Figure 1. M28F010 Block Diagram

M28F010

271111–2 271111–16

271111–3

Figure 2. M28F010 Pin Configurations

Table 1. Pin Description

Symbol Type Name and Function

A0–A16 INPUT ADDRESS INPUTS for memory addresses. Addresses are internally

latched during a write cycle.

DQ0–DQ7INPUT/OUTPUT DATA INPUT/OUTPUT: Inputs data during memory write cycles;

outputs data during memory read cycles. The data pins are active high

and float to tri-state OFF when the chip is deselected or the outputs

are disabled. Data is internally latched during a write cycle.

CE INPUT CHIP ENABLE: Activates the device’s control logic, input buffers,

decoders and sense amplifiers. CE is active low; CE high deselects the

memory device and reduces power consumption to standby levels.

OE INPUT OUTPUT ENABLE: Gates the devices output through the data buffers

during a read cycle. OE is active low.

WE INPUT WRITE ENABLE: Controls writes to the control register and the array.

Write enable is active low. Addresses are latched on the falling edge

and data is latched on the rising edge of the WE pulse.

Note: With VPP sVCC a2V, memory contents cannot be altered.

VPP ERASE/PROGRAM POWER SUPPLY for writing the command

VCC DEVICE POWER SUPPLY (5V g10%)

VSS GROUND

NC NO INTERNAL CONNECTION to device. Pin may be driven or left

floating.

M28F010

271111–4

Figure 3. M28F010 in a M80C186 System

PRINCIPLES OF OPERATION

Flash-memory augments EPROM functionality with

in-circuit electrical erasure and reprogramming. The

M28F010 introduces a command register to manage

this new functionality. The command register allows

for: 100% TTL-level control inputs; fixed power sup-

plies during erasure and programming; and maxi-

mum EPROM compatibility.

In the absence of high voltage on the VPP pin, the

M28F010 is a read-only memory. Manipulation of the

external memory-control pins yields the standard

EPROM read, standby, output disable, and intelli-

gent Identifier operations.

The same EPROM read, standby, and output disable

operations are available when high voltage is ap-

plied to the VPP pin. In addition, high voltage on VPP

enables erasure and programming of the device. All

functions associated with altering memory con-

tentsÐintelligent Identifier, erase, erase verify, pro-

gram, and program verifyÐare accessed via the

command register.

Commands are written to the register using standard

microprocessor write timings. Register contents

serve as input to an internal state-machine which

controls the erase and programming circuitry. Write

cycles also internally latch addresses and data

needed for programming or erase operations. With

the appropriate command written to the register,

standard microprocessor read timings output array

data, access the intelligent Identifier codes, or out-

put data for erase and program verification.

The command register is only alterable when VPP is

at high voltage. Depending upon the application, the

system designer may choose to make the VPP pow-

er supply switchableÐavailable only when memory

updates are desired. When high voltage is removed,

the contents of the register default to the read com-

mand, making the M28F010 a read-only memory.

Memory contents cannot be altered.

M28F010

Table 2. M28F010 Bus Operations

Pins VPP(1) A0A9CE OE WE DQ0–DQ7

Operation

Read VPPL A0A9VIL VIL VIH Data Out

Output Disable VPPL XXV

IL VIH VIH Tri-State

READ-ONLY Standby VPPL XXV

IH X X Tri-State

intelligent Identifier (Mfr)(2) VPPL VIL VID(7) VIL VIL VIH Data e89H

intelligent Identifier (Device)(2) VPPL VIH VID(7) VIL VIL VIH Data eB4H

Read VPPH A0A9VIL VIL VIH Data Out(3)

READ/WRITE Output Disable VPPH XXV

IL VIH VIH Tri-State

Standby(4) VPPH XXV

IH X X Tri-State

Write VPPH A0A9VIL VIH VIL Data In(5)

NOTES:

1. VPPL may be ground, a no-connect with a resistor tied to ground, or as defined in the Characteristics Section. VPPH is the

programming voltage specified for the device. Refer to DC Characteristics. When VPP eVPPL memory contents can be

read but not written or erased.

2. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 3. All other

addresses low.

3. Read operations with VPP eVPPH may access array data or the intelligent Identifier codes.

4. With VPP at high voltage, the standby current equals ICC aIPP (standby).

5. Refer to Table 3 for valid Data-In during a write operation.

6. X can be VIL or VIH.

7. VID is the intelligent Identifier high voltage. Refer to DC Characteristics.

Or, the system designer may choose to ‘‘hardwire’’

VPP, making the high voltage supply constantly

available. In this instance, all operations are per-

formed in conjunction with the command register.

The M28F010 is designed to accommodate either

design practice, and to encourage optimization of

the processor-memory interface.

Integrated Stop Timer

Sucessive command write cycles define the dura-

tions of program and erase operations; specifically,

the program or erase time durations are normally

terminated by associated program or erase verify

commands. An integrated stop timer provides simpli-

fied timing control over these operations; thus elimi-

nating the need for maximum program/erase timing

specifications. Programming and erase pulse dura-

tions are minimums only. When the stop timer termi-

nates a program or erase operation, the device

enters an inactive state and remains inactive until

receiving the appropriate verify or reset command.

Write Protection

The command register is only active when VPP is at

high voltage. Depending upon the application, the

system designer may choose to make the VPP pow-

er supply switchableÐavailable only when memory

updates are desired. When VPP eVPPL, the con-

tents of the register default to the read command,

making the 28F010 a read-only memory. In this

mode, the memory contents cannot be altered.

Or, the system designer may choose to ‘‘hardwire’’

VPP, making the high voltage supply constantly

available. In this case, all Command Register func-

tions are inhibited whenever VCC is below the write

lockout voltage VLKO. (See Power Up/Down Protec-

tion) The 28F010 is designed to accommodate ei-

ther design practice, and to encourage optimization

of the processor-memory interface.

BUS OPERATIONS

Read

The M28F010 has two control functions, both of

which must be logically active, to obtain data at the

outputs. Chip-Enable (CE) is the power control and

should be used for device selection. Output-Enable

(OE) is the output control and should be used

to gate data from the output pins, independent of

device selection. Figure 6 illustrates read timing

waveforms.

M28F010

When VPP is high (VPPH), the read operation can be

used to access array data, to output the intelligent

Identifier codes, and to access data for program/

erase verification. When VPP is low (VPPL), the read

operation can only access the array data.

Output Disable

With Output-Enable at a logic-high level (VIH), output

from the device is disabled. Output pins are placed

in a high-impedance state.

Standby

With Chip-Enable at a logic-high level, the standby

operation disables most of the M28F010’s circuitry

and substantially reduces device power consump-

tion. The outputs are placed in a high-impedance

state, independent of the Output-Enable signal.

If the M28F010 is deselected during erasure, pro-

gramming, or program/erase verification, the

device draws active current until the operation is

terminated.

intelligent Identifier Operation

The intelligent Identifier operation outputs the manu-

facturer code (89H) and device code (B4H). Pro-

gramming equipment automatically matches the de-

vice with its proper erase and programming algo-

rithms.

With Chip-Enable and Output-Enable at a logic low

level, raising A9 to high voltage VID activates the

operation. Data read from locations 0000H and

0001H represent the manufacturer’s code and the

device code, respectively.

The manufacturer- and device-codes can also be

read via the command register, for instances where

the M28F010 is erased and reprogrammed in the

target system. Following a write of 90H to the com-

mand register, a read from address location 0000H

outputs the manufacturer code (89H). A read from

address 0001H outputs the device code (B4H).

Write

Device erasure and programming are accomplished

via the command register, when high voltage is ap-

plied to the VPP pin. The contents of the register

serve as input to the internal state-machine. The

state-machine outputs dictate the function of the

device.

The command register itself does not occupy an ad-

dressable memory location. The register is a latch

used to store the command, along with address and

data information needed to execute the command.

The command register is written by bringing Write-

Enable to a logic-low level (VIL), while Chip-Enable is

low. Addresses are latched on the falling edge of

Write-Enable, while data is latched on the rising

edge of the Write-Enable pulse. Standard microproc-

essor write timings are used.

The three high-order register bits (R7, R6, R5) en-

code the control functions. All other register bits, R4

to R0, must be zero. The only exception is the reset

command, when FFH is written to the register. Reg-

ister bits R7– R0 correspond to data inputs D7– D0.

Refer to AC Write Characteristics and the Erase/

Programming Waveforms for specific timing

parameters.

M28F010

COMMAND DEFINITIONS

When low voltage is applied to the VPP pin, the con-

tents of the command register default to 00H, en-

abling read-only operations.

Placing high voltage on the VPP pin enables read/

write operations. Device operations are selected by

writing specific data patterns into the command reg-

ister. Table 3 defines these M28F010 register

commands.

Table 3. Command Definitions

Bus First Bus Cycle Second Bus Cycle

Command Cycles

Req’d Operation(1) Address(2) Data(3) Operation(1) Address(2) Data(3)

Read Memory 1 Write X 00H

Read intelligent Identifier Codes(4) 2 Write X 90H Read IA ID

Set-up Erase/Erase(5) 2 Write X 20H Write X 20H

Erase Verify(5) 2 Write EA A0H Read X EVD

Set-up Program/Program(6) 2 Write X 40H Write PA PD

Program Verify(6) 2 Write X C0H Read X PVD

Reset(7) 2 Write X FFH Write X FFH

NOTES:

1. Bus operations are defined in Table 2.

2. IA eIdentifier address: 00H for manufacturer code, 01H for device code.

EA eAddress of memory location to be read during erase verify.

PA eAddress of memory location to be programmed.

Addresses are latched on the falling edge of the Write-Enable pulse.

3. ID eData read from location IA during device identification (Mfr e89H, Device eB4H).

EVD eData read from location EA during erase verify.

PD eData to be programmed at location PA. Data is latched on the rising edge of Write-Enable.

PVD eData read from location PA during program verify. PA is latched on the Program command.

4. Following the Read inteligent ID command, two read operations access manufacturer and device codes.

5. Figure 5 illustrates the Quick-Erase Algorithm.

6. Figure 4 illustrates the Quick-Pulse Programming Algorithm.

7. The second bus cycle must be followed by the desired command register write.

M28F010

Read Command

While VPP is high, for erasure and programming,

memory contents can be accessed via the read

command. The read operation is initiated by writing

00H into the command register. Microprocessor

read cycles retrieve array data. The device remains

enabled for reads until the command register con-

tents are altered.

The default contents of the register upon VPP pow-

er-up is 00H. This default value ensures that no spu-

rious alteration of memory contents occurs during

the VPP power transition. Where the VPP supply is

hard-wired to the M28F010, the device powers-up

and remains enabled for reads until the command-

Read Characteristics and Waveforms for specific

timing parameters.

Intelligent Identifier Command

Flash-memories are intended for use in applications

where the local CPU alters memory contents. As

such, manufacturer- and device-codes must be ac-

cessible while the device resides in the target sys-

tem. PROM programmers typically access signature

codes by raising A9 to a high voltage. However, mul-

tiplexing high voltage onto address lines is not a de-

sired system-design practice.

The M28F010 contains an intelligent Identifier oper-

ation to supplement traditional PROM-programming

methodology. The operation is initiated by writing

90H into the command register. Following the com-

mand write, a read cycle from address 0000H re-

trieves the manufacturer code of 89H. A read cycle

from address 0001H returns the device code of

B4H. To terminate the operation, it is necessary to

write another valid command into the register.

Set-up Erase/Erase Commands

Set-up Erase is a command-only operation that

stages the device for electrical erasure of all bytes in

the array. The set-up erase operation is performed

by writing 20H to the command register.

To commence chip-erasure, the erase command

(20H) must again be written to the register. The

erase operation begins with the rising edge of the

Write-Enable pulse and terminates with the rising

edge of the next Write-Enable pulse (i.e., Erase-Veri-

fy Command).

This two-step sequence of set-up followed by execu-

tion ensures that memory contents are not acciden-

tally erased. Also, chip-erasure can only occur when

high voltage is applied to the VPP pin. In the absence

of this high voltage, memory contents are protected

against erasure. Refer to AC Erase Characteristics

and Waveforms for specific timing parameters.

Erase-Verify Command

The erase command erases all bytes of the array in

parallel. After each erase operation, all bytes must

be verified. The erase verify operation is initiated by

writing A0H into the command register. The address

for the byte to be verified must be supplied as it is

latched on the falling edge of the Write-Enable

pulse. The register write terminates the erase opera-

tion with the rising edge of its Write-Enable pulse.

The M28F010 applies an internally-generated mar-

gin voltage to the addressed byte. Reading FFH

from the addressed byte indicates that all bits in the

byte are erased.

The erase-verify command must be written to the

command register prior to each byte verification to

latch its address. The process continues for each

byte in the array until a byte does not return FFH

data, or the last address is accessed.

In the case where the data read is not FFH, another

erase operation is performed. (Refer to Set-up

Erase/Erase). Verification then resumes from the

address of the last-verified byte. Once all bytes in

the array have been verified, the erase step is com-

plete. The device can be programmed. At this point,

the verify operation is terminated by writing a valid

command (e.g. Program Set-up) to the command

trates how commands and bus operations are com-

bined to perform electrical erasure of the M28F010.

Refer to AC Erase Characteristics and Waveforms

for specific timing parameters.

Set-up Program/Program Commands

Set-up program is a command-only operation that

stages the device for byte programming. Writing 40H

into the command register performs the set-up

operation.

Once the program set-up operation is performed,

the next Write-Enable pulse causes a transition to

an active programming operation. Addresses are in-

ternally latched on the falling edge of the Write-En-

able pulse. Data is internally latched on the rising

edge of the Write-Enable pulse. The rising edge of

Write-Enable also begins the programming opera-

tion. The programming operation terminates with the

next rising edge of Write-Enable, used to write the

program-verify command. Refer to AC Program-

M28F010

ming Characteristics and Waveforms for specific

timing parameters.

Program-Verify Command

The M28F010 is programmed on a byte-by-byte ba-

sis. Byte programming may occur sequentially or at

random. Following each programming operation, the

byte just programmed must be verified.

The program-verify operation is initiated by writing

C0H into the command register. The register write

terminates the programming operation with the ris-

ing edge of its Write-Enable pulse. The program-ver-

ify operation stages the device for verification of the

byte last programmed. No new address information

is latched.

The M28F010 applies an internally-generated mar-

gin voltage to the byte. A microprocessor read cycle

outputs the data. A successful comparison between

the programmed byte and true data means that the

byte is successfully programmed. Programming then

proceeds to the next desired byte location. Figure 4,

the M28F010 Quick-Pulse Programming algorithm,

illustrates how commands are combined with bus

operations to perform byte programming. Refer to

AC Programming Characteristics and Waveforms for

specific timing parameters.

Reset Command

A reset command is provided as a means to safely

abort the erase- or program-command sequences.

Following either set-up command (erase or program)

with two consecutive writes of FFH will safely abort

the operation. Memory contents will not be altered.

A valid command must then be written to place the

device in the desired state.

EXTENDED ERASE/PROGRAM CYCLING

EEPROM cycling failures have always concerned

users. The high electrical field required by thin oxide

EEPROMs for tunneling can literally tear apart the

oxide at defect regions. To combat this, some sup-

pliers have implemented redundancy schemes, re-

ducing cycling failures to insignificant levels. Howev-

er, redundancy requires that cell size be doubledÐ

an expensive solution.

Intel has designed extended cycling capability into

its ETOX-II flash memory technology. Resulting im-

provements in cycling reliability come without in-

creasing memory cell size or complexity. First, an

advanced tunnel oxide increases the charge carry-

ing ability ten-fold. Second, the oxide area per cell

subjected to the tunneling electric field is one-tenth

that of common EEPROMs, minimizing the probabili-

ty of oxide defects in the region. Finally, the peak

electric field during erasure is approximately 2 MV/

cm lower than EEPROM. The lower electric field

greatly reduces oxide stress and the probability of

failureÐincreasing time to wearout by a factor of

100,000,000.

The device is programmed and erased using Intel’s

Quick-Pulse Programming and Quick-Erase algo-

rithms. Intel’s algorithmic approach uses a series of

operations (pulses), along with byte verification, to

completely and reliably erase and program the de-

vice.

QUICK-PULSE PROGRAMMING ALGORITHM

The Quick-Pulse Programming algorithm uses pro-

gramming operations of 10 ms duration. Each opera-

tion is followed by a byte verification to determine

when the addressed byte has been successfully pro-

grammed. The algorithm allows for up to 25 pro-

gramming operations per byte, although most bytes

verify on the first or second operation. The entire

sequence of programming and byte verification is

performed with VPP at high voltage. Figure 4 illus-

trates the Quick-Pulse Programming algorithm.

QUICK-ERASE ALGORITHM

Intel’s Quick-Erase algorithm yields fast and reliable

electrical erasure of memory contents. The algo-

rithm employs a closed-loop flow, similar to the

Quick-Pulse Programming algorithm, to simulta-

neously remove charge from all bits in the array.

Erasure begins with a read of memory contents. The

M28F010 is erased when shipped from the factory.

Reading FFH data from the device would immedi-

ately be followed by device programming.

For devices being erased and reprogrammed, uni-

form and reliable erasure is ensured by first pro-

gramming all bits in the device to their charged state

(Data e00H). This is accomplished, using the

Quick-Pulse Programming algorithm, in approxi-

mately two seconds.

Erase execution then continues with an initial erase

operation. Erase verification (data eFFH) begins at

address 0000H and continues through the array to

the last address, or until data other than FFH is en-

countered. With each erase operation, an increasing

number of bytes verify to the erased state. Erase

efficiency may be improved by storing the address of

the last byte verified in a register. Following the next

erase operation, verification starts at that stored ad-

dress location. Erasure typically occurs in one sec-

ond. Figure 5 illustrates the Quick-Erase algorithm.

M28F010

271111–5

Bus Command Comments

Operation

Standby Wait for VPP Ramp to VPPH(1)

Initialize Pulse-Count

Write Set-up Data e40H

Program

Write Program Valid Address/Data

Standby Duration of Program

Operation (tWHWH1)

Write Program(2) Data eC0H; Stops Program

Verify Operation

Standby tWHGL

Read Read Byte to Verify

Programming

Standby Compare Data Output to Data

Expected

Write Read Data e00H, Resets the

Standby Wait for VPP Ramp to VPPL(1)

NOTES:

1. See DC Characteristics for value of VPPH. The VPP

power supply can be hard-wired to the device or

switchable. When VPP is switched, VPPL may be

ground, no-connect with a resistor tied to ground, or as

defined in Characteristics Section. Refer to Principles

of Operation.

2. Program Verify is only performed after byte program-

ming. A final read/compare may be performed (option-

al) after the register is written with the Read command.

3. CAUTION: The algorithm MUST BE FOLLOWED

to ensure proper and reliable operation of the de-

vice.

Figure 4. M28F010 Quick-Pulse Programming Algorithm

M28F010

271111–6

Bus Command Comments

Operation

Entire Memory Must e00H

Before Erasure

Use Quick-Pulse

Programming Algorithm

(Figure 4)

Standby Wait for VPP Ramp to VPPH(1)

Initialize Addresses and

Pulse-Count

Write Set-up Data e20H

Erase

Write Erase Data e20H

Standby Duration of Erase Operation

(tWHWH2)

Write Erase Addr eByte to Verify;

Verify Data eA0H; Stops Erase

Operation

Standby tWHGL

Read Read Byte to Verify Erasure

Standby Compare Output to FFH

Increment Pulse-Count

Write Read Data e00H, Resets the

Standby Wait for VPP Ramp to VPPL(1)

NOTES:

1. See DC Characteristics for value of VPPH. The VPP

power supply can be hard-wired to the device or

switchable. When VPP is switched, VPPL may be

ground, no-connect with a resistor tied to ground, or as

defined in Characteristics Section. Refer to Principles

of Operation.

2. Erase Verify is performed only after chip-erasure. A

final read/compare may be performed (optional) after

the register is written with the read command.

3. CAUTION: The algorithm MUST BE FOLLOWED

to ensure proper and reliable operation of the de-

vice.

Figure 5. M28F010 Quick-Erase Algorithm

M28F010

DESIGN CONSIDERATIONS

Two-Line Output Control

Flash-memories are often used in larger memory ar-

rays. Intel provides two read-control inputs to ac-

commodate multiple memory connections. Two-line

control provides for:

a. the lowest possible memory power dissipation

and,

b. complete assurance that output bus contention

will not occur.

To efficiently use these two control inputs, an ad-

dress-decoder output should drive chip-enable,

while the system’s read signal controls all flash-

memories and other parallel memories. This assures

that only enabled memory devices have active out-

puts, while deselected devices maintain the low

power standby condition.

Power Supply Decoupling

Flash-memory power-switching characteristics re-

quire careful device decoupling. System designers

are interested in three supply current (ICC) issuesÐ

standby, active, and transient current peaks pro-

duced by falling and rising edges of chip-enable. The

capacitive and inductive loads on the device outputs

determine the rnagnitudes of these peaks.

Two-line control and proper decoupling capacitor

selection will suppress transient voltage peaks.

Each device should have a 0.1 mF ceramic capacitor

connected between VCC and VSS, and between VPP

and VSS.

Place the high-frequency, low-inherent-inductance

capacitors as close as possible to the devices. Also,

for every eight devices, a 4.7 mF electrolytic capaci-

tor should be placed at the array’s power supply

connection, between VCC and VSS. The bulk capaci-

tor will overcome voltage slumps caused by printed-

circuit-board trace inductance, and will supply

charge to the smaller capacitors as needed.

VPP Trace on Printed Circuit Boards

Programming flash-memories, while they reside in

the target system, requires that the printed circuit

board designer pay attention to the VPP power sup-

ply trace. The VPP pin supplies the memory cell cur-

rent for programming. Use similar trace widths and

layout considerations given the VCC power bus. Ad-

equate VPP supply traces and decoupling will de-

crease VPP voltage spikes and overshoots.

Power Up/Down Protection

The M28F010 is designed to offer protection against

accidental erasure or programming during power

transitions. Upon power-up, the M28F010 is indiffer-

ent as to which power supply, VPP or VCC, powers

up first Power supply sequencing is not required. In-

ternal circuitry in the M28F010 ensures that the

command register is reset to the read mode on pow-

er up.

A system designer must guard against active writes

for VCC voltages above VLKO when VPP is active.

Since both WE and CE must be low for a command

write, driving either to VIH will inhibit writes. The con-

trol register architecture provides an added level of

protection since alteration of memory contents only

occurs after successful completion of the two-step

command sequences.

M28F010 Power Dissipation

When designing portable systems, designers must

consider battery power consumption not only during

device operation, but also for data retention during

system idle time. Flash nonvolatility increases the

usable battery life of your system because the

M28F010 does not consume any power to retain

code or data when the system is off. Table 4 illus-

trates the power dissipated when updating the

M28F010.

Table 4. M28F010 Typlcal Update Power Dissipation(4)

Operation Notes Power Dissipation

(Watt-Seconds)

Array Program/Program Verify 1 0.171

Array Erase/Erase Verify 2 0.136

One Complete Cycle 3 0.478

NOTES:

1. Formula to calculate typical Program/Program Verify Power e[VPP cÝBytes ctypical ÝProg Pulses (tWHWH1 c

IPP2 typical atWHGL cIPP4 typical)]a[VCC cÝBytes ctypical ÝProg Pulses (tWHWH1 cICC2 typical atWHGL c

ICC4 typical].

2. Formula to calculate typical Erase/Erase Verify Power e[VPP (VPP3 typical ctERASE typical aIPP5 typical ctWHGL c

ÝBytes)]a[VCC (ICC3 typical ctERASE typical aICC5 typical ctWHGL cÝBytes)].

3. One Complete Cycle eArray Preprogram aArray Erase aProgram.

4. ‘‘Typicals’’ are not guaranteed, but based on a limited number of samples from production lots.

M28F010

ABSOLUTE MAXIMUM RATINGS*

Case Temperature Under BiasÀÀÀb55§Ctoa

125§C

Storage Temperature ÀÀÀÀÀÀÀÀÀÀb65§Ctoa

150§C

Voltage on Any Pin with

Respect to Ground ÀÀÀÀÀÀÀÀÀÀb2.0V to a7.0V(1)

Voltage on Pin A9with

Respect to Ground ÀÀÀÀÀÀÀb2.0V to a13.5V(1, 2)

VPP Supply Voltage with

Respect to Ground

During Erase/Program ÀÀÀÀb2.0V to a14.0V(1, 2)

VCC Supply Voltage with

Respect to Ground ÀÀÀÀÀÀÀÀÀÀb2.0V to a7.0V(1)

Output Short Circuit CurrentÀÀÀÀÀÀÀÀÀÀÀÀÀ100 mA(3)

NOTICE: This data sheet contains preliminary infor-

mation on new products in production. The specifica-

tions are subject to change without notice. Verify with

your local Intel Sales office that you have the latest

data sheet before finalizing a design.

WARNING: Stressing the device beyond the ‘‘Absolute

Maximum Ratings’’ may cause permanent damage.

These are stress ratings only. Operation beyond the

‘‘Operating Conditions’’ is not recommended and ex-

tended exposure beyond the ‘‘Operating Conditions’’

may affect device reliability.

NOTES:

1. Minimum DC input voltage is b0.5V. During transitions, inputs may undershoot to b2.0V for periods less

than 20 ns. Maximum DC voltage on output pins is VCC a0.5V, which may overshoot to VCC a2.0V for

periods less than 20 ns.

2. Maximum DC voltage on A9or VPP may overshoot to a14.0V for periods less than 20 ns.

3. Output shorted for no more than one second. No more than one output shorted at a time.

OPERATING CONDITIONS

Symbol Description Min Max Units Comments

VPPL VPP during Read-Only Operations 0.00 VCC a2.0V V NOTE: Erase/Program are

Inhibited when VPP eVPPL

VPPH VPP during Read/Write Operations 11.40 12.60 V

MIL-STD-883

Symbol Description Min Max Units

TCOperating Temperature b55 a125 §C

(Instant On)

VCC Digital Supply Voltage 4.50 5.50 V

Extended Temperature

Symbol Description Min Max Units

TCCase Temperature b40 a110 §C

(Instant On)

VCC Digital Supply Voltage 4.50 5.50 V

Avionics Grade

Symbol Description Min Max Units

TCCase Temperature b40 a125 §C

(Instant On)

VCC Digital Supply Voltage 4.50 5.50 V

M28F010

DC CHARACTERISTICSÐTTL/NMOS COMPATIBLE

Symbol Parameter Limits Unit Comments

Min Max

ILI Input Leakage Current g1.0 mAV

CC eVCC Max

VIN eVCC or VSS

ILO Output Leakage Current g10 mAV

CC eVCC Max

VOUT eVCC or VSS

ICCS VCC Standby Current 1.0 mA VCC eVCC Max

CE eVIH

ICC1 VCC Active Read Current 30 mA VCC eVCC Max, CE eVIL

fe6 MHz, IOUT e0mA

CC2 VCC Programming Current 30 mA Programming in Progress

ICC3 VCC Erase Current 30 mA Erasure in Progress

IPPS VPP Leakage Current g10 mAV

PP eVPPL

IPP1 VPP Read Current 200 mAV

PP eVPPH Max

g10 VPP eVPPL

IPP2 VPP Programming Current 30 mA VPP eVPPH Max

Programming in Progress

IPP3 VPP Erase Current 30 mA VPP eVPPH Max

Erasure in Progress

VIL Input Low Voltage b0.5 0.8 V

VIH Input High Voltage 2.0 VCC a0.5 V

VOL Output Low Voltage 0.45 V IOL e2.1 mA

VCC eVCC Min

VOH1 Output High Voltage 2.4 V IOH eb

2.5 mA

VCC eVCC Min

VID A9intelligent Identifer Voltage 11.50 13.00 V

IID A9intelligent Identifier Current 500 mAA

M28F010

DC CHARACTERISTICSÐCMOS COMPATIBLE (Over Specified Operating Conditions)

Symbol Parameter Limits Unit Comments

Min Max

ILI Input Leakage Current g1.0 mAV

CC eVCC Max

VIN eVCC or VSS

ILO Output Leakage Current g10 mAV

CC eVCC Max

VOUT eVCC or VSS

ICCS VCC Standby Current 100 mAV

CC eVCC Max

CE eVCC g0.2V

ICC1 VCC Active Read Current 30 mA VCC eVCC Max, CE eVIL

fe6 MHz, IOUT e0mA

CC2 VCC Programming Current 30 mA Programming in Progress

ICC3 VCC Erase Current 30 mA Erasure in Progress

IPPS VPP Leakage Current g10 mAV

PP eVPPL

IPP1 VPP Read Current 200 mAV

PP eVPPH Max

g10 VPP eVPPL

IPP2 VPP Programming Current 30 mA VPP eVPPH Max

Programming in Progress

IPP3 VPP Erase Current 30 mA VPP eVPPH Max

Erasure in Progress

VIL Input Low Voltage b0.5 0.8 V

VIH Input High Voltage 0.7 VCC VCC a0.5 V

VOL Output Low Voltage 0.45 V IOL e2.1 mA

VCC eVCC Min

VOH1 Output High Voltage 0.85 VCC VIOH eb

2.5 mA, VCC eVCC Min

VOH2 VCC b0.4 IOH eb

100 mA, VCC eVCC Min

VID A9intelligent Identifer Voltage 11.50 13.00 V

IID A9intelligent Identifier Current 500 mAA

CAPACITANCE TCe25§C, f e1.0 MHz

Symbol Parameter Limits Unit Conditions

Min Max

CIN Address/Control Capacitance 6 pF VIN e0V

COUT Output Capacitance 12 pF VOUT e0V

M28F010

AC TESTING INPUT/OUTPUT WAVEFORM

271111–7

AC Testing: Inputs are driven at VOH1 for a logic ‘‘1’’ and VOL for

a logic ‘‘0’’. Testing measurements are made at VIH for a logic

‘‘1’’ and VIL for a logic ‘‘0’’. Rise/Fall time s10 ns.

AC LOAD CIRCUIT

271111–8

CLe100 pF

CLincludes Jig Capacitance

AC TEST CONDITIONS

Input Rise and Fall Times (10% to 90%)ÀÀÀÀÀÀ10 ns

Input Pulse Levels ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀVOL and VOH1

Input Timing Reference Level ÀÀÀÀÀÀÀÀÀÀVIL and VIH

Output Timing Reference Level ÀÀÀÀÀÀÀÀVIL and VIH

AC CHARACTERISTICSÐRead-Only Operations

Versions M28F010-90 M28F010-12 M28F010-15 M28F010-20 M28F010-25 Unit

Symbol Characteristic Min Max Min Max Min Max Min Max Min Max

tAVAV/tRC Read Cycle Time 90 120 150 200 250 ns

tELQV/tCE Chip Enable 90 120 150 200 250 ns

Access Time

tAVQV/tACC Address Access 90 120 150 200 250 ns

Time

tGLQV/tOE Output Enable 40 50 55 60 65 ns

Access Time

tELQX/tLZ Chip Enable to 0 0 0 0 0 ns

Output in Low Z

tGLQX/tOLZ Output Enable to 0 0 0 0 0 ns

Output in Low Z

tGHQZ/tDF Output Disable to 30 30 35 45 60 ns

Output in High Z

tOH Output Hold from

Address, CE,0 0 0 0 0 ns

or OE Change(1)

tWHGL Write Recovery 6 6 6 6 6 ms

Time before Read

NOTE:

1. Whichever occurs first.

M28F010

Figure 6. AC Waveforms for Read Operations

271111–9

M28F010

AC CHARACTERISTICSÐWrite/Erase/Program Operations(1,2)

Versions M28F010-90 M28F010-12 M28F010-15 M28F010-20 M28F010-25 Unit

Symbol Characteristic Min Max Min Max Min Max Min Max Min Max

tAVAV/tWC Write Cycle Time 90 120 150 200 250 ns

tAVWL/tAS Address Set-Up 0 0 0 0 0 ns

Time

tWLAX/tAH Address Hold Time 60 60 60 90 ns

tDVWH/tDS Data Set-up Time 50 50 50 50 50 ns

tWHDX/tDH Data Hold Time 10 10 10 10 10 ns

tWHGL Write Recovery 6 6 6 6 6 ms

Time before Read

tGHWL Read Recovery 0 0 0 0 0 ms

Time before Write

tELWL/tCS Chip Enable 20 20 20 20 20 ns

Set-Up Time

before Write

tWHEH/tCH Chip Enable 0 0 0 0 0 ns

Hold Time

tWLWH/tWP Write Pulse Width 80 80 80 80 80 ns

tELEH Alternative Write 80 80 80 80 80 ns

Pulse Width

tWHWL/tWPH Write Pulse 20 20 20 20 20 ns

Width High

tWHWH1 Duration of 10 25 10 25 10 25 10 25 10 25 ms

Programming

Operation

tWHWH2 Duration of 9.5 10.5 9.5 10.5 9.5 10.5 9.5 10.5 9.5 10.5 ms

Erase Operation

tVPEL VPP Set-Up 100 100 100 100 100 ns

Time to Chip

Enable Low

NOTES:

1. Read timing characteristics during read/write operations are the same as during read-only operations. Refer to AC Char-

acteristics for Read-Only Operations.

2. Chip-Enable Controlled Writes: Write operations are driven by the valid combination of Chip-Enable and Write-Enable. In

systems where Chip-Enable defines the write pulse width (within a longer Write-Enable timing waveform) all set-up, hold, and

inactive Write-Enable times should be measured relative to the Chip-Enable waveform.

M28F010

ERASE AND PROGRAMMING PERFORMANCE

Parameter Limits Unit Comments

Min Typ Max

Chip Erase Time 5(1) 30 Sec Excludes 00H Programming

Prior to Erasure

Chip Program Time 2(1) 24(2) Sec Excludes System-Level Overhead

Erase/Program Cycles 10,000 100,000 Cycles

NOTES:

1. 25§C, 12.0V VPP, 10,000 Cycles.

2. Minimum byte programming time excluding system overhead is 16 msec (10 msec program a6msec write recovery),

while maximum is 400 msec/byte (16 msec x 25 loops allowed by algorithm). Max chip programming time is specified lower

than the worst case allowed by the programming algorithm since most bytes program significantly faster than the worst case

byte.

271111–10

Figure 7. M28F010 Typical Programming Time vs. Temperature

271111–11

Figure 8. M28F010 Typical Programming Time vs. VPP Voltage

M28F010

271111–12

Figure 9. M28F010 Typical Erase Time vs. Temperature

271111–13

Figure 10. M28F010 Typical Erase Time vs. VPP Voltage

M28F010

Figure 11. AC Waveforms for Programming Operations

Alternative Write Timing

271111–14

M28F010

Figure 12. AC Waveforms for Erase Operations

271111–15

M28F010

ADDITIONAL INFORMATION

Order

Number

ER-20, ‘‘ETOX II Flash Memory Technology 294005

ER-24, ‘‘The Intel 28F010 Flash Memory’’ 294008

RR-60, ‘‘ETOX II Flash Memory Reliability 293002

Data Summary’’

AP-316, ‘‘Using Flash Memory for In-System 292046

Reprogrammable Nonvolatile Storage’’

AP-325, ‘‘Guide to Flash Memory 292059

Reprogramming’’