5962-8867002LX - Cypress Semiconductor

Flash Erasable, Reprogrammable CMOS PAL® Devi ce

PALC22V10D

For new designs, please ref er to the PALCE22 V10

Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600

July 1991 - Revised October 1995

Features

• Ad vanced second- generation PAL architect ure

•Low power

—90 mA max. comme rcial (10 ns)

—1 30 mA m ax. co mm e rc ia l (7 .5 n s)

• CMOS Flash EPR OM technolog y f or electr ical erasabil-

ity and reprogrammabilit y

• Vari able product terms

—2 x(8 thr ough 16) product terms

• User-programmabl e macrocell

—Output polarity control

—Indivi dually select able for regi stered or combinato-

rial operation

• Up to 22 input terms and 10 outputs

• DIP, LCC, and PLCC available

—7.5 ns comme rcial version

5 ns tCO

5 ns tS

7.5 ns tPD

133-M Hz state machine

—10 ns military and indust rial versions

6 ns tCO

6 ns tS

10 ns tPD

110-M Hz state machine

—1 5- n s co mm e rc ia l an d militar y

versions

—2 5- n s co mm e rc ia l an d militar y

versions

• High reliability

—Proven Flash EPROM technology

100% programming and functional testing

Functional Description

The Cypress PALC22V10D is a CMOS Flash Erasable sec-

ond-generation programmable array logic device. It is imple-

mented with the familiar sum-of-products (AND-OR) logic

struct ure and the programmable macroce ll .

The PALC22 V10D is e x e cuted i n a 24-pin 300-mil molded DIP,

a 300-m il cerDIP, a 28-l ead square cer amic l eadless chip car-

rier, a 28-le ad square pl astic leaded chi p carrier, and pro vides

up t o 22 inputs an d 10 outputs . The 22V10D can b e electri cally

erased a nd reprog ram med. The pr ogr ammab le mac rocell pro -

vides the capability of defining the arch it ecture of each output

indiv idually. Each of the 10 potential out puts may be specified

as “reg ister ed” or “com binatorial .” Po larity of each out put ma y

also be individually selected, allowing complete flexibility of

output configuration. Further configurability is provided

through “arra y” configur able “output enable” for each potential

output. This feature allow s the 10 outputs t o be reconf igured

as inputs on an indivi dual basi s, or alternat ely used as a com-

bination I/O cont rolled by t he programmable arra y.

PALC22V10D features a variable product term architecture.

There ar e 5 pa irs of produc t term sums beg in ning at 8 produc t

terms per output and incrementing by 2 to 16 product terms

per output. By providing this variable structure, the PAL C

22V10D is optimized to the configurations found in a majority

of applications without creating devices that bur den the prod-

uct term structures with unusable product terms and lower per-

formance.

Additional features of the Cypress PALC22V10D include a

synchro nous pr eset and an async hronous r eset product term.

These product t erms are common to all macrocells, eliminat-

ing the need t o dedicate standard product term s for ini tializa-

tion funct ions. T he de vice aut omatically res ets upon powe r-up .

The PALC22V10D, featuring programmable macrocells and

variab le produ ct terms, provides a device with the flexibility to

implement l ogi c functions in the 500- to 800-gate-array com-

plexity. Since each of the 10 output pins may be individually

confi gured as i nputs on a temporary or permanent basis , func-

tions requiring up to 21 inputs and only a single output and

down to 12 inputs and 10 outpu ts are possible. The 10 poten-

tial outputs are enabled using product terms. Any output pin

may be permanently selected as an output or arbitrarily en-

abled as an output and an input through the sel ective use of

indiv idual product terms associated with each output. Each of

these out puts is achie ved th rough an individua l programmab le

macrocell. These macrocells are programmable to provide a

combinat orial or regi stered i nverting or non-inve rting o utput. I n

a registered mode of opera tion, the output of the register is f ed

back into the array, providing current status information to the

array. This information is av ailable for establishing the next re-

sult in appli cations such as cont rol state machines. In a com-

binatorial configuration, the combinatori al output or, if the out-

put is disabled, the signal present on the I/O pin is made

available to the array. The flexibi lity provided b y both program-

mab le produ ct term contro l of the outputs and v ariab le product

terms allows a significan t gai n in funct ional de nsity th rough t he

use of programmable logic.

Along with this increase in functional density, the Cypress

PALC22V10D prov ides lo wer-pow er operati on through the use

of CMOS technology, and incr eased testability with Flash re-

programmability.

PAL is a register ed trademark of Advanced Micro Devices

PALC22V10D

Logic Block Diagram(PDIP/CDIP)

Pin Configuration V10D–1

PLCC

Top View

Macrocell

810 12 14 16 16 14 12 10 8

111098765432112

13 14 15 16 17 18 19 20 21 22 23 24

Preset

PROGRAMMABLE

AND ARRAY

(132 X44)

IIIIIIIIIICP/I

VSS

I I/O9I/O8I/O7I/O6I/O5I/O4I/O3I/O2I/O1I/O0VCC

Reset

Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell

I/O

CP/I

I/O

I/O8

I/O

N/C

V10D–2

LCC

Top View

4 3 2 282726

12131415161718

I/O

CP/I

I/O

N/C

V10D–3

11 121314 1516 1718

4 3 2 2827 261

Configura tion Table

Registered/Combinatorial

C1C0Configuration

0 0 Registered/Active LO W

0 1 Registered/ Active HIGH

1 0 Combinator ial/Active LOW

1 1 Combinator ial/Active HIGH

Configuration Table

Registered/Combinatorial

C1C0Configuration

PALC22V10D

Maximum Ratings

(Abo v e which the useful life ma y be impair ed. F or user guide-

li nes, not tested .)

Storage Temperatur e .....................................−65°C to +150°C

Ambient Temperature with

Power Applied..................................................−55°C to +125°C

Supply Voltage to Ground Potential

(Pin 24 to Pi n 12).................................................−0.5V to +7.0V

DC Vol tage Applied to Outputs

in High Z State.....................................................−0.5V to +7.0V

DC Input Voltage.............................................-0.5V to +7.0V

Ou tp u t C urre n t in to O u tp u ts (LOW ) .. ........ ....... ....... .....16 m A

DC Programming Voltage .............................................12.5V

Latch-Up Current....... ................. ................. ............>200 mA

Static Discharge Volt age

(per MIL- STD-883, Method 3015) ... .......... ............. .. .>2001V

]]

Macrocell

OUTPUT

SELECT

MUX

INPUT/

FEEDBACK

MUX

MACROCELL

CV10D–4

Operating Range

Range Ambient

Temperature VCC

Commercial 0°C to +7 5°C 5V ±5%

Military[1] −55°C to +125°C 5V ±10%

Industrial −40°C to +85 °C5V ±10%

Note:

1. TA is the “instant on” case temperature.

Electrical Characteristics Over the Operating Range[2]

Parameter Description Test Conditi ons Min. Max. Unit

VOH Output HIGH Voltage VCC = Mi n.,

VIN = VIH or VIL IOH = -3.2 mA Com’l2.4 V

IOH = -2 mA Mil/Ind

VOL Output LO W Voltage VCC = Min.,

VIN = VIH or VIL IOL = 16 mA Com’l0.5 V

IOL = 12 mA Mil/Ind

VIH Input HIGH Level Guaranteed Input Logical HIGH Voltage for All Inputs[3] 2.0 V

VIL[2] Input LOW Level Guaranteed Input Logical LOW Voltage for All Inputs[3] -0.5 0.8 V

IIX Input Leakage Current VSS < VIN < VCC, VCC = Max. -10 10 µA

IOZ Output Leakage Current VCC = Max., VSS < VOUT < VCC -40 40 µA

ISC Output Short Circuit Cur rent VCC = Max., VOUT = 0.5V[5,6] -30 -90 mA

PALC22V10D

ICC1 Standby Powe r Suppl y

Current VCC = Max.,

VIN = GND,

Outputs Open in

Unprogrammed De-

vice

10, 15, 25 ns Com’l90 mA

7.5 ns Com’l130 mA

15, 25 ns Mil/Ind 120 mA

10 ns Mil/Ind 120 mA

ICC2[6] Operating Power Supply

Current VCC = Max., VIL =

0V, VIH = 3V,

Output Open, De-

vice Programmed

as a 10-Bit Counter,

f = 25 MHz

10, 15, 25 ns Com’l110 mA

7.5 ns Com’l140 mA

15, 25 ns Mil/Ind 130 mA

10 ns Mil/Ind 130 mA

Notes:

2. See the last page of this specification for Group A subgroup testing information.

3. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included.

4. VIL (Min.) is equal to -3.0V for pulse durations less than 20 ns.

5. Not mor e tha n one o utput should be t est ed at a time . Du rati on of the s hort circuit shou ld not b e mor e tha n one second. VOUT = 0.5V has b een chosen t o a v oid test pr ob lems

caused b y tester g ro und deg radati on.

6. Tested initially and after any design or process changes that may affect these parameters.

Electrical Characteristics Over the Operating Range[2]

Parameter Description Test Conditi ons Min. Max. Unit

Capacitance[6]

Parameter D escription Test Conditions Min. Max. Unit

CIN Input Capacitance VIN = 2.0V @ f = 1 MHz 10 pF

COUT Outp ut Capacitance VOUT = 2.0V @ f = 1 MHz 10 pF

Endurance Characteris tics[6]

P arameter Descript ion Test Condi ti ons Min. Max. Unit

N M inimum Reprogramming Cycl es Normal Progr amm ing Conditions 100 Cycles

AC Te st Loads and Waveforms

OUTPUT

INCLUDING

JIG AND

SCOPE

(a) (b)

OUTPUT

INCLUDING

JIG AND

SCOPE

5pF

(c)

OUTPUT

R1238Ω

(319ΩMIL) R1238Ω

(319ΩMIL)

R2170Ω

(236ΩMIL) R2170Ω

(236ΩMIL) 750Ω

(1.2KΩ

MIL)

OUTPUT 2.08V=V thc OUTPUT 2.13V=V thm

90%

10%

3.0V

GND

90%

10%

ALL INPUT PULSES

<2ns <2ns

(d) V10D–5

V10D–6V10D–7

99Ω136Ω

Equivalent to: THÉ VENIN EQUIVALENT(Commercial) Equivalent to: THÉ VENIN EQUIVALENT(Military)

PALC22V10D

Load Speed CLPackage

7.5, 10, 15, 25

ns 50 pF PDIP, CDIP,

PLCC, LCC

Parameter VXOutput Waveform Measurement Level

tER (- ) 1.5V VOH 0.5V VX

0.5V

tER (+) 2.6V VOL VX

tEA (+) 0V

0.5V

tEA (- ) Vthc VXVOL

1.5V

VXVOH

V10D–8

V10D–9

V10D–10

V10D–11

(e) Test Waveforms

PALC22V10D

Commerc ia l Swi tch i ng C h ar acteristi cs PALC 22V10D[2, 7]

22V10D-7 22V10D-10 22V10D-15 22V10D-25

Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Unit

tPD Input to Output

Propagation Del ay[8, 9] 37.5310315325ns

tEA Input to Output Enab le Delay[10] 8 101525ns

tER Input to Output Di sable Delay[11] 8 101525ns

tCO Clock to Output Delay[8, 9] 252728215ns

tS1 Input or Feedback Set-Up Time 5 6 10 15 ns

tS2 Synchronous Preset Set-Up Time 6 7 10 15 ns

tHInput Hold Time 0000ns

tPExternal Clock Period (tCO + tS)10122030 ns

tWH Clock Width HIGH[6] 3 3 6 13 ns

tWL Clock Width LOW[6] 3 3 6 13 ns

fMAX1 External Maximum Frequency

(1/(tCO + tS))[12] 100 76.9 55.5 33.3 MHz

fMAX2 Data Path Maxim um Frequency

(1/(tWH + tWL))[6 , 13] 166 142 83.3 35.7 MHz

fMAX3 Internal Feedback Maxi m um

Frequency (1/(tCF + tS))[6,14] 133 111 68.9 38.5 MHz

tCF Register Clock to

Feedback Input[6, 1 5] 2.5 3 4.5 13 ns

tAW Asynchronous Reset Width 8 10 15 25 ns

tAR Asynchronous Reset Recover y

Time 5 6 10 25 ns

tAP Asynchronous Reset to

Registered O utput Delay 12 13 20 25 ns

tSPR Synchronous Preset Recovery

Time 6 8 10 15 ns

tPR Power-Up Reset Time[6,16] 1111µs

Notes:

7. Part (a) of AC Test Loads and Waveforms is used for all parameters except tER and tEA(+). Part (b) of AC Test Loads and W ave forms is used for tER. Part ( c) of A C Test

Loads and W a v ef orms is used f o r tEA(+).

8. Min. times are tested initially and after any design or process changes that ma y affect these parameters.

9. This specification is guaranteed for all device outputs changing state in a given access cycle .

10. The test load of part (a) of AC Test Loads and W avef orms is used for measuring tEA(-). The te st loa d of part (c) of A C Test Loads and Wa vef orms is us ed for measuring

tEA(+) only. Please see part (e) of A C Tes t Load s and W a v ef orms f or ena ble a nd disa bl e test w a v ef orms and m easureme nt ref er ence le vels.

11. This parameter is measured as the time after output disable input that the previous output data state remains stable on the output. This delay is measured to

the point at which a previous HIGH level has fallen to 0.5 volts below VOH min. or a prev ious LOW le ve l has risen to 0.5 vol ts abov e V OL max. Please see part (e) of AC

Test Load s and W a v ef orms f or ena bl e and di sab le tes t wa veforms and m eas urement r ef erence l e v els .

12. This specification indicates the guaranteed maximum frequency at which a state machine configuration with external feedback can operate.

13. This specification indicates the guaranteed maximum frequency at which the device can operate in data path mode.

14. This specification indicates the guaranteed maximum frequency at which a state machine configuration with internal only feedback can operate.

15. This parameter is calculated from the clock period at fMAX internal (1/fMAX3) as measured ( see Not e abo v e) minus t S.

16. The registers in the PALC22V10D have been designed with the capability to reset during system power-up. Following power-up, all registers will be reset to a

logic LOW state. The output state will depend on the polarity of the output b u ffer. This feature is useful in establishing state machine initialization. To insure

proper operation, the rise in VCC must be mo notonic and the t iming cons traints depicted in P o wer- Up Res et W a v ef orm m ust be satisfied .

PALC22V10D

Milita ry and Industrial Switching Charac teristics PALC22V10D[2, 7]

22V10D-10 22V10D-15 22V10D-25

Parameter Description Min. Max. Min. Max. Min. Max. Unit

tPD Input to Output

Propagation Dela y[8, 9] 310315325ns

tEA Input to Output Enab le Del ay[10] 10 15 25 ns

tER Input to Output Disable Delay[11] 10 15 25 ns

tCO Clock to Out put Delay[8, 9] 2728215ns

tS1 Input or Feedback Set-Up Time 6 10 18 ns

tS2 Synchronous Preset Set-Up Time 7 10 18 ns

tHInput Hold Time 0 0 0 ns

tPExternal Clock Per iod (tCO + tS)12 20 33 ns

tWH Clock Width HIGH[6] 3614ns

tWL Clock Width LOW[6] 3614ns

fMAX1 External Maximum Frequency

(1/(tCO + tS))[12] 76.9 50.0 30.3 MHz

fMAX2 Data Path Maxim um Fre quency

(1/(tWH + tWL))[6 , 13] 142 83.3 35.7 MHz

fMAX3 Internal Feedback Maximum

Frequency (1/(tCF + tS))[6,14] 111 68.9 32.2 MHz

tCF Register C l o ck t o

Feedback Input[6,15] 34.513ns

tAW Asynchronous Reset Width 10 15 25 n s

tAR Asynchronous Reset

Re covery Ti m e 61225ns

tAP Asynchronous Reset to

Registered Output Delay 12 20 25 ns

tSPR Synchronous Preset

Re covery Ti m e 82025ns

tPR Power-Up Reset Time[6, 16] 111µs

PALC22V10D

Swi t ch ing Waveform

Power-Up Reset W avef orm[16]

tStHtWL

tWH

tSPR

tAR

tAW

tAP

tCO

tPD

V10D–12

tER[NO TAG] tEA[NO TAG]

INPUTS I/O,

REGISTERED

FEEDBACK

SYNCHRONOUS

PRESET

ASYNCHRONOUS

RESET

REGISTERED

OUTPUTS

COMBINATORIAL

OUTPUTS

tPR

POWER

CLOCK

tWL

10%

REGISTERED

ACTIVE LOW

OUTPUTS

V10D–13

SUPPLY VOLTAGE

tPRMAX= 1 µs

90% VCC

PALC22V10D

Functional Logic Diagram for PALC22V10D

Macro–

cell

Macro–

cell

Macro–

cell

Macro–

cell

Macro–

cell

Macro–

cell

Macro–

cell

Macro–

cell

Macro–

cell

Macro–

cell

16 20 24 28 32 36 40

128

V10D–14

PALC22V10D

MILITARY SPECIFICATIONS

Gr oup A Subgroup Testing

Orde ring Inform ation

ICC

(mA) tPD

(ns) tS

(ns) tCO

(ns) Orderi ng Code Package

Name P ackage Type Operating

Range

130 7.5 5 5 PALC22V10D-7JC J64 28-Lead Plastic Leaded Chip Carrier Commercial

PALC22V10D-7PC P13 24-Lead (300-Mil) Molded DIP

90 10 6 7 PALC22V10D-10JC J64 28-Lead Plast ic Leaded Chip Carrier Commercial

PALC22V10D-10PC P13 24-Lead (300-Mi l) Molded DIP

150 10 6 7 PALC22V10D-10JI J64 28-Lead Plast ic Leaded Chip Carrier Industrial

PALC22V10D-10PI P13 24-Lead (300-Mi l) Molded DIP

150 10 6 7 PALC22V10D-10DMB D14 24-Lead (300-Mil) CerDIP Military

PALC22V10D-10KMB K73 24-Lead Rectangular Cerpack

PALC22V10D-10LMB L64 28-Square Leadless Chip Carrier

90 15 7.5 10 PALC22V10D-15JC J64 28-Lead Plastic Leaded Chip Carrier Commercial

PALC22V10D-15PC P13 24-Lead (300-Mi l) Molded DIP

120 15 7.5 10 PALC22V10 D-15JI J 64 28-Lead Plast ic Leaded Chip Carrier Industrial

PALC22V10D-15PI P13 24-Lead (300-Mi l) Molded DIP

120 15 7.5 10 PALC22V10 D-15DMB D14 24-Lead (300-Mi l) CerDIP Military

PALC22V10D-15KMB K73 24-Lead Rectangular Cerpack

PALC22V10D-15LMB L64 28-Square Leadless Chip Carrier

90 25 15 15 PALC22V10D-25JC J64 28-Lead Plast ic Leaded Chip Carrier Commercial

PALC22V10D-25PC P13 24-Lead (300-Mi l) Molded DIP

120 25 15 15 PALC22V10D-25JI J64 28-Lead Plastic Leaded Chip Carrier Industrial

PALC22V10D-25PI P13 24-Lead (300-Mi l) Molded DIP

120 25 15 15 PALC22V10 D-25DMB D14 24-Lead (300-Mi l) CerDIP Military

PALC22V10D-25KMB K73 24-Lead Rectangular Cerpack

PALC22V10D-25LMB L64 28-Square Leadless Chip Carrier

DC C h ar acteri stic s

Parameter Subgroups

VOH 1, 2, 3

VOL 1, 2, 3

VIH 1, 2, 3

VIL 1, 2, 3

IIX 1, 2, 3

IOZ 1, 2, 3

ICC 1, 2, 3

Swi tchin g C h ar acteristi cs

Parameter Subgroups

tPD 9, 10, 11

tCO 9, 10, 11

tS9, 10, 11

tH9, 10, 11

Docume nt #: 38-00185-H

PALC22V10D

Package Diag r ams

24–Lead (300–Mil) CerDIP D14

MIL-STD-1835 D-9 Config. A 28–Lead Plastic Leaded ChipCarrier J64

24–Lead Rectangular Cerpack K73

MIL-STD-1835 F-6 Config. A 28–Square Leadless Chip Carrier L64

MIL-STD-1835 C-4

PALC22V10D

of any circui try other than circuitry embodied in a Cypress Semiconductor pr oduct. Nor does it conv ey or imply any l icense under patent or other rights. C ypress Semicondu ctor does not authorize

its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

Package Diag r ams (c ont inued)

24–Lead (300–Mil) Molded DIP P13/P13A