M312L2920CZ0-CB3 - Samsung Semiconductor Division

DDR SDRAM

512MB, 1GB, 2GB Registered DIMM

Rev. 1.2 June 2005

66 TSOP-II and 60 ball FBGA with Pb-Free

(RoHS compliant)

INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,

AND IS SUBJECT TO CHANGE WITHOUT NOTICE.

NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,

EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,

TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL

INFORMATION IN THIS DOCUMENT IS PROVIDED

ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.

1. For updates or additional information about Samsung products, contact your nearest Samsung office.

2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar

applications where Product failure could result in loss of life or personal or physical harm, or any military or

defense application, or any governmental procurement to which special terms or provisions may apply.

* Samsung Electronics rese rves the right to change products or specification without notice.

DDR SDRAM Registered Module

184pin Registered Module based on 512Mb C-die

with 72-bit ECC

DDR SDRAM

512MB, 1GB, 2GB Registered DIMM

Rev. 1.2 June 2005

Table of Contents

1.0 Ordering Information...................................................................................................................4

2.0 Operating Frequencies................................................................................................................4

3.0 Feature.......................................................................................................................................... 4

4.0 Pin Configuration (Front side/back side) ................................................................................. 5

5.0 Pin Description ............................................................................................................................5

6.0 Functional Block Diagram ..........................................................................................................6

6.1 512MB, 64M x 72 ECC Module (M312L6523CUS) .............................................................................. 6

6.2 1GB, 128M x 72 ECC Module (M312L2923CUS) ............................................................................... 7

6.3 1GB, 128M x 72 ECC Module (M312L2920CUS) ............................................................................... 8

6.4 2GB, 256M x 72 ECC Module (M312L5628CU0)................................................................................9

6.5 512MB, 64M x 72 ECC Module (M312L6523CZ0)............................................................................................10

6.6 1GB, 128M x 72 ECC Module (M312L29 23CZ0) ..............................................................................11

6.7 1GB, 128M x 72 ECC Module (M312L2920CZ0)..............................................................................................12

6.8 2GB, 256M x 72 ECC Module (M312L5720CZ0)..............................................................................................13

7.0 Absolute Maximum Ratings......................................................................................................14

8.0 Power & DC Operating Conditions (SSTL_2 In/Out) .............................................................. 14

9.0 DDR SDRAM IDD spec table.....................................................................................................15

9.1 M312L6523CUS [ (64M x 8) * 9 , 512MB Module ] ........................................................................... 15

9.2 M312L2923CUS [ (64M x 8) * 18 , 1GB Module ]..............................................................................15

9.3 M312L2920CUS [ (128M x 4) * 18 , 1GB Module ]............................................................................................ 16

9.4 M312L5628CU0 [ (st .256M x 4) * 18 , 2GB Module ] ........................................................................16

9.5 M312L6523CZ0 [ (64M x 8) * 9 , 512MB Module ]............................................................................................17

9.6 M312L2923BG0 [ (64M x 8) * 18 , 1GB Module ] ............................................................................. 17

9.7 M312L2920BG0 [ (128M x 4) * 18 , 1GB Module ]............................................................................. 18

9.8 M312L5720BG0 [ (128M x 4) * 36, 2GB Module ] .............................................................................18

10.0 AC Operating Conditions........................................................................................................ 19

11.0 Input/Output Capacitance.......................................................................................................19

12.0 AC Timming Parameters & Specifications............................................................................20

13.0 System Characteristics for DDR SDRAM..............................................................................21

14.0 Component Notes....................................................................................................................22

15.0 System Notes...........................................................................................................................23

16.0 Command Truth Table.............................................................................................................24

17.0 Physical Dimensions...............................................................................................................25

17.1 64M x 72 (M312L6523CUS)........................................................................................................ 25

17.2 128Mx72 (M312L2 923CUS), 128Mx72 (M312L2920 CUS) ................................................................ 26

17.3 st.256Mx72 (M312L5628CU0).....................................................................................................27

17.4 64Mx72 (M312L6523CZ0) ..........................................................................................................28

17.5 128Mx72 (M312L2923CZ0), (M312L29 20CZ0)............................................................................... 29

17.6 256Mx72 (M312L5720CZ0) ........................................................................................................ 30

DDR SDRAM

512MB, 1GB, 2GB Registered DIMM

Rev. 1.2 June 2005

Revision History

Revision Month Year History

0.0 September 2004 - First release

0.1 October 2004 - Changed IDD current.

1.0 February 2005 - Revision 1.0 spec. release.

1.1 April 2005 - Added notice.

1.2 June 2005 - changed master format

DDR SDRAM

512MB, 1GB, 2GB Registered DIMM

Rev. 1.2 June 2005

CC(DDR400@CL=3) B3(DDR333@CL=2.5) A2(DDR266@CL=2) B0(DDR266@CL=2.5)

Speed @CL2 - 133MHz 133MHz 100MHz

Speed @CL2.5 166MHz 166MHz 133MHz 133MHz

Speed @CL3 200MHz - - -

CL-tRCD-tRP 3-3-3 2.5-3-3 2-3-3 2.5-3-3

184Pin Registered DIMM based on 512Mb C-die (x4, x8)

• VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333

• VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400

• Double-data-rate architecture; two data transfers per clock cycle

• Bidirectional data strobe [DQ] (x4,x8) & [L(U)DQS] (x16)

• Differential clock inputs(CK and CK)

• DLL aligns DQ and DQS transition with CK transition

• Programmable Read latency : DDR266(2, 2.5 Clock), DDR333(2.5 Clock), DDR400(3 Clock)

• Programmable Burst length (2, 4, 8)

• Programmable Burst type (sequential & interleave)

• Edge aligned data output, center aligned data input

• Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh)

• Serial presence detect with EEPROM

• SSTL_2 Interface

• 66pin TSOP II and 60 ball FBGA Pb-Free package

• RoHS compliant

1.0 Ordering Information

2.0 Operating Frequencies

Part Number Density Organization Component Composition Height

M312L6523CUS-C A2/B0 512MB 64M x 72 64Mx8( K4H510838C) * 9EA 1,200 mil

M312L2923CUS-C A2/B0 1GB 128M x 72 64Mx8( K4H510838C) * 18EA 1,200mil

M312L2920CUS-CA2/B0 1GB 128M x 72 128Mx4( K4H510438C) * 18EA 1,200mil

M312L5628CU0-CA2/B0 2GB 256M x 72 st.256Mx4( K4H1G0638C) * 18EA 1,200mil

M312L6523CZ0-CCC/B3 512MB 64Mx72 64Mx8( K4H510838C) * 9EA 1,125mil

M312L2923CZ0-CCC/B3 1GB 128M x 72 64Mx8( K4H510838C) * 18EA 1,125mil

M312L2920CZ0-CCC/B3 1GB 128M x 72 128Mx4( K4H510438C) * 18EA 1,125mil

M312L5720CZ0-CCC/B3 2GB 256M x 72 128Mx4( K4H510438C) * 36EA 1,200mil

3.0 Feature

DDR SDRAM

512MB, 1GB, 2GB Registered DIMM

Rev. 1.2 June 2005

Note :

1. * : These pins are not used in this module.

2. Pins 111, 158 are NC for 1row module & used for 2row module.

3. Pins 97, 107, 119, 129, 140, 149, 159, 169, 177 : DM (x8 base module) or DQS (x4 base module).

Pin Front Pin Front Pin Front Pin Back Pin Back Pin Back

1 VREF 32 A5 62 VDDQ 93 VSS 124 VSS 154 RAS

2 DQ0 33 DQ24 63 WE 94 DQ4 125 A6 155 DQ45

3 VSS 34 VSS 64 DQ41 95 DQ5 126 DQ28 156 VDDQ

4 DQ1 35 DQ25 65 CAS 96 VDDQ 127 DQ29 157 CS0

5 DQS0 36 DQS3 66 VSS 97 DM0/DQS9 128 VDDQ 158 CS1

6 DQ2 37 A4 67 DQS5 98 DQ6 129 DM3/DQS12 159 DM5/DQS14

7 VDD 38 VDD 68 DQ42 99 DQ7 130 A3 160 VSS

8 DQ3 39 DQ26 69 DQ43 100 VSS 131 DQ30 161 DQ46

9 NC 40 DQ27 70 VDD 101 NC 132 VSS 162 DQ47

10 RESET 41 A2 71 *CS2 102 NC 133 DQ31 163 *CS3

11 VSS 42 VSS 72 DQ48 103 NC 134 CB4 164 VDDQ

12 DQ8 43 A1 73 DQ49 104 VDDQ 135 CB5 165 DQ52

13 DQ9 44 CB0 74 VSS 105 DQ12 136 VDDQ 166 DQ53

14 DQS1 45 CB1 75 *CK2 106 DQ13 137 CK0 167 *A13

15 VDDQ 46 VDD 76 *CK2 107 DM1/DQS10 138 CK0 168 VDD

16 *CK1 47 DQS8 77 VDDQ 108 VDD 139 VSS 169 DM6/DQS15

17 *CK1 48 A0 78 DQS6 109 DQ14 140 DM8/DQS17 170 DQ54

18 VSS 49 CB2 79 DQ50 110 DQ15 141 A10 171 DQ55

19 DQ10 50 VSS 80 DQ51 111 CKE1 142 CB6 172 VDDQ

20 DQ11 51 CB3 81 VSS 112 VDDQ 143 VDDQ 173 NC

21 CKE0 52 BA1 82 VDDID 113 *BA2 144 CB7 174 DQ60

22 VDDQ KEY 83 DQ56 114 DQ20 KEY 175 DQ61

23 DQ16 53 DQ32 84 DQ57 115 A12 145 VSS 176 VSS

24 DQ17 54 VDDQ 85 VDD 116 VSS 146 DQ36 177 DM7/DQS16

25 DQS2 55 DQ33 86 DQS7 117 DQ21 147 DQ37 178 DQ62

26 VSS 56 DQS4 87 DQ58 118 A11 148 VDD 179 DQ63

27 A9 57 DQ34 88 DQ59 119 DM2/DQS11 149 DM4/DQS13 180 VDDQ

28 DQ18 58 VSS 89 VSS 120 VDD 150 DQ38 181 SA0

29 A7 59 BA0 90 NC 121 DQ22 151 DQ39 182 SA1

30 VDDQ 60 DQ35 91 SDA 122 A8 152 VSS 183 SA2

31 DQ19 61 DQ40 92 SCL 123 DQ23 153 DQ44 184 VDDSPD

Note : VDDID defines relationship of VDD and VD DQ, and the default status of it is open (VDD=VDDQ)

Pin Name Function Pin Name Function

A0 ~ A12 Address input (Multiplexed) DM0 ~ DM8 Data - in mask

BA0 ~ BA1A Bank Select Address VDD Power supply

(2.5V for DDR266/333, 2.6V for DDR400)

DQ0 ~ DQ63 Data input/output VDDQ Power Supply for DQS

(2.5V for DDR266/333, 2.6V for DDR400)

DQS0 ~ DQS17 Data Strobe input/output VSS Ground

CK0,CK0 ~ CK2, CK2 Clock input VREF Power supply for reference

CKE0, CKE1(for double banks) Clock enable input VDDSPD Serial EEPROM Power/Supply ( 2.3V to 3.6V )

CS0, CS1(for double banks) Chip select input SDA Serial data I/O

RAS Row address strobe SCL Serial clock

CAS Column address strobe SA0 ~ 2 Address in EEPROM

WE Write enable VDDID VDD, VDDQ level detection

CB0 ~ CB7 Check bit(Data-in/data-out) NC No conne ction

5.0 Pin Description

4.0 Pin Configuration (Front side/back side)

DDR SDRAM

512MB, 1GB, 2GB Registered DIMM

Rev. 1.2 June 2005

(Populated as 1 bank of x8 DDR SDRAM Module)

VSS D0 - D8

VDD/VDDQ D0 - D8

D0 - D8

VREF

VDDSPD SPD

D0 - D8

Serial PD

A1 A2

SA0 SA1 SA2

SCL SDA

RCS0

DQS0

DM0

DM/ CS DQS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQS1

DM1

DM/ CS DQS

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQS2

DM2

DM/ CS DQS

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQS3

DM3

DM/ CS DQS

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQS4

DM4

DM/ CS DQS

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DQS5

DM5

DM/ CS DQS

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DQS6

DM6

DM/ CS DQS

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DQS7

DM7

DM/ CS DQS

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

I/O 7

I/O 5

I/O 2

I/O 0

I/O 6

I/O 4

I/O 3

I/O 1

I/O 0

I/O 2

I/O 5

I/O 7

I/O 1

I/O 3

I/O 4

I/O 6

I/O 5

I/O 3

I/O 1

I/O 7

I/O 4

I/O 2

I/O 0

I/O 2

I/O 5

I/O 6

I/O 1

I/O 3

I/O 4

I/O 7

I/O 0

I/O 2

I/O 5

I/O 7

I/O 1

I/O 3

I/O 4

I/O 6

I/O 7

I/O 4

I/O 2

I/O 0

I/O 6

I/O 5

I/O 3

I/O 1

I/O 0

I/O 2

I/O 5

I/O 7

I/O 1

I/O 3

I/O 4

I/O 6

I/O 4

I/O 2

I/O 0

I/O 7

I/O 5

I/O 3

I/O 1

DQS8

DM8

DM/ CS DQS

CB0

CB1

CB2

CB3

CB4

CB5

CB6

CB7

I/O 5

I/O 4

I/O 2

I/O 0

I/O 7

I/O 6

I/O 3

I/O 1

Notes:

1. DQ-to-I/O wiring is shown as recom-

mended but may be changed.

2. DQ/DQS/DM/CKE/CS relationsh ips

must be maintained as shown.

3. DQ, DQS, DM/DQS resistors: 22 Ohms.

PLL*

CK0,CK0

PCK

RAS

CAS

CKE0

BA0-BA1

A0-A12

CS0

PCK RESET

RCS0

RBA0 - RBA1

RA0 - RA12

RRAS

RCAS

RCKE0

RWE

BA0 -BA1 : SDRAMs DQ0 - D8

A0 -A12 : SDRAMs D0 - D8

RAS : SDRAMs D0 - D8

CAS : SDRAMs D0 - D8

CKE : SDRAMs D0 - D8

WE: SDRAMs D0 - D8

* Wire per Clock Loading table/wiring Diagrams

6.1 512MB, 64M x 72 ECC Module (M312L6523CUS)

6.0 Functional Block Diagram

DDR SDRAM

512MB, 1GB, 2GB Registered DIMM

Rev. 1.2 June 2005

RCS0

DQS0

DM0

DM/ CS DQS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQS1

DM1

DM/ CS DQS

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQS2

DM2

DM/ CS DQS

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQS3

DM3

DM/ CS DQS

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQS4

DM4

DM/ CS DQS

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DQS5

DM5

DM/ CS DQS

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DQS6

DM6

DM/ CS DQS

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DQS7

DM7

DM/ CS DQS

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

I/O 7

I/O 5

I/O 2

I/O 0

I/O 6

I/O 4

I/O 3

I/O 1

I/O 7

I/O 5

I/O 2

I/O 0

I/O 6

I/O 4

I/O 3

I/O 1

I/O 6

I/O 5

I/O 3

I/O 1

I/O 7

I/O 4

I/O 2

I/O 0

I/O 7

I/O 5

I/O 2

I/O 1

I/O 6

I/O 4

I/O 3

I/O 0

I/O 7

I/O 5

I/O 2

I/O 0

I/O 6

I/O 4

I/O 3

I/O 1

I/O 7

I/O 4

I/O 2

I/O 0

I/O 6

I/O 5

I/O 3

I/O 1

I/O 7

I/O 5

I/O 2

I/O 0

I/O 6

I/O 4

I/O 3

I/O 1

I/O 6

I/O 4

I/O 2

I/O 0

I/O 7

I/O 5

I/O 3

I/O 1

DM/ CS DQS

D10

DM/ CS DQS

D11

DM/ CS DQS

D12

I/O 0

I/O 2

I/O 5

I/O 7

I/O 1

I/O 3

I/O 4

I/O 6

DM/ CS DQS

D13

DM/ CS DQS

D14

DM/ CS DQS

D15

DM/ CS DQS

D16

RCS1

I/O 0

I/O 2

I/O 5

I/O 7

I/O 1

I/O 3

I/O 4

I/O 6

I/O 1

I/O 2

I/O 4

I/O 6

I/O 0

I/O 3

I/O 5

I/O 7

I/O 0

I/O 2

I/O 5

I/O 6

I/O 1

I/O 3

I/O 4

I/O 7

I/O 0

I/O 2

I/O 5

I/O 7

I/O 1

I/O 3

I/O 4

I/O 6

I/O 0

I/O 3

I/O 5

I/O 7

I/O 1

I/O 2

I/O 4

I/O 6

I/O 0

I/O 2

I/O 5

I/O 7

I/O 1

I/O 3

I/O 4

I/O 6

I/O 1

I/O 3

I/O 5

I/O 7

I/O 0

I/O 2

I/O 4

I/O 6

VSS D0 - D17

VDD/VDDQ D0 - D17

D0 - D17

VREF

VDDSPD SPD

D0 - D17

Serial PD

A1 A2

SA0 SA1 SA2

SCL SDA

DQS8

DM8

DM/ CS DQS

I/O 5

I/O 4

I/O 2

I/O 0

I/O 7

I/O 6

I/O 3

I/O 1

DM/ CS DQS

D17

I/O 2

I/O 3

I/O 5

I/O 7

I/O 0

I/O 1

I/O 4

I/O 6

CB0

CB1

CB2

CB3

CB4

CB5

CB6

CB7

PCK

RAS

CAS

CKE0

CKE1

CS1

BA0-BA1

A0-A12

CS0

PCK RESET

RCS1

RCS0

RBA0 - RBA1

RA0 - RA12

RRAS

RCAS

RCKE0

RWE

RCKE1

BA0 -BA1 : SDRAMs DQ0 - D17

A0 -A12 : SDRAMs D0 - D17

RAS : SDRAMs D0 - D17

CAS : SDRAMs DQ0 - D17

CKE : SDRAMs D0 - D8

CKE : SDRAMs D9 - D17

WE: SDRAMs D0 - D17

PLL*

CK0,CK0

* Wire per Clock Loading table/wiring Diagrams

Notes:

1. DQ-to-I/O wiring is shown as recom-

mended but may be changed.

2. DQ/DQS/DM/CKE/CS relationships

must be maintained as shown.

3. DQ, DQS, DM/DQS resistors: 22 Ohms.

(Populated as 2 bank of x8 DDR SDRAM Module)

6.2 1GB, 128M x 72 ECC Module (M312L2923CUS)

DDR SDRAM

512MB, 1GB, 2GB Registered DIMM

Rev. 1.2 June 2005

DQ4

DQ5

DQ6

DQ7

DQ0

DQ1

DQ2

DQ3

DQS0

DQ12

DQ13

DQ14

DQ8

DQ9

DQ10

DQ11

DQS9

DQ20

DQ21

DQ22

DQ23

DQ16

DQ17

DQ18

DQ19

DQS11

DQ28

DQ29

DQ30

DQ31

DQ24

DQ25

DQ26

DQ27

DQS12

DQ36

DQ37

DQ38

DQ39

DQ32

DQ33

DQ34

DQ35

DQS13

DQ44

DQ45

DQ46

DQ47

DQ40

DQ41

DQ42

DQ43

DQS14

DQ52

DQ53

DQ54

DQ55

DQ48

DQ49

DQ50

DQ51

DQ60

DQ61

DQ62

DQ63

DQ56

DQ57

DQ58

DQ59

DQS16

RCS0

DQS4

DQS1

DQS5

DQS2

DQS3

DQS15

DQS6

DQS7

DQ15

CB4

CB5

CB6

CB7

CB0

CB1

CB2

CB3

DQS8 DQS17

Notes:

1. DQ-to-I/O wiring is shown as recom-

mended but may be changed.

2. DQ/DQS/DM/CKE/S relationships must

be maintained as shown.

3. DQ, DQS, DM resistors: 22 Ohms.

RAS

CAS

CKE0

BA0-BA1

A0-A12

S0 RS0

RBA0 - RBA1

RA0 - RA12

RRAS

RCAS

RCKE0

RWE

BA0 -BA1 : SDRAMs DQ0 - D17

A0 -A12 : SDRAMs D0 - D17

RAS : SDRAMs D0 - D17

CAS : SDRAMs DQ0 - D17

CKE : SDRAMs D0 - D17

WE: SDRAMs D0 - D17

DQS

I/O 3

I/O 2

I/O 1

I/O 0

CS DM

DQS

I/O 3

I/O 2

I/O 1

I/O 0

CS DM

DQS

I/O 3

I/O 2

I/O 1

I/O 0

CS DM

DQS

I/O 3

I/O 2

I/O 1

I/O 0

CS DM

DQS

I/O 3

I/O 2

I/O 1

I/O 0

CS DM

DQS

I/O 3

I/O 2

I/O 1

I/O 0

CS DM

DQS

I/O 3

I/O 2

I/O 1

I/O 0

CS DM

DQS

I/O 3

I/O 2

I/O 1

I/O 0

CS DM

DQS

I/O 3

I/O 2

I/O 1

I/O 0

CS DM

VSS

DQS

I/O 0

I/O 1

I/O 2

I/O 3

D17

CS DM

DQS

I/O 0

I/O 1

I/O 2

I/O 3

CS DM

DQS

I/O 0

I/O 1

I/O 2

I/O 3

D10

CS DM

DQS

I/O 0

I/O 1

I/O 2

I/O 3

D11

CS DM

DQS

I/O 0

I/O 1

I/O 2

I/O 3

D12

CS DM

DQS

I/O 0

I/O 1

I/O 2

I/O 3

D13

CS DM

DQS

I/O 0

I/O 1

I/O 2

I/O 3

D14

CS DM

DQS

I/O 0

I/O 1

I/O 2

I/O 3

D15

CS DM

DQS

I/O 0

I/O 1

I/O 2

I/O 3

D16

CS DM

DQS10

RESET

PCK

PLL*

CK0,CK0

* Wire per Clock Loading table/wiring Diagrams

Serial PD

A1 A2

SA0 SA1 SA2

SCL SDA

VSS

D0 - D17

VDD/VDDQ D0 - D17

D0 - D17

VREF

Strap: see Note 4

VDDSPD SPD

(DM0)

(DM1)

(DM2)

(DM3)

(DM4)

(DM5)

(DM6)

(DM7)

(DM8)

(Populated as 1 bank of x4 DDR SDRAM Module)

6.3 1GB, 128M x 72 ECC Module (M312L2920CUS)

DDR SDRAM

512MB, 1GB, 2GB Registered DIMM

Rev. 1.2 June 2005

DQ4

DQ5

DQ6

DQ7

DQ0

DQ1

DQ2

DQ3

DQS0

DQ12

DQ13

DQ14

DQ8

DQ9

DQ10

DQ11

DM0/DQS9

DQ20

DQ21

DQ22

DQ23

DQ16

DQ17

DQ18

DQ19

DM2/DQS11

DQ28

DQ29

DQ30

DQ31

DQ24

DQ25

DQ26

DQ27

DM3/DQS12

DQ36

DQ37

DQ38

DQ39

DQ32

DQ33

DQ34

DQ35

DM4/DQS13

DQ44

DQ45

DQ46

DQ47

DQ40

DQ41

DQ42

DQ43

DM5/DQS14

DQ52

DQ53

DQ54

DQ55

DQ48

DQ49

DQ50

DQ51

DQ60

DQ61

DQ62

DQ63

DQ56

DQ57

DQ58

DQ59

DM7/DQS16

RCS0

RCS1

DQS4

DQS1

DQS5

DQS2

DQS3

DM6/DQS15

DQS6

DQS7

DQ15

DQS

I/O 3

I/O 2

I/O 1

I/O 0

CS DM

DQS

I/O 3

I/O 2

I/O 1

I/O 0

DQS

I/O 3

I/O 2

I/O 1

I/O 0

DQS

I/O 3

I/O 2

I/O 1

I/O 0

DQS

I/O 3

I/O 2

I/O 1

I/O 0

DQS

I/O 3

I/O 2

I/O 1

I/O 0

DQS

I/O 3

I/O 2

I/O 1

I/O 0

DQS

I/O 3

I/O 2

I/O 1

I/O 0

DQS

I/O 0

I/O 1

I/O 2

I/O 3

DQS

I/O 0

I/O 1

I/O 2

I/O 3

D10

DQS

I/O 0

I/O 1

I/O 2

I/O 3

D11

DQS

I/O 0

I/O 1

I/O 2

I/O 3

D12

DQS

I/O 0

I/O 1

I/O 2

I/O 3

D13

DQS

I/O 0

I/O 1

I/O 2

I/O 3

D14

DQS

I/O 0

I/O 1

I/O 2

I/O 3

D15

DQS

I/O 0

I/O 1

I/O 2

I/O 3

D16

DM1/DQS10

VSS

DQS

I/O 3

I/O 2

I/O 1

I/O 0

D18

DQS

I/O 3

I/O 2

I/O 1

I/O 0

D19

DQS

I/O 3

I/O 2

I/O 1

I/O 0

D20

DQS

I/O 3

I/O 2

I/O 1

I/O 0

D21

DQS

I/O 3

I/O 2

I/O 1

I/O 0

D22

DQS

I/O 3

I/O 2

I/O 1

I/O 0

D23

DQS

I/O 3

I/O 2

I/O 1

I/O 0

D24

DQS

I/O 3

I/O 2

I/O 1

I/O 0

D25

DQS

I/O 0

I/O 1

I/O 2

I/O 3

D27

DQS

I/O 0

I/O 1

I/O 2

I/O 3

D28

DQS

I/O 0

I/O 1

I/O 2

I/O 3

D29

DQS

I/O 0

I/O 1

I/O 2

I/O 3

D30

DQS

I/O 0

I/O 1

I/O 2

I/O 3

D31

DQS

I/O 0

I/O 1

I/O 2

I/O 3

D32

DQS

I/O 0

I/O 1

I/O 2

I/O 3

D33

DQS

I/O 0

I/O 1

I/O 2

I/O 3

D34

Notes:

1. DQ-to-I/O wiring is shown as recommended

but may be changed.

2. DQ/DQS/DM/CKE/CS relationships must

be maintained as shown.

3. DQ, DQS, DM/DQS resistors: 22 Ohms.

RA0 - RA12 A0-An: SDRAMs D0 - D35

RAS: SDRAMs D0 - D35

RCAS CAS: SDRAMs D0 - D35

RCKE1 CKE: SDRAMs D18 - D35

PCK

WE: SDRAMs D0 - D35

RCKE0

RBA0 - RBA1 BA0-BAn: SDRAMs D0 - D35

RAS

CAS

CKE0

CKE1

RCS1

CS1

BA0-BA1

A0-A12

RRAS

RWE

CS0 RCS0

PCK RESET

CKE: SDRAMs D0 - D17

PLL

CK0,CK0

Serial PD

A1 A2

SA0 SA1 SA2

SCL SDA

VSS

D0 - D35

VDD/VDDQ D0 - D35

D0 - D35

VREF

VDDSPD SPD

CB4

CB5

CB6

CB7

CB0

CB1

CB2

CB3

DQS8 DM8/DQS17

DQS

I/O 3

I/O 2

I/O 1

I/O 0

DM DQS

I/O 3

I/O 2

I/O 1

I/O 0

D17

DQS

I/O 3

I/O 2

I/O 1

I/O 0

D26

DM DQS

I/O 3

I/O 2

I/O 1

I/O 0

D35

CS CS CS

CS CS CS CS

(Populated as 2 bank of x4 DDR SDRAM Module)

6.4 2GB, 256M x 72 ECC Module (M312L5628CU0)

DDR SDRAM

512MB, 1GB, 2GB Registered DIMM

Rev. 1.2 June 2005

DQ4

DQ5

DQ6

DQ7

DQ0

DQ1

DQ2

DQ3

I/O 0

I/O 2

I/O 4

I/O 7

DM0

I/O 3

I/O 1

I/O 6

I/O 5

DQ12

DQ13

DQ14

DQ8

DQ9

DQ10

DQ11

DM1

DQ20

DQ21

DQ22

DQ23

DQ16

DQ17

DQ18

DQ19

DQ28

DQ29

DQ30

DQ31

DQ24

DQ25

DQ26

DQ27

DQ36

DQ37

DQ38

DQ39

DQ32

DQ33

DQ34

DQ35

DM4

DQ44

DQ45

DQ46

DQ47

DQ40

DQ41

DQ42

DQ43

DM5

DQ52

DQ53

DQ54

DQ55

DQ48

DQ49

DQ50

DQ51

DQ60

DQ61

DQ62

DQ63

DQ56

DQ57

DQ58

DQ59

DM7

RCS0

CS CS

DQS0

DQS

DQS4

DQS1 DQS5

DQS

DM6

DQS6

DQS7

DQ15

CB4

CB5

CB6

CB7

CB0

CB1

CB2

CB3

CS DQS

DQS

PCK

RAS

CAS

CKE0

BA0-BA1

A0-A12

CS0

PCK RESET

RCS0

RBA0 - RBA1

RA0 - RA12

RRAS

RCAS

RCKE0

RWE

BA0 -BA1 : DDR SDRAMs D 0 - D8

A0 -A12 : DDR SDRAMs D0 - D8

RAS : DDR SDRAMs D0 - D8

CAS : DDR SDRAMs D0 - D8

CKE : DDR SDRAMs D0 - D8

WE: DDR SDRAMs D0 - D8

PLL*

CK0,CK0

* Wire per Clock Loading table/wiring Diagrams A0

Serial PD

A1 A2

SA0 SA1 SA2

SCL SDA

VSS DDR SDRAMs D0 - D8

VDD/VDDQ DDR SDRAMs D0 - D8

DDR SDRAMs D0 - D8

VREF

VDDSPD SPD

Notes:

1. DQ-to-I/O wiring is shown as recommended but may be changed.

2. DQ/DQS/DM/CKE/CS relationships must be maintained as shown.

3. DQ, DQS, DM/DQS resistors: 22 Ohms.

DM2

DQS2

DM3

DQS3

DM8

DQS8

I/O 7

I/O 5

I/O 3

I/O 0

I/O 4

I/O 6

I/O 1

I/O 2

I/O 0

I/O 2

I/O 4

I/O 7

I/O 3

I/O 1

I/O 6

I/O 5

I/O 7

I/O 5

I/O 3

I/O 0

I/O 4

I/O 6

I/O 1

I/O 2

I/O 7

I/O 5

I/O 3

I/O 0

I/O 4

I/O 6

I/O 1

I/O 2

I/O 7

I/O 5

I/O 3

I/O 0

I/O 4

I/O 6

I/O 1

I/O 2

I/O 7

I/O 5

I/O 3

I/O 0

I/O 4

I/O 6

I/O 1

I/O 2

I/O 0

I/O 2

I/O 4

I/O 7

I/O 3

I/O 1

I/O 6

I/O 5

I/O 7

I/O 5

I/O 3

I/O 0

I/O 4

I/O 6

I/O 1

I/O 2

(Populated as 1 bank of x8 DDR SDRAM Mod ule)

6.5 512MB, 64M x 72 ECC Module (M312L6523CZ0)

DDR SDRAM

512MB, 1GB, 2GB Registered DIMM

Rev. 1.2 June 2005

RCS0

DQS0

DM0

DM/ CS DQS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQS1

DM1

DM/ CS DQS

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQS2

DM2

DM/ CS DQS

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQS3

DM3

DM/ CS DQS

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQS4

DM4

DM/ CS DQS

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DQS5

DM5

DM/ CS DQS

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DQS6

DM6

DM/ CS DQS

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DQS7

DM7

DM/ CS DQS

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

I/O 1

I/O 0

I/O 7

I/O 6

I/O 2

I/O 3

I/O 4

I/O 5

DM/ CS DQS

D10

DM/ CS DQS

D11

DM/ CS DQS

D12

I/O 6

I/O 7

I/O 0

I/O 1

I/O 5

I/O 4

I/O 3

I/O 2

DM/ CS DQS

D13

DM/ CS DQS

D14

DM/ CS DQS

D15

DM/ CS DQS

D16

RCS1

VSS D0 - D17

VDD/VDDQ D0 - D17

D0 - D17

VREF

VDDSPD SPD

D0 - D17

Serial PD

A1 A2

SA0 SA1 SA2

SCL SDA

DQS8

DM8

DM/ CS DQS

D17

CB0

CB1

CB2

CB3

CB4

CB5

CB6

CB7

PCK

RAS

CAS

CKE0

CKE1

CS1

BA0-BA1

A0-A12

CS0

PCK RESET

RCS1

RCS0

RBA0 - RBA1

RA0 - RA12

RRAS

RCAS

RCKE0

RWE

RCKE1

BA0 -BA1 : DDR SDRAM DQ0 - D17

A0 -A12 : DDR SDRAM D0 - D17

RAS : DDR SDRAM D0 - D17

CAS : DDR SDRAM DQ0 - D17

CKE : DDR SDRAM D0 - D8

CKE : DDR SDRAM D9 - D17

WE: DDR SDRAM D0 - D17

PLL*

CK0,CK0

* Wire per Clock Loading table/wiring Diagrams

Notes:

1. DQ-to-I/O wiring is shown as recom-

mended but may be changed.

2. DQ/DQS/DM/CKE/CS relationships

must be maintained as shown.

3. DQ, DQS, DM/DQS resistors: 22 Ohms.

I/O 6

I/O 7

I/O 0

I/O 1

I/O 5

I/O 4

I/O 3

I/O 2

I/O 1

I/O 0

I/O 7

I/O 6

I/O 2

I/O 3

I/O 4

I/O 5

I/O 1

I/O 0

I/O 7

I/O 6

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 5

I/O 4

I/O 3

I/O 2

I/O 1

I/O 0

I/O 7

I/O 6

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 5

I/O 4

I/O 3

I/O 2

I/O 6

I/O 7

I/O 0

I/O 1

I/O 5

I/O 4

I/O 3

I/O 2

I/O 1

I/O 0

I/O 7

I/O 6

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 5

I/O 4

I/O 3

I/O 2

I/O 1

I/O 0

I/O 7

I/O 6

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 5

I/O 4

I/O 3

I/O 2

I/O 1

I/O 0

I/O 7

I/O 6

I/O 2

I/O 3

I/O 4

I/O 5

I/O 1

I/O 0

I/O 7

I/O 6

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 5

I/O 4

I/O 3

I/O 2

I/O 1

I/O 0

I/O 7

I/O 6

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 5

I/O 4

I/O 3

I/O 2

(Populated as 2 bank of x8 DDR SDRAM Mod ule)

6.6 1GB, 128M x 72 ECC Module (M312L2923CZ0)

DDR SDRAM

512MB, 1GB, 2GB Registered DIMM

Rev. 1.2 June 2005

DQ4

DQ5

DQ6

DQ7

DQ0

DQ1

DQ2

DQ3

DQS0

DQ12

DQ13

DQ14

DQ8

DQ9

DQ10

DQ11

DQS9

DQ20

DQ21

DQ22

DQ23

DQ16

DQ17

DQ18

DQ19

DQS11

DQ28

DQ29

DQ30

DQ31

DQ24

DQ25

DQ26

DQ27

DQS12

DQ36

DQ37

DQ38

DQ39

DQ32

DQ33

DQ34

DQ35

DQS13

DQ44

DQ45

DQ46

DQ47

DQ40

DQ41

DQ42

DQ43

DQS14

DQ52

DQ53

DQ54

DQ55

DQ48

DQ49

DQ50

DQ51

DQ60

DQ61

DQ62

DQ63

DQ56

DQ57

DQ58

DQ59

DQS16

RCS0

DQS4

DQS1

DQS5

DQS2

DQS3

DQS15

DQS6

DQS7

DQ15

CB4

CB5

CB6

CB7

CB0

CB1

CB2

CB3

DQS8 DQS17

Notes:

1. DQ-to-I/O wiring is shown as recom-

mended but may be changed.

2. DQ/DQS/DM/CKE/S relationships must

be maintained as shown.

3. DQ, DQS, DM resistors: 22 Ohms.

RAS

CAS

CKE0

BA0-BA1

A0-A12

CS0 RCS0_2

RCS0_1

RBA0 - RBA1

RA0 - RA12

RRAS

RCAS

RCKE0A

RWE

RCKE0B

BA0 -BA1 : DDR SDRAM DQ0 - D17

A0 -A12 :DDR SDRAM D0 - D17

RAS : DDR SDRAM D0 - D17

CAS : DDR SDRAM DQ0 - D17

CKE : DDR SDRAM D0 - D8

CKE : DDR SDRAM D9 - D17

WE:DDR SDRAM D0 - D17

DQS

I/O 3

I/O 2

I/O 1

I/O 0

CS DM

DQS

I/O 3

I/O 2

I/O 1

I/O 0

CS DM

DQS

I/O 3

I/O 2

I/O 1

I/O 0

CS DM

DQS

I/O 3

I/O 2

I/O 1

I/O 0

CS DM

DQS

I/O 3

I/O 2

I/O 1

I/O 0

CS DM

DQS

I/O 3

I/O 2

I/O 1

I/O 0

CS DM

DQS

I/O 3

I/O 2

I/O 1

I/O 0

CS DM

DQS

I/O 3

I/O 2

I/O 1

I/O 0

CS DM

DQS

I/O 3

I/O 2

I/O 1

I/O 0

CS DM

VSS

DQS

I/O 0

I/O 1

I/O 2

I/O 3

CS DM

DQS

D10

CS DM

DQS

D11

CS DM

DQS

D12

CS DM

DQS10

RESET

PCK

PLL*

CK0,CK0

* Wire per Clock Loading table/wiring Diagrams

Serial PD

A1 A2

SA0 SA1 SA2

SCL SDA

VSS

D0 - D17

VDD/VDDQ D0 - D17

D0 - D17

VREF

VDDSPD SPD

(DM0)

(DM1)

(DM2)

(DM3)

(DM4)

(DM5)

(DM6)

(DM7)

(DM8)

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

DQS

D13

CS DM

DQS

D14

CS DM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

DQS

D15

CS DM

DQS

D16

CS DM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

DQS

D17

CS DM

I/O 0

I/O 1

I/O 2

I/O 3

(Populated as 1 bank of x4 DDR SDRAM Mod ule)

6.7 1GB, 128M x 72 ECC Module (M312L2920CZ0)

DDR SDRAM

512MB, 1GB, 2GB Registered DIMM

Rev. 1.2 June 2005

DQ4

DQ5

DQ6

DQ7

DQ0

DQ1

DQ2

DQ3

DQS0

DQ12

DQ13

DQ14

DQ8

DQ9

DQ10

DQ11

DQS9

DQ20

DQ21

DQ22

DQ23

DQ16

DQ17

DQ18

DQ19

DQS11

DQ28

DQ29

DQ30

DQ31

DQ24

DQ25

DQ26

DQ27

DQS12

DQ36

DQ37

DQ38

DQ39

DQ32

DQ33

DQ34

DQ35

DQS13

DQ44

DQ45

DQ46

DQ47

DQ40

DQ41

DQ42

DQ43

DQS14

DQ52

DQ53

DQ54

DQ55

DQ48

DQ49

DQ50

DQ51

DQ60

DQ61

DQ62

DQ63

DQ56

DQ57

DQ58

DQ59

DQS16

RCS0

RCS1

DQS4

DQS1

DQS5

DQS2

DQS3

DQS15

DQS6

DQS7

DQ15

DQS

CS DM

DQS

DQS10

VSS

DQS

I/O 0

I/O 1

I/O 2

I/O 3

D18

DQS

I/O 0

I/O 1

I/O 2

I/O 3

D19

DQS

I/O 0

I/O 1

I/O 2

I/O 3

D20

DQS

I/O 0

I/O 1

I/O 2

I/O 3

D21

DQS

I/O 0

I/O 1

I/O 2

I/O 3

D22

DQS

I/O 0

I/O 1

I/O 2

I/O 3

D23

DQS

I/O 0

I/O 1

I/O 2

I/O 3

D24

DQS

I/O 0

I/O 1

I/O 2

I/O 3

D25

Notes:

1. DQ-to-I/O wiring is shown as recommended but may be changed.

2. DQ/DQS/DM/CKE/CS relationships must be maintained as shown.

3. DQ, DQS, DM/DQS resistors: 22 Ohms.

RA0 - RA12 A0-A12: DDR SDRAM D0 - D35

RAS: DDR SDRAM D0 - D35

RCAS CAS: DDR SDRAM D0 - D35

RCKE1 CKE: DDR SDRAM D18 - D35

PCK

WE: DDR SDRAM D0 - D35

RCKE0

RBA0 - RBA1 BA0-BA1: DDR SDRAM D0 - D35

RAS

CAS

CKE0

CKE1

RCS1

CS1

BA0-BA1

A0-A12

RRAS

RWE

CS0 RCS0

PCK RESET

CKE: DDR SDRAM D0 - D17

Serial PD

A1 A2

SA0 SA1 SA2

SCL SDA

VSS

D0 - D35

VDD/VDDQ D0 - D35

D0 - D35

VREF

VDDSPD SPD

PLL*

CK0,CK0

* Wire per Clock Loading table/wiring Diagrams

CB0

CB1

CB2

CB3

DQS8 DQS

DM DQS

I/O 0

I/O 1

I/O 2

I/O 3

D26

DM CB4

CB5

CB6

CB7

DQS17

(DM0)

(DM1)

(DM2)

(DM3)

(DM4)

(DM5)

(DM6)

(DM7)

(DM8)

CS CS

DQS

DM DQS

I/O 3

I/O 2

I/O 1

I/O 0

D27

CS CS

DQS

D10

DQS

D11

DQS

D12

DQS

D13

DQS

I/O 3

I/O 2

I/O 1

I/O 0

D28

DQS

I/O 3

I/O 2

I/O 1

I/O 0

D29

DQS

I/O 3

I/O 2

I/O 1

I/O 0

D30

DQS

I/O 3

I/O 2

I/O 1

I/O 0

D31

CS CS

DQS

D14

DQS

D15

DQS

D16

DQS

I/O 3

I/O 2

I/O 1

I/O 0

D32

DQS

I/O 3

I/O 2

I/O 1

I/O 0

D33

DQS

I/O 3

I/O 2

I/O 1

I/O 0

D34

DQS

D17

DM DQS

I/O 3

I/O 2

I/O 1

I/O 0

D35

CS CS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 2

I/O 1

I/O 0

I/O 3

I/O 2

I/O 1

I/O 0

I/O 3

I/O 2

I/O 1

I/O 0

I/O 3

I/O 2

I/O 1

I/O 0

I/O 3

I/O 2

I/O 1

I/O 0

I/O 3

I/O 2

I/O 1

I/O 0

I/O 3

I/O 2

I/O 1

I/O 0

I/O 3

I/O 2

I/O 1

I/O 0

I/O 3

I/O 2

I/O 1

I/O 0

(Populated as 2 bank of x4 DDR SDRAM Module)

6.8 2GB, 256M x 72 ECC Module (M312L5720CZ0)

DDR SDRAM

512MB, 1GB, 2GB Registered DIMM

Rev. 1.2 June 2005

Note :

Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.

Functional operation should be restricted to recommended operating condition.

Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

Parameter Symbol Value Unit

Voltage on any pin relative to Vss VIN, VOUT -0.5 ~ 3.6 V

Voltage on VDD supply relative to Vss VDD,VDDQ -1.0 ~ 3.6 V

Storage temperature TSTG -55 ~ +150 °C

Power dissipation PD1.5 * # of component W

Short circuit current IOS 50 mA

Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 70°C)

Note :

1. VREF is expected to be equal to 0.5*VDDQ of the transmitting device, and to track variations in the dc level of same. Peak-to peak noise on VREF may

not exceed +/-2% of the dc value.

2. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track

variations in the DC level of VREF.

3. VID is the magnitude of the difference between the input level on CK and the input level on CK.

4. The ratio of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire temperature and voltage range,

for device drain to source voltages from 0.25V to 1.0V. For a given output, it represents the maximum dif ference between pullup and pulldown drivers

due to process variation. The full variation in the ratio of the maximum to minimum pullup and pulldown current will not exceed 1.7 for device drain to

source voltages from 0.1 to 1.0.

Parameter Symbol Min Max Unit Note

Supply voltage(for device with a nominal VDD of 2.5V for DDR266/333) VDD 2.3 2.7 V

Supply voltage(for device with a nominal VDD of 2.6V for DDR400) VDD 2.5 2.7 V

I/O Supply voltage(for device with a nominal VDD of 2.5V for DDR266/333) VDDQ 2.3 2.7 V

I/O Supply voltage(for device with a nominal VDD of 2.6V for DDR400) VDDQ 2.5 2.7 V

I/O Reference voltage VREF 0.49*VDDQ 0.51*VDDQ V 1

I/O Termination voltage(system) VTT VREF-0.04 VREF+0.04 V2

Input logic high voltage VIH(DC) VREF+0.15 VDDQ+0.3 V

Input logic low voltage VIL(DC) -0.3 VREF-0.15 V

Input Voltage Level, CK and CK inputs VIN(DC) -0.3 VDDQ+0.3 V

Input Differential Voltage, CK and CK inputs VID(DC) 0.36 VDDQ+0.6 V 3

V-I Matching: Pullup to Pulldown Current Ratio VI(Ratio) 0.71 1.4 - 4

Input leakage current II-2 2 uA

Output leakage current IOZ -5 5 uA

Output High Current(Normal strengh driver) ;VOUT = VTT + 0.84V IOH -16.8 mA

Output High Current(Normal strengh driver) ;VOUT = V TT - 0.84V IOL 16.8 mA

Output High Current(Half strengh driver) ;VOUT = VTT + 0.45V IOH -9 mA

Output High Current(Half strengh driver) ;VOUT = VTT - 0.45V IOL 9mA

8.0 Power & DC Operating Conditions (SSTL_2 In/Out)

7.0 Absolute Maximum Ratings

DDR SDRAM

512MB, 1GB, 2GB Registered DIMM

Rev. 1.2 June 2005

(VDD=2.7V, T = 10°C)

* Module IDD was calculated on the basis of comp onent IDD and can be differently measured according to DQ loading cap.

Symbol A2(DDR266@CL=2) B0(DDR266@CL=2.5) Unit Notes

IDD0 1,360 1,360 mA

IDD1 1,630 1,630 mA

IDD2P 350 350 mA

IDD2F 770 770 mA

IDD2Q 530 530 mA

IDD3P 570 570 mA

IDD3N 910 910 mA

IDD4R 1,630 1,630 mA

IDD4W 1,670 1,670 mA

IDD5 2,260 2,260 mA

IDD6 Normal 350 350 mA

Low power 330 330 mA Optional

IDD7A 3,430 3,430 mA

(VDD=2.7V, T = 10°C)

* Module IDD was calculated on the basis of comp onent IDD and can be differently measured according to DQ loading cap.

Symbol A2(DDR266@CL=2) B0(DDR266@CL=2.5) Unit Notes

IDD0 2,010 2,010 mA

IDD1 2,280 2,280 mA

IDD2P 540 540 mA

IDD2F 1,290 1,290 mA

IDD2Q 900 900 mA

IDD3P 990 990 mA

IDD3N 1,560 1,560 mA

IDD4R 2,280 2,280 mA

IDD4W 2,330 2,330 mA

IDD5 2,910 2,910 mA

IDD6 Normal 540 540 mA

Low power 510 510 mA Optional

IDD7A 4,080 4,080 mA

9.1 M312L6523CUS [ (64M x 8) * 9 , 512MB Module ]

9.2 M312L2923CUS [ (64M x 8) * 18 , 1GB Module ]

9.0 DDR SDRAM IDD spec table

DDR SDRAM

512MB, 1GB, 2GB Registered DIMM

Rev. 1.2 June 2005

(VDD=2.7V, T = 10°C)

* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.

Symbol A2(DDR266@CL=2) B0(DDR266@CL=2.5) Unit Notes

IDD0 2,340 2,340 mA

IDD1 2,880 2,880 mA

IDD2P 420 420 mA

IDD2F 1,170 1,170 mA

IDD2Q 780 780 mA

IDD3P 870 870 mA

IDD3N 1,440 1,440 mA

IDD4R 2,880 2,880 mA

IDD4W 2,970 2,970 mA

IDD5 4,140 4,140 mA

IDD6 Normal 420 420 mA

Low power 380 380 mA Optional

IDD7A 6,480 6,480 mA

(VDD=2.7V, T = 10°C)

* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.

Symbol A2(DDR266@CL=2) B0(DDR266@CL=2.5) Unit Notes

IDD0 3,400 3,400 mA

IDD1 3,940 3,940 mA

IDD2P 760 760 mA

IDD2F 1,960 1,960 mA

IDD2Q 1,480 1,480 mA

IDD3P 1,660 1,660 mA

IDD3N 2,500 2,500 mA

IDD4R 3,940 3,940 mA

IDD4W 4,030 4,030 mA

IDD5 5,200 5,200 mA

IDD6 Normal 760 760 mA

Low power 685 685 mA Optional

IDD7A 7,540 7,540 mA

9.4 M312L5628CU0 [ (st.256M x 4) * 18 , 2GB Module ]

9.3 M312L2920CUS [ (128M x 4) * 18 , 1GB Module ]

DDR SDRAM

512MB, 1GB, 2GB Registered DIMM

Rev. 1.2 June 2005

(VDD=2.7V, T = 10°C)

* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.

Symbol CC (DDR400@CL=3) B3 (DDR3 33@CL=2.5) Unit Notes

IDD0 1,830 1,700 mA

IDD1 2,100 1,970 mA

IDD2P 420 420 mA

IDD2F 1,020 1,020 mA

IDD2Q 600 600 mA

IDD3P 780 650 mA

IDD3N 1,290 1,160 mA

IDD4R 2,150 2,010 mA

IDD4W 2,330 2,100 mA

IDD5 2,730 2,600 mA

IDD6 Normal 420 420 mA

Low power 410 410 mA Optional

IDD7A 4,220 3,990 mA

(VDD=2.7V, T = 10°C)

* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.

Symbol CC (DDR400@CL=3) B3 (DDR3 33@CL=2.5) Unit Notes

IDD0 2,500 2,230 mA

IDD1 2,770 2,500 mA

IDD2P 590 590 mA

IDD2F 1,420 1,420 mA

IDD2Q 950 950 mA

IDD3P 1,310 1,040 mA

IDD3N 1,960 1,690 mA

IDD4R 2,810 2,540 mA

IDD4W 2,990 2,630 mA

IDD5 3,400 3,130 mA

IDD6 Normal 590 590 mA

Low power 560 560 mA Optional

IDD7A 4,880 4,520 mA

9.6 M312L2923CZ0 [ (64M x 8) * 18 , 1GB Module ]

9.5 M312L6523CZ0 [ (64M x 8) * 9 , 512MB Module ]

DDR SDRAM

512MB, 1GB, 2GB Registered DIMM

Rev. 1.2 June 2005

(VDD=2.7V, T = 10°C)

* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.

Symbol CC (DDR400@CL=3) B3 (DDR333@CL= 2.5) Unit Notes

IDD0 4,240 3,700 mA

IDD1 4,780 4,240 mA

IDD2P 810 810 mA

IDD2F 2,080 2,080 mA

IDD2Q 1,530 1,530 mA

IDD3P 2,250 1,710 mA

IDD3N 3,160 2,620 mA

IDD4R 4,870 4,330 mA

IDD4W 5,230 4,510 mA

IDD5 6,040 5,500 mA

IDD6 Normal 810 810 mA

Low power 740 740 mA Optional

IDD7A 9,010 8,290 mA

(VDD=2.7V, T = 10°C)

* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.

Symbol CC (DDR400@CL=3) B3 (DDR333@CL=2.5) Unit Notes

IDD0 2,910 2,640 mA

IDD1 3,450 3,180 mA

IDD2P 470 470 mA

IDD2F 1,290 1,290 mA

IDD2Q 830 830 mA

IDD3P 1,190 920 mA

IDD3N 1,830 1,560 mA

IDD4R 3,540 3,270 mA

IDD4W 3,900 3,450 mA

IDD5 4,710 4,440 mA

IDD6 Normal 470 470 mA

Low power 430 430 mA Optional

IDD7A 7,680 7,230 mA

9.8 M312L5720CZ0 [ (128M x 4) * 36, 2GB Module ]

9.7 M312L2920CZ0 [ (128M x 4) * 18 , 1GB Module ]

DDR SDRAM

512MB, 1GB, 2GB Registered DIMM

Rev. 1.2 June 2005

Output Load Circuit (SSTL_2)

Output Z0=50Ω

CLOAD=30pF

VREF

=0.5*VDDQ

RT=50Ω

Vtt=0.5*VDDQ

(TA= 25°C, f=100MHz)

Parameter Symbol M312L6523CUS, M312L2920CUS M312L2923CUS, M312L5720CU0 Unit

Min Max Min Max

Input capacitance(A0 ~ A12, BA0 ~ BA1,RAS,CAS,WE ) CIN1 9 11 9 11 pF

Input capacitance(CKE0) CIN2 9 11 9 11 pF

Input capacitance( CS0) CIN3 9 11 9 11 pF

Input capacitance( CLK0, CLK0 ) CIN411121112pF

Input capacitance(DM0~DM8) CIN5 10 11 14 16 pF

Data & DQS input/output capacitance(DQ0~DQ63) Cout1 10 11 14 16 pF

Data input/output capacitance (CB0~CB7) Cout2 10 11 14 16 pF

Parameter Symbol M312L6523CZ0, M312L2920CZ0 M312L2923CZ0, M312L5720CZ0 Unit

Min Max Min Max

Input capacitance(A0 ~ A12, BA0 ~ BA1,RAS,CAS,WE ) CIN1 9 11 9 11 pF

Input capacitance(CKE0) CIN2 9 11 9 11 pF

Input capacitance( CS0) CIN3 9 11 9 11 pF

Input capacitance( CLK0, CLK0 ) CIN411121112pF

Input capacitance(DM0~DM8) CIN5 10 11 13 15 pF

Data & DQS input/output capacitance(DQ0~DQ63) Cout1 10 11 13 15 pF

Data input/output capacitance (CB0~CB7) Cout2 10 11 13 15 pF

Note :

1. VID is the magnitude of the difference between the input level on CK and the input on CK.

2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same.

Parameter/Condition Symbol Min Max Unit Note

Input High (Logic 1) Voltage, DQ, DQS and DM signals VIH(AC) VREF + 0.31 V

Input Low (Logic 0) Voltage, DQ, DQS an d DM signals. VIL(AC) VREF - 0.31 V

Input Differential Voltage, CK and CK inputs VID(AC) 0.7 VDDQ+0.6 V 1

Input Crossing Point Voltage, CK and CK inputs VIX(AC) 0.5*VDDQ-0.2 0.5*VDDQ+0.2 V 2

11.0 Input/Output Capacitance

10.0 AC Operating Conditions

DDR SDRAM

512MB, 1GB, 2GB Registered DIMM

Rev. 1.2 June 2005

Parameter Symbol CC

(DDR400@CL=3.0) B3

(DDR333@CL=2.5) A2

(DDR266@CL=2.0) B0

(DDR266@CL=2.5) Unit Note

Min Max Min Max Min Max Min Max

Row cycle time tRC 55 60 65 65 ns

Refresh row cycle time tRFC 70 72 75 75 ns

Row active time tRAS 40 70K 42 70K 45 70K 45 70K ns

RAS to CAS delay tRCD 15 18 20 20 ns

Row precharge time tRP 15 18 20 20 ns

Row active to Row active delay tRRD 10 12 15 15 ns

Write recovery time tWR 15 15 15 15 ns

Last data in to Read command tWTR 2 1 1 1 tCK

Clock cycle time CL=2.0 tCK - - 7.5 12 7.5 12 10 12 ns

CL=2.5 6126127.5127.512ns

CL=3.0 510------

Clock high level width tCH 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK

Clock low level width tCL 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK

DQS-out access time from CK/CK tDQSCK -0.55 +0.55 -0.6 +0.6 -0.75 +0.75 -0.75 +0.75 ns

Output data access time from CK/CK tAC -0.65 +0.65 -0.7 +0.7 -0.75 +0.75 -0.75 +0.75 ns

Data strobe edge to ouput data edge tDQSQ - 0.4 - 0.45 - 0.5 - 0.5 ns 22

Read Preamble tRPRE 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 tCK

Read Postamble tRPST 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tCK

CK to valid DQS-in tDQSS 0.72 1.28 0.75 1.25 0.75 1.25 0.75 1.25 tCK

DQS-in setup time tWPRES 0 0 0 0 ns 13

DQS-in hold time tWPRE 0.25 0.25 0.25 0.25 tCK

DQS falling edge to CK rising-setup time tDSS 0.2 0.2 0.2 0.2 tCK

DQS falling edge from CK rising-hold time tDSH 0.2 0.2 0.2 0.2 tCK

DQS-in high level width tDQSH 0.35 0.35 0.35 0.35 tCK

DQS-in low level width tDQSL 0.35 0.35 0.35 0.35 tCK

Address and Control Input setup time(fast) tIS 0.6 0.75 0.9 0.9 ns 15, 17~19

Address and Control Input hold time(fast) tIH 0.6 0.75 0.9 0.9 ns 15, 17~19

Address and Control Input setup time(slow) tIS 0.7 0.8 1.0 1.0 ns 16~19

Address and Control Input hold time(slow) tIH 0.7 0 .8 1.0 1.0 ns 16~19

Data-out high impedence time from CK/CK tHZ -0.65 +0.65 -0.7 +0.7 -0.75 +0.75 -0.75 +0.75 ns 11

Data-out low impedence time from CK/CK tLZ -0.65 +0.65 -0.7 +0.7 -0.75 +0.75 -0.75 +0.75 ns 11

Mode register set cycle time tMRD 10 12 15 15 ns

DQ & DM setup time to DQS tDS 0.4 0.45 0.5 0.5 ns j, k

DQ & DM hold time to DQS tDH 0.4 0.45 0.5 0.5 ns j, k

Control & Address input pulse width tIPW 2.2 2.2 2.2 2.2 ns 18

DQ & DM input pulse width tDIPW 1.75 1.75 1.75 1.75 ns 18

Exit self refresh to non-Read command tXSNR 75 75 75 75 ns

Exit self refresh to read command tXSRD 200 200 200 200 tCK

Refresh interval time tREFI 7.8 7.8 7.8 7.8 us 14

Output DQS valid window tQH tHP

-tQHS -tHP

-tQHS -ns21

Clock half period tHP tCLmin

or tCHmin -tCLmin

or tCHmin - ns 20, 21

Data hold skew factor tQHS 0.5 0.55 0.75 0.75 ns 21

DQS write postamble time tWPST 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tCK 12

Active to Read with Auto precharge

command tRAP 15 18 20 20

Autoprecharge write recovery +

Precharge time tDAL (tWR/tCK)

(tRP/tCK)

(tWR/tCK)

(tRP/tCK)

(tWR/tCK)

(tRP/tCK)

(tWR/tCK)

(tRP/tCK) tCK 23

12.0 AC Timming Parameters & Specifications

DDR SDRAM

512MB, 1GB, 2GB Registered DIMM

Rev. 1.2 June 2005

The following specification parameters are required in systems using DDR333, DDR266 & DDR200 devices to ensure proper system

performance. these characteristics are for system simulation purposes and are guaranteed by design.

Table 1 : Input Slew Rate for DQ, DQS, and DM

Table 2 : Input Setup & Hold Time Derating for Slew Rate

Table 3 : Input/Output Setup & Hold Time Derating for Slew Rate

Table 4 : Input/Output Setup & Hold Derating for Rise/Fall Delta Slew Rate

Table 5 : Output Slew Rate Characteristice (X4, X8 Devices only)

Table 6 : Output Slew Rate Characteristice (X16 Devices only)

Table 7 : Output Slew Rate Matching Ratio Characteristics

AC CHARACTERISTICS DDR333 DDR266 DDR200

PARAMETER SYMBOL MIN MAX MIN MAX MIN MAX Units Notes

DQ/DM/DQS input slew rate measured between

VIH(DC), VIL(DC) and VIL(DC), VIH(DC) DCSLEW TBD TBD TBD TBD 0.5 4.0 V/ns a, m

Input Slew Rate ∆tIS ∆tIH Units Notes

0.5 V/ns 0 0 ps i

0.4 V/ns +50 0 ps i

0.3 V/ns +100 0 ps i

Input Slew Rate ∆tDS ∆tDH Units Notes

0.5 V/ns 0 0 ps k

0.4 V/ns +75 +75 ps k

0.3 V/ns +150 +150 ps k

Delta Slew Rate ∆tDS ∆tDH Units Notes

+/- 0.0 V/ns 0 0 ps j

+/- 0.25 V/ns +50 +50 ps j

+/- 0.5 V/ns +100 +100 ps j

Slew Rate Characteristic Typical Range

(V/ns) Minimum

(V/ns) Maximum

(V/ns) Notes

Pullup Slew Rate 1.2 ~ 2.5 1.0 4.5 a,c,d,f,g,h

Pulldown slew 1.2 ~ 2.5 1.0 4.5 b,c,d,f,g,h

Slew Rate Characteristic Typical Range

(V/ns) Minimum

(V/ns) Maximum

(V/ns) Notes

Pullup Slew Rate 1.2 ~ 2.5 0.7 5.0 a,c,d,f,g,h

Pulldown slew 1.2 ~ 2.5 0.7 5.0 b,c,d,f,g,h

AC CHARACTERISTICS DDR266B DDR200

PARAMETER MIN MAX MIN MAX Notes

Output Slew Rate Matching Ratio (Pullup to Pulldown) TBD TBD 0.67 1.5 e,m

13.0 System Characteristics for DDR SDRAM

DDR SDRAM

512MB, 1GB, 2GB Registered DIMM

Rev. 1.2 June 2005

1. All voltages referenced to Vss.

2. Tests for ac timing, IDD, and electrical, ac and dc characteristics, may be conducted at nominal reference/supply voltage levels, but the related speci-

fications and device operation are guaranteed for the full voltage range specified.

3. Figure 1 represents the timing reference load used in defining the relevant timing parameters of the part. It is not intended to be either a precise rep-

resentation of the typical system environment nor a depiction of the actual load presented by a production tester. System designers will use IBIS or

other simulation tools to correlate the timing reference load to a system environment. Manufacturers will correlate to their production test conditions

(generally a coaxial transmission line terminated at the tester electronics).

4. AC timing and IDD tests may use a VIL to VIH swing of up to 1.5 V in the test environment, but input timing is still referenced to VREF (or to the cross-

ing point for CK/CK), and parameter specifications are guaranteed for the specified ac input levels under normal use conditions. The minimum slew

rate for the input signals is 1 V/ns in the range between VIL(ac) and VIH(ac).

5. The ac and dc input level specifications are as defined in the SSTL_2 Standard (i.e., the receiver will effectively switch as a result of the signal crossing

the ac input level and will remain in that state as long as the signal does not ring back above (below) the dc input LOW (HIGH) level.

6. Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF stabilizes, CKE ≤ 0.2VDDQ is recognized as LOW.

7. Enables on.chip refresh and address counters.

8. IDD specifications are tested after the device is properly initialized.

9. The CK/CK input reference level (for timing referenced to CK/CK) is the point at which CK and CK cross; the input reference level for signals other

than CK/CK, is VREF.

10. The output timing reference voltage level is VTT.

11. tHZ and tLZ transitions occur in the same access time window s as valid data transitions. Th ese parameters are not referenced to a specific voltage

level but specify when the device output is no longer driving (HZ), or begins driving (LZ).

12. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but sys tem performance

(bus turnaround) will degrade accordingly.

13. The specific requirement is that DQS be valid (HIGH, LOW, or at some point on a valid transition) on or before this CK edge. A valid transition is

defined as monotonic and meeting the input slew rate specifications of the device. when no writes were previ ously in pro g ress on the bus, DQS will

be tran sitioning from High- Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW , or transitioning from HIGH to LOW at this

time, depending on tDQSS.

14. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device.

15. For command/address input slew rate ≥ 1.0 V/ns

16. For command/address input slew rate ≥ 0.5 V/ns and < 1.0 V/ns

17. For CK & CK slew rate ≥ 1.0 V/ns

18. These parameters guarantee device timing, but they are not necessarily tested on each device. They may be guaranteed by device design or tester

correlation.

19. Slew Rate is measured between VOH(ac) and VOL(ac).

20. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater

than the minimum specification limits for tCL and tCH).....For example, tCL and tCH are = 50% of the period, less the half period jitter (tJIT(HP)) of the

clock source, and less the half period jitter due to crosstalk (tJIT(crosstalk)) into the clock traces.

21. tQH = tHP - tQHS, where:

tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS accounts for 1) The pulse duration dis-

tortion of on-chip clock circuits; and 2) The worst case push-out of DQS on one tansition followed by the worst case pull-in of DQ on the next transi-

tion, both of which are, separately, due to data pin skew and output pattern effects, and p channel to n-channel variation of the output drivers.

22. tDQSQ - Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers for any given cycle.

23. tDAL = (tWR/tCK) + (tRP/tCK)

For each of the terms above, if not already an integer , round to the next highest integer. Example: For DDR266B at CL=2.5 and tCK=7.5ns tDAL = (15

ns / 7.5 ns) + (20 ns/ 7.5ns) = (2) + (3) tDAL = 5 clocks

Output

VDDQ

50Ω

30pF

(Vout)

Figure 1 : Timing Reference Load

14.0 Component Notes

DDR SDRAM

512MB, 1GB, 2GB Registered DIMM

Rev. 1.2 June 2005

b. Pulldown slew rate is measured under the test conditions shown in Figure 3.

Output Test point

VDDQ

50Ω

Figure 3 : Pulldown slew rate test load

c. Pullup slew rate is measured between (VDDQ/2 - 320 mV +/- 250 mV)

Pulldown slew rate is measured between (VDDQ/2 + 320 mV +/- 250 mV)

Pullup and Pulldown slew rate conditions are to be met for any pattern of data, including all outputs switching and only one output switching.

Example : For typical slew rate, DQ0 is switching

For minmum slew rate, all DQ bits are switching from either high to low, or low to high.

The remaining DQ bits remain the same as for pr evious state.

d. Evaluation conditions

Typical : 25 °C (T Ambient), VDDQ = 2.5V(for DDR266/333) and 2.6V(for DDR400), typical process

Minimum : 70 °C (T Ambient), VDDQ = 2.3V(for DDR266/333) and 2.5V(for DDR400), slow - slow process

Maximum : 0 °C (T Ambient), VDDQ = 2.7V(for DDR266/333) and 2.7V(for DDR400), fast - fast process

e. The ratio of pullup slew rate to pulldown slew rate is specified for the same temperature and voltage, over the entire temperature and voltage range.

For a given output, it represents the maximum difference between pullup and pulldown drivers due to process variation.

f. Verified under typical conditions for qualification purposes.

g. TSOPII package divices only.

h. Only intended for operation up to 266 Mbps per pin.

i. A derating factor will be used to increase tIS and tIH in the case where the input slew rate is below 0.5V/ns as shown in Table 2. The Input slew rate is

based on the lesser of the slew rates detemined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions.

j. A derating factor will be used to increase tDS and tDH in the case where DQ, DM, and DQS slew rates differ, as shown in Tables 3 & 4. Input slew rate

is based on the larger of AC-AC delta rise, fall rate and DC-DC delta rise, Input slew rate is based on the lesser of the slew rates determined by either

VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions. The delta rise/fall rate is calculated as: {1/(Slew Rate1)} - {1/(Slew Rate2)}

For example : If Slew Rate 1 is 0.5 V/ns and slew Rate 2 is 0.4 V/ns, then the delta rise, fall rate is - 0.5ns/V . Using the table given, this

would result in the need for an increase in tDS and tDH of 100 ps.

k. Table 3 is used to increase tDS and tDH in the case where the I/O slew rate is below 0.5 V/ns. The I/O slew rate is based on the lesser on the lesser of

the AC - AC slew rate and the DC- DC slew rate. The inut slew rate is based on the lesser of the slew rates deter mined by either VIH(ac) to VIL(ac) or

VIH(DC) to VIL(DC), and similarly for rising transitions.

m. DQS, DM, and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transi tions through the

DC region must be monotonic.

a. Pullup slew rate is characteristized under the test conditions as shown in Figure 2.

Output Test point

VSSQ

50Ω

Figure 2 : Pullup slew rate test load

15.0 System Notes:

DDR SDRAM

512MB, 1GB, 2GB Registered DIMM

Rev. 1.2 June 2005

(V=Valid, X=Don′t Care, H=Logic High, L=Logic Low)

Note :

1. OP Code : Operand Code. A0 ~ A12 & BA0 ~ BA1 : Program keys. (@EMRS/MRS)

2. EMRS/ MRS can be issued only at all banks precharge state. A new command can be issued 2 clock cycles after EMRS or MRS.

3. Auto refresh functions are same as the CBR refresh of DRAM.

The automatical precharge without row precharge command is meant by "Auto".

Auto/self refresh can be issued only at all banks precharge state.

4. BA0 ~ BA1 : Bank select addresses.

If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.

If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected.

If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected.

If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.

5. If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected.

6. During burst write with auto precharge, new read/write command can not be issued.

Another bank read/write command can be issued after the end of burst.

New row active of the associated bank can be issued at tRP after the end of burst.

7. Burst stop command is valid at every burst length.

8. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0).

9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM.

COMMAND CKEn-1 CKEn CS RAS CAS WE BA0,1 A10/AP A0 ~ A9

A11, A12 Note

Refresh

Auto Refresh HHLL LH X 3

Self

Refresh

Entry L 3

Exit L H LHHH X3

HX XX 3

Bank Active & Row Addr. H X L L H H V Row Address

(A0~A9, A11,A12)

Read &

Column Address Auto Precharge Disable HXLHLHV

LColumn

Address 4

Auto Precharge Enable H 4

Write &

Column Address Auto Precharge Disable HXLHLLV

LColumn

Address 4

Auto Precharge Enable H 4, 6

Burst Stop H X L H H L X 7

Precharge Bank Selection HXLLHL

VL X

All Banks X H 5

Active Power Down Entry H L HX XX XLVVV

Exit L H X X X X

Precharge Power Down Mode Entry H L HX XX

LHHH

Exit L H HX XX

LVVV

DM H X X 8

No operation (NOP) : Not defined H X HX XX X9

LHHH 9

16.0 Command Truth Table

DDR SDRAM

512MB, 1GB, 2GB Registered DIMM

Rev. 1.2 June 2005

Units : Inches (Millimeters)

Tolerances : ± 0.005(.13) unless otherwise specified

The used device is 64Mx8 DDR SDRAM, TSOPII

SDRAM Part No : K4H510838C

A B

REG

PLL

A B

5.25 ± 0.005

5.171

(131.350)

(133.350 ± 0.13)

(30.48 +/-0.15)

1.2 +/-0.06

5.077

(128.950)

0.393

(10.00)

(19.80)

0.78

(17.80)

0.7

0.10 MCBA

R (2.00)

0.0787

(3.00 Min)

0.118 Min

REG

0.157 Max

0.050 ± 0.0039

(1.270 ± 0.10)

(3.99 Max)

(4.00)

(0.157)

0.050

0.0078 ±0.006

(0.20 ±0.15)

(1.270)

0.100 ± 0.0079

(2.50 ± 0.2 )

Detail B

0.250

(6.350)

Detail A

0.071

(1.80)

0.039 ± 0.002

(1.000 ± 0.050)

(3.80)

2.175

0.10 MCA

0.1496

(3.00 Min)

0.118 Min

R (2.00)

0.0787

(4.00 ± 0.1)

0.1575 ± 0.004

0.100

(2.30)

2.500 +0.1/-0.0

17.1 64M x 72 (M312L6523CUS)

17.0 Physical Dimensions

DDR SDRAM

512MB, 1GB, 2GB Registered DIMM

Rev. 1.2 June 2005

Units : Inches (Millimeters)

Tolerances : ± 0.005(.13) unless otherwise specified

The used device is 64Mx8, 128Mx4 DDRSDRAM, TSOPII

SDRAM Part No. : K4H510838C, K4H510438C

A B

REG

PLL

A B

5.25 ± 0.005

5.171

(131.350)

(133.350 ± 0.13)

5.077

(128.950)

0.393

(10.00)

(19.80)

0.78

(17.80)

0.7

0.10 MCBA

R (2.00)

0.0787

REG

0.157 Max

0.050 ± 0.0039

(1.270 ± 0.10)

(3.99 Max)

(4.00)

(0.157)

(30.48 +/-0.15)

1.2 +/-0.06

(3.00 Min)

0.118 Min

0.050

0.0078 ±0.006

(0.20 ±0.15)

(1.270)

0.100 ± 0.0079

(2.50 ± 0.2 )

Detail B

0.250

(6.350)

Detail A

0.071

(1.80)

0.039 ± 0.002

(1.000 ± 0.050)

(3.80)

2.175

0.10 MCA

0.1496

(3.00 Min)

0.118 Min

R (2.00)

0.0787

(4.00 ± 0.1)

0.1575 ± 0.004

0.100

(2.30)

2.500 +0.1/-0.0

17.2 128Mx72 (M312L2923CUS), 128Mx72 (M312L2920CUS)

DDR SDRAM

512MB, 1GB, 2GB Registered DIMM

Rev. 1.2 June 2005

Units : Inches (Millimeters)

Tolerances : ± 0.005(.13) unless otherwise specified

The used device is st.256Mx4 SDRAM, 66TSOPII

SDRAM Part NO : K4H1G0638C

A B

PLL

A B

5.25 ± 0.005

5.171

(131.350)

(133.350 ± 0.13)

5.077

(128.950)

0.393

(10.00)

(19.80)

0.78

(17.80)

0.7

0.10 MCBA

R (2.00)

0.0787

Reg.

0.268 Max

0.050 ± 0.0039

(1.270 ± 0.10)

(6.81 Max)

(4.00)

(0.157)

(30.48 +/-0.15)

1.2 +/-0.06

(3.00 Min)

0.118 Min

0.100

(2.30)

2.500 +0.1/-0 .0

0.050

0.0078 ±0.006

(0.20 ±0.15)

(1.270)

0.100 ± 0.0079

(2.50 ± 0.2 )

Deta il B

0.250

(6.350)

Detail A

0.071

(1.80)

0.039 ± 0.002

(1.000 ± 0.050)

(3.80)

2.175

0.10 MCA

0.1496

(3.00 Min)

0.118 Min

R (2.00)

0.0787

(4.00 ± 0.1)

0.1575 ± 0.004

17.3 st.256Mx72 (M312L5628CU0)

DDR SDRAM

512MB, 1GB, 2GB Registered DIMM

Rev. 1.2 June 2005

Tolerances : ± 0.005(.13) unless otherwise specified

The used device is 64Mx8 DDR SDRAM, FBGA

DDR SDRAM Part No. : K4H510838C-Z***,

133.35 A

128.95 A

2x 3.00 MIN W1

4x 4.00+/-0.1 V1

64.77 P2 49.53 P3

120.65 P1

19.80 B1

28.575 +/-0.15 B

6.35

10.00 B2

192

Detail BDetail A

3.80 W

X1 X2

6.35 X

2.175 4.175

V1.80

D1.0 +/-0.05

0.20 +/-0.15 T

2.50 G

1.27

MAX 0.178 D1

Units : Millimeters

2.99 MAX

12.00

18493

1.27 +/-0.1

2x DIA. 2.50 +0.1/-0.00 N

17.4 64Mx72 (M312L6523CZ0)

DDR SDRAM

512MB, 1GB, 2GB Registered DIMM

Rev. 1.2 June 2005

Tolerances : ± 0.005(.13) unless otherwise specified

The used device is 64Mx8, 128Mx4 DDR SDRAM, FBGA

DDR SDRAM Part No. : K4H510838C-Z***, K4H510438C-Z***

133.35 A

128.95 A

2x 3.00 MIN W1

4x 4.00+/-0.1 V1

64.77 P2 49.53 P3

120.65 P1

19.80 B1

28.575 +/-0.15 B

6.35

10.00 B2

192

Detail BDetail A

3.80 W

X1 X2

6.35 X

2.175 4.175

V1.80

D1.0 +/-0.05

0.20 +/-0.15 T

2.50 G

1.27

MAX 0.178 D1

Units : Millimeters

18493

3.99 MAX

12.00

1.27 +/-0.1

2x DIA. 2.50 +0.1/-0.00 N

17.5 128Mx72 (M312L2923CZ0), (M312L2920CZ0)

DDR SDRAM

512MB, 1GB, 2GB Registered DIMM

Rev. 1.2 June 2005

Tolerances : ± 0.005(.13) unless otherwise specified

The used device is 128Mx4 DDR SDRAM, FBGA

DDR SDRAM Part No : K4H510438C-Z***

Units : Millimeters

133.35 A

128.95 A

2x 3.00 MIN W1

4x 4.00+/-0.1 V1

64.77 P2 49.53 P3

120.65 P1

19.80 B1

30.48 +/-0.15 B

6.35

10.00 B2

192

Detail BDet ail A

3.80 W

X1 X2

6.35 X

2.175 4.175

V1.80

D1.0 +/-0.05

0.20 +/-0 .15 T

2.50 +/-0.2 G

1.27

MAX 0.178 D1

3.99 MAX

12.0 10.0

18493

1.27 +/-0.1

2x DIA. 2.50 +0.1/-0.00 N

17.6 256Mx72 (M312L5720CZ0)