LP3962EP/LP3965EP
1.5A Fast Ultra Low Dropout Linear Regulators
General Description
The LP3962EP/LP3965EP series of fast ultra low-dropout
linear regulators operate from a +2.5V to +7.0V input supply.
Wide range of preset output voltage options are available.
These ultra low dropout linear regulators respond very fast to
step changes in load which makes them suitable for low
voltage microprocessor applications. The LP3962EP/
LP3965EP are developed on a CMOS process which allows
low quiescent current operation independent of output load
current. This CMOS process also allows the LP3962EP/
LP3965EP to operate under extremely low dropout condi-
tions.
Dropout Voltage: Ultra low dropout voltage; typically 38mV
at 150mA load current and 380mV at 1.5A load current.
Ground Pin Current: Typically 5mA at 1.5A load current.
Shutdown Mode: Typically 15µA quiescent current when
the shutdown pin is pulled low.
Error Flag: Error flag goes low when the output voltage
drops 10% below nominal value (for LP3962EP).
SENSE: Sense pin improves regulation at remote loads.
(For LP3965EP)
Precision Output Voltage: Multiple output voltage options
are available ranging from 1.2V to 5.0V and adjustable
(LP3965EP), with a guaranteed accuracy of ±1.5% at room
temperature, and ±3.0% over all conditions (varying line,
load, and temperature).
ENHANCED PLASTIC
•Extended Temperature Performance of −40˚C to +125˚C
•Baseline Control - Single Fab & Assembly Site
•Process Change Notification (PCN)
•Qualification & Reliability Data
•Solder (PbSn) Lead Finish is standard
•Enhanced Diminishing Manufacturing Sources (DMS)
Support
Features
nUltra low dropout voltage
nLow ground pin current
nLoad regulation of 0.04%
n15µA quiescent current in shutdown mode
nGuaranteed output current of 1.5A DC
nAvailable in SOT-223,TO-263 and TO-220 packages
nOutput voltage accuracy ±1.5%
nError flag indicates output status (LP3962EP)
nSense option improves better load regulation
(LP3965EP)
nExtremely low output capacitor requirements
nOvertemperature/overcurrent protection
Applications
nMicroprocessor power supplies
nGTL, GTL+, BTL, and SSTL bus terminators
nPower supplies for DSPs
nSCSI terminator
nPost regulators
nHigh efficiency linear regulators
nSelected Military Applications
nSelected Avionics Applications
Ordering Information
PART NUMBER VID PART NUMBER NS PACKAGE NUMBER (Note 3)
LP3962ES-2.5EP V62/04751-01 TS5B
LP3965ES-2.5EP V62/04751-02 TS5B
LP3965ES-ADJEP V62/04751-03 TS5B
(Notes 1, 2) TBD TBD
Note 1: For the following (Enhanced Plastic) version, check for availability: LP3962EMP-1.8EP, LP3962EMP2.5EP, LP3962EMP-3.3EP, LP3962EMP-
5.0EP, LP3962EMPX1.8EP, LP3962EMPX2.5EP, LP3962EMPX3.3EP, LP3962EMPX5.0EP, LP3962ET-1.8EP, LP3962ET-2.5EP, LP3962ET-3.3EP,
LP3962ET-5.0EP, LP3962ES-1.8EP, LP3962EX-3.3EP, LP3962ES-5.0EP, LP3962ESX-1.8EP, LP3962ESX-2.5EP, LP3962ESX-3.3EP, LP3962ESX-5.0EP,
LP3965EMP-1.8EP, LP3965EMP-2.5EP, LP3965EMP-3.3EP, LP3965EMP-5.0EP, LP3965EMP-ADJEP, LP3965EMPX1.8EP, LP3965EMPX2.5EP,
LP3965EMPX3.3EP, LP3965EMPX5.0EP, LP3965EMPXADJEP, LP3965ET-1.8EP, LP3965ET-2.5EP, LP3965ET-3.3EP, LP3965ET-5.0EP, LP3965ET-
ADJEP, LP3965ES-1.8EP, LP3965ES-3.3EP, LP3965ES-5.0EP, LP3965ESX-1.8EP, LP3965ESX-2.5EP, LP3965ESX-3.3EP, LP3965ESX-5.0EP,
LP3965ESX-ADJEP. Parts listed with an "X" are provided in Tape & Reel and parts without an "X" are in Rails.
Note 2: FOR ADDITIONAL ORDERING AND PRODUCT INFORMATION, PLEASE VISIT THE ENHANCED PLASTIC WEB SITE AT: www.national.com/
mil
Note 3: Refer to package details under Physical Dimensions
January 2005
LP3962EP/LP3965EP 1.5A Fast Ultra Low Dropout Linear Regulators
© 2005 National Semiconductor Corporation DS201147 www.national.com
Typical Application Circuits
20114701
*SD and ERROR pins must be pulled high through a 10kΩpull-up resistor. Connect the ERROR pin to ground if this function is not used. See applications section
for more information.
** See Application Hints.
20114734
*SD and ERROR pins must be pulled high through a 10kΩpull-up resistor. Connect the ERROR pin to ground if this function is not used. See applications section
for more information.
** See Application Hints.
LP3962EP/LP3965EP
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Block Diagram LP3962EP
20114703
Block Diagram LP3965EP
20114729
LP3962EP/LP3965EP
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Block Diagram LP3965-ADJEP
20114735
Connection Diagrams
20114704
Top View
SOT 223-5 Package
20114705
Top View
TO220-5 Package
Bent, Staggered Leads
20114706
Top View
TO263-5 Package
Pin Description for SOT223-5 Package
Pin # LP3962EP LP3965EP
Name Function Name Function
1SD
Shutdown SD Shutdown
2V
IN
Input Supply V
IN
Input Supply
3V
OUT
Output Voltage V
OUT
Output Voltage
4 ERROR ERROR Flag SENSE/ADJ Remote Sense Pin or
Output Adjust Pin
5 GND Ground GND Ground
Pin Description for TO220-5 and TO263-5 Packages
Pin # LP3962EP LP3965EP
Name Function Name Function
1SD
Shutdown SD Shutdown
2V
IN
Input Supply V
IN
Input Supply
3 GND Ground GND Ground
4V
OUT
Output Voltage V
OUT
Output Voltage
5 ERROR ERROR Flag SENSE/ADJ Remote Sense Pin or
Output Adjust Pin
LP3962EP/LP3965EP
www.national.com 4
Absolute Maximum Ratings (Note 4)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Storage Temperature Range −65˚C to +150˚C
Lead Temperature
(Soldering, 5 sec.) 260˚C
ESD Rating (Note 6) 2 kV
Power Dissipation (Note 5) Internally Limited
Input Supply Voltage (Survival) −0.3V to +7.5V
Shutdown Input Voltage
(Survival) −0.3V to V
IN
+0.3V
Output Voltage (Survival), (Note
9), (Note 10) −0.3V to +7.5V
I
OUT
(Survival) Short Circuit Protected
Maximum Voltage for ERROR
Pin V
IN
+0.3V
Maximum Voltage for SENSE Pin V
OUT
+0.3V
Operating Ratings
Input Supply Voltage (Operating),
(Note 15) 2.5V to 7.0V
Shutdown Input Voltage
(Operating) −0.3V to V
IN
+0.3V
Maximum Operating Current (DC) 1.5A
Operating Junction Temp. Range −40˚C to +125˚C
Electrical Characteristics
LP3962ES-2.5EP/LP3965ES-ADJEP Limits in standard typeface are for T
J
= 25˚C, and limits in bold-
face type apply over the full operating temperature range. Unless otherwise specified: V
IN
=V
O(NOM)
+ 1V, I
L
=10mA,
C
OUT
= 33µF, V
SD
=V
IN
-0.3V. (Note 16)
Symbol Parameter Conditions Typ
(Note 7)
LP3962EP/5EP(Note
8)
Units
Min Max
V
O
Output Voltage
Tolerance
(Note 11)
10 mA ≤I
L
≤1.5A
V
OUT
+1 ≤V
IN
≤7.0V 0 -1.5
-3.0
+1.5
+3.0 %
V
ADJ
Adjust Pin Voltage (ADJ
version)
10 mA ≤I
L
≤1.5A
V
OUT
+1.5V ≤V
IN
≤7.0V 1.216 1.198
1.180
1.234
1.253 V
∆V
OL
Output Voltage Line
Regulation (Note 11)
V
OUT
+1V<V
IN
<7.0V, 0.02
0.06
%
∆V
O
/∆I
OUT
Output Voltage Load
Regulation
(Note 11)
10 mA <I
L
<1.5 A 0.04
0.09
%
V
IN
-V
OUT
Dropout Voltage
(Note 13)
I
L
= 150 mA 38 45
55 mV
I
L
= 1.5 A 380 450
550
I
GND
Ground Pin Current In
Normal Operation Mode
I
L
= 150 mA 4 9
10 mA
I
L
= 1.5 A 5 14
15
I
GND
Ground Pin Current In
Shutdown Mode
(Note 14)
V
SD
≤0.2V 15 25
75
µA
I
O(PK)
Peak Output Current (Note 5) 2.5 2.0
1.7
A
SHORT CIRCUIT PROTECTION
I
SC
Short Circuit Current 4.5 A
OVER TEMPERATURE PROTECTION
Tsh(t) Shutdown Threshold 165 ˚C
Tsh(h) Thermal Shutdown
Hysteresis
10 ˚C
LP3962EP/LP3965EP
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Electrical Characteristics
LP3962ES-2.5EP/LP3965ES-ADJEP Limits in standard typeface are for T
J
= 25˚C, and limits in
boldface type apply over the full operating temperature range. Unless otherwise specified: V
IN
=V
O(NOM)
+ 1V, I
L
=10
mA, C
OUT
= 33µF, V
SD
=V
IN
-0.3V. (Note 16) (Continued)
Symbol Parameter Conditions Typ
(Note 7)
LP3962EP/5EP(Note
8)
Units
Min Max
SHUTDOWN INPUT
V
SDT
Shutdown Threshold Output = High V
IN
V
IN
–0.3 V
Output = Low 0 0.2
T
dOFF
Turn-off delay I
L
= 1.5 A 20 µs
T
dON
Turn-on delay I
L
= 1.5 A 25 µs
I
SD
SD Input Current V
SD
=V
IN
1nA
ERROR FLAG COMPARATOR
V
T
Threshold (Note 12) 10 516%
V
TH
Threshold Hysteresis (Note 12) 5 28%
V
EF(Sat)
Error Flag Saturation I
sink
= 100µA 0.02 0.1 V
Td Flag Reset Delay 1 µs
I
lk
Error Flag Pin Leakage
Current
1nA
I
max
Error Flag Pin Sink
Current
V
Error
=0.5V (over temp.) 1 mA
AC PARAMETERS
PSRR Ripple Rejection
V
IN
=V
OUT
+ 1.5V
C
OUT
= 100uF
V
OUT
= 3.3V
60
dB
V
IN
=V
OUT
+ 0.3V
C
OUT
= 100uF
V
OUT
= 3.3V
40
ρ
n(l/f
Output Noise Density f = 120Hz 0.8 µV
e
n
Output Noise Voltage
(rms)
BW = 10Hz – 100kHz 150 µV (rms)
BW = 300Hz – 300kHz 100
Note 4: Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating ratings indicate conditions for which the device is
intended to be functional, but does not guarantee specific performance limits. For guaranteed specifications and test conditions, see Electrical Charateristics. The
guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed
test conditions.
Note 5: At elevated temperatures, devices must be derated based on package thermal resistance. The devices in TO220 package must be derated at θjA = 50˚C/W
(with 0.5in2, 1oz. copper area), junction-to-ambient (with no heat sink). The devices in the TO263 surface-mount package must be derated at θjA = 60˚C/W (with
0.5in2, 1oz. copper area), junction-to-ambient. The devices in SOT223 package must be derated at θjA = 90˚C/W (with 0.5in2, 1oz. copper area), junction-to-ambient.
Note 6: The human body model is a 100pF capacitor discharged through a 1.5kΩresistor into each pin.
Note 7: Typical numbers are at 25˚C and represent the most likely parametric norm.
Note 8: Limits are 100% production tested at 25˚C. Limits over the operating temperature range are guaranteed through correlation using Statistical Quality Control
(SQC) methods. The limits are used to calculate National’s Average Outgoing Quality Level (AOQL).
Note 9: If used in a dual-supply system where the regulator load is returned to a negative supply, the LP396X output must be diode-clamped to ground.
Note 10: The output PMOS structure contains a diode between the VIN and VOUT terminals. This diode is normally reverse biased. This diode will get forward biased
if the voltage at the output terminal is forced to be higher than the voltage at the input terminal. This diode can typically withstand 200mA of DC current and 1Amp
of peak current.
Note 11: Output voltage line regulation is defined as the change in output voltage from the nominal value due to change in the input line voltage. Output voltage
load regulation is defined as the change in output voltage from the nominal value due to change in load current. The line and load regulation specification contains
only the typical number. However, the limits for line and load regulation are included in the output voltage tolerance specification.
Note 12: Error Flag threshold and hysteresis are specified as percentage of regulated output voltage.
Note 13: Dropout voltage is defined as the minimum input to output differential voltage at which the output drops 2% below the nominal value. Dropout voltage
specification applies only to output voltages of 2.5V and above. For output voltages below 2.5V, the drop-out voltage is nothing but the input to output differential,
since the minimum input voltage is 2.5V.
Note 14: This specification has been tested for −40˚C ≤TJ≤85˚C since the temperature rise of the device is negligible under shutdown conditions.
Note 15: The minimum operating value for VIN is equal to either [VOUT(NOM) +V
DROPOUT] or 2.5V, whichever is greater.
Note 16: "Testing and other quality control techniques are used to the extent deemed necessary to ensure product performance over the specified temperature
range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific
PARAMETRIC testing, product performance is assured by characterization and/or design."
LP3962EP/LP3965EP
www.national.com 6
Typical Performance Characteristics Unless otherwise specified, V
IN
=V
O(NOM)
+ 1V, V
OUT
= 2.5V,
C
OUT
= 33µF, I
OUT
= 10mA, C
IN
= 68µF, V
SD
=V
IN
, and T
A
= 25˚C.
Drop-Out Voltage vs Temperature for Different Load
Currents
Drop-Out Voltage vs Temperature for Different Output
Voltages (I
OUT
= 800mA
20114709 20114710
Ground Pin Current vs Input Voltage (V
SD
=V
IN
) Ground Pin Current vs Input Voltage (V
SD
=100mV)
20114711 20114715
Ground Current vs Temperature (V
SD
=V
IN
) Ground Current vs Temperature (V
SD
=0V
20114718 20114712
LP3962EP/LP3965EP
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Typical Performance Characteristics Unless otherwise specified, V
IN
=V
O(NOM)
+ 1V, V
OUT
= 2.5V,
COUT = 33µF, I
OUT
= 10mA, C
IN
= 68µF, V
SD
=V
IN
, and T
A
= 25˚C. (Continued)
Ground Pin Current vs Shutdown Pin Voltage Input Voltage vs Output Voltage
20114716 20114717
Output Noise Density, V
OUT
= 2.5V Output Noise Density, V
OUT
=5V
20114713 20114714
Load Transient Response Ripple Rejection vs Frequency
20114737
20114738
LP3962EP/LP3965EP
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Typical Performance Characteristics Unless otherwise specified, V
IN
=V
O(NOM)
+ 1V, V
OUT
= 2.5V,
COUT = 33µF, I
OUT
= 10mA, C
IN
= 68µF, V
SD
=V
IN
, and T
A
= 25˚C. (Continued)
δV
OUT
vs Temperature Noise Density V
IN
= 3.5V, V
OUT
= 2.5V, I
L
=10mA
20114739 20114740
Line Transient Response Line Transient Response
20114741 20114742
Line Transient Response (I
OUT
= 1.5A) Line Transient Response (I
OUT
= 1.5A)
20114743 20114744
LP3962EP/LP3965EP
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Applications Information
V
IN
RESTRICTIONS FOR PROPER START-UP
Because the LP396XEP devices use on-chip CMOS logic for
analog trimming of the output voltage, care must be taken
not to apply an input voltage which can allow this logic to
shift into random undefined logic states, as this can ad-
versely affect the regulated output voltage. This will most
likely occur if an input voltage between about 50mV and
200mV is applied to V
IN
for a significant amount of time
(more than several seconds). To prevent misoperation, en-
sure that V
IN
is below 50mV before start-up is initiated. This
problem can occur in systems with a backup battery using
reverse-biased "blocking" diodes which may allow enough
leakage current to flow into the V
IN
node to raise it’s voltage
slightly above ground when the main power is removed.
Using low leakage diodes or a resistive pull down can pre-
vent the voltage at V
IN
from rising above the sensitive
threshold. Large bulk capacitors connected to V
IN
may also
cause a start-up problem if they do not discharge fully before
re-start is initiated (but only if V
IN
is allowed to fall below 1V).
A resistor connected across the capacitor will allow it to
discharge more quickly. It should be noted that the probabil-
ity of a "false start" caused by incorrect logic states is ex-
tremely low .
EXTERNAL CAPACITORS
Like any low-dropout regulator, external capacitors are re-
quired to assure stability. these capacitors must be correctly
selected for proper performance.
INPUT CAPACITOR: The LP3962EP/5EP requires a low
source impedance to maintain regulator stability because the
internal bias circuitry is connected directly to V
IN
. The input
capacitor must be located less than 1 cm from the
LP3962EP/5EP device and connected directly to the input
and ground pins using traces which have no other currents
flowing through them (see PCB Layout section).
The minimum allowable input capacitance for a given appli-
cation depends on the type of the capacitor and ESR
(equivalent series resistance). A lower ESR capacitor allows
the use of less capacitance, while higher ESR types (like
aluminum electrolytics) require more capacitance.
The lowest value of input capacitance that can be used for
stable full-load operation is 68 µF (assuming it is a ceramic
or low-ESR Tantalum with ESR less than 100 mΩ).
To determine the minimum input capacitance amount and
ESR value, an approximation which should be used is:
C
IN
ESR (mΩ)/C
IN
(µF) ≤1.5
This shows that input capacitors with higher ESR values can
be used if sufficient total capacitance is provided. Capacitor
types (aluminum, ceramic, and tantalum) can be mixed in
parallel, but the total equivalent input capacitance/ESR must
be defined as above to assure stable operation.
IMPORTANT: The input capacitor must maintain its ESR and
capacitance in the "stable range" over the entire temperature
range of the application to assure stability (see Capacitor
Characteristics Section).
OUTPUT CAPACITOR: An output capacitor is also required
for loop stability. It must be located less than 1 cm from the
LP3962EP/5EP device and connected directly to the output
and ground pins using traces which have no other currents
flowing through them (see PCB Layout section).
The minimum value of the output capacitance that can be
used for stable full-load operation is 33 µF, but it may be
increased without limit. The output capacitor’s ESR is critical
because it forms a zero to provide phase lead which is
required for loop stability. The ESR must fall within the
specified range:
0.2Ω≤C
OUT
ESR ≤5Ω
The lower limit of 200 mΩmeans that ceramic capacitors are
not suitable for use as LP3962EP/5EP output capacitors (but
can be used on the input). Some ceramic capacitance can
be used on the output if the total equivalent ESR is in the
stable range: when using a 100 µF Tantalum as the output
capacitor, approximately 3 µF of ceramic capacitance can be
applied before stability becomes marginal.
IMPORTANT: The output capacitor must meet the require-
ments for minimum amount of capacitance and also have an
appropriate ESR value over the full temperature range of the
application to assure stability (see Capacitor Characteristics
Section).
SELECTING A CAPACITOR
It is important to note that capacitance tolerance and varia-
tion with temperature must be taken into consideration when
selecting a capacitor so that the minimum required amount
of capacitance is provided over the full operating tempera-
ture range. In general, a good Tantalum capacitor will show
very little capacitance variation with temperature, but a ce-
ramic may not be as good (depending on dielectric type).
Aluminum electrolytics also typically have large temperature
variation of capacitance value.
Equally important to consider is a capacitor’s ESR change
with temperature: this is not an issue with ceramics, as their
ESR is extremely low. However, it is very important in Tan-
talum and aluminum electrolytic capacitors. Both show in-
creasing ESR at colder temperatures, but the increase in
aluminum electrolytic capacitors is so severe they may not
be feasible for some applications (see Capacitor Character-
istics Section).
CAPACITOR CHARACTERISTICS
CERAMIC: For values of capacitance in the 10 to 100 µF
range, ceramics are usually larger and more costly than
tantalums but give superior AC performance for bypassing
high frequency noise because of very low ESR (typically less
than 10 mΩ). However, some dielectric types do not have
good capacitance characteristics as a function of voltage
and temperature.
Z5U and Y5V dielectric ceramics have capacitance that
drops severely with applied voltage. A typical Z5U or Y5V
capacitor can lose 60% of its rated capacitance with half of
the rated voltage applied to it. The Z5U and Y5V also exhibit
a severe temperature effect, losing more than 50% of nomi-
nal capacitance at high and low limits of the temperature
range.
X7R and X5R dielectric ceramic capacitors are strongly rec-
ommended if ceramics are used, as they typically maintain a
capacitance range within ±20% of nominal over full operat-
ing ratings of temperature and voltage. Of course, they are
typically larger and more costly than Z5U/Y5U types for a
given voltage and capacitance.
TANTALUM: Solid Tantalum capacitors are recommended
for use on the output because their typical ESR is very close
to the ideal value required for loop compensation. They also
work well as input capacitors if selected to meet the ESR
requirements previously listed.
LP3962EP/LP3965EP
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Applications Information (Continued)
Tantalums also have good temperature stability: a good
quality Tantalum will typically show a capacitance value that
varies less than 10-15% across the full temperature range of
125˚C to −40˚C. ESR will vary only about 2X going from the
high to low temperature limits.
The increasing ESR at lower temperatures can cause oscil-
lations when marginal quality capacitors are used (if the ESR
of the capacitor is near the upper limit of the stability range at
room temperature).
ALUMINUM: This capacitor type offers the most capaci-
tance for the money. The disadvantages are that they are
larger in physical size, not widely available in surface mount,
and have poor AC performance (especially at higher fre-
quencies) due to higher ESR and ESL.
Compared by size, the ESR of an aluminum electrolytic is
higher than either Tantalum or ceramic, and it also varies
greatly with temperature. A typical aluminum electrolytic can
exhibit an ESR increase of as much as 50X when going from
25˚C down to −40˚C.
It should also be noted that many aluminum electrolytics only
specify impedance at a frequency of 120 Hz, which indicates
they have poor high frequency performance. Only aluminum
electrolytics that have an impedance specified at a higher
frequency (between 20 kHz and 100 kHz) should be used for
the LP396XEP. Derating must be applied to the manufactur-
er’s ESR specification, since it is typically only valid at room
temperature.
Any applications using aluminum electrolytics should be
thoroughly tested at the lowest ambient operating tempera-
ture where ESR is maximum.
PCB LAYOUT
Good PC layout practices must be used or instability can be
induced because of ground loops and voltage drops. The
input and output capacitors must be directly connected to the
input, output, and ground pins of the LP3962EP/5EP using
traces which do not have other currents flowing in them
Kelvin connect).
The best way to do this is to lay out C
IN
and C
OUT
near the
device with short traces to the V
IN
,V
OUT
, and ground pins.
The regulator ground pin should be connected to the exter-
nal circuit ground so that the regulator and its capacitors
have a "single point ground".
It should be noted that stability problems have been seen in
applications where "vias" to an internal ground plane were
used at the ground points of the LP3962EP/5EP IC and the
input and output capacitors. This was caused by varying
ground potentials at these nodes resulting from current flow-
ing through the ground plane. Using a single point ground
technique for the regulator and it’s capacitors fixed the prob-
lem.
Since high current flows through the traces going into V
IN
and coming from V
OUT
, Kelvin connect the capacitor leads to
these pins so there is no voltage drop in series with the input
and output capacitors.
RFI/EMI SUSCEPTIBILITY
RFI (radio frequency interference) and EMI (electromagnetic
interference) can degrade any integrated circuit’s perfor-
mance because of the small dimensions of the geometries
inside the device. In applications where circuit sources are
present which generate signals with significant high fre-
quency energy content (>1 MHz), care must be taken to
ensure that this does not affect the IC regulator.
If RFI/EMI noise is present on the input side of the
LP396XEP regulator (such as applications where the input
source comes from the output of a switching regulator), good
ceramic bypass capacitors must be used at the input pin of
the LP396XEP.
If a load is connected to the LP396XEP output which
switches at high speed (such as a clock), the high-frequency
current pulses required by the load must be supplied by the
capacitors on the LP396XEP output. Since the bandwidth of
the regulator loop is less than 100 kHz, the control circuitry
cannot respond to load changes above that frequency. The
means the effective output impedance of the LP396XEP at
frequencies above 100 kHz is determined only by the output
capacitor(s).
In applications where the load is switching at high speed, the
output of the LP396XEP may need RF isolation from the
load. It is recommended that some inductance be placed
between the LP396XEP output capacitor and the load, and
good RF bypass capacitors be placed directly across the
load.
PCB layout is also critical in high noise environments, since
RFI/EMI is easily radiated directly into PC traces. Noisy
circuitry should be isolated from "clean" circuits where pos-
sible, and grounded through a separate path. At MHz fre-
quencies, ground planes begin to look inductive and RFI/
EMI can cause ground bounce across the ground plane.
In multi-layer PCB applications, care should be taken in
layout so that noisy power and ground planes do not radiate
directly into adjacent layers which carry analog power and
ground.
OUTPUT ADJUSTMENT
An adjustable output device has output voltage range of
1.215V to 5.1V. To obtain a desired output voltage, the
following equation can be used with R1 always a 10kΩ
resistor.
For output stability, C
F
must be between 68pF and 100pF.
OUTPUT NOISE
Noise is specified in two ways-
Spot Noise or Output noise density is the RMS sum of all
noise sources, measured at the regulator output, at a spe-
cific frequency (measured with a 1Hz bandwidth). This type
of noise is usually plotted on a curve as a function of fre-
quency.
Total output Noise or Broad-band noise is the RMS sum
of spot noise over a specified bandwidth, usually several
decades of frequencies.
Attention should be paid to the units of measurement. Spot
noise is measured in units µV/√Hz or nV/√Hz and total output
noise is measured in µV(rms).
The primary source of noise in low-dropout regulators is the
internal reference. In CMOS regulators, noise has a low
frequency component and a high frequency component,
which depend strongly on the silicon area and quiescent
current. Noise can be reduced in two ways: by increasing the
transistor area or by increasing the current drawn by the
LP3962EP/LP3965EP
www.national.com11
Applications Information (Continued)
internal reference. Increasing the area will decrease the
chance of fitting the die into a smaller package. Increasing
the current drawn by the internal reference increases the
total supply current (ground pin current). Using an optimized
trade-off of ground pin current and die size, LP3962EP/
LP3965EP achieves low noise performance and low quies-
cent current operation.
The total output noise specification for LP3962EP/
LP3965EP is presented in the Electrical Characteristics
table. The Output noise density at different frequencies is
represented by a curve under typical performance charac-
teristics.
SHORT-CIRCUIT PROTECTION
The LP3962and LP3965 is short circuit protected and in the
event of a peak over-current condition, the short-circuit con-
trol loop will rapidly drive the output PMOS pass element off.
Once the power pass element shuts down, the control loop
will rapidly cycle the output on and off until the average
power dissipation causes the thermal shutdown circuit to
respond to servo the on/off cycling to a lower frequency.
Please refer to the section on thermal information for power
dissipation calculations.
ERROR FLAG OPERATION
The LP3962EP/LP3965EP produces a logic low signal at the
Error Flag pin when the output drops out of regulation due to
low input voltage, current limiting, or thermal limiting. This
flag has a built in hysteresis. The timing diagram in Figure 1
shows the relationship between the ERROR and the output
voltage. In this example, the input voltage is changed to
demonstrate the functionality of the Error Flag.
The internal Error flag comparator has an open drain output
stage. Hence, the ERROR pin should be pulled high through
a pull up resistor. Although the ERROR pin can sink current
of 1mA, this current is energy drain from the input supply.
Hence, the value of the pull up resistor should be in the
range of 10kΩto 1MΩ.The ERROR pin must be con-
nected to ground if this function is not used. It should
also be noted that when the shutdown pin is pulled low, the
ERROR pin is forced to be invalid for reasons of saving
power in shutdown mode.
SENSE PIN
In applications where the regulator output is not very close to
the load, LP3965EP can provide better remote load regula-
tion using the SENSE pin. Figure 2 depicts the advantage of
the SENSE option. LP3962EP regulates the voltage at the
output pin. Hence, the voltage at the remote load will be the
regulator output voltage minus the drop across the trace
resistance. For example, in the case of a 3.3V output, if the
trace resistance is 100mΩ, the voltage at the remote load
will be 3.15V with 1.5 A of load current, I
LOAD
. The
LP3965EP regulates the voltage at the sense pin. Connect-
ing the sense pin to the remote load will provide regulation at
the remote load, as shown in Figure 2. If the sense option pin
is not required, the sense pin must be connected to the V
OUT
pin.
20114707
FIGURE 1. Error Flag Operation
LP3962EP/LP3965EP
www.national.com 12
Applications Information (Continued)
SHUTDOWN OPERATION
A CMOS Logic level signal at the shutdown ( SD) pin will
turn-off the regulator. Pin SD must be actively terminated
through a 10kΩpull-up resistor for a proper operation. If this
pin is driven from a source that actively pulls high and low
(such as a CMOS rail to rail comparator), the pull-up resistor
is not required. This pin must be tied to Vin if not used.
DROPOUT VOLTAGE
The dropout voltage of a regulator is defined as the minimum
input-to-output differential required to stay within 2% of the
output voltage. The LP3962EP/LP3965EP use an internal
MOSFET with an Rds(on) of 240mΩ(typically). For CMOS
LDOs, the dropout voltage is the product of the load current
and the Rds(on) of the internal MOSFET.
REVERSE CURRENT PATH
The internal MOSFET in LP3962EP and LP3965EP has an
inherent parasitic diode. During normal operation, the input
voltage is higher than the output voltage and the parasitic
diode is reverse biased. However, if the output is pulled
above the input in an application, then current flows from the
output to the input as the parasitic diode gets forward biased.
The output can be pulled above the input as long as the
current in the parasitic diode is limited to 200mA continuous
and 1A peak.
MAXIMUM OUTPUT CURRENT CAPABILITY
LP3962 and LP3965 can deliver a continuous current of 1.5
A over the full operating temperature range. A heatsink may
be required depending on the maximum power dissipation
and maximum ambient temperature of the application. Under
all possible conditions, the junction temperature must be
within the range specified under operating conditions. The
total power dissipation of the device is given by:
P
D
=(V
IN
−V
OUT
)I
OUT
+(V
IN
)I
GND
where I
GND
is the operating ground current of the device
(specified under Electrical Characteristics).
The maximum allowable temperature rise (T
Rmax
) depends
on the maximum ambient temperature (T
Amax
) of the appli-
cation, and the maximum allowable junction temperature(T
J-
max
):
T
Rmax
=T
Jmax
−T
Amax
The maximum allowable value for junction to ambient Ther-
mal Resistance, θ
JA
, can be calculated using the formula:
θ
JA
=T
Rmax
/P
D
LP3962 and LP3965 are available in TO-220, TO-263, and
SOT-223 packages. The thermal resistance depends on
amount of copper area or heat sink, and on air flow. If the
maximum allowable value of θ
JA
calculated above is ≥60
˚C/W for TO-220 package, ≥60 ˚C/W for TO-263 package,
and ≥140 ˚C/W for SOT-223 package, no heatsink is
needed since the package can dissipate enough heat to
satisfy these requirements. If the value for allowable θ
JA
falls
below these limits, a heat sink is required.
HEATSINKING TO-220 PACKAGES
The thermal resistance of a TO220 package can be reduced
by attaching it to a heat sink or a copper plane on a PC
board. If a copper plane is to be used, the values of θ
JA
will
be same as shown in next section for TO263 package.
The heatsink to be used in the application should have a
heatsink to ambient thermal resistance,
θ
HA
≤θ
JA
−θ
CH
−θ
JC
.
In this equation, θ
CH
is the thermal resistance from the
junction to the surface of the heat sink and θ
JC
is the thermal
resistance from the junction to the surface of the case. θ
JC
is
about 3˚C/W for a TO220 package. The value for θ
CH
de-
pends on method of attachment, insulator, etc. θ
CH
varies
between 1.5˚C/W to 2.5˚C/W. If the exact value is unknown,
2˚C/W can be assumed.
20114708
FIGURE 2. Improving remote load regulation using LP3965EP
LP3962EP/LP3965EP
www.national.com13
Applications Information (Continued)
HEATSINKING TO-263 AND SOT-223 PACKAGES
The TO-263 and SOT223 packages use the copper plane on
the PCB as a heatsink. The tab of these packages are
soldered to the copper plane for heat sinking. Figure 3
shows a curve for the θ
JA
of TO-263 package for different
copper area sizes, using a typical PCB with 1 ounce copper
and no solder mask over the copper area for heat sinking.
As shown in the figure, increasing the copper area beyond 1
square inch produces very little improvement. The minimum
value for θ
JA
for the TO-263 packag mounted to a PCB is
32˚C/W.
Figure 4 shows the maximum allowable power dissipation
for TO-263 packages for different ambient temperatures,
assuming θ
JA
is 35˚C/W and the maximum junction tempera-
ture is 125˚C.
Figure 5 shows a curve for the θ
JA
of SOT-223 package for
different copper area sizes, using a typical PCB with 1 ounce
copper and no solder mask over the copper area for heat
sinking.
The following figures show different layout scenarios for
SOT-223 package.
20114732
FIGURE 3. θ
JA
vs Copper(1 Ounce) Area for TO-263
package
20114733
FIGURE 4. Maximum power dissipation vs ambient
temperature for TO-263 package
20114719
FIGURE 5. θ
JA
vs Copper(1 Ounce) Area for SOT-223
package
20114720
FIGURE 6. SCENARIO A, θ
JA
= 148˚C/W
20114721
FIGURE 7. SCENARIO B, θ
JA
= 125˚C/W
LP3962EP/LP3965EP
www.national.com 14
Applications Information (Continued)
20114722
FIGURE 8. SCENARIO C, θ
JA
= 92˚C/W
20114723
FIGURE 9. SCENARIO D, θ
JA
= 83˚C/W
20114724
FIGURE 10. SCENARIO E, θ
JA
= 77˚C/W
20114725
FIGURE 11. SCENARIO F, θ
JA
= 75˚C/W
LP3962EP/LP3965EP
www.national.com15
20114726
FIGURE 12. SCENARIO G, θ
JA
= 113˚C/W
20114727
FIGURE 13. SCENARIO H, θ
JA
= 79˚C/W
LP3962EP/LP3965EP
www.national.com 16
Applications Information (Continued)
20114728
FIGURE 14. SCENARIO I, θ
JA
= 78.5˚C/W
LP3962EP/LP3965EP
www.national.com17
Physical Dimensions inches (millimeters)
unless otherwise noted
TO220 5-lead, Molded, Stagger Bend Package (TO220-5)
NS Package Number T05D
LP3962EP/LP3965EP
www.national.com 18
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
TO263 5-Lead, Molded, Surface Mount Package (TO263-5)
NS Package Number TS5B.
LP3962EP/LP3965EP
www.national.com19
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
SOT223, 5-Lead, Molded, Surface Mount Package (SOT223-5)
NS Package Number MP05A
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves
the right at any time without notice to change said circuitry and specifications.
For the most current product information visit us at www.national.com.
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which, (a) are intended for surgical implant into the body, or
(b) support or sustain life, and whose failure to perform when
properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to result
in a significant injury to the user.
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device or system whose failure to perform can be reasonably
expected to cause the failure of the life support device or
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LP3962EP/LP3965EP 1.5A Fast Ultra Low Dropout Linear Regulators
