General Description
The MAX13342E/MAX13345E USB-compliant trans-
ceivers are designed to minimize the area and external
components required to interface low-voltage ASICs to
USB. The devices comply with USB 2.0 specification for
full-speed-only (12Mbps) operation. The transceivers
include an internal 3.3V regulator, an internal 1.5kΩD+
pullup resistor, and built-in ±15kV ESD protection cir-
cuitry to protect the USB I/0 ports (D+,D-). The
MAX13345E also has internal series resistors, allowing
it to be wired directly to a USB connector.
These devices operate with logic-supply voltages as
low as +2.3V, ensuring compatibility with low-voltage
ASICs. A low-power mode reduces current consump-
tion to less than 45µA. An enumerate function controls
the D+ pullup resistor, allowing devices to logically dis-
connect while remaining plugged in.
The MAX13342E has controlled output impedance of
2Ω(max) on D+/D-, allowing the use of external switch-
es to multiplex two different USB devices onto a single
USB connector. The MAX13345E has 43.5Ω(max)
internal resistors on D+/D- for direct connection to the
USB connector.
The MAX13342E/MAX13345E are equipped with DAT
and SE0 interface signals. These transceivers provide a
USB detection function that monitors the presence of
USB VBUS and signals the event.
These devices operate over the extended -40°C to +85°C
temperature range and are available in UCSP™ 2.0mm x
1.5mm and 14-pin TDFN (3mm x 3mm) packages.
UCSP™ is a trademark of Maxim Integrated Products, Inc.
Applications
PDAs
PC Peripherals
Cellular Telephones
Data Cradles
MP3 Players
Features
♦USB 2.0 (Full-Speed, 12Mbps)-Compliant
Transceiver
♦Internal Pullup
♦VBUS Detection
♦Internal Series Resistors (MAX13345E)
♦±15kV (HBM) ESD Protection on D+, D-, and VBUS
♦Enumeration Input Controls D+ Pullup Resistor
♦Supports 3-Wire DAT/SE0 Interface
♦+2.3V to +3.6V Interface Voltage (VL)
♦No Power-Supply Sequencing Required
♦Low USB Output Impedance (MAX13342E)
MAX13342E/MAX13345E
3-Wire Interface Full-Speed USB Transceivers
With/Without Internal Series Resistors
________________________________________________________________ Maxim Integrated Products 1
19-0621; Rev 0; 10/06
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Ordering Information
MAX13342E
SYSTEM
VOLTAGE
SUPPLY
VL
SYSTEM
INTERFACE
BD
DAT
SEO
1µF
1µF
0.1µF
GND D-
D+
VTRM
VBUS
SUS
ENUM
OE
USB
CONNECTOR
31.6Ω
31.6Ω
Typical Operating Circuits
PA RT PIN-
PA CK A G E
T O P
M A RK
PK G C O DE
MAX13342EETD+
14 TD FN- E P
( 3mm x 3m m )
AC Z
T1433- 2
M AX13342E E BC + *12 U C S P
( 2.0m m x 1.5m m )AC U
B12- 3
M A X1 3 3 45 EETD + 14 TD FN- E P
( 3mm x 3m m )
AD A
T1433- 2
M AX13345E E BC + *12 U C S P
( 2.0m m x 1.5m m )AC X
B12- 3
*Future product—contact factory for availability.
+Denotes lead-free package.
EP = Exposed pad.
Pin Configurations and Selector Guide appear at end of data
sheet.
Typical Operating Circuits continued at end of data sheet.
MAX13342E/MAX13345E
3-Wire Interface Full-Speed USB Transceivers
With/Without Internal Series Resistors
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
(All voltages refer to GND unless otherwise noted.)
Supply Voltage (VBUS) .............................................-0.3V to +6V
System Supply Voltage (VL) .....................................-0.3V to +6V
Output of Internal Regulator (VTRM) .........-0.3V to (VBUS + 0.3V)
Input Voltage (D+, D-) ..............................................-0.3V to +6V
SUS, BD ........................................................-0.3V to (VL+ 0.3V)
ENUM, SE0, DAT ..........................................-0.3V to (VL+ 0.3V)
Short-Circuit Current to VBUS or GND (D+, D-) ..............±150mA
Maximum Continuous Current (all other pins) ..................±15mA
Continuous Power Dissipation (TA= +70°C)
14-Pin TDFN (derate 18.5mW/°C above +70°C) .......1482mW
4mm x 3mm UCSP
(derate 6.5mW/°C above +70°C)..............................518mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Bump Soldering ...............................................................+235°C
Lead Soldering (10s) ...................................................... +300°C
ELECTRICAL CHARACTERISTICS
(VBUS = +4.0V to +5.5V, VL= +2.3V to +3.6V, TA= TMIN to TMAX, unless otherwise noted. Typical values are at VBUS = +5.0V, VL=
+2.5V, TA= +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
SUPPLY INPUTS (VBUS, VTRM, VL)
VBUS Input Range VBUS 4.0 5.5 V
VL Input Range VL2.3 3.6 V
Reg ul ated S up p l y- V ol tag e Outp ut
VTRM 3.0 3.3 3.6 V
Operating VBUS Supply Current
IVBUS Full-speed transmitting/receiving at
12Mbps, CL = 50pF on D+ and D- 10 mA
Operating VL Supply Current IVL Ful l - sp eed tr ansm i tti ng /r ecei vi ng at 12M b p s,
CL = 15pF receiver outputs, VL = 2.5V 1.5 mA
Full-speed idle, VD+ >2.7V, VD- <0.3V 500
Full-Speed Idle and SE0 Supply
Current
IVBUS
(
IDLE
)
SE0: VD- <0.3V, VD+ <0.3 500 µA
Static VL Supply Current
IVL
(
STATIC
)
Full-speed idle, SE0 or suspend mode 10 µA
Suspend Supply Current
IVBUS
(
SUSP
)
SE0 = DAT= open;
SUS = OE = high 30 45 µA
Disable-Mode Supply Current
IVBUS
(
DIS
)
VL = GND or open 25 µA
Sharing-Mode VL Supply Current
IV L
(
S H ARIN G
)
VBUS = GND or open, OE = low,
SE0 = DAT = low or high, SUS = high 5µA
D+/D- Supply Current ID+/D- VBUS = GND or open 20 µA
VBUS Power-Supply Detection
Threshold
VTH_VBUS
VL > 2.3V 0.8 3.6 V
VBUS Power-Supply Detection
Hysteresis
VVBUSHYS 100
mV
VL Power-Supply Threshold VTH_VL
850
mV
MAX13342E/MAX13345E
3-Wire Interface Full-Speed USB Transceivers
With/Without Internal Series Resistors
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VBUS = +4.0V to +5.5V, VL= +2.3V to +3.6V, TA= TMIN to TMAX, unless otherwise noted. Typical values are at VBUS = +5.0V, VL=
+2.5V, TA= +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL INPUTS AND OUTPUTS (DAT, SE0, OE, ENUM, SUS, BD)
Input-High Voltage VIH
0.7 x VL
V
Input-Low Voltage VIL
0.3 x VL
V
Output-Voltage High VOH ISOURCE = 2mA
VL - 0.4
V
Output-Voltage Low VOL ISINK = 2mA 0.4 V
Input Leakage Current ILKG -1 +1 µA
Input Capacitance Measured from input to GND 10 pF
ANALOG INPUTS AND OUTPUTS (D+/D-)
Differential Input Sensitivity VID |VD+ - VD-| 200 mV
Differential Common-Mode
Voltage Range VCM Includes VID range 0.8 2.5 V
Single-Ended Input Voltage High
VIHSE 2.0 V
Single-Ended Input Voltage Low
VILSE 0.8 V
Receiver Single-Ended
Hysteresis VHYS
200
mV
Output-Voltage Low VOLD RL = 1.5kΩ from D+ or D- to 3.6V 0.3 V
Output-Voltage High VOHD RL = 15kΩ from D+ or D- to GND 2.8 3.6 V
Off-State Leakage Current Tri-state driver -1 +1 µA
Transceiver Capacitance CIND Measured from D+ or D- to GND 20 pF
MAX13342E 4 14
Driver Output Impedance ROUT MAX13345E 28 43
Ω
Internal Pullup Resistor RPU
1.425 1.500 1.575
kΩ
Input Impedance ZIN Drivers off, tri-state driver, ENUM = 0,
VD+, VD- = 0 OR +3.6V 1MΩ
LINEAR REGULATOR
External Capacitor COUT Compensation of linear regulator 1 µF
ESD PROTECTION (D+, D-)
Human Body Model
±15
kV
IEC 61000-4-2 Air-Gap
Discharge ±8kV
IEC 61000-4-2 Contact
Discharge ±8kV
MAX13342E/MAX13345E
3-Wire Interface Full-Speed USB Transceivers
With/Without Internal Series Resistors
4 _______________________________________________________________________________________
TIMING CHARACTERISTICS
(VBUS = +4V to +5.5V, VL= +2.3V to +3.6V, ENUM = VL, TA= TMIN to TMAX, unless otherwise noted. Typical values are at VBUS =
+5V, VL= +2.5V, TA= +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
TRANSMITTER ( CL = 50pF)
Rise Time tFR
10% to 90% of |VOHD-VOLD| with an external
31.6Ω series resistor (MAX13342E),
Figures 3, 8
420ns
Fall Time tFF
10% to 90% of |VOHD-VOLD| with an external
31.6Ω series resistor (MAX13342E),
Figures 3, 8
420ns
Rise-and-Fall Time Matching
(Note 1) tLR/tLF Figures 3, 8 90
110
%
Output Signal Crossover (Note 2)
VCRS_L,
VCRS_F Figure 4 1.3 2 V
tPLH_DRV Low-to-high transition,
Figures 4, 8 VL > 2.3V 20
Driver
Propagation Delay
tPHL_DRV High-to-low transition,
Figures 4, 8 VL > 2.3V 20
ns
tPZH_DRV
Off-to-high transition,
Figures 5, 8 VL > 2.3V 18
Driver-Enabled Delay Time
tPZL_DRV
Off-to-low transition,
Figures 5, 8 VL > 2.3V 18
ns
tPHZ_DRV
High-to-off transition,
Figure 5, 9 VL > 2.3V 18
Driver Disable Delay
tPLZ_DRV
Low-to-off transition,
Figures 5, 9 VL > 2.3V 18
ns
RECEIVER (CL = 15pF)
tPLH_RCV Low-to-high transition,
Figures 6,10 VL > 2.3V 20
Differential Receiver
Propagation Delay
tPHL_RCV High-to-low transition,
Figures 6,10 VL > 2.3V 20
ns
tPLH_SE Low-to-high transition,
Figures 6,10 18
Single-Ended Receiver
Propagation Delay
tPHL_SE High-to-low transition,
Figures 6,10 18
ns
tPHZ_SE
High-to-off transition,
Figure 7 VL > 2.3V 20
Single-Ended Receiver Disable
Delay tPLZ_SE Low-to-off transition,
Figure 7 VL > 2.3V 20
ns
tPZH_SE
Off-to-high transition,
Figure 7 VL > 2.3V 22
Single-Ended Receiver Enable
Delay tPZL_SE Off-to-low transition,
Figure 7 VL > 2.3V 22
ns
Note 1: Parameters are 100% production tested at +25°C, unless otherwise noted. Limits over temperature are guaranteed by design.
MAX13342E/MAX13345E
3-Wire Interface Full-Speed USB Transceivers
With/Without Internal Series Resistors
_______________________________________________________________________________________ 5
Typical Operating Characteristics
(VBUS = +5V, VL= +3.3V, TA= +25°C, unless otherwise noted.)
4
8
6
12
10
14
16
18
20
1.2 1.8 2.11.5 2.4 2.7 3.0 3.3 3.6
DIFFERENTIAL RECEIVER PROPAGATION
DELAY vs. VL
MAX13342E toc01
VL (V)
PROPAGATION DELAY (ns)
TA = +85°C
TA = +25°C
TA = -40°C
0
8
4
2
6
12
10
14
16
18
20
4.0 4.3 4.6 4.9 5.2 5.5
DIFFERENTIAL RECEIVER PROPAGATION
DELAY vs. VBUS
MAX13342E toc02
VBUS (V)
PROPAGATION DELAY (ns)
TA = +85°C
TA = +25°C
TA = -40°C
10
18
14
12
16
22
20
24
26
28
30
1.2 1.8 2.4 3.01.5 2.1 2.7 3.3 3.6
SINGLE-ENDED RECEIVER PROPAGATION
DELAY vs. VL
MAX13342E toc03
VL (V)
PROPAGATION DELAY (ns)
OE = SUS = HIGH
TA = +85°C
TA = +25°C
TA = -40°C
0
8
4
2
6
12
10
14
16
18
20
4.0 4.3 4.6 4.9 5.2 5.5
SINGLE-ENDED RECEIVER PROPAGATION
DELAY vs. VBUS
MAX13342E toc04
VBUS (V)
PROPAGATION DELAY (ns)
OE = SUS = HIGH
TA = +85°C
TA = +25°CTA = -40°C
0
0.4
0.2
0.1
0.3
0.6
0.5
0.7
0.8
0.9
1.0
-40 -15 10 35 60 85
TRANSMITTER SKEW
vs. TEMPERATURE
MAX13342E toc05
TEMPERATURE (°C)
TRANSMITTER SKEW (ns)
0.6
1.0
0.8
0.7
0.9
1.2
1.1
1.3
1.4
1.5
-40 -15 10 35 60 85
RECEIVER SKEW
vs. TEMPERATURE
MAX13342E toc06
TEMPERATURE (°C)
TRANSMITTER SKEW (ns)
8
16
12
10
14
20
18
22
24
26
0 22 66 110 15444 88 132 176 198 220
VL SUPPLY CURRENT
vs. D+/D- CAPACITANCE
MAX13342E toc07
CAPACITANCE (pF)
VL SUPPLY CURRENT (mA)
1.0
1.2
1.1
1.4
1.3
1.5
1.6
1.7
0 22 66 110 15444 88 132 176 198 220
VBUS SUPPLY CURRENT
vs. D+/D- CAPACITANCE
MAX13342E toc08
CAPACITANCE (pF)
VBUS SUPPLY CURRENT (mA)
VL = 2.5V
20
28
24
22
26
32
30
34
38
36
40
4.0 4.3 4.6 4.9 5.2 5.5
VBUS SUSPEND CURRENT
vs. VBUS SUPPLY VOLTAGE
MAX13342E toc09
VBUS (V)
VBUS SUPPLY CURRENT (µA)
TA = +85°C
TA = +25°C
TA = -40°C
Typical Operating Characteristics (continued)
(VBUS = +5V, VL= +3.3V, TA= +25°C, unless otherwise noted.)
MAX13342E/MAX13345E
3-Wire Interface Full-Speed USB Transceivers
With/Without Internal Series Resistors
6 _______________________________________________________________________________________
MAX13342E/MAX13345E
TRANSMITTING
MAX13342E toc10
D+
D-
2V/div
DAT
2V/div
(2V/div)
SEO
20ns/div
MAX13342E/MAX13345E
RECEIVING
MAX13342E toc11
D-
D+
2V/div
2V/div
2V/div
DAT
2V/div
SEO
100ns/div
MAX13342E/MAX13345E
BUS DETECTION
MAX13342E toc12
1V/div
VBUS
2V/div
BD
4µs
-1
0
1
2
3
4
02010 30 40 50 60 70 80
EYE DIAGRAM
TIME (ns)
D+ AND D- (V)
MAX13342E toc13
MAX13342E/MAX13345E
3-Wire Interface Full-Speed USB Transceivers
With/Without Internal Series Resistors
_______________________________________________________________________________________ 7
Pin Description
PIN
TDFN
UCSP NAME
FUNCTION
1B1V
TRM
Regulated Output Voltage. VTRM provides a 3.3V output derived from VBUS. Bypass VTRM to GND
with a 1µF (min) low-ESR capacitor, such as ceramic or plastic film types. VTRM provides power
to internal circuitry and the internal D+ pullup resistor. Do not use VTRM to power external
circuitry. These USB transceivers can also be powered by an externally regulated 3.3V supply
connected to both VBUS and VTRM.
2A1V
LSystem-Side Power-Supply Input. Connect VL to the systems logic-level power supply. Bypass VL
to GND with a 0.1µF (min) low-ESR ceramic capacitor.
3 A2 SE0
Logic-Side Data Input/Output. SE0 operates as an input when OE is low and as an output when
OE is high. As an input, when SE0 is active high, D+ and D- are both driven low. As an output,
SE0 goes active high when both D+ and D- are low. (See Tables 3 and 4.)
4 A3 DAT Logic-Side Data Input/Output. DAT operates as an input for data on D+/D- when OE is low. DAT
operates as the output of the differential receiver on D+/D- when OE is high. (See Tables 3 and 4.)
5, 12
—N.C. No Connection. Leave N.C. unconnected. N.C. is not internally connected.
6 B3 SUS Suspend Input. Drive SUS low for normal transceiver operation. Drive SUS high for low-power
state.
7 A4 BD USB Detector Output. A high on BD indicates that VBUS is present.
8B4OE
Output Enable. OE controls the USB transmitter outputs (D+/D-) and the interface signals (DAT,
SE0) when in USB mode. Drive OE high to operate D+/D- as inputs and to operate the logic
interface signals as outputs. Drive OE low to operate D+/D- as outputs and to operate the logic
interface signals as inputs.
9 C4 GND Ground
10 C3 D-
Negative USB Differential Data Input/Output. D- is wired to the USB connector directly
(MAX13345E) or through a series resistor (MAX13342E). D- operates as an input when OE is high
and as an output when OE is low.
11 C2 D+
Positive USB Differential Data Input/Output. D+ is wired to the USB connector directly
(MAX13345E) or through a series resistor (MAX13342E). D+ operates as an input when OE is
high and as an output when OE is low.
13 B2
ENUM
Enumerate. Drive ENUM high to connect the internal 1.5kΩ resistor from D+ to VTRM. Drive ENUM
low to disconnect the internal 1.5kΩ resistor.
14 C1 VBUS USB-Side Power-Supply Input. Connect VBUS to the incoming USB power supply. Bypass VBUS to
GND with a 1µF ceramic capacitor.
EP —EP Exposed Paddle. Connect EP to GND.
MAX13342E/MAX13345E
3-Wire Interface Full-Speed USB Transceivers
With/Without Internal Series Resistors
8 _______________________________________________________________________________________
Detailed Description
The MAX13342E/MAX13345E USB-compliant trans-
ceivers are designed to minimize the area and external
components required to interface low-voltage ASICs to
USB. The devices comply with the USB 2.0 specifica-
tion for full-speed (12Mbps) operation. The transceivers
include an internal 3.3V regulator, an internal 1.5kΩD+
pullup resistor, and built-in ±15kV (HBM) ESD protec-
tion circuitry to protect D+, D-. Figure 1 is the
MAX13342E/MAX13345E functional diagram.
The MAX13342E has controlled output impedance of
12Ω(max) on D+/D-, allowing the use of external
switches to multiplex two different USB devices onto a
single USB connector.
The MAX13345E uses internal series resistors on D+/D-
to allow direct interface to the USB connector. A low-
power mode reduces current consumption to less than
45µA. An enumerate function controls connection of the
internal D+ pullup resistor.
The MAX13342E/MAX13345E are equipped with DAT
and SE0 interface signals and support the 3-wire USB
tranceiver interface. Although the 3-wire interface is
commonly associated with USB On-the-Go trans-
ceivers, the MAX13342E/MAX13345E support USB
peripherals only. These transceivers provide a USB
VBUS detection function that monitors the presence of
USB VBUS and signals the event.
LEVEL
TRANSLATOR
AND LOGIC
D+
D-
BD
OE
VL
LDO
REGULATOR VTRM
VBUS
MAX13342E
MAX13345E
ENUM
SUS
DAT
SEO
MAX13345E
Figure 1. MAX13342E/MAX13345E Functional Diagram
MAX13342E/MAX13345E
3-Wire Interface Full-Speed USB Transceivers
With/Without Internal Series Resistors
_______________________________________________________________________________________ 9
Interface
The MAX13342E/MAX13345E control signals are used
to control the USB D+/D- lines. VLpowers the logic-
side interface and sets the input and output thresholds
of these signals. The control signals for the MAX13342E
and MAX13345E are DAT, SE0, and OE.
Power-Supply Configuration
Normal Operating Mode
See Table 1 for various power-supply configurations.
VBUS supplies power to the USB transceivers. Connect
VBUS to a +4V to +5.5V supply. Connect VLto a +2.3V
to +3.6V supply. VBUS is typically connected directly to
the USB connector. An internal regulator provides 3.3V
to internal circuitry, and a regulated 3.3V output at
VTRM, in addition to powering the internal D+ pullup
resistor. The MAX13342E and MAX13345E can be
powered by connecting both VBUS and VTRM to a 3.3V
external regulator.
Low-Power Mode
Operate the transceivers in low-power mode by assert-
ing SUS high. In low-power mode, the USB differential
receiver is turned off and VBUS consumes less than
45µA of supply current. The single-ended D+ and D-
receivers are still active when driving SUS high.
Sharing Mode
Connect VLto a system power supply and leave VBUS
(or VBUS and VTRM) unconnected or connected to
GND. D+ and D- are tri-stated, allowing other circuitry
to share the USB D+ and D- line. VLconsumes less
than 5µA of supply current. When operating the trans-
ceivers in sharing mode, the SUS input is ignored, and
the interface signals (SE0, DAT) are high impedance.
Disable Mode
Connect VBUS to a system power supply and leave VL
unconnected or connect to ground. In disable mode,
D+ and D- are tri-stated, and VBUS and/or VTRM (or
VBUS and VTRM) consume less than 25µA. When oper-
ating the transceivers in disable mode, OE, SUS, and
inputs to the interface control signals are ignored.
(See Table 2.)
VBUS (V) VTRM (V) VL (V) CONFIGURATION NOTES
+4.0 to +5.5 +3.0 to +3.6 output +2.3 to +3.6 Normal mode —
+4.0 to +5.5 +3.0 to +3.6 output GND or floating Disable mode Table 2
GND or Floating High Z +2.3 to +3.6 Sharing mode Table 2
INPUTS/OUTPUTS DISABLE MODE SHARING MODE
VBUS / VTRM 4V to 5.5V Floating or connected to GND
VLFloating or connected to GND 2.3V to 3.6V input
D+ and D- High impedance High impedance
DAT, SE0 High impedance High impedance
SUS High impedance High impedance
BD Low Low
Table 1. Power-Supply Configuration
Table 2. Disable-Mode and Sharing-Mode Connection
MAX13342E/MAX13345E
3-Wire Interface Full-Speed USB Transceivers
With/Without Internal Series Resistors
10 ______________________________________________________________________________________
3-Wire DAT/SE0 Interface
The MAX13342E/MAX13345E use DAT and SE0 to
drive data or a single-ended zero onto the D+/D- lines.
When OE is low, SE0 is an input and functions as a
single-ended zero driver. When SE0 is high, both D+
and D- are driven low. When SE0 is driven low, the
D+/D- outputs are controlled by DAT.
DAT is used to send data on D+/D- when both OE and
SE0 are low. When DAT is high, D+ is driven high and
D- is driven low. When DAT is low, D+ is driven low and
D- is driven high.
In receive mode (OE = high), DAT is the output of the
differential receiver connected to D+ and D-. SE0 only
goes active high when both D+ and D- are low.
Control Signals
USB Detection
The MA13342E/MAX13345E USB detection function
indicates that VBUS is present. The MAX13342E/
MAX13345E push-pull bus detection output (BD) moni-
tors VBUS, and asserts high when VBUS and VLare pre-
sent. BD asserts low if VBUS is less than +3.6V and
enters sharing mode.
OE
OE controls the direction of communication when VL
and VBUS are both present. When OE is low, DAT and
SE0 operate as logic inputs and D+/D - are outputs.
When OE is high, DAT and SE0 operate as logic out-
puts and D+/D- are inputs.
SUS
SUS determines whether the MAX13342E/MAX13345E
operate in normal mode or in suspend mode. Drive
SUS low for normal operation. Drive SUS high to enable
suspend mode. In suspend mode, the single-ended
receivers (D+/D-) are active to detect a wake-up event.
Supply current decreases to less than 45µA in suspend
mode.
The MAX13342E/MAX13345E can transmit data on D+
and D- while in suspend mode. This function is used to
signal a remote wake-up event.
ENUM
A 1.5kΩpullup resistor on D+ is used to indicate full-
speed (12Mbps) operation. Drive ENUM high to con-
nect the internal pullup resistor from D+ to VTRM. Drive
ENUM low to disconnect the internal pullup resistor
from D+ to VTRM.
D+ and D-
D+ and D- are bidirectional signals and are ESD pro-
tected to ±15kV (HBM). OE controls the direction of D+
and D- when in USB normal mode (Tables 3 and 4).
VTRM
An internal linear regulator generates the VTRM voltage
(+3.3V typ). VTRM derives power from VBUS (see the
Power-Supply Configuration section). VTRM powers the
internal USB circuitry and provides the pullup voltage
for the internal 1.5kΩresistor. Bypass VTRM to GND
with a 1µF ceramic capacitor as close to the device as
possible. Do not use VTRM to provide power to external
circuitry.
MAX13342E/MAX13345E
3-Wire Interface Full-Speed USB Transceivers
With/Without Internal Series Resistors
______________________________________________________________________________________ 11
Applications Information
USB Data Transfer
Transmitting Data
The MAX13342E/MAX13345E transmit USB data to the
USB differentially on D+ and D- when OE is low. The
D+ and D- outputs are determined by SE0 and DAT
(see Table 3).
Receiving Data
Drive OE high and SUS low to receive data on D+/D-.
Differential data received on D+ and D- appear at DAT.
SE0 goes high only when both D+ and D- are low
(Table 4).
External Resistors
(MAX13342E)
The MAX13342E provides low internal resistance on
D+/D-. Two external series resistors for impedance
matching are required for USB. Place the resistors in
between the MAX13342E and the USB connector (see
Figure 2).
External Capacitors
Use three external capacitors for proper operation.
Bypass VLto GND with a 0.1µF ceramic capacitor.
Bypass VBUS to GND with a 1µF ceramic capacitor.
Bypass VTRM to GND with a 1µF (min) ceramic or plas-
tic capacitor. Place all capacitors as close to the
device as possible.
UCSP Application Information
For the latest application details on UCSP construction,
dimensions, tape carrier information, printed circuit
board (PCB) techniques, bump-pad layout, and recom-
mended reflow temperature profile, as well as the latest
information on reliability testing results, refer to
Application Note 1891: UCSP—A Wafer-Level Chip-
Scale Package available on Maxim’s website at
www.maxim-ic.com/ucsp.
(OE = 0, SUS = 0)
INPUTS OUTPUTS
DAT SE0 D+ D-
0001
0100
1010
1100
Table 3. Transmit Truth Table
(OE = 1, SUS = 0)
INPUTS OUTPUTS
D+ D- DAT SE0
0 0 *DAT 1
0 1 **0 0
1 0 **1 0
11X0
Table 4. Receive Truth Table
*Last state
**D+/D- differential receiver output
X= Undefined
MAX13342E/MAX13345E
3-Wire Interface Full-Speed USB Transceivers
With/Without Internal Series Resistors
12 ______________________________________________________________________________________
ESD Protection
The MAX13342E/MAX13345E feature ±15kV (HBM) ESD
protection on D+ and D-. The ESD structures withstand
high ESD in all states: normal operation, suspend, and
powered down. For the ±15kV ESD structures to work
correctly, a 1µF or greater capacitor must be connected
from VTRM to GND. VBUS and D+/D- are characterized
for protection to the following limits:
•±15kV using the Human Body Model
•±8kV using the IEC 61000-4-2 Contact Discharge
Method
•±8kV using the IEC 61000-4-2 Air-Gap Method
ESD Test Conditions
ESD performance depends on a variety of conditions.
Contact Maxim for a reliability report that documents
test setup, test methodology, and test results.
Human Body Model
Figure 11 shows the Human Body Model, and Figure
12 shows the current waveform it generates when dis-
charged into a low impedance. This model consists of
a 100pF capacitor charged to the ESD voltage of inter-
est, which is then discharged into the test device
through a 1.5kΩresistor.
IEC 61000-4-2
The IEC 61000-4-2 standard covers ESD testing and
performance of finished equipment; it does not specifi-
cally refer to integrated circuits. The MAX13342E/
MAX13345E help the user design equipment that meets
level 4 of IEC 61000-4-2, without the need for additional
ESD-protection components. The major difference
between tests done using the Human Body Model and
IEC 61000-4-2 is a higher peak current in IEC 61000-4-
2 because series resistance is lower in the IEC 61000-
4-2 model. Hence, the ESD withstand voltage
measured to IEC 61000-4-2 is generally lower than that
measured using the Human Body Model. Figure 13
shows the IEC 61000-4-2 model. The Air-Gap
Discharge Method involves approaching the device
with a charged probe. The Contact Discharge Method
connects the probe to the device before the probe
is energized.
MAX13342E
SYSTEM
VOLTAGE
SUPPLY
VBUS
VL
SYSTEM
INTERFACE
DAT
SEO
GND
D-
D+
GND
D-
D+
VTRM
SUS
ENUM
OE
USB CONNECTOR
31.6Ω
31.6Ω
USB
POWER
0.1µF1.0µF
1.0µF
BD
Figure 2. Adding External Resistors to the USB Connector for the MAX13342E
MAX13342E/MAX13345E
3-Wire Interface Full-Speed USB Transceivers
With/Without Internal Series Resistors
______________________________________________________________________________________ 13
VOHD
VOLD
90%
10%
90%
10%
tFR, tLR tFF, tLF
Figure 3. Rise and Fall Times
DAT CONNECTED TO
GND, SE0 CONNECTED
TO GND. D+ PULLED TO
3.0V WITH 150Ω.
DAT CONNECTED TO
VL, SE0 CONNECTED
TO GND. D+ PULLED
TO GND WITH 150Ω.
DAT CONNECTED TO
VL, SE0 CONNECTED
TO GND. D- PULLED
TO VL WITH 150Ω.
DAT CONNECTED TO
GND, SE0 CONNECTED
TO GND. D- PULLED
TO GND WITH 150Ω.
tPZH_DRV
tPZL_DRV
tPZH_DRV
tPZL_DRV
tPHZ_DRV
tPLZ_DRV
tPHZ_DRV
tPLZ_DRV
D+
D+
D-
D-
OE
Figure 5. Enable and Disable Timing, Transmitter
DAT
SEO
D-
D+
tPLH_DRV tPHL_DRV
VCRS_F , VCRS_L
RISE/FALL TIMES < 4ns
Figure 4. Timing of DAT, SE0 to D+ and D-
Timing Diagrams/Test Circuits
+3V
0V
DAT/SEO
VL
D+/D-
tPLH_RCV,
tPLH_SE
tPHL_RCV,
tPHL_SE
INPUT RISE/FALL TIME < 4ns
Figure 6. D+/D- to DAT, SE0 Propagation Delays
MAX13342E/MAX13345E
3-Wire Interface Full-Speed USB Transceivers
With/Without Internal Series Resistors
14 ______________________________________________________________________________________
D+ CONNECTED TO
GND, D- CONNECTED TO
+3.0V. DAT PULLED TO
V
L
WITH 330Ω.
D+ CONNECTED TO
+3.0V, D- CONNECTED TO
GND. DAT PULLED TO
GND WITH 330Ω.
D+ CONNECTED TO
+3.0V, D- CONNECTED
TO GND. SE0 PULLED
TO V
L
WITH 330Ω.
D+ CONNECTED TO
GND, D- CONNECTED
TO GND. SE0 PULLED
TO GND WITH 330Ω.
t
PZH_SE
t
PZL_SE
t
PZH_SE
t
PZL_SE
t
PHZ_SE
t
PLZ_SE
t
PHZ_SE
t
PLZ_SE
DAT
DAT
SE0
SE0
OE
Figure 7. Receiver Enable and Disable Timing
D+/D-
DUT
31.6Ω
15kΩ50pF
TEST
POINT
FOR THE MAX13342E
LOAD FOR:
1) ENABLE TIME (D+/D-) MEASUREMENT
2) DAT/SEO TO D+/D- PROPAGATION DELAY
3) D+/D- RISE/FALL TIMES
Figure 8. Load for Transmitter Propagation Delay, Enable Time,
Transmitter Rise/Fall Times
D+/D-
DUT
31.6Ω220Ω
50pF
TEST
POINT
FOR THE MAX13342E
NOTES:
1) V = 0 FOR tPHZ
2) V = VTRM FOR tPLZ
±
Figure 9. Load for Disable Time Measurements
DAT/SEO
DUT
15pF
TEST
POINT
LOAD FOR:
1) D+/D- TO DAT/SEO PROPAGATION DELAYS
2) DAT/SEO RISE/FALL TIMES
Figure 10. Load for Receiver Propagation Delay and Receiver
Rise/Fall Times
MAX13342E/MAX13345E
3-Wire Interface Full-Speed USB Transceivers
With/Without Internal Series Resistors
______________________________________________________________________________________ 15
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
STORAGE
CAPACITOR
Cs
100pF
RC
1MΩ
RD
1.5kΩ
HIGH-
VOLTAGE
DC
SOURCE
DEVICE
UNDER
TEST
Figure 11. Human Body ESD Test Model
IP 100%
90%
36.8%
tRL TIME
tDL
CURRENT WAVEFORM
PEAK-TO-PEAK RINGING
(NOT DRAWN TO SCALE)
Ir
10%
0
0
AMPERES
Figure 12. Human Body Model Current Waveform
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
STORAGE
CAPACITOR
Cs
150pF
RC
50MΩ TO 100MΩ
RD
330Ω
HIGH-
VOLTAGE
DC
SOURCE
DEVICE
UNDER
TEST
Figure 13. IEC 61000-4-2 ESD Test Model
MAX13342E/MAX13345E
3-Wire Interface Full-Speed USB Transceivers
With/Without Internal Series Resistors
16 ______________________________________________________________________________________
MAX13342E
MAX4717
SYSTEM
VOLTAGE
SUPPLY
VBUS
VL
SYSTEM
INTERFACE
BD
DAT
SEO
GND D-
D+
VTRM
COM1
NC1
NO1
NC2
NO2
IN1, IN2
SUS
ENUM
OE
GPIO
COM2
MULTIMEDIA
PROCESSOR
USB
CONNECTOR
0.1µF
1µF
1µF
31.6Ω
31.6Ω
Typical Application Circuit
Pin Configurations
TOP VIEW
(BUMP SIDE DOWN)
2.0mm x 1.5mm UCSP
DATSEO BD
VL
1
A
B
C
234
VBUS GND
D+
VTRM SUS OE
ENUM
D-
MAX13345E
MAX13342E
MAX13342E
MAX13345E
3mm x 3mm TDFN
TOP VIEW
245
13 11 10
ENUM
D+
D-
VL
DAT
N.C.
1
14
VBUS
VTRM
3
12
N.C.SE0
6
9
GNDSUS
7
8
OEBD
*CONNECT EP TO GND
*EP
+
+
Chip Information
PROCESS: BiCMOS
MAX13342E/MAX13345E
3-Wire Interface Full-Speed USB Transceivers
With/Without Internal Series Resistors
______________________________________________________________________________________ 17
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
6, 8, &10L, DFN THIN.EPS
H1
2
21-0137
PACKAGE OUTLINE, 6,8,10 & 14L,
TDFN, EXPOSED PAD, 3x3x0.80 mm
COMMON DIMENSIONS
SYMBOL MIN. MAX.
A 0.70 0.80
D 2.90 3.10
E 2.90 3.10
A1 0.00 0.05
L 0.20 0.40
PKG. CODE N D2 E2 eJEDEC SPEC b[(N/2)-1] x e
PACKAGE VARIATIONS
0.25 MIN.k
A2 0.20 REF.
2.30–0.101.50–0.106T633-1 0.95 BSC MO229 / WEEA 1.90 REF0.40–0.05
1.95 REF0.30–0.050.65 BSC2.30–0.108T833-1
2.00 REF0.25–0.050.50 BSC2.30–0.1010T1033-1
2.40 REF0.20–0.05- - - - 0.40 BSC1.70–0.10 2.30–0.1014T1433-1
1.50–0.10
1.50–0.10
MO229 / WEEC
MO229 / WEED-3
0.40 BSC - - - - 0.20–0.05 2.40 REFT1433-2 14 2.30–0.101.70–0.10
T633-2 6 1.50–0.10 2.30–0.10 0.95 BSC MO229 / WEEA 0.40–0.05 1.90 REF
T833-2 8 1.50–0.10 2.30–0.10 0.65 BSC MO229 / WEEC 0.30–0.05 1.95 REF
T833-3 8 1.50–0.10 2.30–0.10 0.65 BSC MO229 / WEEC 0.30–0.05 1.95 REF
-DRAWING NOT TO SCALE-
H
2
2
21-0137
PACKAGE OUTLINE, 6,8,10 & 14L,
TDFN, EXPOSED PAD, 3x3x0.80 mm
2.30–0.10 MO229 / WEED-3 2.00 REF0.25–0.05
0.50 BSC
1.50–0.1010T1033-2
MAX13342E/MAX13345E
3-Wire Interface Full-Speed USB Transceivers
With/Without Internal Series Resistors
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2006 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
12L, UCSP 4x3.EPS
F
1
1
21-0104
PACKAGE OUTLINE, 4x3 UCSP
