*Other brands and names are the property of their respective owners.
Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or
copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make
changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.
December 1995COPYRIGHT ©INTEL CORPORATION, 1995 Order Number: 271312-002
VS28F016SV, MS28F016SV
16-Mbit (1-Mbit x 16, 2-Mbit x 8) FlashFileTM MEMORY
YVS28F016SV
Ðb40§Ctoa
125§C
Ð SE2 Grade
YMS28F016SV
Ðb55§Ctoa
125§C
Ð QML Certified
Ð SE1 Grade
YSmartVoltage Technology
Ð User-Selectable 3.3V or 5V VCC
Ð User-Selectable 5V or 12V VPP
YThree Voltage/Speed Options
Ð 80 ns Access Time, 5.0V g5%
Ð 85 ns Access Time, 5.0V g10%
Ð 120 ns Access Time, 3.3V g10%
Y1 Million Erase Cycles per Block
Typical
Y14.3 MB/sec Burst Write Transfer Rate
YConfigurable x8 or x16 Operation
Y56-Lead SSOP Plastic Package
YBackwards-Compatible with VE28F008,
M28F008 and 28F016SA Command Set
YRevolutionary Architecture
Ð Multiple Command Execution
Ð Write During Erase
Ð Command Super-Set of the Intel
VE28F008, M28F008
Ð Page Buffer Write
YMultiple Power Savings Modes
YTwo 256-Byte Page Buffers
YState-of-the-Art 0.6 mm ETOXTM IV
Flash Technology
Intel’s VS/MS28F016SV, 16-Mbit FlashFiIeTM Memory is the latest member of Intel’s high density, high per-
formance memory family for the Industrial, Special Environment, and Military markets. Its user selectable VCC
and VPP (SmartVoltage Technology), innovative capabilities, 100% compatibility with the VE28F008 and
M28F008, multiple power savings modes, selective block locking, and very fast read/write performance make
it the ideal choice for any applications that need a high density and a wide temperature range memory device.
The VS/MS28F016SV is the ideal choice for designers who need to break free from the dependence on slow
rotating media or battery backed up memory arrays.
With two product grades (SE1: b55§Ctoa
125§C, and SE2: b40§Ctoa
125§C) available, the
VS/MS28F016SV is perfect for the non-PC industries like Telecommunications, Embedded/Industrial, Auto-
motive, Navigation, Wireless Communication, Commercial Aircraft, and all Military programs.
The VS/MS28F016SV’s x8/x16 architecture allows for the optimization of the memory to processor interface.
The flexible block locking options enable bundling of executable application software in a Resident Flash Array
(RFA), PCMCIA Memory or ATA Cards or Memory modules.
The VS/MS28F016SV is offered in a 56-lead SS0P (Shrink Small Outline Package) and is manufactured on
Intel’s 0.6 mm ETOXTM IV process technology.
VS28F016SV, MS28F016SV FlashFileTM MEMORY
CONTENTS PAGE
1.0 INTRODUCTION ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 3
1.1 Enhanced Features ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 3
1.2 Product Overview ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 3
2.0 DEVICE PINOUT ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 5
2.1 Lead Descriptions ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 7
3.0 MEMORY MAPS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 10
3.1 Extended Status Registers Memory
Map ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 11
4.0 BUS OPERATIONS, COMMANDS
AND STATUS REGISTER
DEFINITIONS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 12
4.1 Bus Operations for Word-Wide
Mode (BYTEÝeVIH)ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 12
4.2 Bus Operations for Byte-Wide
Mode (BYTEÝeVIL)ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 12
4.3 VE28F008 or M28F008 Compatible
Mode Command Bus Definitions ÀÀÀÀÀ 13
4.4 VS/MS28F016SV-Performance
Enhancement Command Bus
Definitions ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 14
4.5 Compatible Status Register ÀÀÀÀÀÀÀÀÀ 16
4.6 Global Status Register ÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 17
4.7 Block Status Register ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 18
4.8 Device Configuration Code ÀÀÀÀÀÀÀÀÀ 19
CONTENTS PAGE
5.0 ELECTRICAL SPECIFICATIONS ÀÀÀÀÀ 20
5.1 Absolute Maximum Ratings ÀÀÀÀÀÀÀÀÀ 20
5.2 Capacitance ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 21
5.3 Timing Nomenclature ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 22
5.4 DC Characteristics (VCC e3.3V
g0.5V) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 25
5.5 DC Characteristics (VCC e5.0V
g0.5V) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 28
5.6 AC CharacteristicsÐRead Only
Operations ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 31
5.7 Power-Up and Reset Timings ÀÀÀÀÀÀÀ 35
5.8 AC Characteristics for
WEÝÐControlled Command Write
Operations ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 36
5.9 AC Characteristics for
CEÝÐControlled Command Write
Operations ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 39
5.10 AC Characteristics for
WEÝÐControlled Page Buffer Write
Operations ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 42
5.11 AC Characteristics for
CEÝÐControlled Page Buffer Write
Operations ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 44
5.12 Erase and Word/Byte Write
Performance ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 45
6.0 MECHANICAL SPECIFICATIONS ÀÀÀÀ 47
DEVICE NOMENCLATURE ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 48
ADDITIONAL INFORMATION ÀÀÀÀÀÀÀÀÀÀÀÀ 48
DATA SHEET REVISION HISTORY ÀÀÀÀÀÀ 48
2
VS28F016SV, MS28F016SV FlashFileTM Memory
1.0 INTRODUCTION
The documentation of the Intel VS/MS28F016SV
memory device includes this data sheet, a detailed
user’s manual, and a number of application notes,
all of which are referenced at the end of this data
sheet.
The data sheet is intended to give an overview of
the chip feature-set and of the operating AC/DC
specifications. The 28F016SA (compatible with
VS/MS28F016SV) User’s Manual provides com-
plete descriptions of the user modes, system inter-
face examples and detailed descriptions of all princi-
ples of operation. It also contains the full list of
software algorithm flowcharts, and a brief section on
compatibility with the Intel VE28F008 and M28F008.
1.1 Enhanced Features
The VS/MS28F016SV is backwards compatible with
the VE28F008 and M28F008 and offers the follow-
ing enhancements:
#SmartVoltage Technology
Ð Selectable 5.0V or 12.0V VPP
#VPP Level Bit in Block Status Register
#Additional RY/BYÝConfiguration
Ð Pulse-On-Write/Erase
#Additional Upload Device Information Command
Feedback
Ð Device Revision Number
Ð Device Proliferation Code
Ð Device Configuration Code
#x8/x16 Architecture
#Block Locking
#2 Page Buffers
#Instruction Queuing
1.2 Product Overview
The VS/MS28F016SV is a high-performance,
16-Mbit (16,777,216-bit) block erasable, non-volatile
random access memory, organized as either
1 Mword x 16 or 2 Mbyte x 8. The VS/MS28F016SV
includes thirty-two 64-KB (65,536 byte) blocks or
thirty-two 32-KW (32,768 word) blocks. A chip mem-
ory map is shown in Figure 3.
The implementation of a new architecture, with
many enhanced features, will improve the device op-
erating characteristics and result in greater product
reliability and ease of use.
The VS/MS28F016SV incorporates SmartVoltage
technology, providing VCC operation at both 3.3V
and 5.0V and program and erase capability at VPP e
12.0V or 5.0V. Operating at VCC e3.3V, the
VS/MS28F016SV consumes approximately one-half
the power consumption at 5.0V VCC, while 5.0V VCC
provides highest read performance capability. VPP
e5.0V operation eliminates the need for a separate
12.0V converter, while VPP e12.0V maximizes
write/erase performance. In addition to the flexible
program and erase voltages, the dedicated VPP
gives complete code protection with VPP sVPPLK.
Depending on system design specifications, the
VS/MS28F016SV is capable of supporting
Ð 80 ns access times with a VCC of 5.0V g5% and
loading of 30 pF
Ð 85 ns access times with a VCC of 5.0V g10%
and loading of 100 pF
Ð 120 ns access times with a VCC of 3.3V g5%
and loading of 50 pF
A 3/5Ýinput pin configures the device’s internal cir-
cuitry for optimal 3.3V or 5.0V Read/Write operation.
A Command User Interface (CUI) serves as the sys-
tem interface between the microprocessor or micro-
controller and the internal memory operation.
Internal Algorithm Automation allows Byte/Word
Writes and Block Erase operations to be executed
using a Two-Write command sequence to the CUI in
the same way as the VE28F008 or M28F008 8-Mbit
FlashFile memory.
A super-set of commands has been added to the
basic VE28F008 or M28F008 command-set to
achieve higher write performance and provide addi-
tional capabilities. These new commands and fea-
tures include:
#Page Buffer Writes to Flash
#Command Queuing Capability
#Automatic Data Writes during Erase
#Software Locking of Memory Blocks
#Two-Byte Successive Writes in 8-bit Systems
#Erase All Unlocked Blocks
3
VS28F016SV, MS28F016SV FlashFileTM Memory
Writing of memory data is performed in either byte or
word increments typically within 6 msec (12.0V VPP)
ba 33% improvement over the VE28F008 or
M28F008. A Block Erase operation erases one of
the 32 blocks in about 1.0 sec (12.0V VPP), indepen-
dent of the other blocks, which is about a 65% im-
provement over the VE28F008 or M28F008.
Each block can be written and erased a minimum of
100,000 cycles. Systems can achieve one million
Block Erase Cycles by providing wear-leveling algo-
rithms and graceful block retirement. These tech-
niques have already been employed in many flash
file systems and hard disk drive designs.
The VS/MS28F016SV incorporates two Page Buff-
ers of 256 bytes (128 words) each to allow page
data writes. This feature can improve a system write
performance by up to 4.8 times over previous flash
memory devices, which have no Page Buffers.
All operations are started by a sequence of Write
commands to the device. Three Status Registers
(described in detail later in this data sheet) and a
RY/BYÝoutput pin provide information on the prog-
ress of the requested operation.
While the VE28F008 or M28F008 requires an opera-
tion to complete before the next operation can be
requested, the VS/MS28F016SV allows queuing of
the next operation while the memory executes the
current operation. This eliminates system overhead
when writing several bytes in a row to the array or
erasing several blocks at the same time. The
VS/MS28F016SV can also perform Write operations
to one block of memory while performing Erase of
another block.
The VS/MS28F016SV provides selectable block
locking to protect code or data such as Device Driv-
ers, PCMCIA card information, ROM-Executable
O/S or Application Code. Each block has an associ-
ated non-volatile lock-bit which determines the
lock status of the block. In addition, the
VS/MS28F016SV has a master Write Protect pin
(WPÝ) which prevents any modifications to memory
blocks whose lock-bits are set.
The VS/MS28F016SV contains three types of
Status Registers to accomplish various functions:
#A Compatible Status Register (CSR) which is
100% compatible with the VE28F008 or
M28F008 FlashFile memory Status Register. The
CSR, when used alone, provides a straightfor-
ward upgrade capability to the VS/MS28F016SV
from a VE28F008- or M28F008-based design.
#A Global Status Register (GSR) which informs
the system of command Queue status, Page
Buffer status, and overall Write State Machine
(WSM) status.
#32 Block Status Registers (BSRs) which provide
block-specific status information such as the
block lock-bit status.
The GSR and BSR memory maps for Byte-Wide and
Word-Wide modes are shown in Figures 4 and 5.
The VS/MS28F016SV incorporates an open drain
RY/BYÝoutput pin. This feature allows the user to
OR-tie many RY/BYÝpins together in a multiple
memory configuration such as a Resident Flash Ar-
ray.
Other configurations of the RY/BYÝpin are en-
abled via special CUI commands and are described
in detail in the 16-Mbit Flash Product Family User’s
Manual.
The VS/MS28F016SV’s Upload Device Information
command is enhanced compared to the VE28F008
or M28F008, providing access to additional device
information. This command uploads the Device Re-
vision Number, Device Proliferation Code and De-
vice Configuration Code. The Device Proliferation
Code for the VS/MS28F016SV is 01H, and the De-
vice Configuration Code identifies the current
RY/BYÝconfiguration. Section 4.4 documents the
exact page buffer address locations for all uploaded
information. A subsequent Page Buffer Swap and
Page Buffer Read command sequence is necessary
to read the correct device information.
The VS/MS28F016SV also incorporates a dual chip-
enable function with two input pins, CE0Ýand
CE1Ý. These pins have exactly the same functional-
ity as the regular chip-enable pin, CEÝ,onthe
VE28F008 or M28F008. For minimum chip designs,
CE1Ýmay be tied to ground and system logic may
use CE0Ýas the chip enable input. The
VS/MS28F016SV uses the logical combination of
these two signals to enable or disable the entire
chip. Both CE0Ýand CE1Ýmust be active low to
enable the device. If either one becomes inactive,
the chip will be disabled. This feature, along with the
open drain RY/BYÝpin, allows the system designer
to reduce the number of control pins used in a large
array of 16-Mbit devices.
The BYTEÝpin allows either x8 or x16 read/writes
to the VS/MS28F016SV. BYTEÝat logic low se-
lects 8-bit mode with address A0selecting between
low byte and high byte. On the other hand, BYTEÝ
4
VS28F016SV, MS28F016SV FlashFileTM Memory
at logic high enables 16-bit operation with address
A1becoming the lowest order address and address
A0is not used (don’t care). A device block diagram
is shown in Figure 1.
The VS/MS28F016SV is specified for a maximum
access time of 80 ns (tACC) at 5.0V operation (4.75V
to 5.25V) in either the SE1 or SE2 grades. A corre-
sponding maximum access time of 120 ns at 3.3V
(3.15V to 3.45V) is achieved for reduced power con-
sumption applications.
The VS/MS28F016SV incorporates an Automatic
Power Saving (APS) feature which substantially re-
duces the active current when the device is in static
mode of operation (addresses not switching). In APS
mode, the typical ICC current is 1 mA at 5.0V (0.8 mA
at 3.3V).
A deep power-down mode of operation is invoked
when the RPÝ(called PWDÝon the VE28F008 or
M28F008) pin transitions low. This mode brings the
device power consumption to less than 30.0 mA, typ-
ically, and provides additional write protection by
acting as a device reset pin during power transitions.
A reset time of 500 ns (5.0V VCC operation) is re-
quired from RPÝswitching high until outputs are
again valid. In the Deep Power-Down state, the
WSM is reset (any current operation will abort) and
the CSR, GSR and BSR registers are cleared.
A CMOS standby mode of operation is enabled
when either CE0Ýor CE1Ýtransitions high and
RPÝstays high with all input control pins at CMOS
levels. In this mode, the device typically draws an
ICC standby current of 70 mAat5VV
CC.
2.0 DEVICE PINOUT
The VS/MS28F016SV 56L-SSOP pinout configura-
tion is shown in Figure 2.
5
VS28F016SV, MS28F016SV FlashFileTM Memory
271312–21
Figure 1. Block Diagram
6
VS28F016SV, MS28F016SV FlashFileTM Memory
2.1 Lead Descriptions
Symbol Type Name and Function
A0INPUT BYTE-SELECT ADDRESS: Selects between high and low byte when
device is in x8 mode. This address is latched in x8 Data Writes. Not
used in x16 mode (i.e., the A0input buffer is turned off when BYTEÝ
is high).
A1-A
15 INPUT WORD-SELECT ADDRESSES: Select a word within one 64-Kbyte
block. A6-15 selects 1 of 1024 rows, and A1-5 selects 16 of 512
columns. These addresses are latched during Data Writes.
A16 -A
20 INPUT BLOCK-SELECT ADDRESSES: Select 1 of 32 Erase blocks. These
addresses are latched during Data Writes, Erase and Lock-Block
operations.
DQ0-DQ
7INPUT/OUTPUT LOW-BYTE DATA BUS: Inputs data and commands during CUI write
cycles. Outputs array, buffer, identifier or status data in the
appropriate read mode. Floated when the chip is de-selected or the
outputs are disabled.
DQ8-DQ
15 INPUT/OUTPUT HIGH-BYTE DATA BUS: Inputs data during x16 Data-Write
operations. Outputs array, buffer or identifier data in the appropriate
read mode; not used for Status Register reads. Floated when the
chip is de-selected or the outputs are disabled.
CE0Ý,CE
1
ÝINPUT CHIP ENABLE INPUTS: Activate the device’s control logic, input
buffers, decoders and sense amplifiers. With either CE0Ýor CE1Ý
high, the device is de-selected and power consumption reduces to
standby levels upon completion of any current Data-Write or Erase
operations. Both CE0Ý,CE
1
Ýmust be low to select the device.
All timing specifications are the same for both signals. Device
Selection occurs with the latter falling edge of CE0Ýor CE1Ý. The
first rising edge of CE0Ýor CE1Ýdisables the device.
RPÝINPUT RESET/POWER-DOWN: RPÝlow places the device in a Deep
Power-Down state. All circuits that consume static power, even those
circuits enabled in standby mode, are turned off. When returning from
Deep Power-Down, a recovery time of tPHQV at 5.0V VCC is required
to allow these circuits to power-up.
When RPÝgoes low, any current or pending WSM operation(s) are
terminated, and the device is reset. All Status Registers return to
ready (with all status flags cleared).
Exit from Deep Power-Down places the device in read array mode.
OEÝINPUT OUTPUT ENABLE: Gates device data through the output buffers
when low. The outputs float to tri-state off when OEÝis high.
NOTE:
CExÝoverrides OEÝ, and OEÝoverrides WEÝ.
WEÝINPUT WRITE ENABLE: Controls access to the CUI, Page Buffers, Data
Queue Registers and Address Queue Latches. WEÝis active low,
and latches both address and data (command or array) on its rising
edge. Page Buffer addresses are latched on the falling edge of WEÝ.
7
VS28F016SV, MS28F016SV FlashFileTM Memory
2.1 Lead Descriptions (Continued)
Symbol Type Name and Function
RY/BYÝOPEN DRAIN READY/BUSY: Indicates status of the internal WSM. When low, it indicates
that the WSM is busy performing an operation. RY/BYÝfloating indicates
OUTPUT
that the WSM is ready for new operations (or WSM has completed all
pending operations), or erase is suspended, or the device is in deep power-
down mode. This output is always active (i.e., not floated to tri-state off when
OEÝor CE0Ý,CE
1
Ýare high), except if a RY/BYÝPin Disable command
is issued.
WPÝINPUT WRITE PROTECT: Erase blocks can be locked by writing a nonvolatile lock-
bit for each block. When WPÝis low, those locked blocks as reflected by
the Block-Lock Status bits (BSR.6), are protected from inadvertent data
writes or erases. When WPÝis high, all blocks can be written or erased
regardless of the state ot the lock-bits. The WPÝinput buffer is disabled
when RPÝtransitions low (deep power-down mode).
BYTEÝINPUT BYTE ENABLE: BYTEÝlow places device in x8 mode. All data is then input
or output on DQ0–7, and DQ8–15 float. Address A0selects between the high
and low byte. BYTEÝhigh places the device in x16 mode, and turns off the
A0input buffer. Address A1, then becomes the lowest order address.
3/5ÝINPUT 3.3/5.0 VOLT SELECT: 3/5Ýhigh configures internal circuits for 3.3V
operation. 3/5Ýlow configures internal circuits for 5.0V operation.
NOTE:
Reading the array with 3/5Ýhigh in a 5.0V system could damage the
device. Reference the power-up and reset timings (Section 5.7) for 3/5Ý
switching delay to valid data.
VPP SUPPLY WRITE/ERASE POWER SUPPLY (12.0V g0.6V, 5.0V g0.5V): For erasing
memory array blocks or writing words/bytes/pages into the flash array. VPP
e5.0V g0.5V eliminates the need for a 12V converter, while connection to
1 2.0V g0.6V maximizes Write/Erase Performance.
NOTE:
Successful completion of write and erase attempts is inhibited with VPP at or
below 1.5V. Write and erase attempts with VPP between 1.5V and 4.5V,
between 5.5V and 11.4V, and above 12.6V produce spurious results and
should not be attempted.
VCC SUPPLY DEVICE POWER SUPPLY (3.3V g0.45V, 5.0V g0.5V, 5.0 g0.25V): To
switch 3.3V to 5.0V (or vice versa), first ramp VCC down to GND, and then
power to the new VCC voltage.
Do not leave any power pins floating.
GND SUPPLY GROUND FOR ALL INTERNAL CIRCUITRY: Do not leave any ground pins
floating.
NC NO CONNECT: Lead may be driven or left floating.
8
VS28F016SV, MS28F016SV FlashFileTM Memory
271312–2
24mm x 13.5mm 0.8mm Lead Pitch
Top View
NOTE:
56-Lead SSOP Mechanical Diagrams and dimensions are shown at the end of this data sheet.
Figure 2. SSOP Pinout Configuration
9
VS28F016SV, MS28F016SV FlashFileTM Memory
3.0 MEMORY MAPS
271312–3
Figure 3. VS/MS28F016SV Memory Maps (Byte-Wide and Word-Wide Modes)
10
VS28F016SV, MS28F016SV FlashFileTM Memory
3.1 Extended Status Registers Memory Map
271312–4
Figure 4. Extended Status Register Memory Map
(Byte-Wide Mode)
271312–5
Figure 5. Extended Status Register Memory Map
(Word-Wide Mode)
11
VS28F016SV, MS28F016SV FlashFileTM Memory
4.0 BUS OPERATIONS, COMMANDS AND STATUS REGISTER DEFINITIONS
4.1 Bus Operations for Word-Wide Mode (BYTEÝeVIH)
Mode Notes RPÝCE1ÝCE0ÝOEÝWEÝA1DQ0-15 RY/BYÝ
Read 1,2,7 VIH VIL VIL VIL VIH XD
OUT X
Output Disable 1,6,7 VIH VIL VIL VIH VIH X High Z X
Standby 1,6,7 VIH VIL VIH X X X High Z X
VIH VIL
VIH VIH
Deep Power-Down 1,3 VIL X X X X X High Z VOH
Manufacturer ID 4 VIH VIL VIL VIL VIH VIL 0089H VOH
Device ID 4 VIH VIL VIL VIL VIH VIH 66A0H VOH
Write 1,5,6 VIH VIL VIL VIH VIL XD
IN X
4.2 Bus Operations for Byte-Wide Mode (BYTEÝeVIL)
Mode Notes RPÝCE1ÝCE0ÝOEÝWEÝA0DQ0-7 RY/BYÝ
Read 1,2,7 VIH VIL VIL VIL VIH XD
OUT X
Output Disable 1,6,7 VIH VIL VIL VIH VIH X High Z X
Standby 1,6,7 VIH VIL VIH X X X High Z X
VIH VIL
VIH VIH
Deep Power-Down 1,3 VIL X X X X X High Z VOH
Manufacturer ID 4 VIH VIL VIL VIL VIH VIL 89H VOH
Device ID 4 VIH VIL VIL VIL VIH VIH A0H VOH
Write 1,5,6 VIH VIL VIL VIH VIL XD
IN X
NOTES:
1. X can be VIH or VIL for address or control pins except for RY/BYÝ, which is either VOL or VOH.
2. RY/BYÝoutput is open drain. When the WSM is ready, Erase is suspended or the device is in deep power-down mode.
RY/BYÝwill be at VOH if it is tied to VCC through a resistor. RY/BYÝat VOH is independent of OEÝwhile a WSM
operation is in progress.
3. RPÝat GND g0.2V ensures the lowest deep power-down current.
4. A0and A1at VIL provide device manufacturer codes in x8 and x16 modes respectively. A0and A1at VIH provide device
ID codes in x8 and x16 modes respectively. All other addresses are set to zero.
5. Commands for Erase, Data Write, or Lock-Block operations can only be completed successfully when VPP eVPPH1or
VPP eVPPH2.
6. While the WSM is running, RY/BYÝin level-mode (default) stays at VOL until all operations are complete. RY/BYÝgoes
to VOH when the WSM is not busy or in erase suspend mode.
7. RY/BYÝmay be at VOL while the WSM is busy performing various operations. For example, a Status Register read
during a Write operation.
12
VS28F016SV, MS28F016SV FlashFileTM Memory
4.3 VE28F008 and M28F008 Compatible Mode Command Bus Definitions
Command Notes First Bus Cycle Second Bus Cycle
Oper Addr Data(4) Oper Addr Data(4)
Read Array Write X xxFFH Read AA AD
Intelligent Identiier 1 Write X xx90H Read IA ID
Read Compatible Status Register 2 Write X xx70H Read X CSRD
Clear Status Register 3 Write X xx50H
Word/Byte Write Write X xx40H Write WA WD
Alternate Word/Byte Write Write X xx10H Write WA WD
Block Erase/Confirm Write X xx20H Write BA xxD0H
Erase Suspend/Resume Write X xxB0H Write X xxD0H
ADDRESS DATA
AA eArray Address AD eArray Data
BA eBlock Address CSRD eCSR Data
IA eldentitier Address ID eIdentifier Data
WA eWrite Address WD eWrite Data
XeDon’t Care
NOTES:
1. Following the Intelligent Identifier command, two Read operations access the manutacturer and device signature codes.
2. The CSR is automatically available after device enters data write, erase, or suspend operations.
3. Clears CSR.3, CSR.4 and CSR.5. Also clears GSR.5 and all BSR.5, BSR.4 and BSR.2 bits. See Status Register defini-
tions.
4. The upper byte of the data bus (DQ8–15) during command writes is a ‘‘Don’t Care’’ in x16 operation of the device.
13
VS28F016SV, MS28F016SV FlashFileTM Memory
4.4 VS/MS28F016SVÐPerformance Enhancement Command Bus Definitions
Command Mode Notes First Bus Cycle Second Bus Cycle Third Bus Cycle
Oper Addr Data(13) Oper Addr Data(13) Oper Addr Data
Read Extended 1 Write X xx71H Read RA GSRD
Status Register BSRD
Page Buffer Swap 7 Write X xx72H
Read Page Buffer Write X xx75H Read PA PD
Single Load to Write X xx74H Write PA PD
Page Buffer
Sequential Load to x8 4,6,10 Write X xxE0H Write X BCL Write X BCH
Page Buffer x16 4,5,6,10 Write X xxE0H Write X WCL Write X WCH
Page Buffer Write x8 3,4,9,10 Write X xx0CH Write A0BC(L,H) Write WA BC(H,L)
to Flash x16 4,5,10 Write X xx0CH Write X WCL Write WA WCH
Two-Byte Write x8 3 Write X xxFBH Write A0WD(L,H) Write WA WD(H,L)
Lock Block/ Write X xx77H Write BA xxD0H
Confirm
Upload Status 2 Write X xx97H Write X xxD0H
Bits/Confirm
Upload Device 11 Write X xx99H Write X xxD0H
Information/
Confirm
Erase All Unlocked Write X xxA7H Write X xxD0H
Blocks/Confirm
RY/BYÝEnable to 8 Write X xx96H Write X xx01H
Level-Mode
RY/BYÝPulse- 8 Write X xx96H Write X xx02H
On-Write
RY/BYÝPulse- 8 Write X xx96H Write X xx03H
On-Erase
RY/BYÝDisable 8 Write X xx96H Write X xx04H
RY/BYÝPulse- 8 Write X xx96H Write X xx05H
On-Write/Erase
Sleep 12 Write X xxF0H
Abort Write X xx80H
ADDRESS
BA eBlock Address
PA ePage Butter Address
RA eExtended Register Address
WA eWrite Address
XeDon’t Care
DATA
AD eArray Data
PD ePage Buffer Data
BSRD eBSR Data
GSRD eGSR Data
WC (L,H) eWord Count (Low, High)
BC (L,H) eByte Count (Low, High)
WD (L,H) eWrite Data (Low, High)
14
VS28F016SV, MS28F016SV FlashFileTM Memory
NOTES:
1. RA can be the GSR address or any BSR address. See Figures 4 and 5 for Extended Status Register memory maps.
2. Upon device power-up, all BSR lock-bits come up locked. The Upload Status Bits command must be written to reflect the
actual lock-bit status.
3. A0is automatically complemented to load second byte of data. BYTEÝmust be at VIL.A
0value determines which
WD/BC is supplied first: A0e0 looks at the WDL/BCL, A0e1 looks at the WDH/BCH.
4. BCH/WCH must be at 00H for this product because of the 256-byte (128-word) Page Buffer size, and to avoid writing the
Page Buffer contents to more than one 256-byte segment within an array block. They are simply shown for future Page
Buffer expandability.
5. In x16 mode, only the lower byte DQ0-7 is used for WCL and WCH. The upper byte DQ8-15 is a don’t care.
6. PA and PD (whose count is given in cycles 2 and 3) are supplied starting in the fourth cycle, which is not shown.
7. This command allows the user to swap between available Page Buffers (0 or 1).
8. These commands reconfigure RY/BYÝoutput to one of two pulse-modes or enable and disable the RY/BYÝfunction.
9. Write address, WA, is the Destination address in the flash array which must match the Source address in the Page Buffer.
Refer to the 16-Mbit Flash Product Family User’s Manual.
10. BCL e00H corresponds to a byte count of 1. Similarly, WCL e00H corresponds to a word count of 1.
11. After writing the Upload Device Information command and the Confirm command, the following information is output at
Page Buffer addresses specified below:
Address Information
06H, 07H (Byte Mode) Device Revision Number
03H (Word Mode) Device Revision Number
1EH (Byte Mode) Device Configuration Code
0FH (DQ0–7) (Word Mode) Device Configuration Code
1FH (Byte Mode) Device Proliferation Code (01H)
0FH (DQ8–15) (Word Mode) Device Proliferation Code (01H)
A page buffer swap followed by a page buffer read sequence is necessary to access this information. The contents of
all other Page Buffer locations, after the Upload Device Information command is written, are reserved for future imple-
mentation by Intel Corporation. See Section 4.8 for a description of the Device Configuration Code. This code also
corresponds to data written to the 28F016SV after writing the RY/BYÝReconfiguration command.
12. To ensure that the 28F0165V’s power consumption during Sleep Mode reaches the deep power-down current level, the
system also needs to de-select the chip by taking either or both CE0Ýor CE1Ýhigh.
13. The upper byte of the data bus (DQ8–15) during command wntes is a Don’t Care in x16 operation of the device.
15
VS28F016SV, MS28F016SV FlashFileTM Memory
4.5 Compatible Status Register
WSMS ESS ES DWS VPPS R R R
76543210
NOTES:
CSR.7 eWRITE STATE MACHINE STATUS RY/BYÝoutput or WSMS bit must be checked to
determine completion of an operation (Erase, Erase
1eReady
Suspend, or Data Write) before the appropriate Status bit
0eBusy (ESS, ES or DWS) is checked for success.
CSR.6 eERASE-SUSPEND STATUS
1eErase Suspended
0eErase In Progress/Completed
CSR.5 eERASE STATUS If DWS and ES are set to ‘‘1’’ during an erase attempt, an
improper command sequence was entered. Clear the
1eError In Block Erasure
CSR and attempt the operation again.
0eSuccessful Block Erase
CSR.4 eDATA-WRITE STATUS
1eError in Data Write
0eData Write Successful
CSR.3 eVPP STATUS The VPPS bit, unlike an A/D converter, does not provide
continuous indication of VPP level. The WSM interrogates
1eVPP Error Detect, Operation Abort
VPP’s level only after the Data-Write or Erase command
0eVPP OK sequences have been entered, and informs the system if
VPP has not been switched on. VPPS is not guaranteed to
report accurate feedback between VPPLK(max) and
VPPH1(min) and between VPPH1(max) and VPPH2(min)
and above VPPH2(max).
CSR.2-0 eRESERVED FOR FUTURE ENHANCEMENTS
These bits are reserved for future use; mask them out when polling the CSR.
16
VS28F016SV, MS28F016SV FlashFileTM Memory
4.6 Global Status Register
WSMS OSS DOS DSS QS PBAS PBS PBSS
76543210
NOTES:
GSR.7 eWRITE STATE MACHINE STATUS [1]RY/BYÝoutput or WSMS bit must be checked to
determine completion of an operation (Block Lock,
1eReady
Suspend, any RY/BYÝreconfiguration, Upload Status
0eBusy Bits, Erase or Data Write) before the appropriate Status
bit (OSS or DOS) is checked for success.
GSR.6 eOPERATION SUSPEND STATUS
1eOperation Suspended
0eOperation in Progress/Completed
GSR.5 eDEVICE OPERATION STATUS
1eOperation Unsuccessful
0eOperation Successful or Currently
Running
GSR.4 eDEVICE SLEEP STATUS
1eDevice in Sleep
0eDevice Not in Sleep
MATRIX 5/4
00eOperation Successful or Currently If operation currently running, then GSR.7 e0.
Running
01eDevice in Sleep mode or Pending If device pending sleep, then GSR.7 e0.
Sleep
10eOperation Unsuccessful
11eOperation Unsuccessful or Aborted Operation aborted: Unsuccessful due to Abort
command.
GSR.3 eQUEUE STATUS
1eQueue Full
0eQueue Available
GSR.2 ePAGE BUFFER AVAILABLE STATUS
1eOne or Two Page Buffers Available The device contains two Page Buffers.
0eNo Page Buffer Available
GSR.1 ePAGE BUFFER STATUS
1eSelected Page Buffer Ready
0eSelected Page Buffer Busy Selected Page Buffer is currently busy with WSM
operation
GSR.0 ePAGE BUFFER SELECT STATUS
1ePage Buffer 1 Selected
0ePage Buffer 0 Selected
NOTE:
1. When multiple operations are queued, checking BSR.7 only provides indication of completion for that particular block.
GSR.7 provides indication when all queued operations are completed.
17
VS28F016SV, MS28F016SV FlashFileTM Memory
4.7 Block Status Register
BS BLS BOS BOAS QS VPPS VPPL R
76 5 4 3 2 10
NOTES:
BSR.7 eBLOCK STATUS [1]RY/BYÝoutput or BS bit must be checked to
determine completion of an operation (Block Lock,
1eReady
Suspend, Erase or Data Write) before the appropriate
0eBusy Status bits (BOS, BLS) is checked for success.
BSR.6 eBLOCK LOCK STATUS
1eBlock Unlocked for Write/Erase
0eBlock Locked for Write/Erase
BSR.5 eBLOCK OPERATION STATUS
1eOperation Unsuccessful
0eOperation Successful or
Currently Running
BSR.4 eBLOCK OPERATION ABORT STATUS
1eOperation Aborted The BOAS bit will not be set until BSR.7 e1.
0eOperation Not Aborted
MATRIX 5/4
00eOperation Successful or
Currently Running
01eNot a Valid Combination
10eOperation Unsuccessful
11eOperation Aborted Operation halted via Abort command.
BSR.3 eQUEUE STATUS
1eQueue Full
0eQueue Available
BSR.2 eVPP STATUS
1eVPP Error Detect, Operation Abort
0eVPP OK
BSR.1 eVPP LEVEL BSR.1 is not guaranteed to report accurate feedback
between the VPPH1 and VPPH2 voltage ranges. Writes
1eVPP Detected at 5.0V g10%
and erases with VPP between VPPLK(max) and VPPH1
0eVPP Detected at 12.0V g5% (min), between VPPH1(max) and VPPH2(min), and
above VPPH2(max) produce spurious results and
should not be attempted. BSR.1 was a RESERVED bit
on the 28F016SA.
BSR.0 eRESERVED FOR FUTURE ENHANCEMENTS
This bit is reserved for future use; mask it out when polling the BSRs.
NOTE:
1. When multiple operations are queued, checking BSR.7 only provides indication of completion for that particular block.
GSR.7 provides indication when all queued operations are completed.
18
VS28F016SV, MS28F016SV FlashFileTM Memory
4.8 Device Configuration Code
R R R R R RB2 RB1 RB0
76543 2 1 0
NOTES:
DCC.2-DCC.0 eRY/BYÝCONFIGURATION (RB2-RB0) Undocumented combinations of RB2-RB0
are reserved by Intel Corporation for future
001 eLevel Mode (Default)
implementations and should not be used.
010 ePulse-On-Write
011 ePulse-On-Erase
100 eRY/BYÝDisabled
101 ePulse-On-Write/Erase
DCC.7-DCC.3 eRESERVED FOR FUTURE ENHANCEMENTS
These bits are reserved for future use; mask them out when reading the Device Configuration Code.
Set these bits to ‘‘0’’ when writing the desired RY/BYÝconfiguration to the device.
19
VS28F016SV, MS28F016SV FlashFileTM Memory
5.0 ELECTRICAL SPECIFICATIONS
5.1 Absolute Maximum Ratings*
Temperature Under Bias
ÐSE1 ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀb55§Ctoa
125§C
ÐSE2 ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀb40§Ctoa
125§C
Storage Temperature ÀÀÀÀÀÀÀÀÀÀÀÀb65§to a125§C
NOTICE: This data sheet contains information on
products in the sampling and initial production phases
of development. The specifications are subject to
change without notice. Verify with your local Intel
Sales office that you have the latest data sheet be-
fore finalizing a design.
*
WARNING: Stressing the device beyond the ‘‘Absolute
Maximum Ratings’’ may cause permanent damage.
These are stress ratings only. Operation beyond the
‘‘Operating Conditions’’ is not recommended and ex-
tended exposure beyond the ‘‘Operating Conditions’’
may affect device reliability.
VCC e3.3V g0.15V Systems(4)
Sym Parameter Notes Min Max Units Test Conditions
TCSE2 Operating Temperature, SE2 b40 a125 §C
TCSE1 Operating Temperature, SE1 b55 a125 §C
VCC VCC with Respect to GND 1 b0.2 7.0 V
VPP VPP Supply Voltage with Respect to GND 1,2 b0.2 14.0 V
V Voltage on any Pin (except VCC,VPP) with 1,5 b0.5 VCC V
Respect to GND a0.5
I Current into any Non-Supply Pin 5 g30 mA
IOUT Output Short Circuit Current 3 100 mA
VCC e5.0V g0.5V, VCC e5.0V g0.25V Systems(4, 5)
Sym Parameter Notes Min Max Units Test Conditions
TCSE2 Operating Temperature, SE2 b40 a125 §C
TCSE1 Operating Temperature, SE1 b55 a125 §C
VCC VCC with Respect to GND 1 b0.2 7.0 V
VPP VPP Supply Voltage with Respect to GND 1,2 b0.2 14.0 V
V Voltage on any Pin (except VCC,VPP) with 1,5 b2.0 7.0 V
Respect to GND
I Current into any Non-Supply Pin 5 g30 mA
IOUT Output Short Circuit Current 3 100 mA
NOTES:
1. Minimum DC voltage is b0.5V on input/output pins. During transitions, this level may undershoot to b2.0V for periods
k20 ns. Maximum DC voltage on input/output pins is VCC a0.5V which, during transitions, may overshoot to VCC a2.0V
for periods k20 ns.
2. Maximum DC voltage on VPP may overshoot to a14.0V for periods k20 ns.
3. Output shorted for no more than one second. No more than one output shorted at a time.
4. AC specifications are valid at both voltage ranges. See DC Characteristics tables for voltage range-specific specifications.
5. This specification also applies to pin marked ‘‘NC’’.
6. 5% VCC specifications refer to the VS/MS28F016SV-80 in its high speed test configuration.
20
VS28F016SV, MS28F016SV FlashFileTM Memory
5.2 Capacitance
For a 3.3V g0.15V System:
Sym Parameter Notes Typ Max Units Test Conditions
CIN Capacitance Looking into an 1 6 8 pF TAe25§C, f e1.0 MHz
Address/Control Pin
COUT Capacitance Looking into an 1 8 12 pF TAe25§C, f e1.0 MHz
Output Pin
CLOAD Load Capacitance Driven by 1,2 50 pF For VCC e3.3V g0.15V
Outputs for Timing Specifications
Equivalent Load Timing Circuit 2.5 ns 50Xtransmission line
delay
For a 5.0V System:
Sym Parameter Notes Typ Max Units Test Conditions
CIN Capacitance Looking into an 1 6 8 pF TAe25§C, f e1.0 MHz
Address/Control Pin
COUT Capacitance Looking into an 1 8 12 pF TAe25§C, f e1.0 MHz
Output Pin
CLOAD Load Capacitance Driven by 1,2 100 pF For VCC e5.0V g0.5V
Outputs for Timing Specifications 30 pF For VCC e5.0V g0.25V
Equivalent Testing Load Circuit for 2.5 ns 25Xtransmission line
VCC g10% delay
Equivalent Testing Load Circuit for 2.5 ns 85Xtransmission line
VCC g5% delay
NOTES:
1. Sampled, not 100% tested. Guaranteed by design.
2. To obtain iBIS models for the VS/MS28F016SV, please contact your local Intel/Distribution Sales Office.
21
VS28F016SV, MS28F016SV FlashFileTM Memory
5.3 Timing Nomenclature
All 3.3V system timings are measured from where
signals cross 1.5V.
For 5.0V systems use the standard JEDEC cross
point definitions.
Each timing parameter consists of 5 characters.
Some common examples are defined as follows:
tCE tELQV time(t) from CEÝ(E) going low (L)
to the outputs (Q) becoming valid (V)
tOE tGLQV time(t) from OE Ý(G) going low (L)
to the outputs (Q) becoming valid (V)
tACC tAVQV time(t) from address (A) valid (V) to
the outputs (Q) becoming valid (V)
tAS tAVWH time(t) from address (A) valid (V) to
WEÝ(W) going high (H)
tDH tWHDX time(t) from WEÝ(W) going high
(H) to when the data (D) can become un-
defined (X)
Pin Characters Pin States
A Address Inputs H High
D Data Inputs L Low
Q Data Outputs V Valid
ECE
Ý
(Chip Enable) X Driven, but not Necessarily Valid
F BYTEÝ(Byte Enable) Z High Impedance
GOE
Ý
(Output Enable)
WWE
Ý
(Write Enable)
PRP
Ý
(Deep Power-Down Pin)
R RY/BYÝ(Ready Busy)
V Any Voltage Level
Y 3/5ÝPin
5V VCC at 4.5V Minimum
3V VCC at 3.15V Minimum
22
VS28F016SV, MS28F016SV FlashFileTM Memory
271312–6
AC test inputs are driven at VOH (2.4 VTTL) for a Logic ‘‘1’’ and VOL (0.45 VTTL) for a Logic ‘‘0.’’ Input timing begins at
VIH (2.0 VTTL) and VIL (0.8 VTTL). Output timing ends at VIH and VIL. Input rise and fall times (10% to 90%) k10 ns.
Figure 6. Transient Input/Output Reference Waveform for
VCC e5.0V g10% (Standard Testing Configuration)
271312–7
AC test inputs are driven at 3.15V for a Logic ‘‘1’’ and 0.0V for a Logic ‘‘0.’’ Input timing begins, and output timing ends,
at 1.5V. Input rise and fall times (10% to 90%) k10 ns.
Figure 7. Transient Input/Output Reference Waveform (VCC e3.3V g0.15V)
High Speed Reference Waveform (VCC e5.0V g5%)
NOTE:
1. Testing characteristics for VS/MS28F016SV-085 (Standard Testing Configuration) and VS/MS28F016SV-100.
23
VS28F016SV, MS28F016SV FlashFileTM Memory
2.5 ns of 25XTransmission Line
Total Capacitance e100 pF
271312–8
Figure 8. Transient Equivalent Testing Load Circuit (VCC e5.0V g10%)
2.5 ns of 50XTransmission Line
Total Capacitance e50 pF
271312–9
Figure 9. Transient Equivalent Testing Load Circuit (VCC e3.3V g0.15V)
2.5 ns of 83XTransmission Line
Total Capacitance e30 pF
271312–10
Figure 10. High Speed Transient Equivalent Testing Load Circuit (VCC e5.0V g5%)
24
VS28F016SV, MS28F016SV FlashFileTM Memory
5.4 DC Characteristics
VCC e3.3V g0.15V, TCSE2 eb
40§Ctoa
125§C, TCSE1 eb
55§Ctoa
125§C
Sym Parameter Notes Min Max Units Test Conditions
ILI Input Load Current 1 g1mAV
CC eVCC Max,
VIN eVCC or GND
ILO Output Leakage Current 1 g10 mAV
CC eVCC Max,
VOUT eVCC or GND
ICCS VCC Standby 1,5 130 mAV
CC eVCC Max,
Current CE0Ý,CE
1
Ý
,RP
ÝeV
CC
g0.2V
BYTEÝ,WP
Ý
, 3/5ÝeVCC
g0.2V or GND g0.2V
4mAV
CC eVCC Max,
CE0Ý,CE
1
Ý
,RP
ÝeV
IH
BYTEÝ,WP
Ý
, 3/5ÝeVIH or VIL
ICCD VCC Deep Power- 1 50 mARP
Ý
e
GND g0.2V
Down Current BYTEÝeVCC g0.2V or
GND g0.2V
ICCR1V
CC Read Current 1,4,5 60 mA VCC eVCC Max
CMOS: CE0Ý,CE
1
ÝeGND
g0.2V
BYTEÝeGND g0.2V or
VCC g0.2V
Inputs eGND g0.2V or
VCC g0.2V
TTL: CE0Ý,CE
1
ÝeV
IL,
BYTEÝeVIL or VIH
INPUTS eVIL or VIH,
fe8 MHz, IOUT e0mA
I
CCR2V
CC Read Current 1,4,5,6 40 mA VCC eVCC Max
CMOS: CE0Ý,CE
1
ÝeGND
g0.2V
BYTEÝeGND g0.2V or
VCC g0.2V
Inputs eGND g0.2V or
VCC g0.2V
TTL: CE0Ý,CE
1
ÝeV
IL,
BYTEÝeVIL or VIH
INPUTS eVIL or VIH,
fe4 MHz, IOUT e0mA
25
VS28F016SV, MS28F016SV FlashFileTM Memory
5.4 DC Characteristics (Continued)
VCC e3.3V g0.3V, TCSE2 eb
40§Ctoa
125§C, TCSE1 eb
55§Ctoa
125§C
Sym Parameter Notes Min Max Units Test Conditions
ICCW VCC Write Current 1,6 12 mA Word/Byte Write in Progress
VPP e12.0V g5%
17 mA Word/Byte Write in Progress
VPP e5.0V g10%
ICCE VCC Block Erase 1,6 12 mA Block Erase in Progress
Current VPP e12.0V g5%
17 mA Block Erase in Progress
VPP e5.0V g10%
ICCES VCC Erase 1,2 6 mA CE0Ý,CE
1
ÝeV
IH
Suspend Current Block Erase Suspended
IPPS VPP Standby/Read 1 g100 mAV
PP sVCC
IPPR Current 200 mAV
PP lVCC
IPPD VPP Deep Power- 1 50 mARP
Ý
e
GND g0.2V
Down Current
IPPW VPP Write Current 1 15 mA VPP e12.0V g5%
Word/Byte Write in Progress
25 mA VPP e5.0V g10%
Word/Byte Write in Progress
IPPE VPP Erase Current 1 10 mA VPP e12.0V g5%
Block Erase in Progress
20 mA VPP e5.0V g10%
Block Erase in Progress
IPPES VPP Erase 1 200 mAV
PP eVPPH1 or VPPH2,
Suspend Current Block Erase Suspended
VIL Input Low Voltage b0.3 0.8 V
VIH Input High Voltage VCC
2.0 aV
0.3
VOL Output Low 0.4 V VCC eVCC Min and
Voltage IOLe4mA
26
VS28F016SV, MS28F016SV FlashFileTM Memory
5.4 DC Characteristics (Continued)
VCC e3.3V g0.15V, TCSE2 eb
40§Ctoa
125§C, TCSE1 eb
55§Ctoa
125§C
Sym Parameter Notes Min Max Units Test Conditions
VOH1 Output High 2.4 V IOHeb
2.0 mA
Voltage VCC eVCC Min
VOH2V
CCb0.2 V IOH eb
100 mA
VCC eVCC Min
VPPLK VPP Erase/Write 3 0.0 1.8 V
Lock Voltage
VPPH1 VPP during 3 4.5 5.5 V
Write/Erase
Operations
VPPH2 VPP during 3 11.4 12.6 V
Write/Erase
Operations
VLKO VCC Erase/Write 1.8 V
Lock Voltage
NOTES:
1. All currents are in RMS unless otherwise noted. These currents are valid for all product versions (package and speeds).
2. ICCES is specified with the device de-selected. If the device is read while in erase suspend mode, current draw is the sum
of ICCES and ICCR.
3. Block Erases, Word/Byte Writes and Lock Block operations are inhibited when VPP sVPPLK and not guaranteed in the
ranges between VPPLK(max) and VPPH1(min), between VPPH1(max) and VPPH2(min) and above VPPH2(max).
4. Automatic Power Savings (APS) reduces ICCR to less than 3 mA in static operation.
5. CMOS Inputs are either VCC g0.2V or GND g0.2V. TTL Inputs are either VIL or VIH.
6. Sampled, but not 100% tested. Guaranteed by design.
27
VS28F016SV, MS28F016SV FlashFileTM Memory
5.5 DC Characteristics
VCC e5.0V g0.5V, 5.0V g0.25V, TCSE2 eb
40§Ctoa
125§C, TCSE1 eb
55§Ctoa
125§C
Sym Parameter Notes Min Max Units Test Conditions
ILI Input Load Current 1 g1mAV
CC eVCC Max
VINeVCC or GND
ILO Output Leakage 1 g10 mAV
CCeVCC Max
Current VIN eVCCor GND
ICCS VCC Standby 1,5 130 mAV
CCeVCC Max
Current CE0Ý,CE
1
Ý
,RP
ÝeV
CCg
0.2V
BYTEÝ,WP
ÝeV
CCg
0.2V or GND g0.2V
4mAV
CCeVCC Max
CE0Ý,CE
1
Ý
,RP
ÝeV
IH
BYTEÝ,WP
Ý
, 3/5ÝeVIH or VIL
ICCD VCC Deep Power- 1 50 mARP
Ý
e
GND g0.2V
Down Current BYTEÝeVCC g0.2V or
GND g0.2V
ICCR1V
CC Read Current 1,4,5 135 mA VCC eVCC Max,
CMOS:CE0Ý,CE
1
ÝeGND g
0.2V
BYTEÝeGND g0.2V or
VCC g0.2V
Inputs eGND g0.2V or
VCC g0.2V
TTL: CE0Ý,CE
1
ÝeV
IL,
BYTEÝeVIL or VIH,
Inputs eVIL or VIH,
fe10 MHz, IOUT e0mA
I
CCR2V
CC Read Current 1,4,5,6 90 mA VCC eVCC Max,
CMOS:CE0Ý,CE
1
ÝeGND g
0.2V
BYTEÝeGND g0.2V or
VCC g0.2V
Inputs eGND g0.2V or
VCC g0.2V
TTL: CE0Ý,CE
1
ÝeV
IL,
BYTEÝeVIL or VIH,
Inputs eVIL or VIH,
fe5 MHz, IOUT e0mA
28
VS28F016SV, MS28F016SV FlashFileTM Memory
5.5 DC Characteristics (Continued)
VCC e5.0V g0.5V, 5.0V g0.25V, TCSE2 eb
40§Ctoa
125§C, TCSE1 eb
55§Ctoa
125§C
Sym Parameter Notes Min Max Units Test Conditions
ICCW VCC Write Current 1,6 35 mA Word/Byte in Progress
VPP e12.0V g5%
40 mA Word/Byte in Progress
VPP e5.0V g10%
ICCE VCC Block Erase 1,6 25 mA Block Erase in Progress
Current VPP e12.0V g5%
30 mA Block Erase in Progress
VPP e5.0V g10%
ICCES VCC Erase 1,2 10 mA CE0Ý,CE
1
ÝeV
IH
Suspend Current Block Erase Suspended
IPPS VPP Standby/Read 1 g100 mAV
PP sVCC
IPPR Current 200 mAV
PPlVCC
IPPD VPP Deep Power- 1 50 mARP
Ý
e
GND g0.2V
Down Current
IPPW VPP Write Current 1,6 12 mA VPP e12.0V g5%
Word/Byte Write in Progress
22 mA VPP e5.0V g10%
Word/Byte Write in Progress
IPPE VPP Block Erase 1,6 10 mA VPP e12.0V g5%
Current Block Erase in Progress
20 mA VPP e5.0V g10%
Block Erase in Progress
IPPES VPP Erase 1 200 mAV
PP eVPPH1 or VPPH2,
Suspend Current Block Erase Suspended
VIL Input Low Voltage 6 b0.5 0.8 V
VIH Input High Voltage 6 2.0 VCC V
a0.5
29
VS28F016SV, MS28F016SV FlashFileTM Memory
5.5 DC Characteristics (Continued)
VCC e5.0V g0.5V, 5.0V g0.25V, TCSE2 eb
40§Ctoa
125§C, TCSE1 eb
55§Ctoa
125§C
Sym Parameter Notes Min Max Units Test Conditions
VOL Output Low 6 0.45 V VCCeVCC Min
Voltage IOLe5.8 mA
VOH1 Output High 6 0.85 V IOHeb
2.5 mA
Voltage VCC VCC eVCC Min
VOH26V
CC IOHeb
100 mA
b0.4 VCCeVCC Min
VPPLK VPP Write/Erase 3,6 0.0 1.8 V
Lock Voltage
VPPH1 VPP during 4.5 5.5 V
Write/Erase
Operations
VPPH2 VPP during 11.4 12.6 V
Write/Erase
Operations
VLKO VCC Write/Erase 1.8 V
Lock Voltage
NOTES:
1. All currents are in RMS unless otherwise noted. These currents are valid for all product versions (package and speeds).
2. ICCES is specified with the device de-selected. If the device is read while in erase suspend mode, current draw is the sum
of ICCESand ICCR.
3. Block Erases, Word/Byte Writes and Lock Block operations are inhibited when VPP sVPPLK and not guaranteed in the
ranges between VPPLK(max) and VPPH1(min), between VPPH1(max) and VPPH2(min) and above VPPH2(max).
4. Automatic Power Saving (APS) reduces ICCR to less than 1 mA in Static operation.
5. CMOS Inputs are either VCC g0.2V or GND g0.2V. TTL Inputs are either VIL or VIH.
6. Sampled, not 100% tested. Guaranteed by design.
30
VS28F016SV, MS28F016SV FlashFileTM Memory
5.6 AC CharacteristicsÐRead Only Operations(1)
VCC e3.3V g0.15V, TCSE2 eb
40§Ctoa
125§C, TCSE1 eb
55§Ctoa
125§C, Load e50 pF
Versions Units
Sym Parameter Notes Min Max
tAVAV Read Cycle Time 120 ns
tAVQV Address to Output Delay (TACC) 120 ns
tELQV CEÝto Output Delay (TCE) 2,7 120 ns
tPHQV RPÝHigh to Output Delay 620 ns
tGLQV OEÝto Output Delay (TOE) 2 45 ns
tELQX CEÝto Output in Low Z 3,7 0 ns
tEHQZ CEÝto Output in High Z 3,7 50 ns
tGLQX OEÝto Output in Low Z 3 0 ns
tGHQZ OEÝto Output in High Z 3 30 ns
tOH Output Hold from Address, CEÝor OEÝ3,7 0 ns
Change, Whichever Occurs First
tFLQV BYTEÝto Output Delay 3 120 ns
tFHQV
tFLQZ BYTEÝLow to Output in High Z 3 30 ns
tELFL CEÝLow to BYTEÝHigh or Low 3,7 5 ns
tELFH
Extended Status Register Reads
Sym Parameter Notes Min Max Units
tAVEL Address Setup to CEÝGoing Low 3,7,8,9 0 ns
tAVGL Address Setup to OEÝGoing Low 3,7,9 0 ns
31
VS28F016SV, MS28F016SV FlashFileTM Memory
5.6 AC CharacteristicsÐRead Only Operations(1) (Continued)
VCC e5.0V g0.25V, TCSE2 eb
40§Ctoa
125§C, TCSE1 eb
55§Ctoa
125§C, Load e30 pF
VCC e5.0V g0.5V, TCSE2 eb
40§Ctoa
125§C, TCSE1 eb
55§Ctoa
125§C, Load e100 pF
Versions(4) VS/MS28F016SV-85 VS/MS28F016SV-85 VS/MS28F016SV-100
Unit
VCC g5%(5) VCC g10%(6) VCC g10%
Sym Parameter Notes Min Max Min Max Min Max
tAVAV Read Cycle Time 80 85 100 ns
tAVQV Address to Output 80 85 100 ns
Delay (TACC)
tELQV CEÝto Output 2 80 85 100 ns
Delay (TCE)
tPHQV RPÝto Output 400 480 480 ns
Delay
tGLQV OEÝto Output 2 30 35 40 ns
Delay (TOE)
tELQX CEÝto Output in 3 0 0 0 ns
Low Z
tEHQZ CEÝto Output in 3 25 30 35 ns
High Z
tGLQX OEÝto Output in 3 0 0 0 ns
Low Z
tGHQZ OEÝto Output in 3 25 30 35 ns
High Z
tOH Output Hold from 3 0 0 0 ns
Address, CEÝor
OEÝChange,
Whichever Occurs
First
tFLQV BYTEÝto Output 3 80 85 100 ns
Delay
tFHQV
tFLQZ BYTEÝLow to 3 25 30 35 ns
Output in High Z
tELFL CEÝLow to 3 5 5 5 ns
BYTEÝHigh or
tELFH
Low
Extended Status Register Reads
Sym Parameter Notes Min Max Min Max Min Max Unit
tAVEL Address Setup to CEÝGoing 3,7,8,9 0 0 0 ns
Low
tAVGL Address Setup to OEÝGoing 3,7,9 0 0 0 ns
Low
32
VS28F016SV, MS28F016SV FlashFileTM Memory
NOTES:
1. See AC Input/Output Reference Waveforms for timing measurements, Figures 6 and 7.
2. OEÝmay be delayed up to tELQV –tGLQV after the falling edge of CEÝ, without impacting tELQV.
3. Sampled, not 100% tested. Guaranteed by design.
4. Device speeds are defined as:
80/85, 100 ns at VCC e5.0V equivalent to
120 ns at VCC e3.3V
5. See the high speed AC Input/Output Reference Waveforms and AC Testing Load Circuit.
6. See the standard AC Input/Output Reference Waveforms and AC Testing Load Circuit.
7. CExÝis defined as the latter of CE0Ýor CE1Ýgoing low, or the f.
8. This timing parameter is used to latch the correct BSR data onto the outputs.
9. The address setup requirement for Extended Status Register reads must only be met referenced to the falling edge of the
last control signal to become active (CE0Ý,CE
1
Ý
,orOE
Ý
). For example, if CE0Ýor CE1Ýare activated prior to OEÝfor
an Extended Status Register read, specification tAVGL must be met. On the other hand, if either CE0Ýor CE1Ý(or both)
are activated after OEÝ, specification tAVEL must be referenced.
271312–11
NOTE:
CExÝis defined as the latter of CE0Ýor CE1Ýgoing low, or the first of CE0Ýor CE1Ýgoing high.
Figure 11. Read Timing Waveforms
33
VS28F016SV, MS28F016SV FlashFileTM Memory
271312–12
NOTE:
CExÝis defined as the latter of CE0Ýor CE1Ýgoing low, or the first of CE0Ýor CE1Ýgoing high.
Figure 12. BYTEÝTiming Waveforms
34
VS28F016SV, MS28F016SV FlashFileTM Memory
5.7 Power-Up and Reset Timings
271312–22
Figure 13. VCC Power-Up and RPÝReset Waveforms
Symbol Parameter Notes Min Max Unit
tPLYL RPÝLow to 3/5ÝLow (High) 0 ms
tPLYH
tYLPH 3/5ÝLow (High) to RPÝHigh 1 2 ms
tYHPH
tPL5V RPÝLow to VCC at 4.5V minimum (to VCC at 3.0V min or 2 0 ms
3.6V max)
tPL3V
tPHEL3 RPÝHigh to CEÝLow (3.3V VCC) 1 405 ns
tPHEL5 RPÝHigh to CEÝLow (5V VCC) 1 330 ns
tAVQV Address Valid to Data Valid for VCC e5V g10% 3 70 ns
tPHQV RPÝHigh to Data Valid for VCC e5V g10% 3 400 ns
NOTES:
CE0Ý,CE
1
Ýand OEÝare switched low after Power-Up.
1. The tYLPH and/or tYHPH times must be strictly followed to guarantee all other read and write specifications for the
VS/MS28F016SV.
2. The power supply may start to switch concurrently with RPÝgoing low.
3. The address access time and RPÝhigh to data valid time are shown for 5.0V VCC operation of the 28F016SV-085
(Standard Test Configuration). Refer to the AC ChracteristicsÐRead Only Operations for 3.3V VCC and 5.0V VCC (High
Speed Test Configuration) values.
35
VS28F016SV, MS28F016SV FlashFileTM Memory
5.8 AC Characteristics for WEÝÐControlled Command Write Operations(1)
VCC e3.3V g0.15V, TCSE2 eb
40§Ctoa
125§C, TCSE1 eb
55§Ctoa
125§C, Load e50 pF
Versions Unit
Sym Parameter Notes Min Max
tAVAV Write Cycle Time 120 ns
tVPWH(1,2) VPP Setup to WEÝGoing High 3 100 ns
tPHEL RPÝSetup to CEÝGoing Low 3,7 480 ns
tELWL CEÝSetup to WEÝGoing Low 3,7 10 ns
tAVWH Address Setup to WEÝGoing High 2,6 75 ns
tDVWH Data Setup to WEÝGoing High 2,6 75 ns
tWLWH WEÝPulse Width 75 ns
tWHDX Data Hold from WEÝHigh 2 10 ns
tWHAX Address Hold from WEÝHigh 2 10 ns
tWHEH CEÝHold from WEÝHigh 3,7 10 ns
tWHWL WEÝPulse Width High 45 ns
tGHWL Read Recovery before Write 3 0 ns
tWHRL WEÝHigh to RY/BYÝGoing Low 3 100 ns
tRHPL RPÝHold from Valid Status Register (CSR, 3 0 ns
GSR, BSR) Data and RY/BYÝHigh
tPHWL RPÝHigh Recovery to WEÝGoing Low 3 480 ns
tWHGL Write Recovery before Read 95 ns
tQVVL(1,2) VPP Hold from Valid Status Register (CSR, 3 0 ms
GSR, BSR) Data and RY/BYÝHigh
tWHQV(1) Duration of Word/Byte Write Operation 3,4,5,11 5 ms
tWHQV(2) Duration of Block Erase Operation 3,4 0.3 10 sec
36
VS28F016SV, MS28F016SV FlashFileTM Memory
5.8 AC Characteristics for WEÝÐControlled Command Write Operations(1)
(Continued)
VCC e5.0V g0.25V, TCSE2 eb
40§Ctoa
125§C, TCSE1 eb
55§Ctoa
125§C, Load e30 pF
VCC e5.0V g0.5V, TCSE2 eb
40§Ctoa
125§C, TCSE1 eb
55§Ctoa
125§C, Load e100 pF
Versions VS/MS28F016SV-85 VS/MS28F016SV-85 VS/MS28F016SV-100
Unit
VCC g5% VCC g10% VCC g10%
Sym Parameter Notes Min Max Min Max Min Max
tAVAV Write Cycle 80 85 100 ns
Time
tVPWH(1) VPP Setup to 3 100 100 100 ns
WEÝGoing
tVPWH(2)
High
tPHEL RPÝSetup to 3,7 480 480 480 ns
CEÝGoing
Low
tELWL CEÝSetup to 3,7 0 0 0 ns
WEÝGoing
Low
tAVWH Address 2,6 50 50 50 ns
Setup to
WEÝGoing
High
tDVWH Data Setup to 2,6 50 50 50 ns
WEÝGoing
High
tWLWH WEÝPulse 50 60 70 ns
Width
tWHDX Data Hold 2 10 10 10 ns
from WEÝ
High
tWHAX Address Hold 2 10 10 10 ns
from WEÝ
High
tWHEH CEÝHold 3,7 10 10 10 ns
from WEÝ
High
tWHWL WEÝPulse 30 30 30 ns
Width High
tGHWL Read 3 0 0 0 ns
Recovery
before Write
tWHRL WEÝHigh to 3 100 100 100 ns
RY/BYÝ
Going Low
tRHPL RPÝHold 3 0 0 0 ns
from Valid
Status
Register
(CSR, GSR,
BSR) Data
and RY/BY Ý
High
37
VS28F016SV, MS28F016SV FlashFileTM Memory
5.8 AC Characteristics for WEÝÐControlled Command Write Operations(1)
VCC e5.0V g0.25V, TCSE2 eb
40§Ctoa
125§C, TCSE1 eb
55§Ctoa
125§C, Load e30 pF
VCC e5.0V g0.5V, TCSE2 eb
40§Ctoa
125§C, TCSE1 eb
55§Ctoa
125§C, Load e100 pF
(Continued)
Versions VS/MS28F016SV-85 VS/MS28F016SV-85 VS/MS28F016SV-100
Unit
VCC g5% VCC g10% VCC g10%
Sym Parameter Notes Min Max Min Max Min Max
tPHWL RPÝHigh 3 1 1 1 ms
Recovery to
WEÝGoing
Low
tWHGL Write 60 65 70 ns
Recovery
before Read
tQVVL(1) VPP Hold 3 0 0 0 ms
from Valid
tQVVL(2)
Status
Register
(CSR, GSR,
BSR) Data
and RY/
BYÝHigh
tWHQV(1) Duration of 3,4,5,11 4.5 4.5 4.5 ms
Word/Byte
Write
Operation
tWHQV(2) Duration of 3,4 0.3 10 0.3 10 0.3 10 sec
Block Erase
Operation
NOTES:
1. Read timings during write and erase are the same as for normal read.
2. Refer to command definition tables for valid address and data values.
3. Sampled, not 100% tested. Guaranteed by design.
4. Write/Erase durations are measured to valid Status Register (CSR) Data. VPP e12.0V g0.6V
5. Word/Byte Write operations are typically performed with 1 Programming Pulse.
6. Address and Data are latched on the rising edge of WEÝfor all Command Write operations.
7. CExÝis defined as the latter of CE0Ýor CE1Ýgoing low, or the first of CE0Ýor CE1Ýgoing high.
8. Device speeds are defined as:
80/85, 100 ns at VCC e5.0V equivalent to
120 ns at VCC e3.3V
9. See the high speed AC Input/Output Reference Waveforms and AC Testing Load Circuit.
10. See the standard AC Input/Output Reference Waveforms and AC Testing Load Circuit.
11. The TBD information will be available in a technical paper. Please contact Intel’s Application Hotline or your local sales
office for more information.
38
VS28F016SV, MS28F016SV FlashFileTM Memory
271312–23
NOTES:
1. This address string depicts data write/erase cycles with corresponding verification via ESRD.
2. This address string depicts data write/erase cycles with corresponding verification via CSRD.
3. This cycle is invalid when using CSRD for verification during data write/erase operations.
4. CExÝis defined as the latter of CE0Ýor CE1Ýgoing low or the first of CE0Ýor CE1Ýgoing high.
5. RPÝlow transition is only to show tRHPL; not valid for above Read and Write cycles.
6. VPP voltage during write/erase operations valid at both 12.0V and 5.0V.
7. VPP voltage equal to or below VPPLK provides complete flash memory array protection.
Figure 14. AC Waveforms for Command Write Operations
39
VS28F016SV, MS28F016SV FlashFileTM Memory
5.9 AC Characteristics for CEÝÐControlled Command Write Operations(1)
VCC e3.3V g0.15V, TCSE2 eb
40§Ctoa
125§C, TCSE1 eb
55§Ctoa
125§C, Load e50 pF
Versions Unit
Sym Parameter Notes Min Max
tAVAV Write Cycle Time 120 ns
tPHWL RPÝSetup to WEÝGoing Low 3 480 ns
tVPEH(1,2) VPP Setup to CEÝGoing High 3,7 100 ns
tWLEL WEÝSetup to CEÝGoing Low 3,7 0 ns
tAVEH Address Setup to CEÝGoing High 2,6,7 75 ns
tDVEH Data Setup to CEÝGoing High 2,6,7 75 ns
tELEH CEÝPulse Width 7 75 ns
tEHDX Data Hold from CEÝHigh 2,7 10 ns
tEHAX Address Hold from CEÝHigh 2,7 10 ns
tEHWH WEÝhold from CEÝHigh 3 10 ns
tEHEL CEÝPulse Width High 7 45 ns
tGHEL Read Recovery before Write 3 0 ns
tEHRL CEÝHigh to RY/BYÝGoing Low 3,7 100 ns
tRHPL RPÝHold from Valid Status Register (CSR, 3 0 ns
GSR, BSR) Data and RY/BYÝHigh
tPHEL RPÝHigh Recovery to CEÝGoing Low 3,7 480 ns
tEHGL Write Recovery before Read 95 ns
tQVVL(1,2) VPP Hold from Valid Status Register (CSR, 3 0 ms
GSR, BSR) Data and RY/BYÝHigh
tEHQV(1) Duration of Word/Byte Write Operation 3,4,5,11 5 ms
tEHQV(2) Duration of Block Erase Operation 4 0.3 10 sec
40
VS28F016SV, MS28F016SV FlashFileTM Memory
5.9 AC Characteristics for CEÝÐControlled Command Write Operations(1)
(Continued)
VCC e5.0V g0.25V, TCSE2 eb
40§Ctoa
125§C, TCSE1 eb
55§Ctoa
125§C, Load e30 pF
VCC e5.0V g0.5V, TCSE2 eb
40§Ctoa
125§C, TCSE1 eb
55§Ctoa
125§C, Load e100 pF
Versions(4) VS/MS28F016SV-85 VS/MS28F016SV-85 VS/MS28F016SV-100
VCC g5% VCC g10% VCC g10% Unit
Sym Parameter Notes Min Max Min Max Min Max
tAVAV Write Cycle 80 85 100 ns
Time
tPHWL RPÝSetup to 3 480 480 480 ns
WEÝGoing
Low
tVPEH(1,2) VPP Setup to 3,7 100 100 100 ns
CEÝGoing
High
tWLEL WEÝSetup to 3,7 0 0 0 ns
CEÝGoing
Low
tAVEH Address Setup 2,6,7 50 50 50 ns
to CEÝGoing
High
tDVEH Data Setup to 2,6,7 50 50 50 ns
CEÝGoing
High
tELEH CEÝPulse 7 50 60 70 ns
Width
tEHDX Data Hold from 2,7 10 10 10 ns
CEÝHigh
tEHAX Address Hold 2,7 10 10 10 ns
from CEÝHigh
tEHWH WE Hold from 3,7 10 10 10 ns
CEÝHigh
tEHEL CEÝPulse 7 30 30 30 ns
Width High
tGHEL Read Recovery 3 0 0 0 ns
before Write
tEHRL CEÝHigh to 3,7 100 100 100 ns
RY/BYÝGoing
Low
tRHPL RPÝHold from 3 0 0 0 ns
Valid Status
Register
(CSR, GSR,
BSR) Data and
RY/BYÝHigh
41
VS28F016SV, MS28F016SV FlashFileTM Memory
5.9 AC Characteristics for CEÝÐControlled Command Write Operations(1)
VCC e5.0V g0.25V, TCSE2 eb
40§Ctoa
125§C, TCSE1 eb
55§Ctoa
125§C, Load e30 pF
VCC e5.0V g0.5V, TCSE2 eb
40§Ctoa
125§C, TCSE1 eb
55§Ctoa
125§C, Load e100 pF
(Continued)
Versions(4) VS/MS28F016SV-85 VS/MS28F016SV-85 VS/MS28F016SV-100
VCC g5% VCC g10% VCC g10% Unit
Sym Parameter Notes Min Max Min Max Min Max
tPHEL RPÝHigh 3,7 1 1 1 ms
Recovery to
CEÝGoing
Low
tEHGL Write 60 65 70 ns
Recovery
before Read
tQVVL(1,2) VPP Hold 3 0 0 0 ms
from Valid
Status
Register
(CSR, GSR,
BSR) Data at
RY/BYÝ
High
tEHQV(1) Duration of 3,4,5,11 4.5 4.5 4.5 ms
Word/Byte
Write
Operation
tEHQV(2) Duration of 3,4 0.3 10 0.3 10 0.3 10 sec
Block Erase
Operation
NOTES:
1. Read timings during write and erase are the same as for normal read.
2. Refer to command definition tables for valid address and data values.
3. Sampled, not 100% tested. Guaranteed by design.
4. Write/erase durations are measured to valid Status Data. VPP e12.0V g0.6V.
5. Word/Byte Write operations are typically performed with 1 Programming Pulse.
6. Address and Data are latched on the rising edge of CEÝfor all command write operations.
7. CExÝis defined as the latter of CE0Ýor CE1Ýgoing low, or the first of CE0Ýor CE1Ýgoing high.
8. Device speeds are defined as:
80/85, 100 ns at VCC e5.0V equivalent to
120 ns at VCC e3.3V
9. See the high speed AC Input/Output Reference Waveforms and AC Testing Load Circuit.
10. See the standard AC Input/Output Reference Waveforms and AC Testing Load Circuit.
11. The TBD information will be available in a technical paper. Please contact Intel’s Application Hotline or your local sales
office for more information.
42
VS28F016SV, MS28F016SV FlashFileTM Memory
271312–24
NOTES:
1. This address string depicts data-write/erase cycles with corresponding verification via ESRD.
2. This address string depicts data-write/erase cycles with corresponding verification via CSRD.
3. This cycle is invalid when using CSRD for verification during data write/erase operations.
4. CExÝis defined as the latter of CE0Ýor CE1Ýgoing low or the first of CE0Ýor CE1Ýgoing high.
5. RPÝlow transition is only to show tRHPL; not valid for above Read and Write cycles.
6. VPP voltage during Write/Erase operations valid at both 12.0V and 5.0V.
7. VPP voltage equal to or below VPPLK provides complete flash memory array protection.
Figure 15. Alternate AC Waveforms for Command Write Operations
43
VS28F016SV, MS28F016SV FlashFileTM Memory
5.10 AC Characteristics for WEÝÐControlled Page Buffer Write Operations(1)
VCC e3.3V g0.3V, TCSE2 eb
40§Ctoa
125§C, TCSE1 eb
55§Ctoa
125§C, Load e50 pF
Versions 28F016SV-120 Unit
Sym Parameter Notes Min Typ Max
tAVWL Address Setup to WEÝGoing Low 2 25 ns
VCC e5.0V g0.5V, TCSE2 eb
40§Ctoa
125§C, TCSE1 eb
55§Ctoa
125§C, Load e50 pF
Versions(3) VCC g5% 28F016SV-080(4)
Unit
VCC g10% 28F016SV-080(5) 28F016SV-085(5)
Sym Parameter Notes Min Typ Max Min Typ Max
tAVWL Address Setup 2 15 15 ns
to WEÝGoing Low
NOTES:
1. All other specifications for WEÝÐControlled Write Operations can be found in section 5.8.
2. Address must be valid during the entire WEÝlow pulse.
3. Device speeds are defined as:
80/85, 100 ns at VCC e5.0V equivalent to
120 ns at VCC e3.3V
4. See the high speed AC Input/Output Reference Waveforms and AC Testing Load Circuit.
5. See the standard AC Input/Output Reference Waveforms and AC Testing Load Circuit.
44
VS28F016SV, MS28F016SV FlashFileTM Memory
271312–25
NOTE:
1. CEXÝis defined as the latter of CE0Ýor CE1Ýgoing low, or the first of CE0Ýor CE1Ýgoing high.
Figure 16. WEÝÐControlled Page Buffer Write Timing Waveforms (Loading Data to the Tape Buffer)
45
VS28F016SV, MS28F016SV FlashFileTM Memory
5.11 AC Characteristics for CEÝÐControlled Page Buffer Write Operations(1)
VCC e3.3V g0.3V, TCSE2 eb
40§Ctoa
125§C, TCSE1 eb
55§Ctoa
125§C, Load e50 pF
Versions 28F016SV-120 Unit
Sym Parameter Notes Min Typ Max
tAVEL Address Setup to CEÝGoing Low 2, 3 25 ns
VCC e5.0V g0.5V, TCSE2 eb
40§Ctoa
125§C, TCSE1 eb
55§Ctoa
125§C, Load e50 pF
Versions(4) VCC g5% 28F016SV-080(5)
Unit
VCC g10% 28F016SV-080(6) 28F016SV-085(6)
Sym Parameter Notes Min Typ Max Min Typ Max
tAVEL Address Setup 2, 3 15 15 ns
to CEÝGoing Low
NOTES:
1. All other specifications for CEÝÐControlled Write Operations can be found in section 5.9.
2. Address must be valid during the entire CEÝlow pulse.
3. CExÝis defined as the latter of CE0Ýor CE1Ýgoing low, or the first of CE0Ýor CE1Ýgoing high.
4. Device speeds are defined as:
80/85, 100 ns at VCC e5.0V equivalent to
120 ns at VCC e3.3V
5. See the high speed AC Input/Output Reference Waveforms and AC Testing Load Circuit.
6. See the standard AC Input/Output Reference Waveforms and AC Testing Load Circuit.
271312–26
NOTE:
1. CExÝis defined as the latter of CE0Ýor CE1Ýgoing low, or the first of CE0Ýor CE1Ýgoing high.
Figure 17. Controller Page Buffer Write Timing Waveforms
(Loading Data to the Page Buffer)
46
VS28F016SV, MS28F016SV FlashFileTM Memory
5.12 Erase and Word/Byte Write Performance(3,5)
VCC e3.3V g0.15V, VPP e5.0V g0.5V, TCSE2 eb
40§Ctoa
125§C, TCSE1 eb
55§Ctoa
125§C
Sym Parameter Notes Typ(1) Units Test Conditions
Page Buffer Byte Write Time 2,6,7 8 ms
Page Buffer Word Write Time 2,6,7 16 ms
tWHRH1A Byte Write Time 2,7 29 ms
tWHRH1B Word Write Time 2,7 35 ms
tWHRH(2) Block Write Time 2,7 1.9 sec Byte Write Mode
tWHRH(3) Block Write Time 2,7 1.2 sec Word Write Mode
Block Erase Time 2,7 1.4 sec
Full Chip Erase Time 2,7 44.8 sec
Erase Suspend Latency Time 4 12 ms
to Read
Auto Erase Suspend Latency 15 ms
Time to Write
VCC e3.3V g0.15V, VPP e12.0V g0.6V, TCSE2 eb
40§Ctoa
125§C, TCSE1 eb
55§Ctoa
125§C
Sym Parameter Notes Typ(1) Units Test Conditions
Page Buffer Byte Write Time 2,6,7 2.2 ms
Page Buffer Word Write Time 2,6,7 4.4 ms
tWHRH(1) Word/Byte Write Time 2,7 9 ms
tWHRH(2) Block Write Time 2,7 0.6 sec Byte Write Mode
tWHRH(3) Block Write Time 2,7 0.3 sec Word Write Mode
Block Erase Time 2 0.8 sec
Full Chip Erase Time 2,7 25.6 sec
Erase Suspend Latency Time 4 9 ms
to Read
Auto Erase Suspend Latency 12 ms
Time to Write
47
VS28F016SV, MS28F016SV FlashFileTM Memory
5.12 Erase and Word/Byte Write Performance(3,5) (Continued)
VCC e5.0V, VPP e5.0V g0.5V, TCSE2 eb
40§Ctoa
125§C, TCSE1 eb
55§Ctoa
125§C
Sym Parameter Notes Typ(1) Units Test Conditions
Page Buffer Byte Write Time 2,6,7 8 ms
Page Buffer Word Write Time 2,6,7 16 ms
tWHRH1A Byte Write Time 2,7 20 ms
tWHRH1B Word Write Time 2,7 25 ms
tWHRH(2) Block Write Time 2,7 1.4 sec Byte Write Mode
tWHRH(3) Block Write Time 2,7 0.85 sec Word Write Mode
Block Erase Time 2,7 1.0 sec
Full Chip Erase Time 2,7 32.0 sec
Erase Suspend Latency Time 4 9 ms
to Read
Auto Erase Suspend Latency 12 ms
Time to Write
VCC e5.0V g0.5V, VPP e12.0V g0.6V, TCSE2 eb
40§Ctoa
125§C, TCSE1 eb
55§Ctoa
125§C
Sym Parameter Notes Typ(1) Units Test Conditions
Page Buffer Byte Write Time 2,6,7 2.1 ms
Page Buffer Word Write Time 2,6,7 4.1 ms
tWHRH(1) Word/Byte Write Time 2,7 6 ms
tWHRH(2) Block Write Time 2,7 0.4 sec Byte Write Mode
tWHRH(3) Block Write Time 2,7 0.2 sec Word Write Mode
Block Erase Time 2 0.6 sec
Full Chip Erase Time 2,7 19.2 sec
Erase Suspend Latency Time 4 7 ms
to Read
Auto Erase Suspend Latency 10 ms
Time to Write
NOTES:
1. 25§C, and normal voltages.
2. Excludes system-level overhead.
3. These performance numbers are valid for all speed versions.
4. Specification applies to interrupt latency for single block erase. Suspend latency for erase all unlocked blocks operation
extends the maximum latency time to 270 ms.
5. Sampled, but not 100% tested. Guaranteed by design.
6. Assumes using the full Page Buffer to Write to Flash (256 bytes or 128 words).
48
VS28F016SV, MS28F016SV FlashFileTM Memory
6.0 MECHANICAL SPECIFICATIONS
271312–27
Figure 18. Mechanical Specifications of the VS/MS28F0165V 56-Lead SSOP Package
Family: Shrink Small Out-Line Package
Symbol Millimeters Notes
Minimum Nominal Maximum
A 1.80 1.90
A1 0.47 0.52 0.57
A2 1.18 1.28 1.38
B 0.25 0.30 0.40
C 0.13 0.15 0.20
D 23.40 23.70 24.00
E 13.10 13.30 13.50
e10.80
He15.70 16.00 16.30
N56
L
1
0.45 0.50 0.55
Y 0.10
a2
§
3
§
4
§
b3
§
4
§
5
§
R1 0.45 0.20 0.25
R2 0.15 0.20 0.25
49
VS28F016SV, MS28F016SV FlashFileTM Memory
DEVICE NOMENCLATURE
V S28F016SVÐ85
M S28F016SVÐ85
ll l l
V
e
SE2 S eSSOP
l
Access Speed
MeSE1 SV eSmartVoltage Technology
Depending on system design specifcations, the VS/MS28F016SV-85 is capable of supporting
Ð 85 ns access time with a VCC of 5.0V g10% and loading of 100 pF
Ð 100 ns access time with a VCC of 5.0V g10% and loading of 100 pF
ADDITIONAL INFORMATION
Order Number Document/Tool
297372 16-Mbit Flash Product Family User’s Manual
292163 AP-610 ‘‘Flash Memory In-System Code and Data Update Techinques’’
292144 AP-393 ‘‘28F016SV Compatibility with 28F016SA’’
292127 AP-378 ‘‘System Optimization Using the Enhanced Features of the
28F016SA’’
292126 AP-377 ‘‘16-Mbit Flash Product Family Software Drivers, 28F016SA/
28F016SV/28F016XS/28F016XD’’
292124 AP-387 ‘‘Upgrade Considerations from the 28F008SA to the 28F016SA’’
292123 AP-374 ‘‘Flash Memory Write Protection Techniques’’
292092 AP-357 ‘‘Power Supply Solutions for Flash Memory’’
292165 AB-62 ‘‘Compiling Optimized Code for Embedded Flash RAM Memories’’
294016 ER-33 ‘‘ETOXTM Flash Memory TechnologyÐInsight to Intel’s Fourth
Generation Process Innovation’’
297508 FLASHBuilder Utility
Contact Intel/Distribution Flash Cycling Utility
Sales Office
Contact Intel/Distribution 28F016SV iBIS Models
Sales Office
Contact Intel/Distribution 28F016SV VHDL/Verilog Models
Sales Office
Contact Intel/Distribution 28F016SV Timing Designer Library Files
Sales Office
Contact Intel/Distribution 28F016SV Orcad and ViewLogic Schematic Symbols
Sales Office
DATA SHEET REVISION HISTORY
Number Description
001 Original Version
INTEL CORPORATION, 2200 Mission College Blvd., Santa Clara, CA 95052; Tel. (408) 765-8080
Printed in U.S.A./xxxx/1295/B10M/xx xx
