Not recommend
for new design
To our customers,
Old Company Name in Catalogs and Other Documents
On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology
Corporation, and Renesas Electronics Corporation took over all the business of both
companies. Therefore, although the old company nam e remains in this document, it is a valid
Renesas Electronics document. We appreciate your understanding.
Renesas Electronics website: http://www.renesas.com
April 1st, 2010
Renesas Electronics Corporation
Issued by: Renesas Electronics Corporation (http://www.renesas.com)
Send any inquiries to http://www.renesas.com/inquiry.
Not recommend
for new design
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Rev.2.00, May.26.2004, page 1 of 16
R1LV0416C-I Series
Wide Temperature Range Version
4M SRAM (256-kword × 16-bit)
REJ03C0105-0200Z
Rev. 2.00
May.26.2004
Description
The R1LV0416C-I is a 4-Mbit static RAM organized 256-kword × 16-bit. R1LV0416C-I Series has
realized higher density, higher performance and low power consumption by employing CMOS process
technology (6-transistor memory cell). The R1LV0416C-I Series offers low power standby power
dissipation; therefore, it is suitable for battery backup systems. It has packaged in 44-pin TSOP II.
Features
• Single 2.5 V and 3.0 V supply: 2.2 V to 3.6 V
• Fast access time: 55/70 ns (max)
• Power dissipation:
Active: 5.0 mW/MHz (typ)(VCC = 2.5 V)
: 6.0 mW/MHz (typ) (VCC = 3.0 V)
Standby: 1.25 µW (typ) (VCC = 2.5 V)
: 1.5 µW (typ) (VCC = 3.0 V)
• Completely static memory.
No clock or timing strobe required
• Equal access and cycle times
• Common data input and output.
Three state output
• Battery backup operation.
2 chip selection for battery backup
• Temperature range: −40 to +85°C
R1LV0416C-I Series
Rev.2.00, May.26.2004, page 2 of 16
Ordering Information
Type No. Access time Package
R1LV0416CSB-5SI 55 ns 400-mil 44-pin plastic TSOP II (44P3W-H)
R1LV0416CSB-7LI 70 ns
R1LV0416C-I Series
Rev.2.00, May.26.2004, page 3 of 16
Pin Arrangement
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A4
A3
A2
A1
A0
CS1#
I/O0
I/O1
I/O2
I/O3
V
V
I/O4
I/O5
I/O6
I/O7
WE#
A17
A16
A15
A14
A13
CC
SS
A5
A6
A7
OE#
UB#
LB#
I/O15
I/O14
I/O13
I/O12
V
V
I/O11
I/O10
I/O9
I/O8
CS2
A8
A9
A10
A11
A12
CC
SS
(Top view)
44-pin TSOP
Pin Description
Pin name Function
A0 to A17 Address input
I/O0 to I/O15 Data input/output
CS1# (CS1) Chip select 1
CS2 Chip select 2
OE# (OE) Output enable
WE# (WE) Write enable
LB# (LB) Lower byte select
UB# (UB) Upper byte select
VCC Power supply
VSS Ground
R1LV0416C-I Series
Rev.2.00, May.26.2004, page 4 of 16
Block Diagram
•
•
•
•
•
•
••
•
•
•
I/O0
I/O15
CS2
WE#
OE#
A4 A3 A2 A5 A0
V
V
CC
SS
Row
decoder Memory matrix
2,048 x 2,048
Column I/O
Column decoder
Input
data
control
Control logic
A6
A12
A11
A10
A9
A8
A13
A14
A15
A16
A17
A7
CS1#
LB#
UB#
A1
LSB
MSB
LSB MSB
R1LV0416C-I Series
Rev.2.00, May.26.2004, page 5 of 16
Operation Table
CS1# CS2 WE# OE# UB# LB# I/O0 to I/O7 I/O8 to I/O15 Operation
H × × × × × High-Z High-Z Standby
× L × × × × High-Z High-Z Standby
× × × × H H High-Z High-Z Standby
L H H L L L Dout Dout Read
L H H L H L Dout High-Z Lower byte read
L H H L L H High-Z Dout Upper byte read
L H L × L L Din Din Write
L H L × H L Din High-Z Lower byte write
L H L × L H High-Z Din Upper byte write
L H H H × × High-Z High-Z Output disable
Note: H: VIH, L: VIL, ×: VIH or VIL
Absolute Maximum Ratings
Parameter Symbol Value Unit
Power supply voltage relative to VSS V
CC −0.5 to +4.6 V
Terminal voltage on any pin relative to VSS V
T −0.5*1 to VCC + 0.3*2 V
Power dissipation PT 0.7 W
Operating temperature Topr −40 to +85 °C
Storage temperature range Tstg −65 to +150 °C
Storage temperature range under bias Tbias −40 to +85 °C
Notes: 1. VT min: −3.0 V for pulse half-width ≤ 30 ns.
2. Maximum voltage is +4.6 V.
DC Operating Conditions
(Ta = −40 to +85°C)
Parameter Symbol Min Typ Max Unit Note
Supply voltage VCC 2.2 2.5/3.0 3.6 V
V
SS 0 0 0 V
Input high voltage VCC = 2.2 V to 2.7 V VIH 2.0 V
CC + 0.3 V
V
CC = 2.7 V to 3.6 V VIH 2.2 V
CC + 0.3 V
Input low voltage VCC = 2.2 V to 2.7 V VIL −0.2 0.4 V 1
V
CC = 2.7 V to 3.6 V VIL −0.3 0.6 V 1
Note: 1. VIL min: −3.0 V for pulse half-width ≤ 30 ns.
R1LV0416C-I Series
Rev.2.00, May.26.2004, page 6 of 16
DC Characteristics
Parameter Symbol Min Typ Max Unit Test conditions
Input leakage current |ILI| 1 µA Vin = VSS to VCC
Output leakage current |ILO| 1 µA CS1# = VIH or CS2 = VIL or
OE# = VIH or WE# = VIL or
LB# = UB# = VIH,
VI/O = VSS to VCC
Operating current ICC 5*1 20 mA CS1# = VIL, CS2 = VIH,
Others = VIH/VIL, II/O = 0 mA
Average operating current ICC1 8*1 25 mA Min. cycle, duty = 100%,
II/O = 0 mA, CS1# = VIL,
CS2 = VIH,
Others = VIH/VIL
I
CC2 2*1 5 mA Cycle time = 1 µs,
duty = 100%,
II/O = 0 mA, CS1# ≤ 0.2 V,
CS2 ≥ VCC − 0.2 V
VIH ≥ VCC − 0.2 V, VIL ≤ 0.2 V
Standby current ISB 0.1*1 0.3 mA CS2 = VIL
to +85°C ISB1 10 µA Vin ≥ 0 V
to +70°C ISB1 8 µA (1) 0 V ≤ CS2 ≤ 0.2 V or
to +40°C ISB1 0.7*2 3 µA (2) CS1# ≥ VCC − 0.2 V,
−5SI
to +25°C ISB1 0.5*1 3 µA CS2 ≥ VCC − 0.2 V or
to +85°C ISB1 20 µA (3) LB# = UB# ≥ VCC − 0.2 V,
to +70°C ISB1 16 µA CS2 ≥ VCC − 0.2 V,
to +40°C ISB1 0.7*2 10 µA CS1# ≤ 0.2 V
Standby current
−7LI
to +25°C ISB1 0.5*1 10 µA
Output high
voltage VCC =2.2 V to 2.7 V VOH 2.0 — — V IOH = −0.5 mA
V
CC =2.7 V to 3.6 V VOH 2.4 — — V IOH = −1 mA
V
CC =2.2 V to 3.6 V VOH2 V
CC −0.
2
— — V IOH = −100 µA
Output low voltage VCC =2.2 V to 2.7 V VOL — — 0.4 V IOL = 0.5 mA
V
CC =2.7 V to 3.6 V VOL — — 0.4 V IOL = 2 mA
V
CC =2.2 V to 3.6 V VOL2 — — 0.2 V IOL = 100 µA
Notes: 1. Typical values are at VCC = 3.0 V, Ta = +25°C and specified loading, and not guaranteed.
2. Typical values are at VCC = 3.0 V, Ta = +40°C and specified loading, and not guaranteed.
R1LV0416C-I Series
Rev.2.00, May.26.2004, page 7 of 16
Capacitance
(Ta = +25°C, f = 1.0 MHz)
Parameter Symbol Min Typ Max Unit Test conditions Note
Input capacitance Cin 8 pF Vin = 0 V 1
Input/output capacitance CI/O 10 pF VI/O = 0 V 1
Note: 1. This parameter is sampled and not 100% tested.
AC Characteristics
(Ta = −40 to +85°C, VCC = 2.2 V to 3.6 V, unless otherwise noted.)
Test Conditions
• Input pulse levels: VIL = 0.4 V, VIH = 2.2 V (VCC = 2.2 V to 2.7 V)
: VIL = 0.4 V, VIH = 2.4 V (VCC = 2.7 V to 3.6 V)
• Input rise and fall time: 5 ns
• Input/output timing reference levels: 1.1 V (VCC = 2.2 V to 2.7 V)
: 1.4 V (VCC = 2.7 V to 3.6 V)
• Output load: See figures (Including scope and jig)
Dout
30pF
R1
V
TM
V
TM
= 2.3 V
R2 R1 = 3070 Ω
R2 = 3150 Ω50pF
Dout
RL=500 Ω
1.4 V
Output load (A)
(V
CC
= 2.2 V to 2.7 V) Output load (B)
(V
CC
= 2.7 V to 3.6 V)
R1LV0416C-I Series
Rev.2.00, May.26.2004, page 8 of 16
Read Cycle
R1LV0416C-I
-5SI -7LI
Parameter Symbol Min Max Min Max Unit Notes
Read cycle time tRC 55 70 ns
Address access time tAA 55 70 ns
Chip select access time tACS1 55 70 ns
t
ACS2 55 70 ns
Output enable to output valid tOE 35 40 ns
Output hold from address change tOH 10 10 ns
LB#, UB# access time tBA 55 70 ns
Chip select to output in low-Z tCLZ1 10 10 ns 2, 3
t
CLZ2 10 10 ns 2, 3
LB#, UB# disable to low-Z tBLZ 5 5 ns 2, 3
Output enable to output in low-Z tOLZ 5 5 ns 2, 3
Chip deselect to output in high-Z tCHZ1 0 20 0 25 ns 1, 2, 3
t
CHZ2 0 20 0 25 ns 1, 2, 3
LB#, UB# disable to high-Z tBHZ 0 20 0 25 ns 1, 2, 3
Output disable to output in high-Z tOHZ 0 20 0 25 ns 1, 2, 3
R1LV0416C-I Series
Rev.2.00, May.26.2004, page 9 of 16
Write Cycle
R1LV0416C-I
-5SI -7LI
Parameter Symbol Min Max Min Max Unit Notes
Write cycle time tWC 55 70 ns
Address valid to end of write tAW 50 60 ns
Chip selection to end of write tCW 50 60 ns 5
Write pulse width tWP 40 50 ns 4
LB#, UB# valid to end of write tBW 50 55 ns
Address setup time tAS 0 0 ns 6
Write recovery time tWR 0 0 ns 7
Data to write time overlap tDW 25 30 ns
Data hold from write time tDH 0 0 ns
Output active from end of write tOW 5 5 ns 2
Output disable to output in high-Z tOHZ 0 20 0 25 ns 1, 2, 3
Write to output in high-Z tWHZ 0 20 0 25 ns 1, 2
Notes: 1. tCHZ, tOHZ, tWHZ and tBHZ are defined as the time at which the outputs achieve the open circuit
conditions and are not referred to output voltage levels.
2. This parameter is sampled and not 100% tested.
3. At any given temperature and voltage condition, tHZ max is less than tLZ min both for a given
device and from device to device.
4. A write occures during the overlap of a low CS1#, a high CS2, a low WE# and a low LB# or a low
UB#. A write begins at the latest transition among CS1# going low, CS2 going high, WE# going
low and LB# going low or UB# going low. A write ends at the earliest transition among CS1#
going high, CS2 going low, WE# going high and LB# going high or UB# going high. tWP is
measured from the beginning of write to the end of write.
5. tCW is measured from the later of CS1# going low or CS2 going high to the end of write.
6. tAS is measured from the address valid to the beginning of write.
7. tWR is measured from the earliest of CS1# or WE# going high or CS2 going low to the end of
write cycle.
R1LV0416C-I Series
Rev.2.00, May.26.2004, page 10 of 16
Timing Waveform
Read Timing Waveform (WE# = VIH)
tAA tACS1
tACS2
tCLZ2
tCLZ1
tBLZ
tBA
tOH
tRC
Valid data
Address
Dout
Valid address
High impedance
CS1#
CS2
LB#, UB#
OE#
*1, 2, 3
*1, 2, 3
*2, 3
*2, 3
*2, 3
*1, 2, 3
tOLZ*2, 3
*1, 2, 3
tOE
tCHZ1
tCHZ2
tBHZ
tOHZ
R1LV0416C-I Series
Rev.2.00, May.26.2004, page 11 of 16
Write Timing Waveform (1) (WE# Clock)
Address
WE#
tWC
tAW
tWP*4
tWR*7
tCW*5
tCW*5
tBW
tAS*6
tOW*2
tWHZ*1, 2
tDW tDH
Valid address
Valid data
CS1#
LB#, UB#
Dout
Din
High impedance
CS2
R1LV0416C-I Series
Rev.2.00, May.26.2004, page 12 of 16
Write Timing Waveform (2) (CS# Clock, OE# = VIH)
Address
WE#
tWC
tAW
tWP*4
tWR*7
tCW*5
tCW*5
tBW
tAS*6
tDW tDH
Valid address
Valid data
LB#, UB#
Dout
Din
High impedance
CS2
CS1#
R1LV0416C-I Series
Rev.2.00, May.26.2004, page 13 of 16
Write Timing Waveform (3) (LB#, UB# Clock, OE# = VIH)
Address
WE#
t
WC
t
AW
t
WP
*
4
t
CW
*
5
t
CW
*
5
t
BW
t
WR
*
7
t
DW
t
DH
Valid address
Valid data
LB#, UB#
Dout
Din
High impedance
CS2
CS1#
t
AS
*
6
R1LV0416C-I Series
Rev.2.00, May.26.2004, page 14 of 16
Low VCC Data Retention Characteristics
(Ta = −40 to +85°C)
Parameter Symbol Min Typ Max Unit Test conditions*3
VCC for data retention VDR 2.0 V Vin ≥ 0V
(1) 0 V ≤ CS2 ≤ 0.2 V or
(2) CS2 ≥ VCC − 0.2 V,
CS1# ≥ VCC − 0.2 V or
(3) LB# = UB# ≥ VCC − 0.2 V,
CS2 ≥ VCC − 0.2 V,
CS1# ≤ 0.2 V
to +85°C ICCDR 10 µA
to +70°C ICCDR 8 µA
to +40°C ICCDR 0.7*23 µA
−5SI
to +25°C ICCDR 0.5*13 µA
to +85°C ICCDR 20 µA
to +70°C ICCDR 16 µA
to +40°C ICCDR 0.7*210 µA
VCC = 3.0 V, Vin ≥ 0V
(1) 0 V ≤ CS2 ≤ 0.2 V or
(2) CS2 ≥ VCC − 0.2 V,
CS1# ≥ VCC − 0.2 V or
(3) LB# = UB# ≥ VCC − 0.2 V,
CS2 ≥ VCC − 0.2 V,
CS1# ≤ 0.2 V
Data
retention
current
−7LI
to +25°C ICCDR 0.5*110 µA
Chip deselect to data retention time tCDR 0 ns See retention waveform
Operation recovery time tR t
RC*4 ns
Notes: 1. Typical values are at VCC = 3.0 V, Ta = +25°C and specified loading, and not guaranteed.
2. Typical values are at VCC = 3.0 V, Ta = +40°C and specified loading, and not guaranteed.
3. CS2 controls address buffer, WE# buffer, CS1# buffer, OE# buffer, LB#, UB# buffer and Din
buffer. If CS2 controls data retention mode, Vin levels (address, WE#, OE#, CS1#, LB#, UB#,
I/O) can be in the high impedance state. If CS1# controls data retention mode, CS2 must be
CS2 ≥ VCC − 0.2 V or 0 V ≤ CS2 ≤ 0.2 V. The other input levels (address, WE#, OE#, LB#, UB#,
I/O) can be in the high impedance state.
4. tRC = read cycle time.
R1LV0416C-I Series
Rev.2.00, May.26.2004, page 15 of 16
Low VCC Data Retention Timing Waveform (1) (CS1# Controlled) (VCC = 2.2 V to 2.7 V)
CC
V
2.2 V
2.0 V
0 V
CS1#
t
CDR
t
R
CS1# V – 0.2 V
CC
≥
DR
V
Data retention mode
Low VCC Data Retention Timing Waveform (2) (CS1# Controlled) (VCC = 2.7 V to 3.6 V)
CC
V
2.2 V
2.7 V
0 V
CS1#
t
CDR
t
R
CS1# V – 0.2 V
CC
≥
DR
V
Data retention mode
Low VCC Data Retention Timing Waveform (3) (CS2 Controlled) (VCC = 2.2 V to 2.7 V)
CC
V
2.2 V
0.4 V
0 V
CS2
CDR
t
R
0 V CS2 0.2 V
DR
V
Data retention modet
< <
R1LV0416C-I Series
Rev.2.00, May.26.2004, page 16 of 16
Low VCC Data Retention Timing Waveform (4) (CS2 Controlled) (VCC = 2.7 V to 3.6 V)
CC
V
2.7 V
0.6 V
0 V
CS2
CDR
t
R
0 V CS2 0.2 V
DR
V
Data retention modet
< <
Low VCC Data Retention Timing Waveform (5) (LB#, UB# Controlled) (VCC = 2.2 V to 2.7 V)
CC
V
2.2 V
2.0 V
0 V
LB#, UB#
tCDR tR
LB#, UB# V – 0.2 V
CC
≥
DR
V
Data retention mode
Low VCC Data Retention Timing Waveform (6) (LB#, UB# Controlled) (VCC = 2.7 V to 3.6 V)
CC
V
2.2 V
2.7 V
0 V
LB#, UB#
tCDR tR
LB#, UB# V – 0.2 V
CC
≥
DR
V
Data retention mode
Revision History R1LV0416C-I Series Data Sheet
Contents of Modification Rev. Date
Page Description
1.00 Aug.05.2003 Initial issue
2.00 May.26.2004 5
6
7
8
9
14
Absolute Maximum Ratings
Notes 2 : +7.0 V to +4.6 V
DC characteristics
−5SI and −7LI items’ description are divided.
AC characteristics
Read Cycle/Notes:
tCLZ1/tCLZ2/tBLZ/tOLZ : Addition of [2, 3]
tCHZ1/tCHZ2/tBHZ/tOHZ : Addition of [1, 2, 3]
Write Cycle/Notes:
tOHZ : Addition of [1, 2, 3]
Low VCC Data Retention Characteristics
−5SI and −7LI items’ description are divided.
Keep safety first in your circuit designs!
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble
may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary
circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's
application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party.
2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data,
diagrams, charts, programs, algorithms, or circuit application examples contained in these materials.
3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of
publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is
therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product
information before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
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