93LC56C-I/SNG - Microchip Technology, Inc.

 2002-2012 Microchip Technology Inc. DS21712C-page 1

93LC46/56/66

Features:

• Single supply with programming operation down

to 2.5V

• Low-power CMOS technology

•100A typical active read cur rent at 2.5 V

•3A typical standby current at 2.5V

• ORG pin selectable memory configuration

• 128 x 8- or 64 x 16-bit organization (93LC46)

• 256 x 8- or 128 x 16-bit organization (93LC56)

• 512 x 8 or 256 x 16 bit organization (93LC66)

• Self-timed erase and write cycles

(including auto-erase)

• Automatic ERAL before WRAL

• Power on/off data protection circuitry

• Industry standard 3-wire serial I/O

• Device status signal during erase/write cycles

• Seque nti al read function

• 1,000,000 E/W cycles ensured

• Data retention > 200 years

• 8-pin PDIP/SOIC

(SOIC in JEDEC standards)

• Temperature ranges supported:

Description:

The Microchip Technology Inc. 93LC46/56/66 are 1K,

2K and 4K low voltage serial Electrically Erasable

PROMs (EEPROM). The device memory is configured

as x8 or x16 bits depending on the external logic of

levels of the ORG pin. Advanced CMOS technology

makes these devices ideal for low power nonvolatile

memory applications. The 93LC Series is available in

standard 8-pin PDIP and surface mount SOIC

packages. The rotated pin-out 93LC46X/56X/66X are

offered in the “SN” package only.

Package Types

Block Diagram

- Industrial (I): -40°C to +85°C

93LC46

93LC56

93LC66

CLK

VCC

ORG

VSS

PDIP/SOIC

VCC

CLK

ORG

VSS

ROTATED SOIC

93LC46X

93LC56X

93LC66X

Data Register Output

Memory

Array

CLK

VCC VSS

Clock

Mode

Decode

Logic

ORG

Address

Decoder

Address

Counter

Buffer

1K/2K/4K 2.5V Microwire Serial EEPROM

Not recommended for new designs –

Please use 93LC46C, 93LC56C or 93LC66C.

93LC46/56/66

DS21712C-page 2  2002-2012 Microchip Technology Inc.

1.0 ELECTRICAL CHARAC TERISTICS

Absolute Maximum Ratings(†)

VCC.............................................................................................................................................................................6.5V

All inputs and outputs w.r.t. VSS ........................................................................................................ -0.6V to VCC + 1.0V

Storage temperature ...............................................................................................................................-65°C to +150°C

Ambient temperature with power applied................................................................................................-40°C to +125°C

ESD protection on all pins  4kV

DC CHARACTERISTICS

† NOTICE: Stresses above those listed under “Maximum ratings” may cause permanent damage to the device. This

is a stres s ra tin g on ly a nd functio nal operation of the d evi ce at tho se or an y other cond iti ons abo ve those i ndi ca ted in

the opera tional li stings of this s pecificatio n is not implie d. Exposure to maximum ra ting conditi ons for extend ed periods

may affect device reliability.

DC CHARACTERISTICS VCC = +2.5V to +5.5V

Industrial (I): TA = -40°C to +85°C

Param.

No. Sym Characteristic Min Typ Max Units Conditions

D1 VIH1 High-level input vo ltage 2.0 — VCC +1 V VCC 2.7V

VIH2 0.7 VCC —VCC +1 V VCC 2.7V

D2 VIL1 Low-lev el input v oltage -0 .3 — 0.8 V VCC 2.7V

VIL2 -0.3 — 0.2 VCC VVCC 2.7V

D3 VOL1 Low-level output voltage — — 0.4 V IOL = 2.1 mA, VCC = 4.5V

VOL2——0.3VIOL = 100 A, VCC = 2.5V

D4 VOH1 High-level output voltage 2.4 — — V IOL = 400 A, VCC = 4.5V

VOH2VCC -0.2 — — V IOL = 100 A, VCC = 2.5V

D5 ILI Input leakage current — — ±10 AVIN = 0.1V to VCC

D6 ILO Output leaka ge curre nt — — ±10 AVOUT = 0.1V to VCC

D7 CIN,

COUT Pin capacitance

(all inputs/ou tpu ts) ——7pFVIN/VOUT = 0V (Note 1 & 2)

TA = 25° C, FCLK = 1 MHz

D8 ICC write Operating current — — 3 mA FCLK = 2 MHz, VCC = 5.5V

(Note 2)

D9 ICC read —

—

100

500

—

A

FCLK = 2 MHz, VCC = 5.5V

FCLK = 1 MHz, VCC = 3.0V

FCLK = 1 MHz, VCC = 2.5V

D10 ICCS Standby current —

—

100

—

A

CLK = CS = 0V; VCC = 5.5V

CLK = CS = 0V; VCC = 3.0V

CLK = CS = 0V; VCC = 2.5V

ORG, DI = VSS or VCC

Note 1: This parameter is tested a t TA = 25°C and FCLK = 1 MHz.

2: This parameter is periodically sampled and not 100% tested.

 2002-2012 Microchip Technology Inc. DS21712C-page 3

93LC46/56/66

AC CHARACTERISTICS

FIGURE 1-1: SYNCHRONOUS DATA T I MING

AC CHARACTERISTICS VCC = +2.5V to +5.5V

Industrial (I): TA = -40°C to +85°C

Param.

No. Sym Characteristic Min Typ Max Units Conditions

CLK Clock frequency —

——

—2

1MHz

MHz VCC  4.5V

VCC  4.5V

2TCKH Clock high time 250 — — ns

CKL Clock low time 250 — — ns

4TCSS Chip select setup time 50 — — ns Relative to CLK

5TCSH Chip select hold time 0 — — ns Relative to CLK

CSL Chip select low time 250 — — ns

7TDIS Data input setup time 100 — — ns Relative to CLK

8TDIH Data input hold time 100 — — ns Relative to CLK

PD Data output delay time — — 400 ns CL = 100 pF

10 TCZ Data output disable time — — 100 ns CL = 100 pf (Note 2)

11 TSV Status valid time — — 500 ns CL = 100 pF

12 TWC Program cycl e time — 4 10 ms Erase/Write mode

13 TEC — 8 15 ms ERAL mode (VCC=5V ±10%)

14 TWL — 16 30 ms WRAL mode (VCC=5V ±1 0%)

15 — Endurance 1M — 1M cycles 25°C, VCC = 5.0V, Block

mode (Note 3)

Note 1: This parameter is tested a t TA = 25°C and FCLK = 1 MHz.

2: This parameter is periodically sampled and not 100% tested.

3: This parameter is not tested but ensured by characterization. For endurance estima tes in a spe c ific

applic atio n, please co ns ult the Total Enduran ce™ Mode l whic h ca n be obtained from Microchi p’s w eb site

at: www.microchip.com.

CS VIH

VIL

VIH

VIL

VIH

VIL

VOH

VOL

VOH

VOL

CLK

(Read)

(Write)

Status Valid

93LC46/56/66

DS21712C-page 4  2002-2012 Microchip Technology Inc.

TABLE 1-1: INSTRUCTION SET FOR 93LC46: ORG = 1 (X 16 ORGANIZATION)

TABLE 1-2: INSTRUCTION SET FOR 93LC46: ORG = 0 (X 8 ORGANIZATION)

TABLE 1-3: INSTRUCTION SET FOR 93LC56: ORG = 1 (X 16 ORGANIZATION)

TABLE 1-4: INSTRUCTION SET FOR 93LC56: ORG = 0 (X 8 ORGANIZATION)

Instruction SB Opcode Address Data In Data Out Req. CLK

Cycles

READ 1 10 A5 A4 A3 A2 A1 A0 — D15 - D0 25

EWEN 1 00 1 1 XXXX — High-Z 9

ERASE 1 11 A5 A4 A3 A2 A1 A0 — (RDY/BSY)9

ERAL 1 00 1 0 XXXX — (RDY/BSY)9

WRITE 1 01 A5 A4 A3 A2 A1 A0 D15 - D0 (RDY/BSY)25

WRAL 1 00 0 1 XXXX D15 - D0 (RDY/BSY)25

EWDS 1 00 0 0 XXXX — High-Z 9

Instruction SB Opcode Address Data In Data Out Req. CLK

Cycles

READ 1 10 A6 A5 A4 A3 A2 A1 A0 — D7 - D0 18

EWEN 1 00 1 1 X X X X X — High-Z 10

ERASE 1 11 A6 A5 A4 A3 A2 A1 A0 — (RDY/BSY)10

ERAL 1 00 1 0 X X X X X — (RDY/BSY)10

WRITE 1 01 A6 A5 A4 A3 A2 A1 A0 D7 - D0 (RDY/BSY)18

WRAL 1 00 0 1 X X X X X D7 - D0 (RDY/BSY)18

EWDS 1 00 0 0 X X X X X — High-Z 10

Instruction SB Opcode Address Data In Data Out Req. CLK

Cycles

READ 1 10 X A6 A5 A4 A3 A2 A1 A0 — D15 - D0 27

EWEN 1 00 1 1 X X X X X X — High-Z 11

ERASE 1 11 X A6 A5 A4 A3 A2 A1 A0 — (RDY/BSY)11

ERAL 1 00 1 0 X X X X X X — (RDY/BSY)11

WRITE 1 01 X A6 A5 A4 A3 A2 A1 A0 D15 - D0 (RDY/BSY)27

WRAL 1 00 0 1 X X X X X X D15 - D0 (RDY/BSY)27

EWDS 1 00 0 0 X X X X X X — High-Z 11

Instruction SB Opcode Address Data In Data Out Req. CLK

Cycles

READ 1 10 X A7 A6 A5 A4 A3 A2 A1 A0 — D7 - D0 20

EWEN 1 00 1 1 X X X X X X X — High-Z 12

ERASE 1 11 X A7 A6 A5 A4 A3 A2 A1 A0 — (RDY/BSY)12

ERAL 1 00 1 0 X X X X X X X — (RDY/BSY)12

WRITE 1 01 X A7 A6 A5 A4 A3 A2 A1 A0 D7 - D0 (RDY/BSY)20

WRAL 1 00 0 1 X X X X X X X D7 - D0 (RDY/BSY)20

EWDS 1 00 0 0 X X X X X X X — High-Z 12

 2002-2012 Microchip Technology Inc. DS21712C-page 5

93LC46/56/66

TABLE 1-5: INSTRUCTION SET FOR 93LC66: ORG = 1 (X 16 ORGANIZATION)

TABLE 1-6: INSTRUCTION SET FOR 93LC66: ORG = 0 (X 8 ORGANIZATION)

Instruction SB Opcode Address Data In Data Out Req. CLK

Cycles

READ 1 10 A7 A6 A5 A4 A3 A2 A1 A0 — D15 - D0 27

EWEN 1 00 1 1 X X X X X X — High-Z 11

ERASE 1 11 A7 A6 A5 A4 A3 A2 A1 A0 — (RDY/BSY)11

ERAL 1 00 1 0 X X X X X X — (RDY/BSY)11

WRITE 1 01 A7 A6 A5 A4 A3 A2 A1 A0 D15 - D0 (RDY/BSY)27

WRAL 1 00 0 1 X X X X X X D15 - D0 (RDY/BSY) 27

EWDS 1 00 0 0 X X X X X X — High-Z 11

Instruction SB Opcode Address Data In Data Out Req. CLK

Cycles

READ 1 10 A8 A7 A6 A5 A4 A3 A2 A1 A0 — D7 - D0 20

EWEN 1 00 1 1 X X X X X X X — High-Z 12

ERASE 1 11 A8 A7 A6 A5 A4 A3 A2 A1 A0 — (RDY/BSY)12

ERAL 1 00 1 0 X X X X X X X — (RDY/BSY)12

WRITE 1 01 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 - D0 (RDY/BSY)20

WRAL 1 00 0 1 X X X X X X X D7 - D0 (RDY/BSY)20

EWDS 1 00 0 0 X X X X X X X — High-Z 12

93LC46/56/66

DS21712C-page 6  2002-2012 Microchip Technology Inc.

2.0 FUNCTIONAL DESCRIPTION

When the ORG pin is connected to VCC, the (x16)

organization is selected. When it is connected to

ground, the (x8) organization is selected. Instruc-

tions, addresses and write data are clocked into the

DI pin on the rising edge of the clock (CLK). The DO

pin is normally held in a high-Z state except when

reading data from the device, or when checking the

Ready/Busy status during a programming operation.

The Ready/Busy status can be verified during an

erase/write operation by polling the DO pin; DO low

indicates that programming is still in progress, while

DO high indicates the device is ready. The DO will

enter the high-Z state on the falling edge of the CS.

2.1 Start Condition

The Start bit is detected by the device if CS and DI are

both high with respect to the positive edge of CLK for

the first time.

Before a Start condition is detected, CS, CLK and DI

may change in any combination (except to that of a

Start condition), without resulting in any device opera-

tion (Read, Write, Erase, EWEN, EWDS, ERAL and

WRAL). As s oon as CS is hig h, th e device is no long er

in the Standby mode.

An instruction following a Start condition will only be

executed if the required amount of opcode, address

and dat a bits for any par ticula r instru ction i s cloc ked i n.

After exec uti on of a n in struc tio n (i. e., cloc k in o r out of

the last required address or data bit) CLK and DI

become “don't care” bits until a new Start condition is

detected.

2.2 Data In /Data Out (DI/DO)

It is possible to connect the Data In and Data Out pins

together. However, with this configuration it is possible

for a “bus conflict” to occur during the “dummy zero”

that precedes the read operation, if A0 is a logic high

level. Under such a condition the voltage level seen at

Data Out is undefined and will depend upon the relative

impedances of Data Out and the signal source driving

A0. The higher the current sourcing capability of A0,

the higher the voltage at the Data Out pin.

2.3 Data Protection

During power-up, all programming modes of operation

are i nhibit ed unti l VCC has reache d a lev el gre ater tha n

1.4V. During power-down, the source data protection

circuitry acts to inhibit all programming modes when

VCC has fallen below 1.4V at nominal conditions.

The EWEN and EWDS commands give additional

protection against accidentally programming during

normal ope rati on.

After power-up, the device is automatically in the

EWDS mode. Therefore, an EWEN instruction must be

performed before any ERASE or WRITE instruction can

be executed.

2.4 Read

The READ instruction outputs the serial data of the

addressed memory location on the DO pin. A dummy

zero bit prec edes th e 16 -bit (x1 6 org ani zatio n) or 8- bit

(x8 orga nizati on) output string . The output dat a b its will

toggle on the rising edge of the CLK and are stable

after the specified time delay (TPD). Sequential read is

possible when CS is held high. The memory data will

automatically cycle to the next register and output

sequentially.

2.5 Erase/Write Enable and Disable

(EWEN, EWDS)

The 93LC46/56/66 power up in the Erase/Write Disable

(EWDS) state. All programming modes must be

preceded by an Erase/Write Enable (EWEN) instruction.

Once the EWEN instruction is executed, programming

remains enabled until an EWDS instruction is executed

or VCC is re moved fr om t he de vic e. To prot ect ag ainst

accidental data disturb, the EWDS instruction can be

used to disable all erase/write functions and should

follow all programming operations. Execution of a READ

instruction is independent of both the EWEN and EWDS

instructions.

2.6 Erase

The ERASE ins tru c ti o n f o rc e s al l da ta bi ts o f t he spec i-

fied address to the logical “1” state. CS is brought low

follow ing th e l oa ding of the las t a ddress b it. This fal lin g

edge o f the CS pin in itiates the sel f-timed p rogrammin g

cycle.

The DO pin indicates the Ready/Busy status of the

device if CS is brought high after a minimum of 250 ns

low (TCSL). DO at logical “0” indicates that program-

ming is s til l in progre ss . DO a t log ical “1” indic ate s that

the register at the specified address has been erased

and the device is ready for another instruction.

The erase cycle takes 4 ms per word typical.

 2002-2012 Microchip Technology Inc. DS21712C-page 7

93LC46/56/66

2.7 Write

The WRITE instruction is followe d by 16 bits (or b y 8

bits) of data which are written into the specified

address. After the last data bit is put on the DI pin,

CS must be b rought low befor e the next rising ed ge

of the CLK clock. This falling edge of CS initiates the

self-timed auto-era se and programming cycle.

The DO pin indicates the Ready/Busy status of the

device if CS is brought high after a minimum of 250 ns

low (T CSL) and be fore the entire write cycle is complete.

DO at logical “0” indicates that programming is still in

progre ss. DO at lo gical “1” indi cates that th e regist er at

the specified address has been written with the data

specified and the device is ready for another

instruction.

The write cycle takes 4 ms per word typi cal.

2.8 Erase All (ERAL)

The ERAL instruction will erase the entire memory array

to the logical “1” state. The ERAL cycle is identical to

the ERASE cycle except for the different opcode. The

ERAL cycle is completely self-timed and commences

at the fal ling e dge of the C S. Clock ing of the CLK pi n is

not necessary after the device has entered the self

clocking mode. The ERAL instruction is ensured at 5V

±10%.

The DO pin indicates the Ready/Busy status of the

device if CS is brought high after a minimum of 250 ns

low (TCSL) and before the entire write cycle is complete.

The ERAL cycle takes (8 ms typical).

2.9 Write All (WRAL)

The WRAL instructio n will write the entire memor y array

with the data specified in the command. The WRAL

cycle is completely self-timed and commences at the

falling edge of the CS. Clocking of the CLK pin is not

necessary after the device has entered the self clock-

ing mode. The WRAL command does include an auto-

matic ERAL cycle for the device. Therefore, the WRAL

instruction does not require an ERAL instructio n but the

chip m ust be in the EWEN st atus. The WRAL instruction

is en sure d at 5V ±10%.

The DO pin indicates the Ready/Busy status of the

device if CS is brought high after a minimum of 250 ns

low ( Tcsl ).

The WRAL cy cle takes 16 ms typical.

FIGURE 2-1: READ TIMING

CLK

110

An ••• A0

High-Z 0Dx ••• D0 Dx ••• D0 •••Dx D0

93LC46/56/66

DS21712C-page 8  2002-2012 Microchip Technology Inc.

FIGURE 2-2: EWEN TIMING

FIGURE 2-3: EWDS TIMING

FIGURE 2-4: WRITE TIMING

DI 00 1 1X

•••

CLK

DI 10

000X••• X

CLK

101An ••• A0 Dx ••• D0

Busy Ready

High-Z

 2002-2012 Microchip Technology Inc. DS21712C-page 9

93LC46/56/66

FIGURE 2-5: WRAL TIMING

FIGURE 2-6: ERASE TIMING

FIGURE 2-7: ERAL TIMING

CLK

DO High-Z

10001X••• XDx ••• D0

High-Z Busy Ready

Ensured by Characterization at VCC = 4.5V to +5.5V.

11 10

CLK

Check Status

111An An-1 An-2 ••• A0

11 10

Busy Ready High-Z

High-Z

CLK

Check Status

100 10X••• X

11 10

Busy Ready High-Z

High-Z

Ensured by Characterization at Vcc = 4.5V to +5.5V.

93LC46/56/66

DS21712C-page 10  2002-2012 Microchip Technology Inc.

3.0 PIN DESCRIPTION

The descriptions of the pins are listed in Table 3-1.

TABLE 3-1: PIN FUNCTION TABLE

3.1 Chip Select (CS)

A high level selects the device. A low level deselects

the dev ice and fo rces it i nto S t andby mode. H owever , a

programming cycle which is already initiated and/or in

progress will be completed, regardless of the CS input

signal . I f C S is brou ght low duri ng a p rogra m c yc le, th e

device will go into Standby mode as soon as the

programming cycle is completed.

CS must be low for 250 ns minimum (TCSL) between

consecutive instructions. If CS is low, the internal

control logic is held in a Reset status.

3.2 Serial Clock (CLK)

The se rial clock is used to synch ronize the communic a-

tion between a master device and the 93LC46/56/66.

Opcode, address and data bits are clocked in on the

positiv e e dge of CLK. D at a bit s ar e also cloc ked out on

the positive edge of CLK.

CLK can be stopped anywhere in the transmission

sequence (at high or low level) and can be continued

anytime with respect to clock high time (TCKH) and

clock low time (TCKL). This gives the controlling master

freedom in preparing opcode, address and data.

CLK is a “don't care” if CS is l ow (devic e desele cted). If

CS is high, but Start condition has not been detected,

any number of clock cycles can be received by the

device withou t chan ging i ts st atus (i.e., waiting for Start

condition).

CLK cycles are not required during the self-timed write

(i.e., auto erase/write) cycle.

After detection of a S tart condition the specified number

of clock cycles (respectively low-to-high transitions of

CLK) must be provided. These clock cycles are required

to clock in all required opcode, address and data bits

before an instruction is executed (see instruction set

truth table). CLK and DI then become “don't care” inputs

waiting for a new Start condition to be detected.

3.3 Data In (DI)

Data In is used to clock in a Start bit, opcode, address

and data synchronously with the CLK input.

3.4 Data Out (DO)

Dat a O ut i s u sed in t he Read mod e to outp ut data syn-

chronously with the CLK input (TPD after the positive

edge of CLK).

This pin also provides Ready/Busy status information

during era se and write cyc les. Ready/Bu sy status inf or-

mation is available on the DO pin if CS is brought high

af ter being low for mini mum c hip selec t low time (TCSL)

and an erase or write operation has been initiated.

The Status signal is not available on DO, if CS is held

low or high during the entire write or erase cycle. In all

other cases DO is in the High-Z mode. If status is

checked after the write/erase cycle, a pull-up resistor

on DO is required to read the Ready signal.

3.5 Organization (ORG)

When ORG is connected to VCC, the (x16) memory

organ iz atio n i s s ele cte d. When OR G i s ti ed t o VSS, the

(x8) memory organi zation is selected. ORG can only be

floated for clock speeds of 1 MHz or less for the (x16)

memory organization. For clock speeds greater than

1 MHz, ORG must be tied to VCC or VSS.

Name PDIP SOIC ROTATED

TSSOP Description

CS 1 1 3 Chip Select

CLK 2 2 4 Serial Data Clock

DI 3 3 5 Serial Data Input

DO 4 4 6 Serial Data Output

VSS 5 5 7 Ground

ORG 6 6 8 Memory Configuration

NU 7 7 1 Not Utilized

Vcc 8 8 2 +1.8V to 5.5V Power Supply

Note: CS must go low between consecutive

instructions.

 2002-2012 Microchip Technology Inc. DS21712C-page 11

93LC46/56/66

4.0 PACKAGING INFORMATION

4.1 Package Marking Information

XXXXXXXX

XXXXXNNN

YYWW

8-Lead PDIP (300 mil) Example:

8-Lead SOIC (150 mil) Example:

XXXXXXXX

XXXXYYWW

NNN

93LC46

I/PNNN

YYWW

93LC46

I/SNYYWW

NNN

8-Lead Rotated SOIC (150 mil) Example:

XXXXXXXX

XXXXYYWW

NNN

93LC46X

I/SNYYWW

NNN

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanumeric traceability code

Pb-free JEDEC designator for Matte Tin (Sn)

*This package is Pb-free. The Pb-free JEDEC designator ( )

can be found on the outer packaging for this package.

Note: In the event th e full Mi crochi p pa rt numbe r cannot be ma rked on on e line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

93LC46/56/66

DS21712C-page 12  2002-2012 Microchip Technology Inc.

8-Lead Plastic Dual In-line (P) – 300 mil (PDIP)





Units INCHES* MILLIMETERS

Dimen sion Li mits MI N NOM MAX MIN NOM MAX

Number of Pins n88

Pitch p.100 2.54

Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32

Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68

Base to Seating Plane A1 .015 0.38

Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26

Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60

Overall Length D .360 .373 .385 9.14 9.46 9.78

Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43

Lead Thic kness c.008 .012 .015 0.20 0.29 0.38

Upper Lea d Width B1 .045 .05 8 .070 1.14 1.46 1. 78

Lower Lea d Width B .014 .018 .022 0.36 0.46 0.56

Overall Row Spacing § eB .310 .370 .430 7.87 9.40 10.92

Mold Draft Angle Top 5 10 15 5 10 15

Mold Draft Angle Bottom 5 10 15 5 10 15

* Controlling Parameter

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

JEDEC Equiva lent : MS- 001

Drawing No. C04-018

.010” (0.254mm) per side.

§ Significant Characteristic

Note: For the most current package drawings, please see the Microchip Packaging Specification located

at http://www.microchip.c om /p a ckagi ng

 2002-2012 Microchip Technology Inc. DS21712C-page 13

93LC46/56/66

8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC)

Foot Angle f048048

1512015120



Mold Draft Angle Bottom 1512015120



Mold Draft Angle Top 0.510.420.33.020.017.013BLead Width 0.250.230.20.010.009.008

Lead Thic kness

0.760.620.48.030.025.019LFoot Length 0.510.380.25.020.015.010hChamfer Distance 5.004.904.80.197.193.189DOverall Length 3.993.913.71.157.154.146E1Molded Package Width 6.206.025.79.244.237.228EOverall Width 0.250.180.10.010.007.004A1Standoff § 1.551.421.32.061.056.052A2Molded Package Thickness 1.751.551.35.069.061.053AOverall Height 1.27.050

Pitch 88

Number of Pins MAXNOMMINMAXNOMMINDimension Limits MILLIMETERSINCHES*Units



45×



* Controlling Parameter

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254mm) per side.

JEDEC Equivalent: MS-012

Drawing No. C04-057

§ Significa nt Char acte risti c

Note: For the most cu rr e nt pac ka ge dr aw i ngs, p le ase se e t he Mi c ro c hi p Pa ck ag ing Specifica t i on lo ca t ed

at http://www.microchip.com/packaging

93LC46/56/66

DS21712C-page 14  2002-2012 Microchip Technology Inc.

APPENDIX A: REVISION HISTORY

Revision B

Added note to page 1 header (Not recommended for

new designs).

Updated document format.

Revision C

Added a note to each package outline drawing.

 2002-2012 Microchip Technology Inc. DS21712C-page 15

93LC46/56/66

THE MICROCHIP WEB SITE

Microc hip pro vides onl ine s upport v ia our W WW site at

www.microchip.com. This web site i s us ed as a m ean s

to make files and information easily available to

customers. Accessible by using your favorite Internet

browser, the web site contains the following

information:

•Product Support – Data sheets and errata,

application notes and sample programs, design

resources, user’s guides and hardware support

documents, latest software releases and archived

software

•General Technical Support – Frequently Asked

Questions (FAQ), technical support requests,

online dis cu ss io n gr oups, Mi cro chi p con sul t an t

program member listing

•Business of Microchip – Product selector and

ordering guides, latest Microchip press releases,

listing of seminar s and events, listings of

Microchip sales offices, distributors and factory

representatives

CUSTOMER CHANGE NOTIFICATION

SERVICE

Microchip’s customer notification service helps keep

customers current on Microchip products. Subscribers

will receive e-mail notification whenever there are

changes, updates, revisions or errata related to a

specif ied produ ct family or develo pment tool of interes t.

To register, access the Microchip web site at

www.microchip.com. Under “Support”, click on

“Customer Change Notification” and follow the

registration instructions.

CUSTOMER SUPP ORT

Users of Microchip products can receive assistance

through several channels:

• Distributor or Representative

• Local S ales Office

• Field Application Engineer (FAE)

• Technical Support

Customers should contact their distributor,

representative or field application engineer (FAE) for

support. Local sales offices are also available to help

customers. A listing of sales offices and locations is

included in the back of this document.

Technical s upport is a vailable through the web si te

at: http://microchip.com/support

93LC46/56/66

DS21712C-page 16  2002-2012 Microchip Technology Inc.

READER RESP ONSE

It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip

product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our

documentation can better serve you, please FAX your comments to the Technical Publications Manager at

(480) 792-4150.

Please list the following information, and use this outline to provide us with your comments about this document.

TO: Technical Publications Manager

RE: Reader Response Total Pages Sent ________

From: Name

Company

Address

City / State / ZIP / Country

Telephone: (_______) _________ - _________

Application (optional):

Would you like a reply? Y N

Device: Literature Number:

Questions:

FAX: (______) _________ - _________

DS21712C93LC46/56/66

1. What are the best features of this document?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this document easy to follow? If not, why?

4. What additions to the document do you think would enhance the structure and subject?

5. What deletions from the document could be made without affecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

 2002-2012 Microchip Technology Inc. DS21712C-page 17

93LC46/56/66

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Sales and Support

PART NO. X/XX XXX

PatternPackageTemperature

Range

Device

Device 93LC46: 1K 2.5V Microwire Serial EEPROM

93LC46X: 1K 2.5V Microwire Serial EEPROM in

alternate pinouts (SN package only)

93LC46T: 1K 2.5V Microwire Serial EEPROM

(Tape and Reel)

93LC46XT: 1K 2.5V Microwire Serial EEPROM

(Tape and Reel)

93LC56: 2K 2.5V Microwire Serial EEPROM

93LC56X: 2K 2.5V Microwire Serial EEPROM in

alternate pinouts (SN package only)

93LC56T: 2K 2.5V Microwire Serial EEPROM

(Tape and Reel)

93LC56XT:2K 2.5V Microwire Serial EEPROM

(Tape and Reel)

93LC66: 4K 2.5V Microwire Serial EEPROM

93LC66X: 4K 2.5V Microwire Serial EEPROM in

alternate pinouts (SN package only)

93LC66T: 4K 2.5V Microwire Serial EEPROM

(Tape and Reel)

93LC66XT: 4K 2.5V Microwire Serial EEPROM

(Tape and Reel)

Temperature

Range I= -40C to +85C

Package P = Plastic DIP (300 mil body), 8-lead

SN = Plastic SOIC (150 mil body), 8-lead

Examples:

a) 93LC46-I/P: 1K, 128x8 or 64x16 Serial

EEPROM, PDIP package

b) 93LC46-I/SN: 1K, 128x8 or 64x16 Serial

EEPRO M , SO IC package

c) 93LC46T-I/SN: 1K, 128x8 or 64x16

Serial EEPROM, SOIC package, tape

and reel

d) 93LC46X-I/SN: 1K, 128x8 or 64x16

Serial EEPROM, Rotated SOIC package

e) 93LC56-I/P: 2K, 256x8 or 128x16 Serial

EEPROM, PDIP package

f) 93LC56-I/SN: 2K, 256x8 or 128x16

Serial EEPRO M, SO IC pack age

g) 93LC56T-I/SN: 2K, 256x8 or 128x16

Serial EEPROM, SOIC package, tape

and reel

h) 93LC56X-I/SN: 2K, 256x8 or 128x16

Serial EEPROM, Rotated SOIC package

i) 93LC66-I/P: 4K, 512x8 or 256x16 Serial

EEPROM, PDIP package

j) 93LC66-I/SN: 4K, 512x8 or 256x16

Serial EEPRO M, SO IC pack age

k) 93LC66T-I/SN: 4K, 512x8 or 256x16

Serial EEPROM, SOIC package, tape

and reel

l) 93LC66X-I/SN: 4K, 512x8 or 256x16

Serial EEPROM, Rotated SOIC package

Data Sheets

Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and

recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:

1. Your local Microchip sales office

2. The Microchip Worldwide Site (www.microchip.com)

Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.

New Customer Notification System

93LC46/56/66

DS21712C-page 18  2002-2012 Microchip Technology Inc.

NOTES:

 2002-2012 Microchip Technology Inc. DS21712C-page 19

Information contained in this publication regarding device

applications a nd the lik e is provided only f or your convenien ce

and may be supers ed ed by u pda t es . I t is your respons ibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC,

FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,

PICSTART, PI C 32 logo, rfPIC, SST, SST Logo, SuperFlash

and UNI/O are registered trademarks of Microchip T echnology

Incorporated in the U.S.A. and other countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,

MTP, SEEVAL and The Embedded Control Solutions

Company are registered trademarks of Microchip Technology

Incorporated in the U.S.A.

Silicon Storage Technology is a registered trademark of

Microchip Technology Inc. in other countries.

Analog-for-the-Digital Age, Application Maestro, BodyCom,

chipKIT, chipKIT logo, CodeGuard, dsPICDEM ,

dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,

ECONOMONIT OR, FanSense, HI-TIDE, In-Circuit Serial

Programm ing, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB

Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code

Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,

PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O,

Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA

and Z-Scale are trademarks of Microchip Technology

Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip T echnology Incorporated

in the U.S.A.

GestIC and ULPP are registered trademarks of Microchip

Tec hnolo gy Germany II Gm bH & Co. & KG, a subsidiary of

Microchip Technology Inc., in other countries.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

ISBN: 9781620767337

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure famili es of its kind on the market today, when used in the

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is c onstantly evolving. We a t Microc hip are co m mitted to continuously improving the code prot ect ion featur es of our

products. Attempts to break Microchip’ s code protection feature may be a violation of the Digital Mill ennium Copyright Act. If such act s

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:2009 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code ho pping

devices, Serial EEPROMs, microperiph erals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

QUALITY MANAGEMENT S

YSTEM

CERTIFIED BY DNV

== ISO/TS 16949 ==

DS21712C-page 20  2002-2012 Microchip Technology Inc.

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10/26/12