74HCT165PW,118 - NXP Semiconductors / Philips Semiconductors

1. General description

The 74HC165; 74HCT165 are high-speed Si-gate CMOS devices that comply with

JEDEC standard no. 7A. They are pin compatible with Low-power Schottky TTL (LSTTL).

The 74HC165; 74HCT165 are 8-bit parallel-load or serial-in shift registers with

complementary serial outputs (Q7 and Q7) available from the last stage. When the

parallel load (PL) input is LOW, parallel data from the D0 to D7 inputs are loaded into the

When PL is HIGH, data enters the register serially at the DS input and shifts one place to

the right (Q0 → Q1 → Q2, etc.) with each positive-going clock transition. This feature

allows parallel-to-serial converter expansion by tying the Q7 output to the DS input of the

succeeding stage.

The clock input is a gated-OR structure which allows one input to be used as an active

LOW clock enable (CE) input. The pin assignment for the CP and CE inputs is arbitrary

and can be reversed for layout convenience. The LOW-to-HIGH transition of input CE

should only take place while CP HIGH for predictable operation. Either the CP or the CE

should be HIGH before the LOW-to-HIGH transition of PL to prevent shifting the data

when PL is activated.

2. Features

nAsynchronous 8-bit parallel load

nSynchronous serial input

nComplies with JEDEC standard no. 7A

nESD protection:

uHBM JESD22-A114E exceeds 2000 V

uMM JESD22-A115-A exceeds 200 V

nSpeciﬁed from −40 °Cto+85°C and from −40 °C to +125 °C

3. Applications

nParallel-to-serial data conversion

74HC165; 74HCT165

8-bit parallel-in/serial out shift register

Rev. 03 — 14 March 2008 Product data sheet

Product data sheet Rev. 03 — 14 March 2008 2 of 22

NXP Semiconductors 74HC165; 74HCT165

8-bit parallel-in/serial out shift register

4. Ordering information

5. Functional diagram

Table 1. Ordering information

Type number Package

Temperature range Name Description Version

74HC165N −40 °C to +125 °C DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4

74HCT165N

74HC165D −40 °C to +125 °C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1

74HCT165D

74HC165DB −40 °C to +125 °C SSOP16 plastic shrink small outline package; 16 leads; body width

5.3 mm SOT338-1

74HCT165DB

74HC165PW −40 °C to +125 °C TSSOP16 plastic thin shrink small outline package; 16 leads; body

width 4.4 mm SOT403-1

74HCT165PW

74HC165BQ −40 °C to +125 °C DHVQFN16 plastic dual in-line compatible thermal enhanced very thin

quad ﬂat package; no leads; 16 terminals; body

2.5 ×3.5 ×0.85 mm

SOT763-1

74HCT165BQ

Fig 1. Logic symbol Fig 2. IEC logic symbol

mna985

CP CE

mna986

≥ 11C3/

C2[LOAD]

G1[SHIFT]

SRG8

Product data sheet Rev. 03 — 14 March 2008 3 of 22

NXP Semiconductors 74HC165; 74HCT165

8-bit parallel-in/serial out shift register

6. Pinning information

6.1 Pinning

Fig 3. Functional diagram

mna992

8-BIT SHIFT REGISTER

PARALLEL-IN/SERIAL-OUT

2Q7

D0 D1 D2 D3 D4 D5 D6 D7

12 13 14 3 4 5 6

(1) The die substrate is attached to this pad using

conductive die attach material. It can not be used as

supply pin or input.

Fig 4. Pin conﬁguration (DIP16, SO16

and (T)SSOP16) Fig 5. Pin conﬁguration (DHVQFN16)

74HC165

74HCT165

PL VCC

CP CE

D4 D3

D5 D2

D6 D1

D7 D0

Q7 DS

GND Q7

001aah564

001aah565

74HC165

74HCT165

Q7 DS

GND(1)

D7 D0

D6 D1

D5 D2

D4 D3

CP CE

GND

VCC

Transparent top view

7 10

6 11

5 12

4 13

3 14

2 15

terminal 1

index area

Product data sheet Rev. 03 — 14 March 2008 4 of 22

NXP Semiconductors 74HC165; 74HCT165

8-bit parallel-in/serial out shift register

6.2 Pin description

7. Functional description

[1] H = HIGH voltage level;

h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;

L = LOW voltage level;

l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;

q = state of the referenced output one set-up time prior to the LOW-to-HIGH clock transition;

X = don’t care;

↑ = LOW-to-HIGH clock transition.

Table 2. Pin description

Symbol Pin Description

PL 1 asynchronous parallel load input (active LOW)

CP 2 clock input (LOW-to-HIGH edge-triggered)

Q7 7 complementary output from the last stage

GND 8 ground (0 V)

Q7 9 serial output from the last stage

DS 10 serial data input

D0 to D7 11, 12, 13, 14, 3, 4, 5, 6 parallel data inputs (also referred to as Dn)

CE 15 clock enable input (active LOW)

VCC 16 positive supply voltage

Table 3. Function table[1]

Operating modes Inputs Qn registers Outputs

PL CE CP DS D0 to D7 Q0 Q1 to Q6 Q7 Q7

parallel load L XXXLLL to LLH

LXXXHHH to HHL

serial shift H L ↑l X L q0 to q5 q6 q6

HL↑h X H q0 to q5 q6 q6

H↑L l X L q0 to q5 q6 q6

H↑L h X H q0 to q5 q6 q6

hold “do nothing” H H X X X q0 q1 to q6 q7 q7

H X H X X q0 q1 to q6 q7 q7

Product data sheet Rev. 03 — 14 March 2008 5 of 22

NXP Semiconductors 74HC165; 74HCT165

8-bit parallel-in/serial out shift register

8. Limiting values

Fig 6. Timing diagram

mna993

inhibit serial shift

load

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V)

Symbol Parameter Conditions Min Max Unit

VCC supply voltage −0.5 +7 V

IIK input clamping current VI < −0.5 V or VI>V

CC + 0.5 V [1] -±20 mA

IOK output clamping current VO < −0.5 V or VO>V

CC + 0.5 V [1] -±20 mA

IOoutput current −0.5 V < VO< VCC + 0.5 V - ±25 mA

ICC supply current - 50 mA

IGND ground current −50 - mA

Tstg storage temperature −65 +150 °C

Product data sheet Rev. 03 — 14 March 2008 6 of 22

NXP Semiconductors 74HC165; 74HCT165

8-bit parallel-in/serial out shift register

[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

[2] Ptot derates linearly with 12 mW/K above 70 °C.

[3] Ptot derates linearly with 8 mW/K above 70 °C.

[4] Ptot derates linearly with 5.5 mW/K above 60 °C.

[5] Ptot derates linearly with 4.5 mW/K above 60 °C.

9. Recommended operating conditions

10. Static characteristics

Ptot total power dissipation Tamb = −40 °C to +125 °C

DIP16 package [2] - 750 mW

SO16 package [3] - 500 mW

(T)SSOP16 package [4] - 500 mW

DHVQFN16 package [5] - 500 mW

Table 4. Limiting values

…continued

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V)

Symbol Parameter Conditions Min Max Unit

Table 5. Recommended operating conditions

Voltages are referenced to GND (ground = 0 V)

Symbol Parameter Conditions 74HC165 74HCT165 Unit

Min Typ Max Min Typ Max

VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V

VIinput voltage 0 - VCC 0-V

CC V

VOoutput voltage 0 - VCC 0-V

CC V

Tamb ambient temperature −40 - +125 −40 - +125 °C

∆t/∆V input transition rise and fall rate VCC = 2.0 V - - 625 - - - ns/V

VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V

VCC = 6.0 V - - 83 - - - ns/V

Table 6. Static characteristics

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions 25 °C−40 °C to +85 °C−40 °C to +125 °C Unit

Min Typ Max Min Max Min Max

74HC165

VIH HIGH-level

input voltage VCC = 2.0 V 1.5 1.2 - 1.5 - 1.5 - V

VCC = 4.5 V 3.15 2.4 - 3.15 - 3.15 - V

VCC = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V

VIL LOW-level

input voltage VCC = 2.0 V - 0.8 0.5 - 0.5 - 0.5 V

VCC = 4.5 V - 2.1 1.35 - 1.35 - 1.35 V

VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V

Product data sheet Rev. 03 — 14 March 2008 7 of 22

NXP Semiconductors 74HC165; 74HCT165

8-bit parallel-in/serial out shift register

VOH HIGH-level

output voltage VI = VIH or VIL

IO = −20 µA; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V

IO = −20 µA; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V

IO = −20 µA; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V

IO = −4.0 mA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V

IO = −5.2 mA; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V

VOL LOW-level

output voltage VI = VIH or VIL

IO = 20 µA; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V

IO = 20 µA; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V

IO = 20 µA; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V

IO = 4.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V

IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V

IIinput leakage

current VI = VCC or GND;

VCC = 6.0 V --±0.1 - ±1-±1µA

ICC supply current VI = VCC or GND; IO=0A;

VCC = 6.0 V - - 8.0 - 80 - 160 µA

CIinput

capacitance - 3.5 - - - - - pF

74HCT165

VIH HIGH-level

input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - 2.0 - V

VIL LOW-level

input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 - 0.8 V

VOH HIGH-level

output voltage VI = VIH or VIL; VCC = 4.5 V

IO = −20 µA 4.4 4.5 - 4.4 - 4.4 - V

IO = −4.0 mA 3.98 4.32 - 3.84 - 3.7 - V

VOL LOW-level

output voltage VI = VIH or VIL; VCC = 4.5 V

IO = 20 µA; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V

IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V

IIinput leakage

current VI = VCC or GND;

VCC = 6.0 V --±0.1 - ±1-±1µA

ICC supply current VI = VCC or GND; IO=0A;

VCC = 6.0 V - - 8.0 - 80 - 160 µA

∆ICC additional

supply current per input pin;

VI=V

CC −2.1 V;

other inputs at VCC or GND;

VCC = 4.5 V to 5.5 V

Dn and DS inputs - 35 126 - 157.5 - 171.5 µA

CP CE, and PL inputs - 65 234 - 292.5 - 318.5 µA

CIinput

capacitance - 3.5 - - - - - pF

Table 6. Static characteristics

…continued

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions 25 °C−40 °C to +85 °C−40 °C to +125 °C Unit

Min Typ Max Min Max Min Max

Product data sheet Rev. 03 — 14 March 2008 8 of 22

NXP Semiconductors 74HC165; 74HCT165

8-bit parallel-in/serial out shift register

11. Dynamic characteristics

Table 7. Dynamic characteristics

GND (ground = 0 V); C

= 50 pF unless otherwise speciﬁed; for test circuit, see Figure 12

Symbol Parameter Conditions 25 °C−40 °C to +85 °C−40 °C to +125 °C Unit

Min Typ Max Min Max Min Max

74HC165

tpd propagation

delay CP or CE to Q7, Q7;

see Figure 7 [1]

VCC = 2.0 V - 52 165 - 205 - 250 ns

VCC = 4.5 V - 19 33 - 41 - 50 ns

VCC = 6.0 V - 15 28 - 35 - 43 ns

VCC = 5.0 V; CL=15pF - 16 - - - - - ns

PL to Q7, Q7; see Figure 8

VCC = 2.0 V - 50 165 - 205 - 250 ns

VCC = 4.5 V - 18 33 - 41 - 50 ns

VCC = 6.0 V - 14 28 - 35 - 43 ns

VCC = 5.0 V; CL=15pF - 15 - - - - - ns

D7 to Q7, Q7; see Figure 9

VCC = 2.0 V - 36 120 - 150 - 180 ns

VCC = 4.5 V - 13 24 - 30 - 36 ns

VCC = 6.0 V - 10 20 - 26 - 31 ns

VCC = 5.0 V; CL=15pF - 11 - - - - - ns

tttransition

time Q7, Q7 output; see Figure 7 [2]

VCC = 2.0 V - 19 75 - 95 - 110 ns

VCC = 4.5 V - 7 15 - 19 - 22 ns

VCC = 6.0 V - 6 13 - 16 - 19 ns

tWpulse width CP input HIGH or LOW;

see Figure 7

VCC = 2.0 V 80 17 - 100 - 120 - ns

VCC = 4.5 V 16 6 - 20 - 24 - ns

VCC = 6.0 V 14 5 - 17 - 20 - ns

PL input LOW; see Figure 8

VCC = 2.0 V 80 14 - 100 - 120 - ns

VCC = 4.5 V 16 5 - 20 - 24 - ns

VCC = 6.0 V 14 4 - 17 - 20 - ns

trec recovery time PL to CP, CE; see Figure 8

VCC = 2.0 V 100 22 - 125 - 150 - ns

VCC = 4.5 V 20 8 - 25 - 30 - ns

VCC = 6.0 V 17 6 - 21 - 26 - ns

Product data sheet Rev. 03 — 14 March 2008 9 of 22

NXP Semiconductors 74HC165; 74HCT165

8-bit parallel-in/serial out shift register

tsu set-up time DS to CP, CE; see Figure 10

VCC = 2.0 V 80 11 - 100 - 120 - ns

VCC = 4.5 V 16 4 - 20 - 24 - ns

VCC = 6.0 V 14 3 - 17 - 20 - ns

CE to CP and CP to CE;

see Figure 10

VCC = 2.0 V 80 17 - 100 - 120 - ns

VCC = 4.5 V 16 6 - 20 - 24 - ns

VCC = 6.0 V 14 5 - 17 - 20 - ns

Dn to PL; see Figure 11

VCC = 2.0 V 80 22 - 100 - 120 - ns

VCC = 4.5 V 16 8 - 20 - 24 - ns

VCC = 6.0 V 14 6 - 17 - 20 - ns

thhold time DS to CP, CE and Dn to PL;

see Figure 10

VCC = 2.0 V 5 6 - 5 - 5 - ns

VCC = 4.5 V 5 2 - 5 - 5 - ns

VCC = 6.0 V 5 2 - 5 - 5 - ns

CE to CP and CP to CE;

see Figure 10

VCC = 2.0 V 5 −17 - 5 - 5 - ns

VCC = 4.5 V 5 −6- 5 - 5 - ns

VCC = 6.0 V 5 −5- 5 - 5 - ns

fmax maximum

frequency CP input; see Figure 7

VCC = 2.0 V 6 17 - 5 - 4 - MHz

VCC = 4.5 V 30 51 - 24 - 20 - MHz

VCC = 6.0 V 35 61 - 28 - 24 - MHz

VCC = 5.0 V; CL= 15 pF - 56 - - - - - MHz

CPD power

dissipation

capacitance

per package;

VI= GND to VCC

[3] -35- - - - - pF

Table 7. Dynamic characteristics

…continued

GND (ground = 0 V); C

= 50 pF unless otherwise speciﬁed; for test circuit, see Figure 12

Symbol Parameter Conditions 25 °C−40 °C to +85 °C−40 °C to +125 °C Unit

Min Typ Max Min Max Min Max

Product data sheet Rev. 03 — 14 March 2008 10 of 22

NXP Semiconductors 74HC165; 74HCT165

8-bit parallel-in/serial out shift register

74HCT165

tpd propagation

delay CE, CP to Q7, Q7;

see Figure 7 [1]

VCC = 4.5 V - 17 34 - 43 - 51 ns

VCC = 5.0 V; CL=15pF - 14 - - - - - ns

PL to Q7, Q7; see Figure 8

VCC = 4.5 V - 20 40 - 50 - 60 ns

VCC = 5.0 V; CL=15pF - 17 - - - - - ns

D7 to Q7, Q7; see Figure 9

VCC = 4.5 V - 14 28 - 35 - 42 ns

VCC = 5.0 V; CL=15pF - 11 - - - - - ns

tttransition

time Q7, Q7 output; see Figure 7 [2]

VCC = 4.5 V - 7 15 - 19 - 22 ns

tWpulse width CP input; see Figure 7

VCC = 4.5 V 16 6 - 20 - 24 - ns

PL input; see Figure 8

VCC = 4.5 V 20 9 - 25 - 30 - ns

trec recovery time PL to CP, CE; see Figure 8

VCC = 4.5 V 20 8 - 25 - 30 - ns

tsu set-up time DS to CP, CE; see Figure 10

VCC = 4.5 V 20 2 - 25 - 30 - ns

CE to CP and CP to CE;

see Figure 10

VCC = 4.5 V 20 7 - 25 - 30 - ns

Dn to PL; see Figure 11

VCC = 4.5 V 20 10 - 25 - 30 - ns

thhold time DS to CP, CE and Dn to PL;

see Figure 10

VCC = 4.5 V 7 −1 - 9 - 11 - ns

CE to CP and CP to CE;

see Figure 10

VCC = 4.5 V 0 −7- 0 - 0 - ns

fmax maximum

frequency CP input; see Figure 7

VCC = 4.5 V 26 44 - 21 - 17 - MHz

VCC = 5.0 V; CL= 15 pF - 48 - - - - - MHz

Table 7. Dynamic characteristics

…continued

GND (ground = 0 V); C

= 50 pF unless otherwise speciﬁed; for test circuit, see Figure 12

Symbol Parameter Conditions 25 °C−40 °C to +85 °C−40 °C to +125 °C Unit

Min Typ Max Min Max Min Max

Product data sheet Rev. 03 — 14 March 2008 11 of 22

NXP Semiconductors 74HC165; 74HCT165

8-bit parallel-in/serial out shift register

[1] tpd is the same as tPHL and tPLH.

[2] tt is the same as tTHL and tTLH.

[3] CPD is used to determine the dynamic power dissipation (PD in µW).

PD = CPD × VCC2× fi + Σ (CL× VCC2× fo) where:

fi = input frequency in MHz;

fo = output frequency in MHz;

Σ (CL× VCC2× fo) = sum of outputs;

CL = output load capacitance in pF;

VCC = supply voltage in V.

12. Waveforms

CPD power

dissipation

capacitance

per package;

VI= GND to VCC − 1.5 V [3] -35- - - - - pF

Table 7. Dynamic characteristics

…continued

GND (ground = 0 V); C

= 50 pF unless otherwise speciﬁed; for test circuit, see Figure 12

Symbol Parameter Conditions 25 °C−40 °C to +85 °C−40 °C to +125 °C Unit

Min Typ Max Min Max Min Max

Measurement points are given in Table 8.

VOL and VOH are typical voltage output levels that occur with the output load.

Fig 7. The clock (CP) or clock enable (CE) to output (Q7 or Q7) propagation delays, the clock pulse width, the

maximum clock frequency and the output transition times

mna987

CP or CE input

Q7 or Q7 output

tPHL

tTHL tTLH

tPLH

1/fmax

VOH

GND

VOL

Product data sheet Rev. 03 — 14 March 2008 12 of 22

NXP Semiconductors 74HC165; 74HCT165

8-bit parallel-in/serial out shift register

Measurement points are given in Table 8.

VOL and VOH are typical voltage output levels that occur with the output load.

Fig 8. The parallel load (PL) pulse width, the parallel load to output (Q7 or Q7) propagation delays, the parallel

load to clock (CP) and clock enable (CE) recovery time

mna988

PL input

CE, CP input

Q7 or Q7 output

tPHL

tWtrec

VOH

GND

VOL

Measurement points are given in Table 8.

VOL and VOH are typical voltage output levels that occur with the output load.

Fig 9. The data input (D7) to output (Q7 or Q7) propagation delays when PL is LOW

mna989

D7 input

Q7 output

tPHL

VOH

GND

VOH

VOL

tPLH

Product data sheet Rev. 03 — 14 March 2008 13 of 22

NXP Semiconductors 74HC165; 74HCT165

8-bit parallel-in/serial out shift register

The shaded areas indicate when the input is permitted to change for predictable output performance

Measurement points are given in Table 8.

VOL and VOH are typical voltage output levels that occur with the output load.

(1) CE may change only from HIGH-to-LOW while CP is LOW, see Section 1.

Fig 10. The set-up and hold times from the serial data input (DS) to the clock (CP) and clock enable (CE) inputs,

from the clock enable input (CE) to the clock input (CP) and from the clock input (CP) to the

clock enable input (CE)

tsu tsu

GND

DS input

tsu

mna990

GND

CP, CE input

(1)

Measurement points are given in Table 8.

VOL and VOH are typical voltage output levels that occur with the output load.

Fig 11. The set-up and hold times from the data inputs (Dn) to the parallel load input (PL)

mna991

Dn input

PL input

tsu th

GND

tsu th

Table 8. Measurement points

Type Input Output

VIVMVM

74HC165 VCC 0.5VCC 0.5VCC

74HCT165 3 V 1.3 V 1.3 V

Product data sheet Rev. 03 — 14 March 2008 14 of 22

NXP Semiconductors 74HC165; 74HCT165

8-bit parallel-in/serial out shift register

Test data is given in Table 9.

Deﬁnitions for test circuit:

RT = Termination resistance should be equal to output impedance Zo of the pulse generator.

CL = Load capacitance including jig and probe capacitance.

RL = Load resistance.

S1 = Test selection switch

Fig 12. Test circuit for measuring switching times

VMVM

10 %

90 %

0 V

negative

pulse

positive

pulse

0 V

VMVM

90 %

10 %

001aad983

DUT

VCC VCC

VIVO

RLS1

open

Table 9. Test data

Type Input Load S1 position

VItr, tfCLRLtPHL, tPLH

74HC165 VCC 6 ns 15 pF, 50 pF 1 kΩopen

74HCT165 3 V 6 ns 15 pF, 50 pF 1 kΩopen

Product data sheet Rev. 03 — 14 March 2008 15 of 22

NXP Semiconductors 74HC165; 74HCT165

8-bit parallel-in/serial out shift register

13. Package outline

Fig 13. Package outline SOT38-4 (DIP16)

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

SOT38-4 95-01-14

03-02-13

(e )

seating plane

pin 1 index

0 5 10 mm

scale

Note

1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

UNIT A

max. 12 b1(1) (1) (1)

b2cD E e M Z

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

min. A

max. bmax.

1.73

1.30 0.53

0.38 0.36

0.23 19.50

18.55 6.48

6.20 3.60

3.05 0.2542.54 7.62 8.25

7.80 10.0

8.3 0.764.2 0.51 3.2

inches 0.068

0.051 0.021

0.015 0.014

0.009

1.25

0.85

0.049

0.033 0.77

0.73 0.26

0.24 0.14

0.12 0.010.1 0.3 0.32

0.31 0.39

0.33 0.030.17 0.02 0.13

DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4

Product data sheet Rev. 03 — 14 March 2008 16 of 22

NXP Semiconductors 74HC165; 74HCT165

8-bit parallel-in/serial out shift register

Fig 14. Package outline SOT109-1 (SO16)

detail X

vMA

(A )

pin 1 index

UNIT A

max. A1A2A3bpcD

(1) E(1) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

inches

1.75 0.25

0.10 1.45

1.25 0.25 0.49

0.36 0.25

0.19 10.0

9.8 4.0

3.8 1.27 6.2

5.8 0.7

0.6 0.7

0.3 8

0.25 0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

1.0

0.4

SOT109-1 99-12-27

03-02-19

076E07 MS-012

0.069 0.010

0.004 0.057

0.049 0.01 0.019

0.014 0.0100

0.0075 0.39

0.38 0.16

0.15 0.05

1.05

0.041

0.244

0.228 0.028

0.020 0.028

0.012

0.01

0.25

0.01 0.004

0.039

0.016

0 2.5 5 mm

scale

SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1

Product data sheet Rev. 03 — 14 March 2008 17 of 22

NXP Semiconductors 74HC165; 74HCT165

8-bit parallel-in/serial out shift register

Fig 15. Package outline SOT338-1 (SSOP16)

UNIT A1A2A3bpcD

(1) E(1) eH

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.21

0.05 1.80

1.65 0.25 0.38

0.25 0.20

0.09 6.4

6.0 5.4

5.2 0.65 1.25

7.9

7.6 1.03

0.63 0.9

0.7 1.00

0.55 8

0.130.2 0.1

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

SOT338-1 99-12-27

03-02-19

(1)

vMA

16 9

detail X

(A )

MO-150

pin 1 index

0 2.5 5 mm

scale

SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1

max.

Product data sheet Rev. 03 — 14 March 2008 18 of 22

NXP Semiconductors 74HC165; 74HCT165

8-bit parallel-in/serial out shift register

Fig 16. Package outline SOT403-1 (TSSOP16)

UNIT A1A2A3bpcD

(1) E(2) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.15

0.05 0.95

0.80 0.30

0.19 0.2

0.1 5.1

4.9 4.5

4.3 0.65 6.6

6.2 0.4

0.3 0.40

0.06 8

0.13 0.10.21

DIMENSIONS (mm are the original dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

0.75

0.50

SOT403-1 MO-153 99-12-27

03-02-18

0.25

16 9

detail X

(A )

vMA

0 2.5 5 mm

scale

TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1

max.

1.1

pin 1 index

Product data sheet Rev. 03 — 14 March 2008 19 of 22

NXP Semiconductors 74HC165; 74HCT165

8-bit parallel-in/serial out shift register

Fig 17. Package outline SOT763-1 (DHVQFN16)

terminal 1

index area

0.51

A1Eh

UNIT ye

0.2

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 3.6

3.4

2.15

1.85

2.6

2.4 1.15

0.85

2.5

0.30

0.18

0.05

0.00 0.05 0.1

DIMENSIONS (mm are the original dimensions)

SOT763-1 MO-241 - - -- - -

0.5

0.3

0.1

0.05

0 2.5 5 mm

scale

SOT763-1

DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;

16 terminals; body 2.5 x 3.5 x 0.85 mm

A(1)

max.

AA1c

detail X

y1C

15 10

terminal 1

index area

E(1)

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

D(1)

02-10-17

03-01-27

Product data sheet Rev. 03 — 14 March 2008 20 of 22

NXP Semiconductors 74HC165; 74HCT165

8-bit parallel-in/serial out shift register

14. Abbreviations

15. Revision history

Table 10. Abbreviations

Acronym Description

CMOS Complementary Metal-Oxide Semiconductor

DUT Device Under Test

ESD ElectroStatic Discharge

HBM Human Body Model

MM Machine Model

TTL Transistor-Transistor Logic

Table 11. Revision history

Document ID Release date Data sheet status Change notice Supersedes

74HC_HCT165_3 20080314 Product data sheet - 74HC_HCT165_CNV_2

Modiﬁcations: •The format of this data sheet has been redesigned to comply with the new identity

guidelines of NXP Semiconductors.

•Legal texts have been adapted to the new company name where appropriate.

•Package SOT763-1 (DHVQFN16) added to Section 4 “Ordering information” and Section

13 “Package outline”.

•Family data added, see Section 10 “Static characteristics”

74HC_HCT165_CNV_2 December 1990 Product speciﬁcation - -

Product data sheet Rev. 03 — 14 March 2008 21 of 22

NXP Semiconductors 74HC165; 74HCT165

8-bit parallel-in/serial out shift register

16. Legal information

16.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Deﬁnitions”.

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

16.2 Deﬁnitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

16.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

16.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

17. Contact information

For more information, please visit: http://www.nxp.com

For sales ofﬁce addresses, please send an email to: salesaddresses@nxp.com

Document status[1][2] Product status[3] Deﬁnition

Objective [short] data sheet Development This document contains data from the objective speciﬁcation for product development.

Preliminary [short] data sheet Qualiﬁcation This document contains data from the preliminary speciﬁcation.

Product [short] data sheet Production This document contains the product speciﬁcation.

NXP Semiconductors 74HC165; 74HCT165

8-bit parallel-in/serial out shift register

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 14 March 2008

Document identifier: 74HC_HCT165_3

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

18. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

4 Ordering information. . . . . . . . . . . . . . . . . . . . . 2

5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2

6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3

6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

7 Functional description . . . . . . . . . . . . . . . . . . . 4

8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5

9 Recommended operating conditions. . . . . . . . 6

10 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6

11 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8

12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 15

14 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 20

15 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 20

16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 21

16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 21

16.2 Deﬁnitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

16.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 21

16.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 21

17 Contact information. . . . . . . . . . . . . . . . . . . . . 21

18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22