PTN3500
Maintenance and control device
Product specification
Supersedes data of 2000 Nov 22 2001 Jan 17
INTEGRATED CIRCUITS
Philips Semiconductors Product specification
PTN3500Maintenance and control device
2
2001 Jan 17 853-2226 25435
FEATURES
•I2C to parallel port expander
•Internal 256x8 E2PROM
•Self timed write cycle (5 ms typ.)
•Four byte page write operation
•Controlled pull-up on address lines
•Low voltage VCC range of +2.5 V to +3.6 V
•5 V – tolerant I/Os
•Low standby current (< 60 µA )
•Power on Reset
•Supports Live Insertion
•Compatible with SMBus specification version 1.1
•High E2PROM endurance and data retention
•Available in SO16 and TSSOP16 package options
DESCRIPTION
The PTN3500 is a general purpose maintenance and control device.
It features an on-board E2PROM that can be used to store error
codes or board manufacturing data for read–back by application
software for diagnostic purposes.
The eight quasi bidirectional data pins can be independently
assigned as inputs or outputs to monitor board level status or
activate indicator devices such as LEDs.
The PTN3500 has three address pins allowing up to 8 devices to
share the common two wire I2C software protocol serial data bus.
The PTN3500 supports live insertion to facilitate usage in removable
cards on backplane systems.
PIN CONFIGURATION
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
A0
A1
A2
P0
P1
P2
P3
SDA
SCL
P7
P6
P5
P4
VSS
WC
VDD
SW00541
PTN3500
Figure 1.
PIN DESCRIPTION
PIN NUMBER SYMBOL NAME AND FUNCTION
1,2,3 A0:2 Address Lines
4,5,6,7 P0:3 Quasi–bidirectional i/o pins
8 VSS Supply Ground
9,10,11,12 P4:7 Quasi–bidirectional i/o pins
13 WC Write Control Pin. Should be
tied LOW.
14 SCL I2C Serial Clock
15 SDA I2C Serial Data
16 VDD Supply Voltage
ORDERING INFORMATION
Type n mber
Package
Type
n
u
mber
Name Description Version
PTN3500D SO16 Plastic small-outline package; 16 leads; body width 7.5 mm SOT162-1
PTN3500DH TSSOP16 Plastic thin shrink small-outline package; 16 leads; body width 4.4 mm SOT403-1
FUNCTIONAL DIAGRAM
WC
SCL
SDA
A2:0
I2C
Control
E2PROM
256 x 8
8-Bit
I/O
Port P7:0
SW00562
Figure 2.
Philips Semiconductors Product specification
PTN3500Maintenance and control device
2001 Jan 17 3
CHARACTERISTICS OF THE I2C-BUS
The I2C-bus is for 2-way, 2-line communication between different ICs
or modules. The two lines are a serial data line (SDA) and a serial
clock line (SCL). Both lines must be connected to a positive supply
via a pull-up resistor when connected to the output stages of a device.
Data transfer may be initiated only when the bus is not busy.
Bit transfer
One data bit is transferred during each clock phase. The data on the
SDA line must remain stable during the HIGH period of the clock
pulse as changes in the data line at this time will be interpreted as
control signals (See Figure 3).
Start and stop conditions
Both data and clock lines remain HIGH when the bus is not busy. A
HIGH-to-LOW transition of the data line, while the clock is HIGH is
defined as the start condition (S). A LOW-to-HIGH transition of the
data line while the clock is HIGH is defined as the stop condition (P)
(see Figure 4).
System configuration
A device generating a message is a “transmitter”, a device receiving
is the “receiver”. The device that controls the message is the
“master” and the devices which are controlled by the master are the
“slaves” (see Figure 5).
SDA
SCL
SW00542
DATA LINE
STABLE;
DATA VALID
CHANGE
OF DATA
ALLOWED
Figure 3. Bit transfer
SDA
SCL P
SDA
SCL
S
SW00543
START CONDITION STOP CONDITION
Figure 4. Definition of start and stop conditions
SDA
SCL
SW00544
MASTER
TRANSMITTER/
RECEIVER SLAVE
RECEIVER SLAVE
TRANSMITTER/
RECEIVER MASTER
TRANSMITTER MASTER
TRANSMITTER/
RECEIVER
Figure 5. System configuration
Philips Semiconductors Product specification
PTN3500Maintenance and control device
2001 Jan 17 4
Acknowledge (see Figure 6)
The number of data bytes transferred between the start and the stop
conditions from transmitter to receiver is not limited. Each byte of
eight bits is followed by one acknowledge bit. The acknowledge bit
is a HIGH level put on the bus by the transmitter whereas the
master generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge
after the reception of each byte. Also a master must generate an
acknowledge after the reception of each byte that has been clocked
out of the slave transmitter. The device that acknowledges has to
pull down the SDA line during the acknowledge clock pulse, so that
the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse, set–up and hold times must be
taken into account.
A master receiver must signal an end of data to the transmitter by
not generating an acknowledge on the last byte that has been
clocked out of the slave. In this event the transmitter must leave the
data line HIGH to enable the master to generate a stop condition.
S
9821
SW00545
DATA OUTPUT
BY TRANSMITTER
DATA OUTPUT
BY RECEIVER
SCL FROM
MASTER
ACKNOWLEDGE
NOT ACKNOWLEDGE
CLOCK PULSE FOR
ACKNOWLEDGEMENT
START
CONDITION
Figure 6. Acknowledgment on the I2C-bus
FUNCTIONAL DESCRIPTION
SW00546
WRITE PULSE
DATA FROM
SHIFT REGISTER
POWER-ON
RESET
READ PULSE
DATA TO
SHIFT REGISTER
VDD
P0 TO P7
VSS
100 µA
CIS
DQ
FF
CIS
DQ
FF
Figure 7. Simplified schematic diagram of each I/O
Philips Semiconductors Product specification
PTN3500Maintenance and control device
2001 Jan 17 5
Addressing
For addressing, see Figure 8.
S 0 1 0 0 A2 A1 A0 0 A 0 0 AS 1 1 0 A2 A1 A0
a. b.
(a) I/O EXPANDER
(b) MEMORY
SW00547
SLAVE ADDRESSSLAVE ADDRESS
Figure 8. PTN3500 slave addresses
Asynchronous Start
Following any Start condition on the bus, a minimum of 9 SCL clock cycles must be completed before a Stop condition can be issued. The
device does not support a Stop or a repeated Start condition during this time period.
I/O OPERATIONS (see also Figure 7)
Each of the PTN3500’s eight I/Os can be independently used as an input or output. Input I/O data is transferred from the port t o the
microcontroller by the READ mode (See Figure 10). Output data is transmitted to the port by the I/O WRITE mode (see Figure 9).
S 0 1 0 0 A2 A1 A0 0 A DATA 1 ADATA 2 ASDA
SCL
tpv
12345678
tpv
DATA 2 VALIDDATA 1 VALID
SW00548
ACKNOWLEDGE
FROM SLAVE
R/WSTART CONDITION ACKNOWLEDGE
FROM SLAVE ACKNOWLEDGE
FROM SLAVE
SLAVE ADDRESS (I/O EXPANDER) DATA TO PORT DATA TO PORT
WRITE TO
PORT
DATA OUT
FROM PORT
Figure 9. I/O WRITE mode (output)
S 0 1 0 0 A2 A1 A0 1 A DATA 1 ADATA 4 1SDA
tph tps
DATA 4
P
DATA 2 DATA 3
SW00549
SLAVE ADDRESS (I/O EXPANDER) DATA FROM PORT DATA FROM PORT
READ FROM
PORT
DATA INTO
PORT
START CONDITION ACKNOWLEDGE
FROM SLAVE
R/W ACKNOWLEDGE
FROM MASTER STOP
CONDITION
DATA 1
Figure 10. I/O READ mode (input)
Philips Semiconductors Product specification
PTN3500Maintenance and control device
2001 Jan 17 6
Quasi-bidirectional I/Os (see Figure 11)
A quasi-bidirectional I/O can be used as an input or output without the use of a control signal for data direction. At power-on the I/Os are HIGH.
In this mode, only a current source to VDD is active. An additional strong pull-up to VDD allows fast rising edges into heavily loaded outputs.
These devices turn on when an output is written HIGH, and are switched off by the negative edge of SCL. The I/Os should be HIGH before
being used as inputs.
S 0 1 0 0 A2 A1 A0 0 A A ASDA
SCL 12345678
SW00757
ACKNOWLEDGE
FROM SLAVE
R/WSTART CONDITION ACKNOWLEDGE
FROM SLAVE
SLAVE ADDRESS (PTN3500) DATA TO PORT DATA TO PORT
1
P3
0
P3
P
P3
OUTPUT
VOLTAGE
P3
PULL-UP
OUTPUT
CURRENT IOHt IOH
Figure 11. Transient pull-up current IOHt while P3 changes from LOW-to-HIGH and back to LOW
SYMBOL PARAMETER MIN TYP MAX UNIT
tpv Output data valid; CL ≤ 100 pF 4µs
tps Input data setup time; CL ≤ 100 pF 0µs
tph Input data hold time; CL ≤ 100 pF 4µs
Philips Semiconductors Product specification
PTN3500Maintenance and control device
2001 Jan 17 7
MEMORY OPERATIONS
Write operations
Write operations require an additional address field to indicate the
memory address location to be written. The address field is eight
bits long, providing access to any one of the 256 words of memory.
There are two types of write operations, byte write and page write.
Byte Write (see Figure 12)
To perform a byte write the start condition is followed by the memory
slave address and the R/W bit set to 0. The PTN3500 will respond
with an acknowledge and then consider the next eight bits sent as
the word address and the eight bits after the word address as the
data. The PTN3500 will issue an acknowledge after the receipt of
both the word address and the data. To terminate the data transfer
the master issues the stop condition, initiating the internal write cycle
to the non-volatile memory. Only write and read operations to the
Quasi-bidirectional I/O are allowed during the internal write cycle.
Page Write (see Figure 13)
A page write is initiated in the same way as the byte write. If after
sending the first word of data, the stop condition is not received the
PTN3500 considers subsequent words as data. After each data
word the PTN3500 responds with an acknowledge and the two least
significant bits of the memory address field are incremented. Should
the master not send a stop condition after four data words the
address counter will return to its initial value and overwrite the data
previously written. After the receipt of the stop condition the inputs
will behave as with the byte write during the internal write cycle.
P
SW00553
SDA
SLAVE
ADDRESS
(MEMORY) WORD
ADDRESS DATA
S1010A2A1A0 A A
R/W
START CONDITION STOP
CONDITION
0A
ACKNOWLEDGE
FROM SLAVE ACKNOWLEDGE
FROM SLAVE
ACKNOWLEDGE
FROM SLAVE
Figure 12. Byte write
SP
SDA
SW00554
SLAVE
ADDRESS
(MEMORY) WORD
ADDRESS DATA TO MEMORY
1010A2A1A0 AA
0
START
CONDITION R/W ACKNOWLEDGE
FROM SLAVE ACKNOWLEDGE
FROM SLAVE
DATA n A
ACKNOWLEDGE
FROM SLAVE
DATA +3n
DATA TO MEMORY
STOP
CONDITION
A
Figure 13. Page Write
Philips Semiconductors Product specification
PTN3500Maintenance and control device
2001 Jan 17 8
Read operations
PTN3500 read operations are initiated in an identical manner to
write operations with the exception that the memory slave address’
R/W bit is set to a one. There are three types of read operations;
current address, random and sequential.
Current Address Read (see Figure 14)
The PTN3500 contains an internal address counter that increments
after each read or write access, as a result if the last word accessed
was at address n then the address counter contains the address
n+1.
When the PTN3500 receives its memory slave address with the
R/W bit set to one it issues an acknowledge and uses the next eight
clocks to transmit the data contained at the address stored in the
address counter. The master ceases the transmission by issuing the
stop condition after the eighth bit. There is no ninth clock cycle for
the acknowledge.
Random Read (see Figure 15)
The PTN3500’ s random read mode allows the address to be read
from to be specified by the master. This is done by performing a
dummy write to set the address counter to the location to be read.
The master must perform a byte write to the address location to be
read, but instead of transmitting the data after receiving the
acknowledge from the PTN3500 the master reissues the start
condition and memory slave address with the R/W bit set to one.
The PTN3500 will then transmit an acknowledge and use the next
eight clock cycles to transmit the data contained in the addressed
location. The master ceases the transmission by issuing the stop
condition after the eighth bit, omitting the ninth clock cycle
acknowledge.
Sequential Read (see Figure 16)
The PTN3500 sequential read is an extension of either the current
address read or random read. If the master doesn’t issue a stop
condition after it has received the eighth data bit, but instead issues
an acknowledge, the PTN3500 will increment the address counter
and use the next eight cycles to transmit the data from that location.
The master can continue this process to read the contents of the
entire memory. Upon reaching address 255 the counter will return to
address 0 and continue transmitting data until a stop condition is
received. The master ceases the transmission by issuing the stop
condition after the eighth bit, omitting the ninth clock cycle
acknowledge.
SP
SW00556
SLAVE
ADDRESS
(MEMORY) DATA FROM MEMORY
SDA
START
CONDITION
1 0 1 0 A2A1A0 1 A
R/W ACKNOWLEDGE
FROM SLAVE
STOP
CONDITION
Figure 14. Current Address Read
SP
SDA
SW00557
SLAVE
ADDRESS
(MEMORY) WORD
ADDRESS
1010A2A1A0 A A
0
START
CONDITION R/W
ACKNOWLEDGE
FROM SLAVE
ACKNOWLEDGE
FROM SLAVE
A
ACKNOWLEDGE
FROM SLAVE
DATA FROM MEMORY
STOP
CONDITION
S
START
CONDITION
1010A2A1A0
1
R/W
SLAVE
ADDRESS
(MEMORY)
Figure 15. Random Read
SP
SDA
SW00558
SLAVE
ADDRESS
(MEMORY) DATA
FROM MEMORY DATA
FROM MEMORY
1010A2A1A0 AA
1
START
CONDITION R/W ACKNOWLEDGE
FROM SLAVE ACKNOWLEDGE
FROM MASTER
DATA n A
ACKNOWLEDGE
FROM MASTER
DATA N+X
STOP
CONDITION
DATA n+1
DATA
FROM MEMORY
Figure 16. Sequential Read
Philips Semiconductors Product specification
PTN3500Maintenance and control device
2001 Jan 17 9
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied.
SYMBOL PARAMETER MIN MAX UNIT
VCC Supply Voltage –0.5 4.0 V
VIInput Voltage VSS – 0.5 5.5 V
IIDC Input Current –20 20 mA
IODC Output Current –25 25 mA
IDD Supply Current –100 100 mA
ISS Supply Current –100 100 mA
Ptot Total Power Dissipation 400 mW
POTotal Power Dissipation per Output 100 mW
TSTG Storage Temperature –65 +150 _C
TAMB Operating Temperature –40 +85 _C
VESD Electrostatic Discharge:
Human Body Model, 1.5 kΩ, 100 pF – >2000 V
Machine Model, 0 Ω, 200 pF – >200 V
DC ELECTRICAL CHARACTERISTICS
Tamb = –40_C to +85_C unless otherwise specified; VCC = 3.3 V
SYMBOL PARAMETER MIN TYP MAX UNIT
Supply
VDD Supply Voltage 2.5 3.3 3.6 V
IDDQ Standby Current; A0, A1, A2, WC = HIGH 60 µA
IDD1 Supply Current Read 1 mA
IDD2 Supply Current Write 2 mA
VPOR Power on Reset Voltage 2.4 V
Input SCL; input, output SDA
VIL Input LOW voltage –0.5 0.3 VDD V
VIH Input HIGH voltage 0.7 VDD 5.5 V
IOL Output LOW current @ VOL = 0.4 V 3 mA
ILInput leakage current @ VI = VDD or VSS –1 1µA
CIInput capacitance @ VI = VSS 7 pF
I/O Expander Port
VIL Input LOW voltage –0.5 0.3 VDD V
VIH Input HIGH voltage 0.7 VDD 5.5 V
IIHL(max) Input current through protection diodes –400 400 µA
IOL Output LOW current @ VOL = 1 V 10 25 mA
IOH Output HIGH current @ VOH = Vss 30 100 300 µA
IOHt T ransient pull-up current 2 mA
CIInput Capacitance 10 pF
COOutput Capacitance 10 pF
Address Inputs (A0, A1, A2), WC input
VIL Input LOW voltage –0.5 0.3 VDD V
VIH Input HIGH voltage 0.7 VDD 5.5 V
ILInput leakage current @ VI = VDD –1 1µA
Input leakage (pull-up) current @ VI = VSS 10 25 100 µA
Philips Semiconductors Product specification
PTN3500Maintenance and control device
2001 Jan 17 10
I2C-BUS TIMING CHARACTERISTICS
SYMBOL PARAMETER MIN. TYP. MAX. UNIT
I2C-bus timing (see Figure 17; Note 1)
fSCL SCL clock frequency – – 400 kHz
tSW tolerable spike width on bus – – 50 ns
tBUF bus free time 1.3 – – µs
tSU;STA ST ART condition set–up time 0.6 – – µs
tHD;STA ST ART condition hold time 0.6 – – µs
trSCL and SDA rise time – – 0.3 µs
tfSCL and SDA fall time – – 0.3 µs
tSU;DAT data set–up time 250 – – ns
tHD;DAT data hold time 0 – – ns
tVD;DAT SCL LOW to data out valid – – 1.0 µs
tSU;STO ST OP condition set–up time 0.6 – – µs
NOTE:
1. All the timing values are valid within the operating supply voltage and ambient temperature range and refer to VIL and VIH with an input
voltage swing of VSS to VDD.
handbook, full pagewidth
SCL
SDA
MBD820
BIT 0
LSB
(R/W)
tHD;STA tSU;DAT tHD;DAT tVD;DAT tSU;STO
tf
r
t
tBUF
tSU;STA 1 / f SCL
START
CONDITION
(S)
BIT 7
MSB
(A7)
BIT 6
(A6) ACKNOWLEDGE
(A) STOP
CONDITION
(P)
SW00561
PROTOCOL
Figure 17.
Philips Semiconductors Product specification
PTN3500Maintenance and control device
2001 Jan 17 11
POWER-UP TIMING
SYMBOL PARAMETER MAX. UNIT
tPUR1Power-up to Read Operation 1 ms
tPUW1Power-up to Write Operation 5 ms
NOTE:
1. tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. These parameters are
guaranteed by design.
WRITE CYCLE LIMITS
SYMBOL PARAMETER MIN. TYP. (5) MAX. UNIT
tWR1Write Cycle Time – 5 10 ms
NOTE:
1. tWR is the maximum time that the device requires to perform the internal write operation.
Write Cycle Timing
SCL
SDA 8th Bit
Word n
ACK
Stop
Condition Start
Condition
MEMORY
ADDRESS
tWR
SW00560
Figure 18.
Philips Semiconductors Product specification
PTN3500Maintenance and control device
2001 Jan 17 12
SOLDERING
Introduction
There is no soldering method that is ideal for all IC packages. W ave
soldering is often preferred when through-hole and surface mounted
components are mixed on one printed-circuit board. However, wave
soldering is not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these situations
reflow soldering is often used.
This text gives a very brief insight to a complex technology. A more
in-depth account of soldering ICs can be found in our
IC Package
Databook
(order code 9398 652 90011).
DIP
Soldering by dipping or by wave
The maximum permissible temperature of the solder is 260°C;
solder at this temperature must not be in contact with the joint for
more than 5 seconds. The total contact time of successive solder
waves must not exceed 5 seconds.
The device may be mounted up to the seating plane, but the
temperature of the plastic body must not exceed the specified
maximum storage temperature (Tstg max). If the printed-circuit board
has been pre-heated, forced cooling may be necessary immediately
after soldering to keep the temperature within the permissible limit.
Repairing soldered joints
Apply a low voltage soldering iron (less than 24 V) to the lead(s) of
the package, below the seating plane or not more than 2 mm above
it. If the temperature of the soldering iron bit is less than 300°C it
may remain in contact for up to 10 seconds. If the bit temperature is
between 300 and 400°C, contact may be up to 5 seconds.
SO and SSOP
Reflow soldering
Reflow soldering techniques are suitable for all SO and SSOP
packages.
Reflow soldering requires solder paste (a suspension of fine solder
particles, flux and binding agent) to be applied to the printed-circuit
board by screen printing, stencilling or pressure-syringe dispensing
before package placement.
Several techniques exist for reflowing; for example, thermal
conduction by heated belt. Dwell times vary between 50 and 300
seconds depending on heating method. Typical reflow temperatures
range from 215 to 250°C.
Preheating is necessary to dry the paste and evaporate the binding
agent. Preheating duration: 45 minutes at 45°C.
W ave soldering
W ave soldering is not recommended for SSOP packages. This is
because of the likelihood of solder bridging due to closely-spaced
leads and the possibility of incomplete solder penetration in
multi-lead devices.
If wave soldering cannot be avoided, the following conditions
must be observed:
•A double-wave (a turbulent wave with high upward pressure
followed by a smooth laminar wave) soldering technique
should be used.
•The longitudinal axis of the package footprint must be
parallel to the solder flow and must incorporate solder
thieves at the downstream end.
Even with these conditions, only consider wave soldering
SSOP packages that have a body width of 4.4 mm, that is
SSOP16 (SOT369–1) or SSOP20 (SOT266–1).
During placement and before soldering, the package must be fixed
with a droplet of adhesive. The adhesive can be applied by screen
printing, pin transfer or syringe dispensing. The package can be
soldered after the adhesive is cured.
Maximum permissible solder temperature is 260°C, and maximum
duration of package immersion in solder is 10 seconds, if cooled to
less than 150°C within 6 seconds. Typical dwell time is 4 seconds at
250°C.
A mildly-activated flux will eliminate the need for removal of
corrosive residues in most applications.
Repairing soldered joints
Fix the component by first soldering two diagonally opposite end
leads. Use only a low voltage soldering iron (less than 24 V) applied
to the flat part of the lead. Contact time must be limited to
10 seconds at up to 300 °C. When using a dedicated tool, all other
leads can be soldered in one operation within 2 to 5 seconds
between 270 and 320°C.
PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent
to use the components in the I2C system provided the system conforms to the
I2C specifications defined by Philips. This specification can be ordered using the
code 9398 393 40011.
Philips Semiconductors Product specification
PTN3500Maintenance and control device
2001 Jan 17 13
SO16: plastic small outline package; 16 leads; body width 7.5 mm SOT162-1
Philips Semiconductors Product specification
PTN3500Maintenance and control device
2001 Jan 17 14
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1
Philips Semiconductors Product specification
PTN3500Maintenance and control device
2001 Jan 17 15
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may af fect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Copyright Philips Electronics North America Corporation 2001
All rights reserved. Printed in U.S.A.
Date of release: 01-01
Document order number: 9397 750 07932
Data sheet
status
Objective
specification
Preliminary
specification
Product
specification
Product
status
Development
Qualification
Production
Definition [1]
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
Data sheet status
[1] Please consult the most recently issued datasheet before initiating or completing a design.
