M=IC PRELIMINARY MX29L8000T/B 8M-BIT [1M x 8] CMOS SINGLE VOLTAGE 3V ONLY FLASH EEPROM FEATURES Extended single-supply voltage range 2.7V to 3.6V for read and write JEDEC-standard EEPROM commands Endurance : 100,000 cycles Fast access time: 120ns Optimized block architecture - One 16 Kbyte protected block(16K-block) - Two 8 Kbyte parameter blocks - One 96 Kbyte main block - Seven 128 Kbyte main blocks Hardware and software data protaction - Hardware Write Protection pin (WP) - Hardware Lockout bit for 16K-block - Software command data protection * Software EEPROM emulation with parameter blocks * Status register - For detection of program or erase cycle completion Auto Erase operation - Automatically erases any one of the sectors or the whole chip - Erase suspend capability - Fast erase time: 50ms typical for chip erase * . * * 1.0 GENERAL DESCRIPTION The MX29L8000T/B is a 8 Mbit, 3 V-only Flash memory organized as a1 Mbytes of 8 bits each. For flexible erase and program capability, the 8 Mbits of data is divided into 11 sectors of one 16 Kbyte protected block, two 8 Kbyte parameter blocks, one 96 Kbyte main block, and seven 128 Kbyte main blocks. To allow for simple in-system operation, the device can be operated with a single 2.7 V to 3.6 V supply voltage. Since many designs read from the flash memory a large percentage of the time, significant power saving is achieved with the 2.7 V VCC operation. Manufactured with MXIC's advanced nonvolatile memory technology, the device offers access times of 120 ns, and alow 111 A typical deep power-down current. The MX29L8000T/B command set is compatible with the JEDEC single-power-supply flash standard. Commands are written to the command register using standard microprocessor write timings. MXIC's flash memory augments EPROM functionality with an internal state machine which controls the erase and program circuitry. The device Status Register provides a convenient way to monitor when a program or erase cycle is complete, and the success or failure of that cycle. Auto Page Program operation - Automatically programs and verifies data at specified addresses - Internal address and data latches for 128 bytes per page Low power dissipation - 20mA active current - 20\UA standby current - 1A deep power-down current Hardware Reset pin (RP) - Reset internal state machine, and put the device into deep power-down mode * Built-in 128 Bytes Page Buffer - Work as SRAM for temporary data storage - Fast access to temporary data Low Vec write inhibit < 1.8V Industry standard surface mount packaging - 40-Lead TSOP Type I Programming the MX29L8000T/B is performed on apage basis; 128 bytes of data are loaded into the device and then programmed simultaneously. The typical Page Program time is 5ms.The device can also be reprogrammed in standard EPROM programmers. Reading data out of the device is similar to reading from an EPROM or other flash. Erase is accomplished by executing the Erase command sequence. This will invoke the Auto Erase algorithm which is an intemal algorithm that automatically times the erase pulse widths and verifies proper cell margin. This device features both chip erase and block erase. Each block can be erased and programmed without affecting other blocks. Using MXIC's advanced design tachnology, no preprogram is required (internally or externally). As a result, the whole chip can be typically erased and verified in as fast as 50 ms. A combined feature of Write Protection pin (WP), Reset pin (RP), 16K-block lockout bit, and software command sequences provides complete data protection. First, software data protection protects the device from P/N: PMQ446 REV.1.4, Jan 12, 1998vic inadvertent program or erase. Two "unlock" write cycles must be presented to the device before the program or erase command can be accepted by the device. For hardware data protection, the WP pin and RP pin provide protection against unwanted command writes due to invalid system bus condition that may occur during system reset and power-up/down sequence. Finally, with 16K-block lockout bit feature, the device provides complete core security for the kernel code required for system initialization. The device has 128 Bytes built-in page buffer, which can serve as SRAM. This feature provides a convenient way to store temporary data for fast read and write. MXIC's Flash technology reliably stores memory contents after 100,000 erase and program cycles. The MXIC's cell is designed to optimize the erase and program mechanism. In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and program operations produce reliable cycling. The highest degree of latch-up protection is achieved with MXIC's proprietary non-epi process. Latch-up protection is proved for stresses up to 100 milliamps on address and data pin from -1V to VCC +1V. 1.2 PINOUTS 40TSOP (TPYE 1} 10 x 20mm MX29L8000T/B PIN CONFIGURATIONS SYMBOL PIN NAME AQ-A19 = Address Input Q0- Q7 Data Input/Output CE Chip Enable Input OE Output Enable Input WE Write Enable RP Reset/Deep Power-down WP Write Protect vec Power Supply Pin (2.7 - 3.6V) GND Ground Pin A16 Ais Ald AIS At? Atl Ag Aa WE RP NG WP A1B Ay AG AS Ad Aa Aa Al ow moe wh s+ oo co Sm om te he POONA AOA AAA ih o MX29L8000T/B Al7 Nc Ala Alo DO? DQG bas og4 voc voc NC bog Dae bat Dao GND CE AG VUUU UU NUD UU UU ooovic FFFFFH amg hes 1S nso k=) Iz Oo on Nes ToS TNs 193 It OOQ0Q0H 1.1 MX29L8000T/B SECTOR ARCHITECTURE 16-Kbyte BLOGK 8-Kbyte PARAMETER BLOCK 8-Kbyte PARAMETER BLOCK 96-Kbyte MAIN BLOCK 128-Kbyte MAIN BLOCK 128-Kbyte MAIN BLOCK 128-Kbyte MAIN BLOCK 128-Kbyte MAIN BLOCK 128-Kbyte MAIN BLOCK 128-Kbyte MAIN BLOCK 128-Kbyte MAIN BLOCK MX29L8000T Memory Map Aa Nes 1S 1S To rx on Nes 1 1S No rx +N Ne 1 1S Te rz o Seta so o Yn Ooo o TNeToeTNs o TNoeToTNs o TMeT0T90 xm rmrrrirse MX29L8000T/B 128-Kbyte MAIN BLOCK 128-Kbyte MAIN BLOCK 128-Kbyte MAIN BLOCK 128-Kbyte MAIN BLOCK 128-Kbyte MAIN BLOCK 128-Kbyte MAIN BLOGK 128-Kbyte MAIN BLOCK 96-Kbyte MAIN BLOCK 8-Kbyte PARAMETER BLOCK 8-Kbyte PARAMETER BLOCK 16-Kbyte BLOGK MX29L3000B Memory MapMic MX29L8000T/B BLOCK DIAGRAM AP, WP Ib WRITE re CONTROL PROGRAM/ERASE _ STATE OE INPUT HIGH VOLTAGE < WE oaic _ | MACHINE (WSM) COMMAND INTERFACE ~L Se REGISTER o MX29L8000T/B CIR) ADDRESS o FLASH Oo LATCH m ARRAY ARRAY AQ-A19 J SOURCE AND HV COMMAND BUFFER DATA Y-PASS GATE DECODER SENSE Pam DATAle AMPLIFIER HY COMMAND J i DATA LATCH PAGE PROGRAM |. DATA LATGH 0-07 < VO BUFFERMic MX29L8000T/B Table 1 .PIN DESCRIPTIONS SYMBOL TYPE NAME AND FUNCTION AQ - A19 INPUT ADDRESS INPUTS: for memory addresses. Addresses are internally latched during a write cycle. Q0 - Q7 INPUT/OUTPUT INFUTS/OUTPUTS DATA BUS: Input data and commands during Command Interface Register(CIR) write cycles. Outputs array,status ,identifier data, and page buffer in the appropriate read mode. Float to tri-state when the chip is de- selected or the outputs are disabled. INPUT CHIP ENABLE INPUTS: Activate the device's control logic, input buffers, decoders and sense amplifiers. With CE high, the device is deselected and power consumption reduces to Standby level upon completion of any current program or erase operations. CE must be low to select the device. INPUT OUTPUT ENABLES: Gates the device's data through the output buffers during aread cycle. OE is active low. INPUT WRITE ENABLE: Controls writes to the Command Interface Register(CIR). WE is active low. INPUT RESET/DEEP POWER-DOWN: When PP is low, the device is in reset/deep power-down mode. When FP is high, the device is in standard operation. INPUT WRITE PROTECTION: Provides a method for locking the 16K-block, using three voltage levels (VIL, VIH, and VHH). When WP is low, the 16K-block is locked. When WPis high the 16K-block isunlocked, ifthe 16K-block lockout bit is disabled. When WP is at VHH, the 16K-block is unlocked. This overrides the status of the lockout bit. See Section3 for details of data-protection vcc DEVICE POWER SUPPLY(2.7V - 3.6V) GND 1.3 BUS OPERATION Flash memory reads, erases and writesin-system via the localCPU. Allbuscyclesto or from the flash memory conform to standard microprocessor bus cycles. These bus operations are summarized below. Table2 MX29L8000T/B Bus Operations GROUND Mode Notes | CE OE WE | RP _| AO Ai | Ag Q0-07 Read VIL VIL VIH VIH x xX xX DOUT OutputDisable VIL VIH VIH VIH x x x HighZ Standby VIH x x VIH x xX xX High# Deeppowerdown x x x VIL x xX xX HighZ ManufacturerlD VIL VIL VIH VIH VIL VIL VHH G2H DevicelD VIL VIL VIH VIH VIH VIL VHH 83H(TopBoot) 82H(BottomBoot) Write VIL VIH VIL VIH x x x DIN NOTES :1.X can be VIH or VIL for address or control pins. 2. VHH = 11.5V- 12.5.vic 1.4 WRITE OPERATIONS The Gommand Interface Register (CIR) is the interface between the microprocessor and the internal chip controller. Device operations are selected by writing specific address and data sequence inte the CIR, using standard microprocessor write timings. Writing incorrect data value or writing them in improper sequence will reset the device to the read mode.(read array or read buffer) Table 3 defines the valid command sequences. Note that the Erase Suspend (BOH) and Erase Resume (30H) are valid only while an erase operation is in progress and will be ignored in other circumstance. There are four read modes: Read Array, Read Silicon ID, Read Status Register, and Read Page Buffer. For Program and Erase MX29L8000T/B inform the internal state machine that aprogram or erase sequence has been requested. During the execution of program or erase operation, the state machine will control the program /erase sequence. After the state machine has completed its task, it will set bit 7 of the Status Register (SR. 7) toa "1", which indicates that the CIR can respond to the full command set. TABLE 3. COMMAND DEFINITIONS Command Read/ Silicon |Page/Byte | Chip Block Erase Erase Sleep Sequence Reset | ID Read] Program | Erase Erase | Suspend] Resume} Mode Bus Write 1 4 4 6 6 1 1 3 Cycles Required First Bus Addr XXXXH | 5555H | 5555H 9 5555H 5555H | XXXXH | XXXXH | 5555H Write Cycde Data FOH AAH AAH AAH AAH BOH 30H AAH Second Bus Addr RA 2AAAH | 2AAAH JP 2AAAH | 2AAAH 2AAAH Write Cycle Data RD 55H 55H 55H 55H 55H Third Bus Addr 5555H 5555H 5555H 5555H 5555H Write Cyde Data 90H AOH 80H 80H COH Fourth Bus Adar 00H/01H PA 5555H 5555H ReadWrite Cydey Data C2H/83H], PD AAH AAH Fifth Bus Addr 2AAAH | 2AAAH Write Cyde Data 55H 55H Sixth Bus Addr 5555H SA Write Cycle Data 10H 30Hvic MX29L8000T/B COMMAND DEFINITIONS(continue Table 3.) Command Lock [Lock Status Read Write Read Clear Clear Seqirence +6}-btock React Payee Cota Page Buffet Stats Register Status Register Buffer Bus Write 6 4 4 4 3 3 3 7 Cycles Required First Bus Addr 5555H 5555H 5555H 5555H 5555H 5555H 5555H Write Gyche Brartar RAH AAH AA AAH AAH AA ADAH Second Bus Adar 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH Write Cyclo Data 55H 55H 55H 55H 554 55H 55H Third Bus Addr 5555H 5555H 5555H 5555H 5555H 5555H 5555H Write Cycte Bata 60H S04 75H EoH TOA 504 O4H Fourth Bus Adar 5555H 02H RA RA ReadAAiite Cyc ft Bratt AAH C200 AE RG Fifth Bus Addr 2AAAH Naat I. Pot rei WTI Wy rte Crete ITT Sixth Bus Addr SA Write-Gycle Bata 20H Notes: 1.Address bit A15 A19 =X = Don't care for all address commands except for Program Address{PA} and Sector Address{S A}, 5555H and 2AAAH address command codes stand for Hex number starting from AO to A14. 2. Bus operations are defined in Table 2. 3. RA = Address of the memory location to be read. __ PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE pulse. SA = Address of the block tobe erased. The combination of A13 -- A19 will uniquely select any block. 4, RD = Data read from location RA during a read operation. __ PD = Data to be programmed at location PA. Data is latched on the rising edge of WE. on aa SA02H = FFFO#H for Top Boat . Erase can be suspended during sector erase with Addr = don't care, Data = BOH . Erase can be resumed after suspend with Addr = don't care, Data = 30H. . Clear Buffer set all buffer data to 1. . In lock status Read, SA02H = 00002H for Bottom BootMic MX29L8000T/B 2.0 DEVICE OPERATION 2.1 SILICON ID READ The Silicon ID Read mode allows the reading out of a MX?9L8000T/B is erased or programmed in a system binary code from the device and will identify its without access to high voltage on the AQ pin. The manufacturer and type. This mode is intended for use by command sequence is illustrated in Table 3. programming equipment for the purpose of automatically matching the device to be programmed with its Following the command write, a read cycle with AO = VIL corresponding programming algorithm. This mode is retrieves the manufacturer code of C2H. A read cycle functional over the entire temperature range of the with AQ = VIH returns the device code . MX29L8000T device. Device Code =83H, MX29L8000B Device Code = 82H To activate this mode, the programming equipment must force VHH (11.5V~12.5V) on address pin A9. Two To terminate the operation, it is necessary to write the identifier bytes may then be sequenced from the device Read/Reset command sequence into the CIR. outputs by toggling address AO from VIL to VIH. All addresses are don't cares except AO and A1. The manufacturer and device codes may alsobe read via the command register, for instances when the Table 4. MX29L8000T/B Silion ID Codes and Verify Sector Protect Code Type A,~A, A,| A, /Code(HEX)/DQ, |DQ,, DQ,/DG,/DQ,) DQ,, DQ,/Da, Manufacturer Code x VIL} VIL C2H 1 1 Oo; 0; 0] 0 1) 0 MX293L8000T Device Code x VIL] VIH 83H 1 0; ao; 0/0] 0} 1] 1 MX29L8000B Device Cade x VIL} VIH 82H 1 0; 0; 0/0); oO) 14] 0 Verify 16K-Block Protect** SA VIH| VIL} C2H* 1 1 Oo; 0; 0; Oo; 1] 0 * Qutputs C2H if 16K-block is protected (lockout bit is enabled), OOH otherwise. ** Only the 16K-Block has protect-bit feature.vic 2.2 READ/RESET COMMAND The read or reset operation is initiated by writing the Read/Reset command sequence into the command register. Microprocessor read cycles retrieve array data from the memory. The device remains ready for reads until the CIR contents are altered by a valid command sequence. The device will automatically power-up in the read/reset state. In this case, a command sequence is not required to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no spurious alteration of the memory content occurs during the power transition. Refer to the AC Read Characteristics and Waveforms for the specific timing parameters. The MX29L8000T/B is accessed like an EPROM. When CE andOE are low and WE is high the data stored at the memory location determined by the address pins is asserted on the outputs. The oufputs are putin the high impedance state whenever CE or OE is high. This dual line control gives designers flexibility in preventing bus contention. Note that the Read/Reset command is not valid when program or erase is in progress. 2.3 PAGE PROGRAM To initiate Page program mode, a three-cycle command sequence is required. There are two " unlock" write cycles. These are followed by writing the page program command AOH. Any attemptto write tothe device without the three-cycle command sequence will not start the intarnal Write State Machine(WSM), no data will be written to the device. After three-cycle command sequence is given, a byte loadis performed by applying alowpulse onthe WE orCE input with CE or WE low (respectively) and OE high. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Maximum of 128 bytes of data may be loaded into each page. MX29L8000T/B 2.3.1 PROGRAM Any page tobe programmed should have the page in the erased state first, i.e. performing sector erase is suggested before page programming can be performed. The davice is programmed on a page basis. If abyte of data within a page is to be changed, data for the entire page can be loaded into the device. Any byte that isnot loaded during the programming of its page will be still in the erased state (i.e. FFH). Once the bytes of a page are loaded into the device, they are simultaneously programmed during the internal programming period. After the first data byte has been loaded into the device, successive bytes are entered in the same manner. Each new byte to be programmed must have its high to low transition on WE (or GE) within 30us of the low to high transition of WE (or CE) of the preceding byte. A7 to A19 specify the page address, i.e., the device is page-aligned on 128 bytes boundary. The page address mustbe valid during each high to low transition of WE or CE. AO toA6 specify the byte address within the page The byte may be loadedin any order; sequential loading is not required. If a high to low transition of CE or WE is not detected whithin 100us of the last low to high transition, the load period will end and the internal programming period will start. The load period will also endif the same addressis consecutively loaded twice. The first data and address will be treated as normal data to be programmed. The second data needs to be '00' to terminate the load cycle. Other numbers besides '00' are reserved for future use. The status of program canbe determinedby checking the Status Register. While the program operation is in progress, bit7 of the Status Register (SR. 7) is"0". When the Status Register indicates that program is complete (when SR. 7 = 1), the Program Status bit should be checked to verify that the program operation was successful. If the program operation was unsuccessful, SR. 4 of the Status Register will be set to "1" to indicate aprogram failure. The Status Register shouldbe cleared before attempting the next operation.vic 2.4 CHIP ERASE Chip erase is a six-bus cycle operation. There are two "unlock" write cycles. These are followed by writing the "set-up" command-80H. Two more "unlock" write cycles are then followedby the Chip Erase command 10H. Chip erase does not require the user to program the device prior to erase. The 16K-Block will not be erased if it is protected (16K-Block Lockout bit enabled). The Auto Chip Erase begins on the rising edge of the last WE pulse in the command sequence and terminates when the status on SR.7 is "1". While the erase sequence is in progress, SR.7 of the Status Register is "0". When erase is complete, the Erase Status bit should be checked. If the erase operation was unsuccessful, SR.5 of the Status Register is set to a'"1" to indicate an erase failure. Clear the Status Register before attempting the next operation. 2.5 BLOCK ERASE Sector erase is a six-bus cycle operation. There are two "unlock" write cycles. These are followed by writing the set-up command 80H. Two more "unlock" write cycles are then followed by the sector erase command-30H. The sector address is latched on the falling edge of WE, while the command (data) is latched on the rising edge of WE. Only one sector can be erased at a time. Sector erase does not require the user to program the device prior to erase. The system is not required to provide any controls or timings during these operations. The AutomaticBlock Erase begins on the rising edge of the last WE pulse in the command sequence and terminates when the data on SR.7 is "1". When erasing a block, the remaining unselected blocks are unaffected.During the execution of the Block Erase command, only the Erase Suspend and Erase Resume commands are allowed. The Erase Suspend/Resume command may be issued as many time as required. Similar to the Chip Erase mode, the Status Register should be checked when erase is complete. MX29L8000T/B 2.6 ERASE SUSPEND AND RESUME The Erase Suspend command is provided to allow the user to interrupt an erase sequence and then read data from a block other than that which is being erased. This command is applicable only during the erase operation. During the erase operation, writing the Erase Suspend command to the CIR will cause the internal state machine to pause the erase sequence at a predetermined point. The Status Register will indicate when the erase operation has been suspended. Once in erase suspend, a Read Array command can be written to the CIR in order to read data from blocks not being erase suspended. The only other valid commands during erase suspend are Erase Resume and Read Status Register commands. Read Page Buffer command, however, is not applicable during erase suspend. To resume the erase operation, the Erase Resume command 30H should be written to the CIR. Another Erase Suspend command can be written after the chip has resumed erasing. 10vic MX29L8000T/B Table5. Status Register Bit Definition WSMS | ESS ES PS SLP SLK 7 6 5 4 2 1 NOTE : SR.7 = WRITE STATE MACHINE STATUS(WSMS) State machine bit must first be checked to determine 1 = Ready Program or Erase completion, before the Program or 0 = Busy Erase Status bits are checked for success. SR.6 = ERASE-SUSPEND STATUS (ESS) When Erase Suspend is issued, state machine halts 1 = Erase Suspended execution and sets both WSMS and ESS bits to"1," ESS 0 = Erase in Progress/Completed bit remains set to "1" until an Erase Resume command is issued. SR.5= ERASE STATUS When this bit set to "1," state machine has applied the 1 = Error in Erase maximum number of erase pulses tothe device andis still 0 = Successful Erasure unable to successfully verify erasure. $R.4= PROGRAM STATUS When this bit is set to "1," state machine has attempted 1 = Error in Page/Byte Program but failed to program page data. 0 = Successful Page/Byte Program SR.2 = SLEEP STATUS When thisbitis setto"1", the device is in sleep mode(deep 1 = Device in sleep mode power-down). Writing the Read Array command will 0 = Device not in sleep mode wake up the device, and the device will retum to standby. SR.3=0 SR.1 = Boot sector lock status 1: lock, 0: unlock Others = Reserved for future enhancements 2.7 STATUS REGISTER The device contains a Status Register which may be read to determine when a Program or Erase operation is complete, and whether that operation completed successfully. The Status Register may be read at any time by writing the Read Status command to the command interface. After writing this command, all subsequent Read operations output data from the Status Register until another command is written to the command interface. A Read Array command must be written to the command interface to return to the read array mode. The Status Register bits are output on DOQ[0:7]. The contents of the Status Register are latched on the falling edge of OE or CE, whichever occurs last in the read cycle. This prevents possible bus errors which might occur if the contents of the Status Register change while reading the Status Register. CE or OE must be toggled with each subsequent status read, or the completion of a Program or Erase operation will not be evident from the Status Register. When the state machine is active, this register will indicate the status of the state machine, and will also hold the bits indicating whether or not the state machine was successful in performing the desired operation. 2.7.1 CLEARING THE STATUS REGISTER The state machine sets status bits 4 through 7 to "1", and clears bits 6 and7 to"O", but cannot clear status bits 4 and 5to"0". Bits 4 and 5 can only be cleared by the controlling CPU through the use ofthe Clear Status Register command. These bits can indicate various error conditions. By allowing the system software to 11vic control the resetting of these bits, several operations may be performed (such as cumulatively program- ming several bytes or erasing multiple blocks in se- quence). The Status Register may then be read to determine if an error occurred during that programming or erasure series. This adds flexibility to the way the device may be programmed or erased. Once an error occurred, the command Interface only responds to clear Status Register, Read Status Register and Read Array. To clear the Status Regis- ter, the Clear Status Register command is written to the command interface. Then, any other command may he issued to the commandintertace. Note, again, that before read cycle can be initiated, a Read Array command mustbe written to the command interface to specify whether the read data is to come from the Memory Array, Status Register, Page Buffer, or silicon ID. 2.8 SLEEP MODE The MX2SL8000T/B features a sofware controlled low power modes: Sleep modes. Sleep mode is allowed during any current operations except that once Suspend command is issued, Sleep command is ignored. To activate Sleep mode, a three-bus cycle operation is required. The COH command (Refer to Table 3) puts the device in the Sleep made. Once in the Sleep mode and with CMOS input level applied, the power of the device is reduced to deep power-down current levels. The only power consumed is diffusion leakage, transistor subthreshold conduction, input leakage, and output leakage. The Sleep command allows the davice to complete its current operations before going into Sleep mode. During Sleep mode, Silicon ID codes remain valid and can still be read. The Device Sleep Status bit SR.2 will indicate that the device in the sleep mode. The device is in read SR. mode during sleep mode. Writing the Read Array command wakes up the device out of sleep mode. SR.2 is reset to "0" and device returns to standby current level. 2.9 PAGE BUFFER READ AND WRITE The MX29L8000T/B has 128 Bytes of page buffers, which can work as SRAM to store temporary data for fast access purpose. To write data into page buffers, the Write Page Buffer command is written tothe CIR. There are two "unlock'write cycles, followed by the command EQH. Loading data to page buffer is similar to that in Page MX29L8000T/B Program. Sequential loading is not required. AO to AG must be valid to specify byte address within the page buffers during each high-to-low transition of WE or CE. Each new byte to be stored must have its high-to-low transition of WE or CE within 30 us of the low-to-high transition of WE or CE of the preceding byte. Otherwise, the Write Page Buffer mode is terminated automatically. To read data from the page buffer, the Read Page Buffer command is written to the CIR. There are two "unlock" write cycles, which are followed by the command 75H. Each subsequent toggle of address (orOE, CE) willread data from the specified byte address of the page buffer (AO to A6). To terminate the operation, itis necessary to write the Read/Reset command sequence into the CIR. 3.0 DATA PROTECTION The MX?29L8000T/B is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. During power up the device automatically resets the internal state machine in the Read Array mode. Also, with its control register architecture, altaration of the memory contents only occurs after successful completion of specific multi-bus cycle command sequences. The device also incorporates several features toprevent inadvertent write cycles resulting from VCC power-up 3.1 16K-BLOCK LOCKING The MX29L8000T/B features hardware 16K-Block protection. This feature will disable both program and erase operationsin the 16K-Block. The block protection feature is enabled using system software by the user(Refer to Table 3). The device is shipped with 16K- Block unprotected. Alternatively, MXIC may protect 16K-Block in the factory prior to shipping the device. Execute lock bit protection operation three additional times after protect bit is verified successfully to guarantee lock bit status under all conditions. 3.1.1 LOCK BLOCK To activate this mode, a six-bus cycle operation is 12vic required. There are two'unlock' write cycles. These are followed by writing the 'set-up' command. Two more unlock write cycles are then followed by the Lock Sector command 20H. The automaticLock operation begins on the rising edge of the last WE pulse in the command sequence and terminates when the status on SR.7 is'1' at which time the device stays at the read mode. 3.1.2 LOCK STATUS READ To verify the Protect status of the 16K-Block, operation is initiated by writing Silicon ID read command into the command register. Following the commandwrite, aread cycle from address SA02H(see Table 3) retrieves the Manutacturer code of C2H if the 16K-Block is protected. Ifthe 16K-Block is unprotected, 00H willbe read instead. To terminate the operation, it is necessary to write the Read/Reset command sequence into the CIR. The lock status information can also be retrieved by reading SR... The $R.1 ="1" if 16K-Block islocked. The 8R.1 ="0" if 16K-Block is unlocked. A few retries are required if Protect status can not be veritied successtully after each operation. 3.2 HARDWARE PROTECTION Protection for parameter blocks and main blocks can be achieved using combinations of RP and WP pins. 3.2.1 RP = VIL FOR COMPLETE PROTECTION For complete data protection of all blocks, the RP can be held low. 3.2.2 WP = VIL FOR 16K-BLOCK LOCKING When WP = VIL, the 16K-block is locked, while all other blocks remain unlocked in this condition and can be programmed or erased normally. 3.2.3 WP = VHH FOR 16K-BLOCK UNLOCKING If WP = VHH, the 16K-Block is unlocked and can be programmed or erased. Note that this feature will override the 16K-Block Lock bit protection. 3.2.4 WP = VIH FOR REGULAR BLOCK MX29L8000T/B UNLOCKING lf WP = VIH and RP = VIH, all the regular blocks (parameter blocks and main blocks) are unlocked and can be programmed or erased. In this condition, whether the 16K-Block is locked is dependent on the 16K-Block Lock bit. If the 16K-Block Lock bit is enabled, then the 16K-Block is still protected; otherwise, itis unlocked. The following truth table clearly defines the write protection methods. Table 5. WRITE PROTECTION TRUTH TABLE FOR MX29L8000T/B RP | WP |16K-Block | Write Protection Provided Lockout bit) 16K-Block | Regular Block VIH | VHH x unlocked unlocked VIL 4 x locked locked VIH | VIL x locked unlocked VIH | VIH 1 locked unlocked VIH | VIH 0 unlocked unlocked 3.3 LOW VCC WRITE INHIBIT To avoid initiation of a write cycle during VCC power-up and power-down, a write cycle is locked out for VCC less than VLKO( typically 1.8V). If VCC < VLKO, the command register is disabled and all internal program/erase circuits are disabled. Under this condition the device will reset to the reaadmode. Subsequent writes will be ignored until the VCC level is greater than VLKO. It is the user's responsibility to ensure that the control pins are logically correct to prevent unintentional write when VCC is above VLKO. 3.4 WRITE PULSE "GLITCH" PROTECTION Noise pulses of less than 5ns (typical) on CE or WE will not initiate a write cycle. 3.5 LOGICAL INHIBIT Writing is inhibited by holding any one of OE = VIL,.CE = VIH or WE = VIH. To initiate_a write cycle CE and WE must be a logical zero while OE is a logical one. 13Mic MX29L8000T/B Figure 1. AUTO PAGE PROGRAM FLOW CHART START Write Program Crd Sequence Write Program Data/Addrasa Leading End? YES Read Stalus Register = NO YES YES Program Fail NO Page Program CompletedM=ic MX29L8000T/B Figure 2. AUTO ERASE FLOW CHART Write Erase Cmd Sequence J h A Read Status Register YES Ta Execute Suspend Mode ? Erase Suspend Flow (Figure 3.) Erase Completed 15Mic MX29L8000T/B Figure 3. ERASE SUSPEND/ERASE RESUME FLOW CHART START Write BOH : Read Status Register . { Erase Completed ) Erase Suspended Write FOH Read Array Done Reading Write 30H Erase Resumed 16Mic MX29L8000T/B Figure 4. 16K-BLOCK PROTECTION FLOW CHART START Write 16K-Block Protect Cmd Sequence Read Status Register a YES Sector Protect Completed Figure 5. VERIFY 16K-BLOCK PROTECT FLOW CHART START Write Verify-Protecion and Sequence Read Protect Status Note: 1. Protect Status: Data Outputs (G2H in byte mode, 0OC2H in word mode} if block is protected(lockout bit is enabled}. Data Outputs (00H in byte mode, OOOOH in word mode) otherwise 2, Silicon |D can be read via this Flow Chart. Refer to Table 4. 3. SR1 also contains the lock bit information Refer to Table 5. 4, Execute lock bit protection operation three additional times after protect bit is verified successfully to guarantee lock bit bit status under all conditions. 7vic 5.0 ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS RATING VALUE MX29L8000T/B OPERATING RANGES RATING VALUE Ambient Temperature oc to 7C(Comm.) -40C to 85C (Ind.) Ambient Temperature -40C to 85C Storage Temperature -65C to 125C Applied Input Voltage -0.5V to VOC + 4.5 Applied Output Voltage -0.5V to VOC + 0.6 VCC to Ground Potential -0.5V to 5.5V AS, WP -0.5V to 13.0V CAPACITANCE TA = 25C, f = 1.0 MHz Vcc Supply Voltage 2.7V to 3.6V NOTICE: 1.This document contains information on product in the dsign phase of development Revised information will be published when the product is available. 2.Specifications contained within the following tables are subject to change. WARNING: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is stress rating only and functional operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended period may affect reliability. SYMBOL PARAMETER MIN. TYP. MAX. UNIT CONDITIONS CIN Input Capacitance 14 pF VIN = OV COUT Output Capacitance 16 pF VOUT = 0V SWITCHING TEST CIRCUITS DEVIGE L-1 2.7KQ UNDER NY Ww 3.8V TEST CL DIODES = IN3064 S 6.2K 0 OR EQUIVALENT GL = 100 pF Including jig capacitance for 150/200ns GL = 50 pF for 120ns SWITCHING TEST WAVEFORMS 2.4V _f- . 2.0V TEST POINTS S. #0.8v 0.45V INPUT OUTPUT AC TESTING: Inputs are driven at 2.4V for a logic "1" and 0.45 for alogic "0". Input pulse rise and fall times are Sns. 18Mic MX29L8000T/B 5.1 DC CHARACTERISTICS Vcc = 2.7V to 3.6V SYMBOL PARAMETER NOTES MIN. TYP. MAX. UNITS TEST CONDITIONS HL Input Load 1 +1 HA VCC = VCC Max Current VIN = VCC or GND ILO Output Leakage 1 +10 pA VCC = VCC Max Current VIN = VCC or GND ISB1 VCG Standby 1 20 30 pA VEC = VCC Max Curren({CMOS} CE = VIH ISB2 VCC Standby 1 2 mA VOG = VOC Max Current(TTL) CE =VIH ioc VCC Read 1 20 35 mA VCC = VCC Max Current f= 10MHz, IOUT =OmA Icc2 VCC Erase 1,2 5 mA CE = VIH Suspend Current Block Erase Suspended Icc3 VCC Program 1 15 30 mA Program in Progress Current Icc4 VCC EraseCurrent 1 15 30 mA Erase in Progress IPPD VCC Deep Power-down 1 8 pA VOC = VCC Max Current RP = VIL VIL InputLow Voltage 3 -0.3 0.6 V VIH Input High Voltage 4 2.0 VCC+0.3 =V VOL Output Low Voltage 0.45 V IOL = 2.1mA, Vee = Vcc Min VOH Output High Voltage 24 V IOH = -100UA, Vee = Vee Min NOTES: 1. All currents are in RMS unless otherwise noted. Typical values at VOC = 3.0V,T = 25C. These currents are valid for all product versions (package and speeds). 2. IC C2 is specified with the device de-selected. Ifthe device is read while in erase suspend mode, current draw is the sum of ICC2 and ICC 1. 3. VIL min. = -1.0V for pulse width < 50ns. VIL min. = -2.0 for pulse width < 20ns. 4, Vidimax. = VCC + 1.5 for pulse width < 20ns. If VIH is over the specified maximum value, read operation cannotbe guaranteed. 19M=ie MX29L8000T/B 5.2 AC CHARACTERISTICS READ OPERATIONS 29L8000T/B-12 29L8000T/B-15 29L8000T/B-20 SYMBOL DESCRIPTIONS MIN. MAX. MIN. MAX. MIN. MAX. UNIT CONDITIONS tAcc Address to Output Delay 120(1) 150 200 2=ons CE=OE=VIL iCE CE to Output Delay 120(1) 150 200 ~ons OF=VIL tOE OE to Cutput Delay 60 75 100 ons TE=VIL tDF(2) OE High to Output Delay 0 55 0 55 0 55 ns CE-VIL tOH Address to Output hold 0 a) 0 ns CE=OE=VIL TEST CONDITIONS: NOTE: * Input pulse levels: 0.45V/2.4V 1. 120ns is the data while Vcc = 3.3V + 0.3V. When Vcc goes down to 2.7V, the value willbe 150ns. 2. iDF is defined as the time at which the output achieves the open circuit condition and data is no longer driven. * Input rise and fall times: 5ns * Outputload: 1TTL gate+100pFf{Including scope and jig) ((00pF loading for 150ns, 200ns read speed.) ( 50pF loading for 120ns read speed.) Reference levels for measuring timing: 1.5V 20N=Ic MX29L8000T/B Figure 6. READ TIMING WAVEFORMS Device and Standby Outputs Enabled Standay Veco Power-up address selection Data valid Voo Power-down VIH ADDRESSES ADDRESSES STABLE VIL VIH CE VIL VIH VIL OE VIH WE IL VOH DATA OUT Data out valid HIGH Z VOL 21vic MX29L8000T/B 5.3 AC CHARACTERISTICS WRITE/ERASE/PROGRAM OPERATIONS 29L8000T/B-12 29L8000-T/B15 29L8000-T/B20 SYMBOL DESCRIPTION MIN. MAX MIN. MAX. MIN. MAX. UNIT WC Write Cycle Time 120 150 200 ns tAS Address Setup Time 0 0 0 ns tAH Address Hold Time 60 60 60 ns DS Data Setup Time 50 50 50 ns (DH Data Hold Time 10 10 10 ns tOES Qutput Enable Setup Time 0 0 0 ns CES CE Setup Time 0 ) 0 ns tGHWL Read Recover Time Before Write 0 0 0 ns (Cs CE Setup Time 0 0 0 ns (CH CE Hold Time 0 0 0 ns twWP Write Pulse Width 60 60 60 ns tWPH Write Pulse Width High 40 40 40 ns (BALC Byte Address Load Cycle 0.2 0.2 30 0.2 30 ps (BAL Byte Address Load Time 100 100 100 js tSRA Status Register Access Time 120 150 200 ns 1CESR CE Setup before S.R. Read 100 100 100 ns tPHWL RP High Recovery to WE Going Low 1 1 1 ys VCS VCC Setup Time 2 2 2 Ls 22M=ic MX29L8000T/B Figure 7. COMMAND WRITE TIMING WAVEFORMS ADDRESSES DATA VGG 23Mic MX29L8000T/B Figure 8. AUTOMATIC PAGE PROGRAM/WRITE PAGE BUFFER TIMING WAVEFORMS AO-AG Byte cffset AT~A14 Page Address 2** A15~A19 Page Address 2 cE WE OE DATA Last Write RP NOTE: 1.Please refer to SECTION 2.3 for detail page program operation. **2 Page address is not required for Write Page Buffer 24Mic MX29L8000T/B Figure 9. AUTOMATIC BLOCK/CHIP ERASE TIMING WAVEFORMS ene Le LEER MERTEN ENE MEE ETE AO~A14 oy 5555H x 2AAAH x 5555H x 5555H x 2AAAH x 1 5555H i a = sm 1aS 1AH Latte! | a8 A13~A19 EICIIESO CHICO CEC CEC CECE ICCC SCAN SSO OO, ote Grete reheat rat erat eaten ra eR Pa aE Se SERS NTIS OTR ROCHE RIGHT RE IR SA oe Deck batre Gene cementarsene Genin orerteters ech tCESR . - J S D ) r / awe | [we =a , D a D D ] two - t m4 =| e _/ tbs {DH ee tSRA ; ~ DATA _{| AAH 55H an 80H on AAH 4 55H ){30H/10H { spp ) TPHWL et $n RP NOTES: 4."X" means "don't care in this diagram 2."SA" means "Block Address"(required for Block Erase only) 25Mic MX29L8000T/B 5.4 AC CHARACTERISTICS. WRITE/ERASE/PROGRAM OPERATIONS (Alternate CE Controlled) 29L8000T/B-12 29L8000T/B-15 29L8000T/B-20 SYMBOL DESCRIPTION MIN. MAX. MIN. MAX. MIN. MAX. UNIT twe Write Cycle Time 120 150 200 ns tAS Address Setup Time 10 10 10 ns tAH Address Hold Time 60 60 60 ns tDS Data Setup Time 50 50 50 ns {DH Data Hold Time 10 10 10 ns tOES Output Enable Setup Time 0 0 0 ns tCES CE Setup Time 0 0 0 ns tGHWL Read Recover TimeBefore Write 0 0 0 ns tws WE Setup Time 0 0 0 ns tWH WE Hold Time a 0 a ns tCP CE Pulse Width 60 60 60 ns tGPH GE Pulse Width High 40 40 40 ns VCS VGC Setup Time 2 2 2 Us 26Mic MX29L8000T/B Figure 10. COMMAND WRITE TIMING WAVEFORMS(Alternate CE Controlled) ADDRESSES DATA VOG 27vic = MxX29L8000T /B Figure 11. AUTOMATIC PAGE PROGRAM TIMING WAVEFORM(Alternate CE Controlled) AQ~A6 A7~A14 Page Address A15~A19 Page Address DATA Last Write 28vic MX29L8000T /B 5.5 ERASE AND PROGRAMMING PERFORMANCE LIMITS PARAMETER MIN. TYP. MAX. UNITS Chip/Sector Erase Time 50 ms Page Programming Time 5 ms Chip Programming Time 40 Sec Byte Program Time(average) 40 Hs Erase/Program Cycles 100,000 Cycles 5.6 LATCHUP CHARACTERISTICS MIN. MAX. Input Voltage with respect to GND on all pins except I/O pins -1.0V 13.5V Input Voltage with respect to GND on all I/O pins -1.0V Vee + 1.0V Current -100mA +100mA Includes all pins except Vcc. Test conditions: Vcc = 3.0V, one pin at a time. Revision History Revision # Description Date 1.1 Change from "Advance Information" to "Preliminary. 14/1997 1.2 Changes Program/Erase cycles from 1,000 to 1,000/10,000. 22/1997 Page 8: Table 4 "Verify 16K-block protect" : A18~-A2 X--->SA. 1.3 Write-Erase cycles change from 1,000/10,000 to 100,000. 10/29/1997 1.4 Adding Notes Item 8 on Page 7 to make the table more clear 01/12/1998 Al 8/ 29M=ic MX29L8000T/B MACRONIX INTERNATIONAL CO., LTD HEADQUARTERS : TEL : +886-3-578-8888 FAX : 4886-3-578-8887 EUROPE OFFICE: TEL : +32-2-456-8020 FAX : +32-2-456-8021 JAPAN OFFICE: TEL : +81-44-246-9100 FAX: +81-44-246-9105 SINGAPORE OFFICE : TEL: +65-747-2309 PAX : 465-748 4090 TAIPEI OFFICE : TEL : +886-2-2509-3300 FAX : 4886-2-2509-2200 MAC RONIX AMERICA INC. TEL : +1-408-453-8088 PAX : +1-408-453-8488 CHICAGO OFFICE : TEL : +1-847-963-1900 FAX : +1-847-963- 1909 hitp : //www.macronix.com MACRONIX INTERNA TIONAL COL, LTD. reserves the right te change produet and specifications without notice. 30