©2001 Fairchild Semiconductor Corporation HUF76113T3ST Rev. B
HUF76113T3ST
4.7A, 30V, 0.031 Ohm
,
N-Channel, Logic
Level UltraFET Power MOSFET
This N-Channel power MOSFET is
manufactured using the innovative
UltraFET process. This advanced
process technology achieves the
lowest possible on-resistance per silicon area, resulting in
outstanding performance. This device is capable of
withstanding high energy in the avalanche mode and the
diode exhibits very low reverse recovery time and stored
charge. It was designed for use in applications where power
efficiency is important, such as switching regulators, switching
converters, motor drivers, relay drivers, low-voltage bus
switches, and power management in portable and battery-
operated products.
Formerly developmental type TA76113.
Features
• Logic Level Gate Drive
• 4.7A, 30V
• Ultra Low On-Resistance, r
DS(ON)
= 0.031
Ω
• Temperature Compensating PSPICE
®
Model
• Temperature Compensating SABER™ Model
• Thermal Impedance SPICE Model
• Thermal Impedance SABER Model
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• Related Literature
- TB334, “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
Packaging
SOT-223
Ordering Information
PART NUMBER PACKAGE BRAND
HUF76113T3ST SOT-223 76113
NOTE: HUF76113T3ST is available only in tape and reel.
®
D
G
S
SOURCE
GATE
DRAIN
DRAIN
(FLANGE)
Data Sheet December 2001
©2001 Fairchild Semiconductor Corporation HUF76113T3ST Rev. B
Absolute Maximum Ratings
T
A
= 25
o
C, Unless Otherwise Specified
HUF76113T3ST UNITS
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DSS
30 V
Drain to Gate Voltage (R
GS
= 20k
Ω
) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DGR
30 V
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
GS
±
16 V
Drain Current
Continuous (T
A
= 25
o
C, V
GS
= 10V) (Figure 2) (Note 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
D
Continuous (T
A
= 100
o
C, V
GS
= 5V) (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
D
Continuous (T
A
= 100
o
C, V
GS
= 4.5V) (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
D
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I
DM
4.7
2.7
2.6
Figure 4
A
A
A
Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E
AS
Figure 6
Power Dissipation (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
D
Derate Above 25
o
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1
0.0091
W
W/
o
C
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
J
, T
STG
-55 to 150
o
C
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T
L
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
pkg
300
260
o
C
o
C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. T
J
= 25
o
C to 150
o
C.
Electrical Specifications
T
A
= 25
o
C, Unless Otherwise Specified
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
OFF STATE SPECIFICATIONS
Drain to Source Breakdown Voltage BV
DSS
I
D
= 250
µ
A, V
GS
= 0V (Figure 12) 30 - - V
Zero Gate Voltage Drain Current I
DSS
V
DS
= 25V, V
GS
= 0V - - 1
µ
A
V
DS
= 25V, V
GS
= 0V, T
C
= 150
o
C - - 250
µ
A
Gate to Source Leakage Current I
GSS
V
GS
=
±
16V - -
±
100 nA
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage V
GS(TH)
V
GS
= V
DS
, I
D
= 250
µ
A (Figure 11) 1 - 3 V
Drain to Source On Resistance r
DS(ON)
I
D
= 4.7A, V
GS
= 10V (Figure 9, 10) - 0.027 0.031 W
I
D
= 2.7A, V
GS
= 5V (Figure 9) - 0.033 0.038 W
I
D
= 2.6A, V
GS
= 4.5V (Figure 9) - 0.035 0.040 W
THERMAL SPECIFICATIONS
Thermal Resistance Junction to Ambient R
θ
JA
Pad Area = 0.173 in
2
(Note 2) - - 110
o
C/W
Pad Area = 0.068 in
2
(See TB377) - - 133
o
C/W
Pad Area = 0.026 in
2
(See TB377) - - 157
o
C/W
SWITCHING SPECIFICATIONS
(V
GS
= 4.5V)
Turn-On Time t
ON
V
DD
= 15V, I
D
≅
2.6A,
R
L
= 5.8
Ω
, V
GS
=
4.5V,
R
GS
= 18
Ω
(Figure 15)
- - 90 ns
Turn-On Delay Time t
d(ON)
-12-ns
Rise Time t
r
-46-ns
Turn-Off Delay Time t
d(OFF)
-31-ns
Fall Time t
f
-31-ns
Turn-Off Time t
OFF
- - 95 ns
HUF76113T3ST
©2001 Fairchild Semiconductor Corporation HUF76113T3ST Rev. B
SWITCHING SPECIFICATIONS
(V
GS
= 10V)
Turn-On Time t
ON
V
DD
= 15V, I
D
≅
4.7A,
R
L
= 3.2
Ω
, V
GS
=
10V,
R
GS
= 9.1
Ω
(Figure 16)
- - 40 ns
Turn-On Delay Time t
d(ON)
-4-ns
Rise Time t
r
-21-ns
Turn-Off Delay Time t
d(OFF)
-31-ns
Fall Time t
f
-25-ns
Turn-Off Time t
OFF
- - 85 ns
GATE CHARGE SPECIFICATIONS
Total Gate Charge Q
g(TOT)
V
GS
= 0V to 10V V
DD
= 15V, I
D
≅
2.7A,
R
L
= 5.5
Ω
I
g(REF)
= 1.0mA
(Figure 14)
- 17.0 20.5 nC
Gate Charge at 5V Q
g(5)
V
GS
= 0V to 5V - 9.5 11.5 nC
Threshold Gate Charge Q
g(TH)
V
GS
= 0V to 1V - 0.73 0.90 nC
Gate to Source Gate Charge Q
gs
- 1.50 - nC
Gate to Drain “Miller” Charge Q
gd
- 4.30 - nC
CAPACITANCE SPECIFICATIONS
Input Capacitance CISS VDS = 25V, VGS = 0V,
f = 1MHz
(Figure 13)
- 625 - pF
Output Capacitance COSS - 310 - pF
Reverse Transfer Capacitance CRSS -60-pF
NOTES:
2. Rated with RθJA=110oC/W measured using FR-4 board with 0.173 in2 copper at 1000 seconds.
Electrical Specifications TA = 25oC, Unless Otherwise Specified
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Source to Drain Diode Specifications
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Source to Drain Diode Voltage VSD ISD = 4.7A - - 1.25 V
ISD = 2.7A - - 1.00 V
Reverse Recovery Time trr ISD = 2.7A, dISD/dt = 100A/µs--44ns
Reverse Recovered Charge QRR ISD = 2.7A, dISD/dt = 100A/µs--46nC
Typical Performance Curves
FIGURE 1. NORMALIZED POWER DISSIPATION vs AMBIENT
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
AMBIENT TEMPERATURE
TA, AMBIENT TEMPERATURE (oC)
POWER DISSIPATION MULTIPLIER
0
0 25 50 75 100 150
0.2
0.4
0.6
0.8
1.0
1.2
125
0
1
2
3
4
5
25 50 75 100 125 150
ID, DRAIN CURRENT (A)
TA, AMBIENT TEMPERATURE (oC)
VGS = 4.5V, RθJA = 110oC/W
VGS = 10V, RθJA = 110oC/W
HUF76113T3ST
©2001 Fairchild Semiconductor Corporation HUF76113T3ST Rev. B
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
FIGURE 4. PEAK CURRENT CAPABILITY
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA
NOTE: Refer to Fairchild Application Notes AN9321 and AN9322.
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
CAPABILITY
Typical Performance Curves (Continued)
0.001
0.01
0.1
1
2
10-5 10-4 10-3 10-2 10-1 100101102103
t, RECTANGULAR PULSE DURATION (s)
ZθJA, NORMALIZED
THERMAL IMPEDANCE
SINGLE PULSE NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJA x RθJA + T
A
PDM
t1
t2
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.01
0.02
RθJA = 110oC/W
1
10
100
500
10-5 10-4 10-3 10-2 10-1 100101102103
IDM, PEAK CURRENT (A)
t, PULSE WIDTH (s)
VGS = 5V
RθJA = 110oC/W
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
TC = 25oC
I = I25 150 - TA
125
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
VGS = 10V
1
10
100
200
1 10 100
TJ = MAX RATED
100µs
10ms
1ms
VDSS(MAX) = 30V
VDS, DRAIN TO SOURCE VOLTAGE (V)
ID, DRAIN CURRENT (A)
LIMITED BY rDS(ON)
AREA MAY BE
OPERATION IN THIS
TA = 25oC
1
10
40
0.01 0.1 1 10 100
IAS, AVALANCHE CURRENT (A)
tAV, TIME IN AVALANCHE (ms)
STARTING TJ = 25oC
STARTING TJ = 150oC
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R = 0
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
HUF76113T3ST
©2001 Fairchild Semiconductor Corporation HUF76113T3ST Rev. B
FIGURE 7. TRANSFER CHARACTERISTICS FIGURE 8. SATURATION CHARACTERISTICS
FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
FIGURE 10. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
FIGURE 11. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
FIGURE 12. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
Typical Performance Curves (Continued)
0
5
10
15
20
25
30
012345
ID, DRAIN CURRENT (A)
VGS, GATE TO SOURCE VOLTAGE (V)
150oC
-55oC
25oC
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = 15V
0
5
10
15
20
25
30
01234
ID, DRAIN CURRENT (A)
VDS, DRAIN TO SOURCE VOLTAGE (V)
PULSE DURATION = 80µs
TA = 25oC
VGS = 5V
VGS = 10V
VGS = 4V
VGS = 3.5V
VGS = 3V
DUTY CYCLE = 0.5% MAX
30
40
50
60
70
80
468102
20
ID = 0.5A
VGS, GATE TO SOURCE VOLTAGE (V)
ID = 4.7A
PULSE DURATION = 80µs
rDS(ON), DRAIN TO SOURCE
ON RESISTANCE (mΩ)
DUTY CYCLE = 0.5% MAX
0.6
1.0
1.2
1.8
-80 -40 0 40 80 120 160
0.8
1.4
1.6
NORMALIZED DRAIN TO SOURCE
TJ, JUNCTION TEMPERATURE (oC)
ON RESISTANCE
VGS = 10V, ID = 4.7A
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
0.6
0.8
1.0
1.2
-80 -40 0 40 80 120 160
0.7
0.9
1.1
NORMALIZED GATE
TJ, JUNCTION TEMPERATURE (oC)
VGS = VDS, ID = 250µA
THRESHOLD VOLTAGE
0.9
1.0
1.1
1.2
-80 -40 0 40 80 120 160
TJ, JUNCTION TEMPERATURE (oC)
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
ID = 250µA
HUF76113T3ST
©2001 Fairchild Semiconductor Corporation HUF76113T3ST Rev. B
FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.
FIGURE 14. GATE CHARGE WAVEFORMS FOR CONSTANT
GATE CURRENT
FIGURE 15. SWITCHING TIME vs GATE RESISTANCE FIGURE 16. SWITCHING TIME vs GATE RESISTANCE
Typical Performance Curves (Continued)
0
200
400
600
800
1000
0 5 10 15 20 25 30
C, CAPACITANCE (pF)
VDS, DRAIN TO SOURCE VOLTAGE (V)
CISS
COSS
CRSS
VGS = 0V, f = 1MHz
CISS = CGS + CGD
CRSS = CGD
COSS = CDS + CGD
0
2
4
6
8
10
0 5 10 15 20
VGS , GATE TO SOURCE VOLTAGE (V)
VDD = 15V
Qg, GATE CHARGE (nC)
ID = 4.7A
ID = 0.5A
WAVEFORMS IN
DESCENDING ORDER:
0
20
40
60
80
100
0 1020304050
SWITCHING TIME (ns)
RGS, GATE TO SOURCE RESISTANCE (Ω)
VGS = 4.5V, VDD = 15V, ID = 2.6A, RL = 5.8Ω
tr
tf
td(OFF)
td(ON)
0
30
60
90
120
150
0 1020304050
SWITCHING TIME (ns)
RGS, GATE TO SOURCE RESISTANCE (Ω)
VGS = 10V, VDD = 15V, ID = 4.7A, RL = 3.2Ω
tr
tf
td(OFF)
td(ON)
Test Circuits and Waveforms
FIGURE 17. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 18. UNCLAMPED ENERGY WAVEFORMS
tP
VGS
0.01Ω
L
IAS
+
-
VDS
VDD
RG
DUT
VARY tP TO OBTAIN
REQUIRED PEAK IAS
0V
VDD
VDS
BVDSS
tP
IAS
tAV
0
HUF76113T3ST
©2001 Fairchild Semiconductor Corporation HUF76113T3ST Rev. B
Thermal Resistance vs. Mounting
Pad Area
The maximum rated junction temperature, TJM, and the
thermal resistance of the heat dissipating path determines
the maximum allowable device power dissipation, PDM, in an
application. Therefore the application’s ambient temperature,
TA (oC), and thermal resistance RθJA (oC/W) must be
reviewed to ensure that TJM is never exceeded. Equation 1
mathematically represents the relationship and serves as the
basis for establishing the rating of the part.
In using surface mount devices such as the SOT-223
package, the environment in which it is applied will have a
significant influence on the part’s current and maximum
power dissipation ratings. Precise determination of PDM is
complex and influenced by many factors:
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
2. The number of copper layers and the thickness of the
board.
3. The use of external heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
FIGURE 19. GATE CHARGE TEST CIRCUIT FIGURE 20. GATE CHARGE WAVEFORMS
FIGURE 21. SWITCHING TIME TEST CIRCUIT FIGURE 22. SWITCHING TIME WAVEFORM
Test Circuits and Waveforms (Continued)
RL
VGS +
-
VDS
VDD
DUT
Ig(REF)
VDD
Qg(TH)
VGS = 1V
Qg(5)
VGS = 5V
Qg(TOT)
VGS = 10
VDS
VGS
Ig(REF)
0
0
VGS
RL
RGS
DUT
+
-
VDD
VDS
VGS
tON
td(ON)
tr
90%
10%
VDS 90%
10%
tf
td(OFF)
tOFF
90%
50%
50%
10% PULSE WIDTH
VGS
0
0
(EQ. 1)
PDM
TJM TA
–()
ZθJA
-------------------------------=
HUF76113T3ST
©2001 Fairchild Semiconductor Corporation HUF76113T3ST Rev. B
Fairchild provides thermal information to assist the
designer’s preliminary application evaluation. Figure 23
defines the RθJA for the device as a function of the top
copper (component side) area. This is for a horizontally
positioned FR-4 board with 1oz copper after 1000 seconds
of steady state power with no air flow. This graph provides
the necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse applications
can be evaluated using the Fairchild device Spice thermal
model or manually utilizing the normalized maximum
transient thermal impedance curve. Displayed on the curve
are RθJA values listed in the Electrical Specifications table.
The points were chosen to depict the compromise between
the copper board area, the thermal resistance and ultimately
the power dissipation, PDM. The smallest areas represent
the minimum bond pad area and the package outline area
respectively as determined from the package diagram
Thermal resistances corresponding to other copper areas
can be obtained from Figure 23 or by calculation using
Equation 2. RθJA is defined as the natural log of the area
times a coefficient added to a constant. The area, in square
inches is the top copper area including the gate and source
pads.
The transient thermal impedance (ZθJA) is also effected by
varied top copper board area. Figure 24 shows the effect of
copper pad area on single pulse transient thermal
impedance. Each trace represents a copper pad area in
square inches corresponding to the descending list in the
graph. Spice and SABER thermal models are provided for
each of the listed pad areas.
Copper pad area has no perceivable effect on transient
thermal impedance for pulse widths less than 100ms. For
pulse widths less than 100ms the transient thermal
impedance is determined by the die and package.
Therefore, CTHERM1 through CTHERM5 and RTHERM1
through RTHERM5 remain constant for each of the thermal
models. A listing of the model component values is
available in Table 1.
FIGURE 23. THERMAL RESISTANCE vs MOUNTING PAD ARE
A
50
100
150
200
0.01 0.1 1
157oC/W - 0.026in2
AREA, TOP COPPER AREA (in2)
RθJA (oC/W)
133oC/W - 0.068in2
110oC/W - 0.173in2
RθJA = 65.3 - 25 * ln(AREA)
(EQ. 2)
RθJA 65.3 25 Area()ln×–=
FIGURE 24. THERMAL IMPEDANCE vs MOUNTING PAD AREA
0
20
40
60
80
100
120
10-1 100101102103
t, RECTANGULAR PULSE DURATION (s)
ZθJA, THERMAL
IMPEDANCE (oC/W)
COPPER BOARD AREA - DESCENDING ORDER
0.077 in2
0.308 in2
0.535 in2
0.760 in2
0.996 in2
HUF76113T3ST
©2001 Fairchild Semiconductor Corporation HUF76113T3ST Rev. B
PSPICE Electrical Model
.SUBCKT HUF76113T3 2 1 3 ; REV August 1998
CA 12 8 8.7e-10
CB 15 14 8.7e-10
CIN 6 8 5.6e-10
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
EBREAK 11 7 17 18 34.3
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
IT 8 17 1
LDRAIN 2 5 1e-9
LGATE 1 9 1.69e-9
LSOURCE 3 7 4.1e-10
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 9.2e-3
RGATE 9 20 2.5
RLDRAIN 2 5 10
RLGATE 1 9 16.9
RLSOURCE 3 7 4.1
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 12.5e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*180),2.5))}
.MODEL DBODYMOD D (IS = 9.35e-13 RS = 1.39e-2 TRS1 = 1.12e-6 TRS2 = 1.05e-6 CJO = 9.85e-10 TT = 2.82e-8 M = 0.42)
.MODEL DBREAKMOD D (RS = 1.5e-1 TRS1 = 3.51e-3 TRS2 = -5e-5)
.MODEL DPLCAPMOD D (CJO = 4.4e-10 IS = 1e-30 N = 10 M = 0.6)
.MODEL MMEDMOD NMOS (VTO = 1.95 KP = 3.55 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 2.5)
.MODEL MSTROMOD NMOS (VTO = 2.23 KP = 29 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 1.68 KP = 0.095 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 25 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 9.7e-4 TC2 = -5e-7)
.MODEL RDRAINMOD RES (TC1 = 5.8e-3 TC2 = 1.12e-5)
.MODEL RSLCMOD RES (TC1 = -9.92e-3 TC2 = -2.06e-5)
.MODEL RSOURCEMOD RES (TC1 = 3e-3 TC2 = 0)
.MODEL RVTHRESMOD RES (TC = -1.2e-3 TC2 = -5.42e-6)
.MODEL RVTEMPMOD RES (TC1 = -1.9e-3 TC2 = 1e-6)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -7.0 VOFF = -1.5)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -1.5 VOFF = -7.0)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -0.8 VOFF = 0.6)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.6 VOFF = -0.8)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
18
22
+-
6
8
+
-
5
51
+
-
19
8
+-
17
18
6
8
+
-
5
8+
-
RBREAK
RVTEMP
VBAT
RVTHRES
IT
17 18
19
22
12
13
15
S1A
S1B
S2A
S2B
CA CB
EGS EDS
14
8
13
8
14
13
MWEAK
EBREAK DBODY
RSOURCE
SOURCE
11
73
LSOURCE
RLSOURCE
CIN
RDRAIN
EVTHRES 16
21
8
MMED
MSTRO
DRAIN
2
LDRAIN
RLDRAIN
DBREAK
DPLCAP
ESLC
RSLC1
10
5
51
50
RSLC2
1
GATE RGATE
EVTEMP
9
ESG
LGATE
RLGATE
20
+
-
+
-
+
-
6
HUF76113T3ST
©2001 Fairchild Semiconductor Corporation HUF76113T3ST Rev. B
SABER Electrical Model
REV October 1998
template huf76113T3 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
d..model dbodymod = (is = 9.35e-13, cjo = 9.85e-10, tt = 2.82e-8, m = 0.42)
d..model dbreakmod = ()
d..model dplcapmod = (cjo = 4.4e-10, is = 1e-30, n = 10, m = 0.6)
m..model mmedmod = (type=_n, vto = 1.95, kp = 3.55, is = 1e-30, tox = 1)
m..model mstrongmod = (type=_n, vto = 2.23, kp = 29, is = 1e-30, tox = 1)
m..model mweakmod = (type=_n, vto = 1.68, kp = 0.095, is = 1e-30, tox = 1)
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -7.0, voff = -1.5)
sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -1.5, voff = -7.0)
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -0.8, voff = 0.6)
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.6, voff = -0.8)
c.ca n12 n8 = 8.7e-10
c.cb n15 n14 = 8.7e-10
c.cin n6 n8 = 5.6e-10
d.dbody n7 n71 = model=dbodymod
d.dbreak n72 n11 = model=dbreakmod
d.dplcap n10 n5 = model=dplcapmod
i.it n8 n17 = 1
l.ldrain n2 n5 = 1e-9
l.lgate n1 n9 = 1.69e-9
l.lsource n3 n7 = 4.1e-10
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
res.rbreak n17 n18 = 1, tc1 = 9.7e-4, tc2 = -5e-7
res.rdbody n71 n5 = 1.39e-2, tc1 = 1.12e-6, tc2 = 1.05e-6
res.rdbreak n72 n5 = 1.5e-1, tc1 = 3.51e-3, tc2 = -5e-5
res.rdrain n50 n16 = 9.2e-3, tc1 = 5.8e-3, tc2 = 1.12e-5
res.rgate n9 n20 = 2.5
res.rldrain n2 n5 = 10
res.rlgate n1 n9 = 16.9
res.rlsource n3 n7 = 4.1
res.rslc1 n5 n51 = 1e-6, tc1 = -9.92e-3, tc2 = -2.06e-5
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 12.5e-3, tc1 = 3e-3, tc2 = 0
res.rvtemp n18 n19 = 1, tc1 = -1.9e-3, tc2 = 1e-6
res.rvthres n22 n8 = 1, tc1 = -1.2e-3, tc2 = -5.42e-6
spe.ebreak n11 n7 n17 n18 = 34.3
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/180))** 2.5))
}
}
18
22
+-
6
8
+
-
19
8
+-
17
18
6
8
+
-
5
8+
-
RBREAK
RVTEMP
VBAT
RVTHRES
IT
17 18
19
22
12
13
15
S1A
S1B
S2A
S2B
CA CB
EGS EDS
14
8
13
8
14
13
MWEAK
EBREAK
DBODY
RSOURCE
SOURCE
11
73
LSOURCE
RLSOURCE
CIN
RDRAIN
EVTHRES 16
21
8
MMED
MSTRO
DRAIN
2
LDRAIN
RLDRAIN
DBREAK
DPLCAP
ISCL
RSLC1
10
5
51
50
RSLC2
1
GATE RGATE
EVTEMP
9
ESG
LGATE
RLGATE
20
+
-
+
-
+
-
6
RDBODY
RDBREAK
72
71
HUF76113T3ST
©2001 Fairchild Semiconductor Corporation HUF76113T3ST Rev. B
SPICE Thermal Model
REV August 1998
HUF76113T3ST
Copper Area = 0.077 in2
CTHERM1 th 8 1.9e-5
CTHERM2 8 7 9.5e-4
CTHERM3 7 6 1.9e-3
CTHERM4 6 5 3.5e-3
CTHERM5 5 4 2.0e-2
CTHERM6 4 3 6.5e-2
CTHERM7 3 2 2.4e-1
CTHERM8 2 tl 9.0e-1
RTHERM1 th 8 3.5e-3
RTHERM2 8 7 3.1e-2
RTHERM3 7 6 2.0e-1
RTHERM4 6 5 8.0e-1
RTHERM5 5 4 2.1
RTHERM6 4 3 11
RTHERM7 3 2 32
RTHERM8 2 tl 66
SABER Thermal Model
Copper Area = 0.077 in2
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 8 = 1.9e-5
ctherm.ctherm2 8 7 = 9.5e-4
ctherm.ctherm3 7 6 = 1.9e-3
ctherm.ctherm4 6 5 = 3.5e-3
ctherm.ctherm5 5 4 = 2.0e-2
ctherm.ctherm6 4 3 = 6.5e-2
ctherm.ctherm7 3 2 = 2.4e-1
ctherm.ctherm8 2 tl = 9.0e-1
rtherm.rtherm1 th 8 = 3.5e-3
rtherm.rtherm2 8 7 = 3.1e-2
rtherm.rtherm3 7 6 = 2.0e-1
rtherm.rtherm4 6 5 = 8.0e-1
rtherm.rtherm5 5 4 = 2.1
rtherm.rtherm6 4 3 = 11
rtherm.rtherm7 3 2 = 32
rtherm.rtherm8 2 tl = 66
}
RTHERM6
RTHERM8
RTHERM7
RTHERM5
RTHERM4
RTHERM3
CTHERM4
CTHERM6
CTHERM5
CTHERM3
CTHERM2
CTHERM1
tl
2
3
4
5
6
7
JUNCTION
AMBIENT
8
th
RTHERM2
RTHERM1
CTHERM7
CTHERM8
TABLE 1. THERMAL MODELS
COMPONENT 0.077 in20.308 in20.535 in20.76 in20.996 in2
CTHERM6 6.5e-2 6.7e-2 6.7e-2 6.7e-2 6.7e-2
CTHERM7 2.4e-1 3.5e-1 3.5e-1 3.5e-1 3.5e-1
CTHERM8 9.0e-1 1.7 1.9 2 2.4
RTHERM6 11 9999
RTHERM7 32 18 16 15.5 14.5
RTHERM8 66 45.5 40 36 31.5
HUF76113T3ST
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER
NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.
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The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification Product Status Definition
Advance Information
Preliminary
No Identification Needed
Obsolete
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
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OPTOLOGIC™
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PACMAN™
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STAR*POWER is used under license
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