M48ST59W-100MH6TR - STMicroelectronics, Inc.

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PRELIMINARY DATA

January 2001

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

M48ST59W

64 Kbit (8 Kbit x 8) SUPERVISORY TIMEKEEPERSRAM

FEATURES SUMMARY

■2.7V to 3.6V OPERATING VOLTAGE

■INTEGRATED ULTRA-LOW POWER SRAM,

REAL TIME CLOCK (RTC), POWER-FAIL

CONTROL CIRCUIT, CRYSTAL, and

BATTERY

■1.25V REFERENCE (for PFI/PFO)

■AUTOMATIC POWER-FAIL CHIP DESELECT

and WRITE PROTECTION

■WRITE PROTECT VOLTAGES

■VPFD (Power-fail Deselect Voltage):

M48ST59W: 2.50V ≤VPFD ≤2.70V

■MICROPROCESSOR POWER-ON RESET

(Valid even during battery back-up mode)

■PROGRAMMABLE ALARM and INTERRUPT

FUNCTION (valid even during battery back-up

mode).

■BYTEWIDE, RAM-LIKE CLOCK ACCESS

■BCD CODED YEAR, MONTH, DAY, DATE,

HOURS, MINUTES, and SECONDS

■FREQUENCY TEST OUTPUT FOR RTC

CALIBRATION

■BATTERY LOW FLAG

■PROGRAMMABLE TREC

■PACKAGING INCLUDES a44-LEADSOIC and

SNAPHAT TOP (to be ordered separately)

■SOIC PACKAGE PROVIDES DIRECT

CONNECTION for a SNAPHAT TOP which

CONTAINS the BATTERY and CRYSTAL

Figure 1. Package

SNAPHAT (SH)

Battery & Crystal

SO44 (MH)

M48ST59W

2/29

TABLE OF CONTENTS

SUMMARY DESCRIPTION. . . . . . . . ...................................................4

Logic Diagram (Figure 2.) . . . . . . ...................................................4

Signal Names (Table 1.) . . ........................................................4

SOIC Pin Connections (Figure 3.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ............4

Block Diagram (Figure 4.) . . . . . . . . . . . . . ............................................5

OPERATING MODES . . . . . . . . . . . . . . . . . . . ............................................6

Operating Modes (Table 2.). . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . 6

Read Mode . . . .................................................................8

Read Mode AC Waveforms (Figure 5.) . . . . . . . ........................................8

Read Mode AC Characteristics (Table 4.). ............................................8

Write Mode . . . . . . . . . . . . . . . . . . . . . . . . ............................................9

Write Mode AC Waveforms (Figure 6.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ............9

Chip Enable Controlled, Write Mode AC Waveforms (Figure 7.) . . . ........................9

Write Mode AC Characteristics (Table 5.) . ...........................................10

Data Retention Mode. . . . . .......................................................11

Power-On Reset . . . . . . . . .......................................................11

Programmable Interrupts. . . . . . . . . . . ..............................................11

Interrupt Reset Waveforms (Figure 8.) . . . ...........................................11

CLOCK OPERATIONS . . . ..........................................................12

Reading the Clock. . . . . . . . . . . . . . . . . . . ...........................................12

Setting the Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...................................12

Stopping and Starting the Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Calibrating the Clock . . . . . . ......................................................12

Crystal Accuracy Across Temperature(Figure 9.) . . . . .................................13

Clock Calibration (Figure 10.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...........13

Setting Alarm Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . .................................14

Alarm Repeat Mode(Table 6.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...........14

Back-up Mode Alarm Waveform (Figure 11.) . . . . . .. . . . . . . . . . . . . . . . . . . . . ..............14

Watchdog Timer . ..............................................................15

Battery Low Flag . . . . . . . . .......................................................15

Power-Fail Comparator . .........................................................15

Adding Hysteresis (Figure 12.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....16

Hysteresis on Rising VIN (Figure 13.) . . . . . . . . . . . . . . . . . ..............................16

Century Bit. . . . . . . . . . . . . . ......................................................17

TREC Bit . . . . . . . ..............................................................17

tREC Definitions POWER-ON (Table 7.). . ...........................................17

Power-on Reset. . . .. . . . . . . . . . . . . . . . . ...........................................17

Initial Power-On Defaults. . . . . . . . . . . . . . ...........................................17

Default Values (Table 8.). . . . . . . . . . . . . . . . . . . . . . ...................................17

3/29

M48ST59W

POWER SUPPLY DECOUPLING AND UNDERSHOOT PROTECTION. . . . . . . . . . . . . . . . . . . . . . . 18

Supply Voltage Protection (Figure 14.) . . . ...........................................18

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . ...........................................19

Absolute Maximum Ratings (Table 9.) ..............................................19

DC AND AC PARAMETERS. . . . . . . ..................................................20

DC and AC Measurement Conditions (Table 10.). . . ...................................20

AC Testing Load Circuit (Figure 15.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . 20

Capacitance (Table 11.) . . .......................................................20

DC Characteristics(Table 12.) . . ..................................................21

Power Down/Up Mode AC Waveforms(Figure 16.) . . . . . . . . . . . . . . .. . . . . . . . . . ...........22

Power Down/Up Trip Points DC Characteristics (Table 13.). . . . . . . . . . . . . . . . . . . . . . . . . . ....22

Power Down/Up AC Characteristics(Table 14.) . . . . . . . . . . . . . . . . . .. . . . . . . . . . ...........23

PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

PART NUMBERING . . . . . . . . . ......................................................27

REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . ....................................28

M48ST59W

4/29

SUMMARY DESCRIPTION

The M48ST59W SUPERVISORY TIMEKEEPER

RAM is an 8Kbit x 8 non-volatile static RAM and

real time clock. The monolithic chip is available in

a surface mount package to provide a highly inte-

grated battery backed-up memory and real time

clock solution. The 44-pin, 330mil SOIC package

provides sockets with gold-plated contacts at both

ends for direct connection to a separate

SNAPHAT housing containing the battery and

crystal. The unique design allows the SNAPHAT

battery package to be attached after the surface

mount process.

Insertion of the SNAPHAT housing after reflow

prevents potential battery andcrystal damage due

to the high temperatures required for device sur-

face-mounting. TheSNAPHAT housing is keyed to

prevent reverse insertion. The SOIC and battery/

crystal packages areshipped separately in plastic,

anti-static tubes or in Tape & Reel form (see Table

18, page 27) for the part numbering scheme.)

The battery/crystal package (e.g., SNAPHAT) part

number is “M4T28-BR12SH” or “M4T32-

BR12SH”.

Caution: Donotplacethe SNAPHAT battery/crys-

tal package “M4TXX-BR12SH” in conductive

foam, as this will drain the lithium button-cell bat-

tery.

Figure 2. Logic Diagram

Table 1. Signal Names

Figure 3. SOIC Pin Connections

A0-A12 Address inputs

DQ0–DQ7 Data Inputs/Outputs

IRQ/FT Interrupt/Frequency TestOutput

(Open Drain)

RST Reset Output (Open Drain)

E Chip Enable

G Output Enable Input

W Write Enable Input

PFO Power Fail Output

PFI Power Fail Input

VCC Supply VoltageInput

VSS Ground

A0-A12

DQ0-DQ7

VCC

M48ST59W

VSS

PFI

PFO

RST

IRQ/FT

AI04600

VSS

A11

VCC

M48ST59W

A6 IRQ/FT

PFI

RST DQ7

DQ5

DQ0

DQ1 DQ3

DQ4

DQ6

PFO

A12

A10

DQ2

AI04601

5/29

M48ST59W

Figure 4. Block Diagram

LITHIUM

CELL

OSCILLATOR AND

CLOCK CHAIN

VPFD

VCC VSS

32,768 Hz

CRYSTAL

VOLTAGE SENSE

AND

SWITCHING

CIRCUITRY

16 x 8 TIMEKEEPER

REGISTERS

8,176 x 8

SRAM ARRAY

A0-A12

DQ0-DQ7

POWER

PFO

1.25V

PFI

RST

IRQ/FT

AI04602

M48ST59W

6/29

OPERATING MODES

The static memory array and the quartz-controlled

clock oscillator of the M48ST59W are integrated

on one silicon chip (see Figure 4, page 5). The

memory locations used to provide user accessible

BYTEWIDEclock information are in the bytes

with addresses 1FFFh-1FF9h (see Table 3, page

7). These clock locations contain the century,

year, month, date, day, hour, minute, and second

in 24 hour, BCD format. Corrections for 28, 29

(leap year - compliant until the year 2100), 30, and

31 day months are made automatically.

Byte 1FF8h isthe clock control register. This byte

controls user access to the clock information and

also stores the clock calibration setting.

The eight clock bytes are not the actual clock

counters themselves; they are memory locations

consisting of BiPORT read/write memory cells.

The M48ST59W includes a clock control circuit

which updates the clock bytes with current infor-

mation approximately once per second. The infor-

mation can be accessed by the user in the same

manner as any other location in the static memory

array.

The M48ST59W also has its own Power-fail De-

tect circuit. The control circuitry constantly moni-

tors the single VCC supply for an out of tolerance

condition. When VCC is out of tolerance, the circuit

writes protects the SRAM, providing a high degree

of data security in the midst of unpredictable sys-

tem operation brought on by low VCC.AsV

CC falls

below VSO, the control circuitry connects the bat-

tery which maintains data and clock operation until

valid power returns.

Table 2. Operating Modes

Note: X = VIH or VIL;V

SO = Battery Back-up Switchover Voltage.

1. See Table 13 on page 22.

Symbol VCC E G W DQ7 – DQ0 Power

Deselect

2.7 to 3.6V

VIH X X High Z Standby

Write VIL XVIL DIN Active

Read VIL VIL VIH DOUT Active

Read VIL VIH VIH High Z Active

Deselect VSO to VPFD (min)(2) X X X High Z CMOS Standby

Deselect ≤VSO X X X High Z Battery Back-up Mode

7/29

M48ST59W

Table 3. Register Map

Keys: S = SIGN Bit

FT = FREQUENCY TEST Bit

R = READ Bit

W = WRITE Bit

ST = STOP Bit

0 = Must be set to zero

Y = ’1’ or ’0

Z = ’0’ and are Read only

AF = Alarm Flag

BL = Battery Low

WDS = Watchdog Steering Bit

BMB0-BMB4 = Watchdog Multiplier Bits

RB0-RB1 = Watchdog Resolution Bits

AFE = Alarm Flag Enable

ABE = Alarm in Battery Back-up Mode Enable

RPT1-RPT4 = Alarm Repeat Mode Bits

WDF = Watchdog Flag

CEB = Century Enable Bit

CB = Century Bit

TR = TREC Bit

Address Data Function/Range

BCD Format

D7 D6 D5 D4 D3 D2 D1 D0

1FFFh 10 Years Year Year 00-99

1FFEh 0 0 0 10 M Month Month 01-12

1FFDh 0 0 10 Date Date Date 01-31

1FFCh TR FT CB CEB 0 Day Century/

Day 00-01/

01-07

1FFBh 0 0 10 Hours Hours Hour 00-23

1FFAh 0 10 Minutes Minutes Minutes 00-59

1FF9h ST 10 Seconds Seconds Seconds 00-59

1FF8h W R S Calibration Control

1FF7h WDS BMB4 BMB3 BMB2 BMB1 BMB0 RB1 RB0 Watchdog

1FF6h AFE Y ABE Y Y Y Y Y Interrupts

1FF5h RPT4 Y Al. 10 Date Alarm Date Alarm Date 01-31

1FF4h RPT3 Y Al. 10 Hours Alarm Hours Alarm

Hours 00-23

1FF3h RPT2 Alarm 10 Minutes Alarm Minutes Alarm

Minutes 00-59

1FF2h RPT1 Alarm 10 Seconds Alarm Seconds Alarm

Seconds 00-59

1FF1h YYYYYYYYUnused

1FF0h WDF AF Z BL ZZZZFlags

M48ST59W

8/29

Read Mode

The M48ST59W is in the Read Mode whenever

Write Enable (W) is high and Chip Enable (E) is

low. The unique address specified by the 13 Ad-

dress Inputs defines which one of the 8,176 bytes

of data is to be accessed. Valid data will be avail-

able at the Data I/O pins within Address Access

Time (tAVQV) after the last address input signal is

stable, providing that the E and Output Enable (G)

access times are also satisfied. If the E and G ac-

cess times are not met, valid data will be available

after the latter of the Chip Enable Access Time

(tELQV) or Output Enable Access Time (tGLQV).

The state of the eight three-state Data I/O signals

is controlled by E and G. If the outputs are activat-

ed before tAVQV, the data lines will be driven to an

indeterminate state until tAVQV. If the Address In-

puts are changed while E and G remain active,

output data will remain valid for Output Data Hold

Time (tAXQX) but will be indeterminate until the

next Address Access.

Figure 5. Read Mode AC Waveforms

Table 4. Read Mode AC Characteristics

Note: 1. CL= 50 pF (see Figure 15, page 20).

2. CL= 5 pF (see Figure 15, page 20).

Symbol Parameter

M48ST59W

Unit-70

Min Max

tAVAV Read Cycle Time 70 ns

tAVQV(1) Address Valid to Output Valid 70 ns

tELQV(1) Chip Enable Low to Output Valid 70 ns

tGLQV(1) Output Enable Low to Output Valid 35 ns

tELQX(2) Chip Enable Low to Output Transition 5 ns

tGLQX(2) Output Enable Low to Output Transition 5 ns

tEHQZ(2) Chip Enable High to Output Hi-Z 25 ns

tGHQZ(2) Output Enable High to Output Hi-Z 25 ns

tAXQX(1) Address Transition to Output Transition 10 ns

VALID

A0-A12

DQ0-DQ7

VALID

tAVAV

tAVQV

tELQV

tAXQX

tEHQX

tELQX

tGLQV tGHQZ

tGLQX

AI04606

9/29

M48ST59W

Write Mode

The M48ST59W is in the Write Mode wheneverW

and E are low. The start of a write is referenced

from the latter occurring falling edge of W or E. A

write is terminated by the earlier rising edge of W

or E. The addresses must be held valid throughout

the cycle. E or W must return high for a minimum

of tEHAX from Chip Enable or tWHAX from Write En-

able prior to the initiation of another read or write

cycle. Data-in must be valid tDVWH priorto the end

of write and remain valid for tWHDX afterward. G

should be kept high during write cycles to avoid

bus contention; although, if the output bus has

been activatedby alow on Eand G alow onW will

disable the outputs tWLQZ after W falls.

Figure 6. Write Mode AC Waveforms

Figure 7. Chip Enable Controlled, Write Mode AC Waveforms

DATA INPUT

A0-A12

DQ0-DQ7

VALID

tAVAV

tAVWH

tAVEL

tWLQZ

tWHAX

tWLWH

tWHQX

tWHDX

tDVWH

tAVWL

AI04607

A0-A12

DQ0-DQ7

VALID

DATA INPUT

tAVAV

tAVEL

tAVWL

tAVEH

tELEH tEHAX

tEHDX

tDVEH AI04608

M48ST59W

10/29

Table 5. Write Mode AC Characteristics

Note: 1. CL= 5pF (see Figure 15, page 20).

2. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.

Symbol Parameter

M48ST59W

Unit-70

Min Max

tAVAV Write Cycle Time 70 ns

tAVWL Address Valid to Write Enable Low 0 ns

tAVEL Address Valid to Chip Enable Low 0 ns

tWLWH Write Enable Pulse Width 50 ns

tELEH Chip Enable Low to Chip Enable High 55 ns

tWHAX Write Enable High to Address Transition 0 ns

tEHAX Chip Enable High to Address Transition 0 ns

tDVWH Input Valid to Write Enable High 30 ns

tDVEH Input Valid to Chip Enable High 30 ns

tWHDX Write Enable High to Input Transition 5 ns

tEHDX Chip Enable High to Input Transition 5 ns

tWLQZ (1, 2) Write Enable Low to Output Hi-Z 25 ns

tAVWH Address Valid to Write Enable High 60 ns

tAVE1H Address Valid to Chip Enable High 60 ns

tWHQX (1, 2) Write Enable High to Output Transition 5 ns

11/29

M48ST59W

Data Retention Mode

With valid VCC applied, the M48ST59W operates

as a conventional BYTEWIDEstatic RAM.

Should the supply voltage decay, the RAMwill au-

tomatically power-fail deselect, write protecting it-

self when VCC within the VPFD (max), VPFD (min)

window. All outputs become high impedance, and

all inputs are treated as “don’t care.”

Note: A power failure during a writecycle may cor-

rupt data at the currently addressed location, but

does notjeopardize the rest of the RAM’s content.

At voltages below VPFD(min), the user can be as-

sured thememory will be ina writeprotected state,

provided the Vcc fall time is not less than tF.The

M48ST59W mayrespond to transientnoise spikes

on VCC that reachinto the deselect window during

the time the device is sampling VCC. Therefore,

decoupling of the power supply lines is recom-

mended.

When VCC drops below VSO, the control circuit

switches power to the internal battery which pre-

serves data and powers the clock. The internal

button cell will maintain data in the M48ST59W for

an accumulated period of tDR (at room tempera-

ture when VCC is less than VSO; see Table 13,

page 22). As system power returns and VCC rises

above VSO, the battery is disconnected, and the

power supply is switched to external VCC. Normal

RAM operation can resume tREC after VCC reach-

es VPFD(max).

For more information on Data Retention Storage

Life refer to the Application Note AN1012.

Power-On Reset

The M48ST59W continuously monitors VCC.

When VCC falls to the power fail detect trip point,

the RST pulls low (open drain) and remains low on

power-up for 40ms to 200ms after VCC passes

VPFD. RST is valid for all VCC conditions. The RST

pin is an open drain output and an appropriate re-

sistor toVCC shouldbe chosen tocontrol rise time.

Programmable Interrupts

The M48ST59W provides two programmable in-

terrupts; an alarm and a watchdog. When an inter-

rupt condition occurs, the M48ST59W sets the

appropriate flag bit in the flag register 1FF0h. The

interrupt enable bits (AFE and ABE) in 1FF6h and

the Watchdog Steering bit (WDS) in 1FF7h allow

the interrupt to activate the IRQ/FT pin.

The interrupt flags and the IRQ/FT output are

cleared by a read to the flags register. An interrupt

condition reset will not occur unless the addresses

are stable at the flag location for at least 15ns

while the device is in theread mode(see Figure 8,

page 11).

The IRQ/FT pin is an open drain output and re-

quires a pull-up resistor (10k

Ω

recommended) to

VCC. The pin remains in the high impedance state

unless an interrupt occurs or the frequency test

mode is enabled.

Figure 8. Interrupt Reset Waveforms

15 ns Min

A0-A12

ACTIVE FLAG BIT

IRQ/FT

ADDRESS 1FF0h

HIGH-Z

AI04609

M48ST59W

12/29

CLOCK OPERATIONS

Reading the Clock

Updates to the TIMEKEEPER registers should be

halted before clock data is read to prevent reading

data in transition. Because the BiPORT TIME-

KEEPER cells in the RAM array are only data reg-

isters, and not the actual clock counters, updating

the registers can be halted without disturbing the

clock itself.

Updating is halted when a ’1’ is written to the

READ bit, D6 in the Control register (1FF8h). As

long as a ’1’ remains in that position, updating is

halted.

After a halt is issued, the registers reflect the

count; that is, theday, date, and thetime that were

current at the moment the halt command was is-

sued.

All of the TIMEKEEPER registers are updated si-

multaneously. A halt will not interrupt an update in

progress. Updating occurs within a second after

the bit is reset to a ’0’.

Setting the Clock

Bit D7 of the Control register (1FF8h) is the

WRITE bit. Setting the WRITE bit to a ’1’, like the

READ bit, halts updates to the TIMEKEEPER reg-

isters. The user can then load them with the cor-

rect day, date, and time data in 24 hour BCD

format (see Table 3, page 7).

Resetting the WRITE bit to a ’0’then transfers the

values of all time registers (1FF9h-1FFFh) to the

actual TIMEKEEPER counters and allows normal

operation to resume. After the WRITE bit is reset,

the next clock update will occur within approxi-

mately one second.

Note: Upon power-up following a power failure,

both the WRITE bit and the READ bit will be reset

to ‘0’.

Stopping and Starting the Oscillator

The oscillator may be stopped at any time. If the

device is going to spend a significant amount of

time on the shelf, the oscillator can be turned off to

minimize current drain on the battery. The STOP

bit is the MSB of the seconds register. Setting it to

a ’1’ stops the oscillator. When reset to a ’0’, the

M48ST59W oscillator starts within one second.

Note: It is not necessary to set the WRITE bit

when setting or resetting the FREQUENCY TEST

bit (FT), the STOP bit (ST) or the CENTURY EN-

ABLE bit (CEB).

Calibrating the Clock

The M48ST59W is driven by a quartz controlled

oscillator with a nominal frequency of 32,768Hz.

The devices are tested not to exceed 35 ppm

(parts per million) oscillator frequency error at

25°C, which equates to about ±1.53 minutes per

month. With the calibration bits properly set, the

accuracy of each M48ST59W improves to better

than +1/–2 ppm at 25°C.

The oscillation rate of any crystal changes with

temperature (see Figure 9, page 13). Most clock

chips compensate for crystal frequency and tem-

perature shift error with cumbersome trim capaci-

tors. The M48ST59W design, however, employs

periodic counter correction. The calibration circuit

adds or subtracts counts fromthe oscillator divider

circuit at the divide by 256 stage (see Figure 10,

page 13). The number of times pulses are blanked

(subtracted, negative calibration) or split (added,

positive calibration) depends upon the value load-

ed into the five-bit Calibration byte found in the

Control Register. Adding counts speeds the clock

up, subtracting counts slows the clock down.

The Calibration byte occupies the five lower order

bits (D4-D0) in the Control register (1FF8h). These

bits can be set to represent any value between 0

and 31 in binary form. Bit D5 is a Sign bit; ’1’indi-

cates positive calibration, ’0’ indicates negative

calibration. Calibration occurs within a 64 minute

cycle. The first 62 minutes in the cycle may, once

per minute, have one second either shortened by

128 or lengthened by 256 oscillator cycles. If a bi-

nary ’1’ is loaded into the register, only the first 2

minutes in the 64 minute cycle will be modified; if

a binary 6 is loaded, the first 12 will be affected,

and so on.

Therefore, each calibration step has the effect of

adding 512 or subtracting 256 oscillator cycles;for

every 125,829,120 actual oscillator cycles, that is

+4.068 or –2.034 ppm of adjustment per calibra-

tion step in the calibration register. Assuming that

the oscillatoris in fact running at exactly 32,768Hz,

each of the 31 increments in the Calibration byte

would represent +10.7 or –5.35 seconds per

month which corresponds to a total range of +5.5

or –2.75 minutes per month.

Two methods are available for ascertaining how

much calibration a given M48ST59W may require.

The first involves simply setting the clock, letting it

run for a month and comparing it to a known accu-

rate reference (like WWV broadcasts). While that

may seem crude,it allows the designer to give the

end user the ability to calibrate his clock as his en-

vironment may require, even after the final product

is packaged in a non-user serviceable enclosure.

All the designer has to do is provide a simple utility

that accesses the Calibration byte.

13/29

M48ST59W

The second approach is better suited to a manu-

facturing environment, and involves the use of the

IRQ/FT pin. The pin will toggle at 512Hz when the

Stop bit (D7 of 1FF9h) is ’0’, the FT bit (D6 of

1FFCh) is ’1’, the AFE bit (D7 of 1FF6h) is ’0’, and

the Watchdog Steering bit (D7 of 1FF7h) is ’1’ or

the Watchdog Register is reset (1FF7h = 0).

Any deviation from 512Hz indicates the degree

and direction of oscillator frequencyshift atthe test

temperature. Forexample, a readingof 512.01024

Hz would indicate a +20 ppm oscillator frequency

error, requiring a –10 (WR001010) to be loaded

into the Calibration Byte for correction. Note that

setting or changing the Calibration Byte does not

affect the Frequency test output frequency.

The IRQ/FT pin is an open drain output which re-

quires a pull-up resistor for proper operation. A

500-10kΩresistor is recommended in order to

control therise time. The FT bit iscleared on pow-

er-down.

Note: For more information on calibration, see the

Application Note AN934, “TIMEKEEPER Calibra-

tion.”

Figure 9. Crystal Accuracy Across Temperature

Figure 10. Clock Calibration

AI00999

–160

0 10203040506070

Frequency (ppm)

Temperature °C

80–10–20–30–40

–100

–120

–140

–40

–60

–80

–20

∆F= -0.038 (T - T0)2±10%

Fppm

T0=25°C

AI00594B

NORMAL

POSITIVE

CALIBRATION

NEGATIVE

CALIBRATION

M48ST59W

14/29

Setting Alarm Clock

Registers 1FF5h-1FF2h contain the alarm set-

tings. The alarm can be configured to go off at a

prescribed time on a specific day of the month or

repeat every month, day, hour, minute, or second.

It can also be programmed to go off while the

M48ST59W is in the battery back-up mode of op-

eration to serve as a system wake-up call.

RPT1-RPT4 put the alarm in the repeat mode of

operation. Possible configurations are shown in

Table 6. Codesnot listed in the table default to the

once per second mode to quickly alert the user of

an incorrect alarm setting.

Note: The user must transition address (or toggle

chip enable) to see the Flag bitchange.

When the clock information matches the alarm

clock settings based on the match criteria defined

by RPT1-RPT4, AF (Alarm Flag) is set. If AFE

(Alarm Flag Enable) is also set, the alarm condi-

tion activates the IRQ/FT pin. To disable alarm,

write ‘0’ to the Alarm Date register and RPT1-4.

The alarm flag and the IRQ/FT output are cleared

by a read to the Flags register.

The IRQ/FT pin can also be activated in the bat-

tery back-up mode. The IRQ/FT will go low if an

alarm occurs and both ABE (Alarm in Battery

Back-up Mode Enable)and AFE are set. The ABE

and AFE bits are reset during power-up, therefore

an alarm generated during power-up will only set

AF. The user can read the Flag Register at system

boot-up to determine if an alarm was generated

while the M48ST59W was in the deselect mode

during power-up. Figure 11 illustrates the back-up

mode alarm timing.

Table 6. Alarm Repeat Mode

Figure 11. Back-up Mode Alarm Waveform

RPT4 RPT3 RPT2 RPT1 Alarm Activated

1111Once per Second

1110Once per Minute

1100Once per Hour

1000Once per Day

0000Once per Month

ABE, AFE bit in Interrupt Register

AF bit in Flags Register

HIGH-Z

IRQ/FT

HIGH-Z

tREC

VCC

VPFD (max)

VPFD (min)

VSO

AI04610

15/29

M48ST59W

Watchdog Timer

The watchdog timer can be used to detect an out-

of-control microprocessor. The user programs the

watchdog timer by setting the desired amount of

time-out into the eight bit Watchdog Register (Ad-

dress 1FF7h). The five bits (BMB4-BMB0) store a

binary multiplier andthe two lower order bits (RB1-

RB0) select the resolution, where 00 = 1/16 sec-

ond, 01 = 1/4 second, 10 = 1 second, and 11 = 4

seconds. The amount of time-out is then deter-

mined to be the multiplication of the five bit multi-

plier value with the resolution. (For example:

writing 00001110 inthe Watchdog Register =3 x 1

or 3 seconds).

Note: Accuracy oftimer isa function of the select-

ed resolution.

If the processor does not reset the timer within the

specified period, the M48ST59W sets the WDF

(Watchdog Flag) and generates a watchdog inter-

rupt or a microprocessor reset. The WDF is reset

by reading the Flags Register (Address 1FF0h).

The most significant bit of the Watchdog Register

is the Watchdog SteeringBit. When setto a ’0’, the

watchdog will activatethe IRQ/FT pin when timed-

out. When WDS is set to a ’1’, the watchdog will

output a negative pulse on the RST pin for a dura-

tion of40ms to200ms. The Watchdog register and

the FTbit will reset to a ’0’at theend of awatchdog

time-out when the WDS bit is set to a ’1’.

The watchdog timer resets when the microproces-

sor performs a re-write of the Watchdog Register.

The time-out period then starts over. Should the

watchdog timer time-out, a value of 00h needs to

be written to the Watchdog Register in order to

clear the IRQ/FT pin. This will also disable the

watchdog function until it is again programmed

correctly. A read of the Flags Register will reset

the Watchdog Flag (D7, Register 1FF0h). The

watchdog function is automatically disabled upon

power-up and the Watchdog Register is cleared. If

the watchdog function is set to output to the IRQ/

FT pinand thefrequency test functionis activated,

the watchdog or alarm function prevails and the

frequency test function is denied.

Battery Low Flag

The M48ST59W automatically performs periodic

battery voltage monitoring upon power-up and at

factory-programmed time intervals of 24 hours (at

day rollover) as long as the deviceis powered and

the oscillatoris running. The Battery Low flag (BL),

Bit D4 of the Flags Register 1FF0h, will be assert-

ed highif the SNAPHAT battery is found to be less

than approximately 2.5V. The BL flag will remain

active until completion of battery replacement and

subsequent battery low monitoring tests, either

during the next power-up sequence or the next

scheduled 24-hour interval.

If a battery low is generated during a power-up se-

quence, this indicates that the battery voltage is

below 2.5V (approximately), which may be insuffi-

cient to maintain data integrity. Data should be

considered suspectand verified as correct.A fresh

battery should be installed.

If a battery low indication is generated during the

24-hour interval check, this indicates that the bat-

tery is near end oflife. However, data has not been

compromised due to the fact that a nominal VCC is

supplied. In order to insure data integrity during

subsequent periods of battery back-up mode, it is

recommended that the battery be replaced. The

SNAPHAT top may be replaced while VCC is ap-

plied to the device.

Note:Battery monitoringis a useful technique only

when performed periodically. The M48ST59W

only monitors the battery when a nominal VCC is

applied to the device. Thus applications which re-

quire extensive durations in the battery back-up

mode should be powered-up periodically (at least

once every few months) in orderfor this technique

to be beneficial. Additionally, if a battery low is in-

dicated, data integrity should be verified upon

power-up via a checksum or other technique.

Power-Fail Comparator

The Power-Fail Input (PFI) is compared to an in-

ternal reference voltage (independent from the

VPFD comparator). If PFI is less thanthe power-fail

threshold (VPFI), the Power-Fail Output (PFO) will

go low. This function is intended for use as an un-

dervoltage detector to signal a failing power sup-

ply. Typically PFI is connected through an external

voltage divider to either the unregulated DC input

(if it isavailable) or the regulated output of the VCC

regulator. The voltage divider can be set up such

that the voltage at PFI falls below VPFI severalmil-

liseconds before the regulated VCC input to the

M48ST59W or the microprocessor drops below

the minimum operating voltage.

During battery back-up, the power-fail comparator

turns off and PFO goes (or remains) low. This oc-

curs after VCC drops below VPFD(min). When pow-

er returns, PFO is forced high, irrespective of VPFI

for the write protect time (tREC), which is the time

from VPFD(max) until the inputs arerecognized. At

the end of this time, the power-fail comparator is

enabled and PFO follows PFI.If the comparator is

unused, PFIshould be connected to VSS and PFO

left unconnected.

M48ST59W

16/29

Hysteresis may be added to PFI for additional

noise margin if desired (see Figure 12, page 16).

The ratio of R1 and R2 should be selected such

that PFI sees VPFI when VIN falls to its trip point

(VTRIP). Connecting R3 between PFI and PFO

provides the hysteresis and should typically be

more than ten (10) times the value of R1 or R2.

The hysteresis window will extend both above

(VH) and below (VL) the original trip point (Vt).

Connecting an ordinary signal diode in series with

R3 causesthe lower trip point (VL) to coincide with

the trip point without hysteresis, so the entire hys-

teresis window occurs above VTRIP (see Figure

13). This method provides additional noise margin

without compromising the accuracy of the power-

fail thresholdwhen themonitored voltage is falling.

The current through R1 and R2 should be at least

1uA toensure that the 25nA PFI inputcurrent does

not shift the trip point. R3 should be larger than

82K Ohms to avoid loading down the PFO pin. The

capacitor C1 is added for noise rejection, but is op-

tional.

Figure 12. Adding Hysteresis

Figure 13. Hysteresis on Rising VIN

PFO

VCC

PFI

R3R2

VIN

GND

CONTROLLER

VIN

PFO

VLVH

VTRIP

VTRIP =V

PFI R1 + R2

VH=1+1+1

VPFI +VPFH

()R1() R2 R3

VL=R1 ()

1+1+1

VPFI R2 R3 VCC

–

where

VPFH = 10mV

VPFI =1.25V

[]

()

AI04611

PFO

VCC

PFI

R3R2

VIN

GND

CONTROLLER

VIN

PFO

VTRIP VH

VTRIP =V

PFI R1 + R2

VH=R1 V

PFI +VPFH

()

1+1+1

R1 R2 R3 VD

–

VPFH= 10mV

where

VPFI = 1.25V

VD= Diode Forward VoltageDrop

[]()

()

AI04612

17/29

M48ST59W

Century Bit

Bits D5 and D4 of Clock Register 1FFCh contain

the CENTURY ENABLE Bit (CEB) and the CEN-

TURY Bit (CB). Setting CEB to a “1” will cause CB

to toggle, either from a “0” to “1” or from “1” to “0”

at the turn of the century (depending upon its initial

state). If CEB is set to a “0”, CB will not toggle.

Note: The WRITE Bit must be set in order to write

to the CENTURY Bit.

TREC Bit

Bit D7 of Clock Register 1FFCh contains the

TREC Bit (TR). TREC refers to the automatic con-

tinuation of the deselect time after VCC reaches

VPFD (max). This allows for a voltage settling time

before writes may again be performed to the de-

vice after a power-down condition. The TREC Bit

will allow the user to set the length of thisdeselect

time as defined by Table 7.

Table 7. tREC Definitions POWER-ON

Note: 1. Initial default is undefined.

Power-on Reset

The M48ST59W continuously monitors VCC.

When VCC falls to the power fail detect trip point,

the RST pulls low (open drain) and remains low on

power-up for tREC (see Table 7) after VCC passes

VPFD. The RST pin is an open drain output and an

appropriate pull-up resistor should be chosen to

control rise time.

Initial Power-On Defaults

Upon application of power to the device, the fol-

lowing register bits are set to a ’0’ state: WDS;

BMB0-BMB4; RB0-RB1; AFE; ABE; W; R; and FT

(see Table 8):

Table 8. Default Values

Note: 1. WDS, BMB0-BMB4, RBO, RB1.

2. State of other control bits undefined.

3. State of other control bits remains unchanged.

4. Assuming these bits set to ’1’ prior to power-down.

TREC Bit (TR) tREC Time(1)

0 40 ms to 200 ms

1 2 ms (max)

Condition W R FT AFE ABE WATCHDOG(1)

Initial Power-up

(Battery Attach for SNAPHAT)(2) 00000 0

Subsequent Power-up / RESET(3) 00000 0

Power-down(4) 00011 0

M48ST59W

18/29

POWER SUPPLY DECOUPLING AND UNDERSHOOT PROTECTION

ICC transients,including those produced by output

switching, can produce voltage fluctuations, re-

sulting in spikes on the VCC bus. These transients

can be reduced if capacitors are used to store en-

ergy, which stabilizes the VCC bus. The energy

stored in the bypass capacitors will be released as

low going spikes are generated or energy will be

absorbed when overshoots occur. A ceramic by-

pass capacitor value of 0.1µF (see Figure 14) is

recommended in order to provide the needed fil-

tering.

In addition to transients that are caused bynormal

SRAM operation,power cycling can generate neg-

ative voltage spikes on VCC that drive it to values

below VSS by as much as one Volt. These nega-

tive spikes can cause data corruption in the SRAM

while in battery backup mode. To protect from

these voltage spikes, it is recommended to con-

nect a Schottky diode from VCC to VSS (cathode

connected to VCC, anode to VSS). Schottky diode

1N5817 is recommended for through hole and

MBRS120T3 is recommended for surface mount.

Figure 14. Supply Voltage Protection

VCC

0.1mF DEVICE

VCC

VSS

AI04603

19/29

M48ST59W

MAXIMUM RATING

Stressing the device above the rating listed in the

Absolute Maximum Ratings” table may cause per-

manent damage to the device. These are stress

ratings only and operation of the device at these or

any other conditions above those indicated in the

Operating sections of this specification is not im-

plied. Exposure to Absolute Maximum Rating con-

ditions for extended periods may affect device

reliability. Refer also to the STMicroelectronics

SURE Program and other relevant quality docu-

ments.

Table 9. Absolute Maximum Ratings

Note: 1. Soldering temperature not to exceed 260°C for 10 seconds (totalthermal budget not to exceed 150°C for longer than 30 seconds).

CAUTION! Negative undershootsbelow -0.3V are notallowed on any pin while in the Battery Back-up Mode.

CAUTION! Do NOT wave-solder the SOIC to avoid damaging the SNAPHAT sockets.

Symbol Parameter Value Unit

TAOperating Temperature Grade 1 0 to 70 °C

Grade 6 –40 to 85 °C

TSTG(2) Storage Temperature (VCC, Oscillator Off) SNAPHAT –40 to 85 °C

SOIC –55 to 125 °C

TSLD Lead Solder Temperature for 10 seconds 260 °C

VCC Supply Voltage (on any pin relative to Ground) –0.3 to 4.6 V

VIO Input or Output Voltages –0.3 to 4.6 V

IOOutput Current 20 mA

PDPower Dissipation 1 W

M48ST59W

20/29

DC AND AC PARAMETERS

This section summarizes the operating and mea-

surement conditions, as well as the DC and AC

characteristics of the device. The parameters in

the following DC and AC Characteristic tables are

derived from tests performed under the Measure-

ment Conditions listed in the relevant tables. De-

signers should checkthatthe operating conditions

in their projects match the measurement condi-

tions when using the quoted parameters.

Table 10. DC and AC Measurement Conditions

Figure 15. AC Testing Load Circuit

Table 11. Capacitance

Note: Effective capacitance measured with power supply at 3.6V. Sampled only, not 100% tested.

1. Outputs were deselected.

Parameter M48ST59W

VCC Supply Voltage 2.7 to 3.6V

Ambient Operating Temperature –40 to 85°C

Load Capacitance (CL)50pF

Input Rise and Fall Times ≤5ns

Input Pulse Voltages 0to3V

Input and Output Timing Ref.Voltages 1.5V

CL=50pF

Lincludes JIG capacitance

645

Ω

DEVICE

UNDER

TEST

1.75V

or 5 pF

AI04604

Symbol Parameter Test Condition Min Max Unit

CIN Input Capacitance VIN =0V 10 pF

CIO(1) Input / Output Capacitance VOUT =0V 10 pF

21/29

M48ST59W

Table 12. DC Characteristics

Note: 1. Outputs deselected.

2. Negative spikes of –1V allowed for up to 10ns once per cycle.

3. The IRQ/FT and RST pins are Open Drain.

Symbol Parameter Test Condition M48ST59W Unit

Min Typ Max

ILI(1) Input Leakage Current 0V ≤VIN ≤VCC ±1µA

Input Leakage Current (PFI) 0V ≤VIN ≤VCC –25 2 25

ILO(1) Output Leakage Current 0V ≤VOUT ≤VCC ±1µA

ICC1 Supply Current Outputs open 30 mA

ICC2 Supply Current (Standby) TTL E = VIH 2mA

CC3 Supply Current (Standby)

CMOS E=V

CC – 0.2V 1mA

IL(2) Input Low Voltage –0.2 0.8 V

VIH Input High Voltage 2 VCC + 0.2 V

VOL

Output Low Voltage IOL = 2.1mA 0.4 V

Output Low Voltage (IRQ/FT

and RST)(3) IOL = 10mA 0.4 V

VOH Output High Voltage IOH = –1mA 2.4 V

M48ST59W

22/29

Figure 16. Power Down/Up Mode AC Waveforms

Table 13. Power Down/Up Trip Points DC Characteristics

Note: 1. All voltages referenced to VSS.

2. Using larger M4T32-BR12SH6 SNAPHAT top (recommended for Industrial Temperature Range - grade 6 device).

3. At 25°C

Symbol Parameter Min Typ Max Unit

VPFD Power-fail Deselect Voltage 2.5 2.6 2.7 V

VSO Battery Back-up Switchover Voltage VPFD –100mV mV

VPFI PFI Input Threshold 1.225 1.250 1.275 V

tDR(3) Expected Data Retention Time (at 25 °C) Grade 1 7 Years

Grade 6(2) 10 Years

VCC

INPUTS

(PER CONTROL INPUT)

OUTPUTS

DON’T CARE

HIGH-Z

VALID VALID

(PER CONTROL INPUT)

RECOGNIZED

VPFD (max)

VPFD (min)

VSO

RST

VALID VALIDPFO

tFB tDR

tPD tRB tR

tREC

AI04605

23/29

M48ST59W

Table 14. Power Down/Up AC Characteristics

Note: 1. VPFD (max) to VPFD (min) Fall Time of less than tFmay result in deselection/write protection not occurring until 200 µs after VCC

passes VPFD (min).

2. VPFD (min) to VSS Fall Time of less than tFB may cause corruption of RAM data.

3. tREC is undefined at initial power-up. Refer to Table 7 on page 17.

Symbol Parameter Min Typ Max Unit

tPD E or W at VIH before Power Down 0 µs

tF(1) VPFD (max) to VPFD (min) VCC FallTime 300 µs

tFB(2) VPFD (min) to VSS VCC Fall Time 10 µs

tRVPFD (min) to VPFD (max) VCC Rise Time 10 µs

tRB VSS to VPFD (min) VCC Rise Time 1µs

tPFD PFI to PFO Propagation Delay 15 25 µs

tREC(3) VPFD (max) to RST High Note 3 ms

M48ST59W

24/29

PACKAGE MECHANICAL

Figure 17. SO44 – 44-lead Plastic Small Outline, Package Outline

Note: Drawing is not to scale.

Table 15. SOH44 – 44-lead Plastic Small Outline, Package Mechanical Data

Symb mm inches

Typ Min Max Typ Min Max

A 3.05 0 0.120

A1 0.05 0.36 0.002 0.014

A2 2.34 2.69 0.092 0.106

B 0.36 0.46 0.014 0.018

C 0.15 0.32 0.006 0.012

D 17.71 18.49 0.697 0.728

E 8.23 8.89 0.324 0.350

e 0.81 – – 0.032 – –

eB 3.20 3.61 0.126 0.142

H 11.51 12.70 0.453 0.500

L 0.41 1.27 0.016 0.050

a0°8°0°8°

N4444

CP 0.10 0.004

SOH-A

LA1 α

25/29

M48ST59W

Figure 18. SH – 4-pin SNAPHAT Housing for 48 mAh Battery and Crystal, Package Outline

Note: Drawing is not to scale.

Table 16. SH – 4-pin SNAPHAT Housing for 48 mAh Battery and Crystal, Package Mechanical Data

Symb mm inches

Typ Min Max Typ Min Max

A 9.78 0 0.385

A1 6.73 7.24 0.265 0.285

A2 6.48 6.99 0.255 0.275

A3 0.38 0 0.015

B 0.46 0.56 0.018 0.022

D 21.21 21.84 0.835 0.860

E 14.22 14.99 0.560 0.590

eB 3.20 3.61 0.126 0.142

L 2.03 2.29 0.080 0.090

SHTK-A

A1 A

M48ST59W

26/29

Figure 19. SH – 4-pin SNAPHAT Housing for 120 mAh Battery and Crystal, Package Outline

Note: Drawing is not to scale.

Table 17. SH – 4-pin SNAPHATHousing for 120 mAh Batteryand Crystal, Package Mechanical Data

Symb mm inches

Typ Min Max Typ Min Max

A 10.54 0 0.415

A1 8.00 8.51 0.315 0.335

A2 7.24 8.00 0.285 0.315

A3 0.38 0 0.015

B 0.46 0.56 0.018 0.022

D 21.21 21.84 0.835 0.860

E 17.27 18.03 0.680 0.710

eB 3.20 3.61 0.126 0.142

L 2.03 2.29 0.080 0.090

SHTK-A

A1 A

27/29

M48ST59W

PART NUMBERING

Table 18. Ordering Information Scheme

Note: The SOIC package(SOH44) requires the battery crystal package (SNAPHAT)which isordered separately under part number “M4TXX-

BR12SHX” in plastic tube or “M4TXX-BR12SHXTR” in Tape & Reel form.

Caution: Do not place the SNAPHAT battery/crystal package “M4Txx-BR12SHx” in conductive foam

since thiswill drain the lithium button-cell battery.

For a list ofavailable options (e.g.,Speed, Package) or for further information on any aspect of this device,

please contact the ST Sales Office nearest to you.

Table 19. SNAPHAT Battery Table

Example: M48ST 59W –70 MH 1 TR

Device Type

M48ST

Supply Voltage and Write Protect Voltage

59W = VCC = 2.7 to 3.6V; VPFD = 2.5 to 2.7V

Speed

–70 = 70ns

–100 = 100ns

Package

MH(1) = SOH44

Temperature Range

1=0to70°C

6=–40to85°C

Shipping Method for SOIC

blank = Tubes

TR = Tape & Reel

Part Number Description Package

M4T28-BR12SH Lithium Battery (48mAh) SNAPHAT SH

M4T32-BR12SH Lithium Battery (120mAh) SNAPHAT SH

M48ST59W

28/29

REVISION HISTORY

Table 20. Document Revision History

Date Revision Details

September 2000 First cut

10/10/00 First markups entered, text added, graphics changed

12/18/00 Reformatted, TOC added, and PFI ILI added (Table 12)

29/29

M48ST59W

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences

of useof such information nor for any infringement of patents orother rights of third parties which may result from itsuse. No license is granted

by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject

to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

authorized for use as critical components in lifesupport devices or systems without express written approval of STMicroelectronics.

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