PRELIMINARY MARKETING REQUIREMENTS DOCUMENT AE0.1E FLASH MEMORY CMOS 16M (2M x 8) BIT MBM29F017E 70/90/12 FEATURES * 0.23 m Process Technology * Single 5.0 V read, write, and erase Minimizes system level power requirements * Compatible with JEDEC-standard commands Pinout and software compatible with single-power supply Flash Superior inadvertent write protection * Address don't care during the command sequence * 48-pin TSOP(I) (Package Suffix: TN-Normal Bend Type, TR-Reverse Bend Type) * Minimum 1,000,000 program/erase cycles * High performance 70 ns maximum access time * Sector erase architecture Uniform sectors of 64 K bytes each Any combination of sectors can be erased. Also supports full chip erase. * Embedded EraseTM Algorithms Automatically pre-programs and erases the chip or any sector * Embedded ProgramTM Algorithms Automatically programs and verifies data at specified address * Data Polling and Toggle Bit feature for detection of program or erase cycle completion * Ready/Busy output (RY/BY) Hardware method for detection of program or erase cycle completion * Low VCC write inhibit 3.2 V * Hardware RESET pin Resets internal state machine to the read mode * Erase Suspend/Resume Suspends the erase operation to allow a read data and/or program in another sector within the same device * Sector group protection Hardware method that disables any combination of sector groups from write or erase operation (a sector group consists of 4 adjacent sectors of 64 K bytes each) * Sector Group Protection Set function by Extended sector group protection command * Fast Programming Function by Extended Command * Temporary sector groups unprotection Temporary sector group unprotection via the RESET pin * In accordance with CFI (Common Flash Memory Interface) Embedded EraseTM, Embedded ProgramTM and ExpressFlashTM are trademarks of Advanced Micro Devices, Inc. This document contains information on product under development at Fujitsu. The information is intended to help you evaluate this product. Fujitsu reserves the right to change this proposed product without notice. MBM29F017E 70/90/12 PACKAGE 48-pin Plastic TSOP(I) 48-pin Plastic TSOP(I) Marking Side Marking Side (FPT-48P-M19) 2 (FPT-48P-M20) MBM29F017E 70/90/12 GENERAL DESCRIPTION The MBM29F017E is a 16 M-bit, 5.0 V-Only Flash memory organized as 2 M bytes of 8 bits each. The 2 M bytes of data is divided into 32 sectors of 64 K bytes for flexible erase capability. The 8 bit of data will appear on DQ0 to DQ7. The MBM29F017E is offered in a 48-pin TSOP(I) package. This device is designed to be programmed in-system with the standard system 5.0 V VCC supply. A 12.0 V VPP is not required for program or erase operations. The device can also be reprogrammed in standard EPROM programmers. The standard MBM29F017E offers access times between 70 ns and 120 ns allowing operation of high-speed microprocessors without wait states. To eliminate bus contention the device has separate chip enable (CE), write enable (WE), and output enable (OE) controls. The MBM29F017E is command set compatible with JEDEC standard E2PROMs. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from 12.0 V Flash or EPROM devices. The MBM29F017E is programmed by executing the program command sequence. This will invoke the Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. Each sector can be programmed and verified in less than 0.5 seconds. Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. This device also features a sector erase architecture. The sector erase mode allows for sectors of memory to be erased and reprogrammed without affecting other sectors. A sector is typically erased and verified within 1 second (if already completely preprogrammed). The MBM29F017E is erased when shipped from the factory. The MBM29F017E device also features hardware sector group protection. This feature will disable both program and erase operations in any combination of eight sector groups of memory. A sector group consists of four adjacent sectors grouped in the following pattern: sectors 0-3, 4-7, 8-11, 12-15, 16-19, 20-23, 24-27, and 28-31. Fujitsu has implemented an Erase Suspend feature that enables the user to put erase on hold for any period of time to read data from or program data to a non-busy sector. Thus, true background erase can be achieved. The device features single 5.0 V power supply operation for both read and program functions. Internally generated and regulated voltages are provided for the program and erase operations. A low VCC detector automatically inhibits write operations during power transitions. The end of program or erase is detected by Data Polling of DQ7, or by the Toggle Bit I feature on DQ6 or RY/BY output pin. Once the end of a program or erase cycle has been completed, the device automatically resets to the read mode. The MBM29F017E also has a hardware RESET pin. When this pin is driven low, execution of any Embedded Program or Embedded Erase operations will be terminated. The internal state machine will then be reset into the read mode. The RESET pin may be tied to the system reset circuity. Therefore, if a system reset occurs during the Embedded Program or Embedded Erase operation, the device will be automatically reset to a read mode. This will enable the system microprocessor to read the boot-up firmware from the Flash memory. Fujitsu's Flash technology combines years of EPROM and E2PROM experience to produce the highest levels of quality, reliability, and cost effectiveness. The MBM29F017E memory electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The bytes are programmed one byte at a time using the EPROM programming mechanism of hot electron injection. 3 MBM29F017E 70/90/12 FLEXIBLE SECTOR-ERASE ARCHITECTURE * Thirty two 64 K byte sectors * 8 sector groups each of which consists of 4 adjacent sectors in the following pattern; sectors 0-3, 4-7, 8-11, 12-15, 16-19, 20-23, 24-27, and 28-31 * Individual-sector or multiple-sector erase capability * Sector group protection is user-definable 1FFFFFH 64 K byte SA31 1EFFFFH 64 K byte SA30 Sector 1DFFFFH Group 7 64 K byte SA29 1CFFFFH 64 K byte SA28 1BFFFFH 1AFFFFH 19FFFFH 18FFFFH 17FFFFH 16FFFFH 15FFFFH 14FFFFH 13FFFFH 12FFFFH 11FFFFH 10FFFFH 32 Sectors Total 0FFFFFH 0EFFFFH 0DFFFFH 0CFFFFH 0BFFFFH 0AFFFFH 09FFFFH 08FFFFH 07FFFFH 06FFFFH 05FFFFH 04FFFFH 4 SA3 64 K byte SA2 64 K byte SA1 64 K byte SA0 64 K byte 03FFFFH 02FFFFH 01FFFFH 00FFFFH 000000H Sector Group 0 MBM29F017E 70/90/12 PRODUCT LINE UP Part No. MBM29F017E VCC = 5.0 V 5% 70 -- -- VCC = 5.0 V 10% -- 90 12 Max. Address Access Time (ns) 70 90 120 Max. CE Access Time (ns) 70 90 120 Max. OE Access Time (ns) 30 35 50 Ordering Part No. BLOCK DIAGRAM DQ0 to DQ7 VCC VSS RY/BY Buffer RY/BY Erase Voltage Generator WE Input/Output Buffers State Control RESET Command Register Program Voltage Generator Chip Enable Output Enable Logic CE OE STB Low VCC Detector Timer for Program/Erase Address Latch STB Data Latch Y-Decoder Y-Gating X-Decoder Cell Matrix A0 to A20 5 MBM29F017E 70/90/12 CONNECTION DIAGRAMS TSOP(I) N.C. N.C. A19 A18 A17 A16 A15 A14 A13 A12 CE VCC N.C. RESET A11 A10 A9 A8 A7 A6 A5 A4 N.C. N.C. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 (Marking Side) Standard Pinout 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 N.C. N.C. A20 N.C. WE OE RY/BY DQ7 DQ6 DQ5 DQ4 VCC VSS VSS DQ3 DQ2 DQ1 DQ0 A0 A1 A2 A3 N.C. N.C. FPT-48P-M19 N.C. N.C. A4 A5 A6 A7 A8 A9 A10 A11 RESET N.C. VCC CE A12 A13 A14 A15 A16 A17 A18 A19 N.C. N.C. 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 (Marking Side) Reverse Pinout FPT-48P-M20 6 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 N.C. N.C. A3 A2 A1 A0 DQ0 DQ1 DQ2 DQ3 VSS VSS VCC DQ4 DQ5 DQ6 DQ7 RY/BY OE WE N.C. A20 N.C. N.C. MBM29F017E 70/90/12 LOGIC SYMBOL Table 1 MBM29F017E Pin Configuration Pin Function A0 to A20 21 A 0 to A 20 Address Inputs DQ0 to DQ7 8 Data Inputs/Outputs DQ0 to DQ7 CE OE CE Chip Enable OE Output Enable WE Write Enable WE RESET RY/BY Table 2 RY/BY Ready/Busy Output RESET Hardware Reset Pin/Temporary Sector Group Unprotection N.C. No Internal Connection VSS Device Ground VCC Device Power Supply MBM29F017E User Bus Operations CE OE WE A0 A1 A6 A9 Auto-Select Manufacturer Code (1) L L H L L L VID Code H Auto-Select Device Code (1) L L H H L L VID Code H Read (2) L L H A0 A1 A6 A9 DOUT H Standby H X X X X X X HIGH-Z H Output Disable L H H X X X X HIGH-Z H Write (Program/Erase) L H L A0 A1 A6 A9 DIN H Enable Sector Group Protection (3) L VID X X X VID X H Verify Sector Group Protection (3) L L H L H L VID Code H Temporary Sector Group Unprotection X X X X X X X X VID Reset (Hardware) X X X X X X X HIGH-Z L Operation Legend: L = VIL, H = VIH, X = VIL or VIH, DQ0 to DQ7 RESET = Pulse Input. See DC Characteristics for voltage levels. Notes: 1. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 6. 2. WE can be VIL if OE is VIL, OE at VIH initiates the write operations. 3. Refer to the section on Sector Group Protection. 7 MBM29F017E 70/90/12 FUNCTIONAL DESCRIPTION Read Mode The MBM29F017E has two control functions which must be satisfied in order to obtain data at the outputs. CE is the power control and should be used for a device selection. OE is the output control and should be used to gate data to the output pins if a device is selected. Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable access time (tCE) is the delay from stable addresses and stable CE to valid data at the output pins. The output enable access time is the delay from the falling edge of OE to valid data at the output pins (Assuming the addresses have been stable for at least tACC-tOE time). When reading out a data without changing addresses after power-up, it is necessary to input hardware reset or to change CE pin from "H" or "L". Standby Mode There are two ways to implement the standby mode on the MBM29F017E device, one using both the CE and RESET pins; the other via the RESET pin only. When using both pins, a CMOS standby mode is achieved with CE and RESET inputs both held at VCC 0.3 V. Under this condition the current consumed is less than 5 A. A TTL standby mode is achieved with CE and RESET pins held at VIH. Under this condition the current is reduced to approximately 1 mA. During Embedded Algorithm operation, VCC Active current (ICC2) is required even CE = VIH. The device can be read with standard access time (tCE) from either of these standby modes. When using the RESET pin only, a CMOS standby mode is achieved with RESET input held at VSS 0.3 V (CE = "H" or "L"). Under this condition the current consumed is less than 5 A. A TTL standby mode is achieved with RESET pin held at VIL (CE = "H" or "L"). Under this condition the current required is reduced to approximately 1 mA. Once the RESET pin is taken high, the device requires tRH of wake up time before outputs are valid for read access. In the standby mode the outputs are in the high impedance state, independent of the OE input. Output Disable With the OE input at a logic high level (VIH), output from the device is disabled. This will cause the output pins to be in a high impedance state. Autoselect The autoselect mode allows the reading out of a binary code from the device and will identify its manufacturer and type. This mode is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. This mode is functional over the entire temperature range of the device. To activate this mode, the programming equipment must force VID (11.5 V to 12.5 V) on address pin A9. Two identifier bytes may then be sequenced from the device outputs by toggling address A0 from VIL to VIH. All addresses are don't cares except A0, A1, and A6. (See Table 3.) The manufacturer and device codes may also be read via the command register, for instances when the MBM29F017E is erased or programmed in a system without access to high voltage on the A9 pin. The command sequence is illustrated in Table 6. (Refer to Autoselect Command section.) Byte 0 (A0 = VIL) represents the manufacturer's code (Fujitsu = 04H) and byte 1 (A0 = VIH) represents the device identifier code for MBM29F017E = 3DH. These two bytes are given in the table 3. All identifiers for manufactures and device will exhibit odd parity with DQ7 defined as the parity bit. In order to read the proper device codes when executing the Autoselect, A1 must be VIL. (See Table 3.) 8 MBM29F017E 70/90/12 The Autoselect mode also facilitates the determination of sector group protection in the system. By performing a read operation at the address location XX02H with the higher order address bits A20, A19 and A18 set to the desired sector group address, the device will return 01H for a protected sector group and 00H for a non-protected sector group. Table 3 MBM29F017E Sector Group Protection Verify Autoselect Codes A20 to A18 Type A6 A1 A0 Code (HEX) DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 Manufacture's Code X X X VIL VIL VIL 04H 0 0 0 0 0 1 0 0 Device Code X X X VIL VIL VIH 3DH 0 0 1 1 1 1 0 1 Sector Group Protection Sector Group Addresses VIL VIH VIL 01H* 0 0 0 0 0 0 0 1 * : Outputs 01H at protected sector addresses and outputs 00H at unprotected sector addresses. 9 MBM29F017E 70/90/12 Table 4 10 Sector Address Table A20 A19 A18 A17 A16 Address Range SA0 0 0 0 0 0 000000H to 00FFFFH SA1 0 0 0 0 1 010000H to 01FFFFH SA2 0 0 0 1 0 020000H to 02FFFFH SA3 0 0 0 1 1 030000H to 03FFFFH SA4 0 0 1 0 0 040000H to 04FFFFH SA5 0 0 1 0 1 050000H to 05FFFFH SA6 0 0 1 1 0 060000H to 06FFFFH SA7 0 0 1 1 1 070000H to 07FFFFH SA8 0 1 0 0 0 080000H to 08FFFFH SA9 0 1 0 0 1 090000H to 09FFFFH SA10 0 1 0 1 0 0A0000H to 0AFFFFH SA11 0 1 0 1 1 0B0000H to 0BFFFFH SA12 0 1 1 0 0 0C0000H to 0CFFFFH SA13 0 1 1 0 1 0D0000H to 0DFFFFH SA14 0 1 1 1 0 0E0000H to 0EFFFFH SA15 0 1 1 1 1 0F0000H to 0FFFFFH SA16 1 0 0 0 0 100000H to 10FFFFH SA17 1 0 0 0 1 110000H to 11FFFFH SA18 1 0 0 1 0 120000H to 12FFFFH SA19 1 0 0 1 1 130000H to 13FFFFH SA20 1 0 1 0 0 140000H to 14FFFFH SA21 1 0 1 0 1 150000H to 15FFFFH SA22 1 0 1 1 0 160000H to 16FFFFH SA23 1 0 1 1 1 170000H to 17FFFFH SA24 1 1 0 0 0 180000H to 18FFFFH SA25 1 1 0 0 1 190000H to 19FFFFH SA26 1 1 0 1 0 1A0000H to 1AFFFFH SA27 1 1 0 1 1 1B0000H to 1BFFFFH SA28 1 1 1 0 0 1C0000H to 1CFFFFH SA29 1 1 1 0 1 1D0000H to 1DFFFFH SA30 1 1 1 1 0 1E0000H to 1EFFFFH SA31 1 1 1 1 1 1F0000H to 1FFFFFH MBM29F017E 70/90/12 Table 5 Sector Group Addresses A20 A19 A18 Sectors SGA0 0 0 0 SA0 to SA3 SGA1 0 0 1 SA4 to SA7 SGA2 0 1 0 SA8 to SA11 SGA3 0 1 1 SA12 to SA15 SGA4 1 0 0 SA16 to SA19 SGA5 1 0 1 SA20 to SA23 SGA6 1 1 0 SA24 to SA27 SGA7 1 1 1 SA28 to SA31 Write Device erasure and programming are accomplished via the command register. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. The command register itself does not occupy any addressable memory location. The register is a latch used to store the commands, along with the address and data information needed to execute the command. The command register is written by bringing WE to VIL, while CE is at VIL and OE is at VIH. Addresses are latched on the falling edge of WE or CE, whichever happens later; while data is latched on the rising edge of WE or CE, whichever happens first. Standard microprocessor write timings are used. Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters. Sector Group Protection The MBM29F017E features hardware sector group protection. This feature will disable both program and erase operations in any combination of eight sector groups of memory. Each sector group consists of four adjacent sectors grouped in the following pattern: sectors 0-3, 4-7, 8-11, 12-15, 16-19, 20-23, 24-27, and 28-31 (see Table 5). The sector group protection feature is enabled using programming equipment at the user's site. The device is shipped with all sector groups unprotected. To activate this mode, the programming equipment must force VID on address pin A9 and control pin OE, (suggest VID = 11.5 V), CE = VIL. The sector addresses (A20, A19, and A18) should be set to the sector to be protected. Tables 4 and 5 define the sector address for each of the thirty two (32) individual sectors, and the sector group address for each of the eight (8) individual group sectors. Programming of the protection circuitry begins on the falling edge of the WE pulse and is terminated with the rising edge of the same. Sector addresses must be held constant during the WE pulse. Refer to Figures 14 and 21 for sector group protection waveforms and algorithm. To verify programming of the protection circuitry, the programming equipment must force VID on address pin A9 with CE and OE at VIL and WE at VIH. Scanning the sector addresses (A20, A19, and A18) while (A6, A1, A0) = (0, 1, 0) will produce a logical "1" code at device output DQ0 for a protected sector. Otherwise the device will produce 00H for unprotected sector. In this mode, the lower order addresses, except for A0, A1, and A6 are DON'T CARES. Address locations with A1 = VIL are reserved for Autoselect manufacturer and device codes. It is also possible to determine if a sector group is protected in the system by writing an Autoselect command. Performing a read operation at the address location XX02H, where the higher order addresses (A20, A19, and A18) are the desired sector group address will produce a logical "1" at DQ0 for a protected sector group. See Table 3 for Autoselect codes. 11 MBM29F017E 70/90/12 Temporary Sector Group Unprotection This feature allows temporary unprotection of previously protected sector groups of the MBM29F017E device in order to change data. The Sector Group Unprotection mode is activated by setting the RESET pin to high voltage (VID). During this mode, formerly protected sector groups can be programmed or erased by selecting the sector group addresses. Once the VID is taken away from the RESET pin, all the previously protected sector groups will be protected again. Refer to Figures 15 and 22. 12 MBM29F017E 70/90/12 Table 6 Command Sequence Bus Write Cycles Req'd MBM29F017E Command Definitions First Bus Second Bus Third Bus Fourth Bus Fifth Bus Sixth Bus Write Cycle Write Cycle Write Cycle Read/Write Write Cycle Write Cycle Cycle Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Read/Reset 1 XXXH F0H Reset/Read 3 Autoselect -- -- -- -- -- -- XXXH AAH XXXH 55H XXXH F0H RA RD -- -- -- -- 3 XXXH AAH XXXH 55H XXXH 90H -- -- -- -- -- -- Byte Program 4 XXXH AAH XXXH 55H XXXH A0H PA PD -- -- -- -- Chip Erase 6 XXXH AAH XXXH 55H XXXH 80H XXXH AAH XXXH 55H XXXH 10H Sector Erase 6 XXXH AAH XXXH 55H XXXH 80H XXXH AAH XXXH 55H SA 30H Erase Suspend 1 XXXH B0H -- -- -- -- -- -- -- -- -- -- Erase Resume 1 XXXH 30H -- -- -- -- -- -- -- -- -- -- Set to Fast Mode 3 XXXH AAH XXXH 55H XXXH 20H -- -- -- -- -- -- Fast Program *1 2 XXXH A0H PD -- -- -- -- -- -- -- -- Reset from Fast Mode *1 2 XXXH 90H XXXH F0H -- -- -- -- -- -- -- -- Extended Sector Group Protection *2 4 XXXH 60H Query *3 1 XXH 98H -- PA -- -- -- SPA 60H SPA 40H SPA SD -- -- -- -- -- -- -- -- -- -- -- -- -- -- Notes: 1. Address bits X = "H" or "L" for all address commands except or Program Address (PA) and Sector Address (SA). 2. Bus operations are defined in Table 2. 3. RA = Address of the memory location to be read. PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE pulse. SA = Address of the sector to be erased. The combination of A20, A19, A18, A17, and A16 will uniquely select any sector. 4. RD = Data read from location RA during read operation. PD = Data to be programmed at location PA. Data is latched on the rising edge of WE. 5. Read and Byte program functions to non-erasing sectors are allowed in the Erase Suspend mode. 6. X = "H" or "L" *1:This command is valid while Fast Mode. *2:This command is valid while RESET = VID. *3:The valid addresses are A6 to A0. 13 MBM29F017E 70/90/12 Command Definitions Device operations are selected by writing specific address and data sequences into the command register. Writing incorrect data values or writing them in the improper sequence will reset the device to the read mode. Table 6 defines the valid register command sequences. Note that the Erase Suspend (B0H) and Erase Resume (30H) commands are valid only while the Sector Erase operation is in progress. Moreover, both Read/Reset commands are functionally equivalent, resetting the device to the read mode. Read/Reset Command The read or reset operation is initiated by writing the read/reset command sequence into the command register. Microprocessor read cycles retrieve array data from the memory. The device remains enabled for reads until the command register contents are altered. The device will automatically power-up in the read/reset state. In this case, a command sequence is not required to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no spurious alteration of the memory content occurs during the power transition. Refer to the AC Read Characteristics and Waveforms for the specific timing parameters. Autoselect Command Flash memories are intended for use in applications where the local CPU alters memory contents. As such, manufacture and device codes must be accessible while the device resides in the target system. PROM programmers typically access the signature codes by raising A9 to a high voltage. However, multiplexing high voltage onto the address lines is not generally desirable system design practice. The device contains an autoselect command operation to supplement traditional PROM programming methodology. The operation is initiated by writing the autoselect command sequence into the command register. Following the command write, a read cycle from address XX00H retrieves the manufacture code of 04H. A read cycle from address XX01H returns the device code 3DH. (See Table 3). All manufacturer and device codes will exhibit odd parity with the DQ7 defined as the parity bit. Sector state (protection or unprotection) will be informed by address XX02H. Scanning the sector group addresses (A20, A19, A18) while (A6, A1, A0) = (0, 1, 0) will produce a logical "1" at device output DQ0 for a protected sector group. To terminate the operation, it is necessary to write the read/reset command sequence into the register and also to write the Autoselect command during the operation, execute it after writing Read/Reset command sequence. Byte Programming The device is programmed on a byte-by-byte basis. Programming is a four bus cycle operation. There are two "unlock" write cycles. These are followed by the program set-up command and data write cycles. Addresses are latched on the falling edge of CE or WE, whichever happens later and the data is latched on the rising edge of CE or WE, whichever happens first. The rising edge of CE or WE (whichever happens first) begins programming. Upon executing the Embedded Program Algorithm command sequence, the system is not required to provide further controls or timings. The device will automatically provide adequate internally generated program pulses and verify the programmed cell margin. This automatic programming operation is completed when the data on DQ7 is equivalent to data written to this bit at which time the device returns to the read mode and addresses are no longer latched. (See Table 7, Hardware Sequence Flags.) Therefore, the device requires that a valid address to the device be supplied by the system at this particular instance of time. Data Polling must be performed at the memory location which is being programmed. 14 MBM29F017E 70/90/12 Any commands written to the chip during this period will be ignored. If a hardware reset occurs during the programming operation, it is impossible to guarantee the data are being written. Programming is allowed in any sequence and across sector boundaries. Beware that a data "0" cannot be programmed back to a "1". Attempting to do so may either hang up the device or result in an apparent success according to the data polling algorithm but a read from reset/read mode will show that the data is still "0". Only erase operations can convert "0"s to "1"s. Figure 17 illustrates the Embedded ProgrammingTM Algorithm using typical command strings and bus operations. Chip Erase Chip erase is a six bus cycle operation. There are two "unlock" write cycles. These are followed by writing the "set-up" command. Two more "unlock" write cycles are then followed by the chip erase command. Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded Erase Algorithm command sequence the device will automatically program and verify the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. The automatic erase begins on the rising edge of the last WE pulse in the command sequence and terminates when the data on DQ7 is "1" (see Write Operation Status section) at which time the device returns to read the mode. Figure 18 illustrates the Embedded EraseTM Algorithm using typical command strings and bus operations. Sector Erase Sector erase is a six bus cycle operation. There are two "unlock" write cycles. These are followed by writing the "set-up" command. Two more "unlock" write cycles are then followed by the Sector Erase command. The sector address (any address location within the desired sector) is latched on the falling edge of WE, while the command (Data = 30H) is latched on the rising edge of WE. After time-out of "tTOW" from the rising edge of the last sector erase command, the sector erase operation will begin. Multiple sectors may be erased concurrently by writing the six bus cycle operations on Table 6. This sequence is followed with writes of the Sector Erase command to addresses in other sectors desired to be concurrently erased. The time between writes must be less than "tTOW" otherwise that command will not be accepted and erasure will start. It is recommended that processor interrupts be disabled during this time to guarantee this condition. The interrupts can be re-enabled after the last Sector Erase command is written. A time-out of "tTOW" from the rising edge of the last WE will initiate the execution of the Sector Erase command(s). If another falling edge of the WE occurs within the "tTOW" time-out window the timer is reset. (Monitor DQ3 to determine if the sector erase timer window is still open, see section DQ3, Sector Erase Timer.) Any command other than Sector Erase or Erase Suspend during this time-out period will reset the device to the read mode, ignoring the previous command string. Resetting the device once execution has begun will corrupt the data in that sector. In that case, restart the erase on those sectors and allow them to complete. (Refer to the Write Operation Status section for DQ3, Sector Erase Timer operation.) Loading the sector erase buffer may be done in any sequence and with any number of sectors (0 to 31). Sector erase does not require the user to program the device prior to erase. The device automatically programs all memory locations in the sector(s) to be erased prior to electrical erase. When erasing a sector or sectors the remaining unselected sectors are not affected. The system is not required to provide any controls or timings during these operations. 15 MBM29F017E 70/90/12 The automatic sector erase begins after the "tTOW" time out from the rising edge of the WE pulse for the last sector erase command pulse and terminates when the data on DQ7 is "1" (see Write Operation Status section) at which time the device returns to the read mode. Data polling must be performed at an address within any of the sectors being erased. Figure 18 illustrates the Embedded EraseTM Algorithm using typical command strings and bus operations. Erase Suspend/Resume The Erase Suspend command allows the user to interrupt a Sector Erase operation and then perform data reads from or programs to a sector not being erased. This command is applicable ONLY during the Sector Erase operation which includes the time-out period for sector erase. The Erase Suspend command will be ignored if written during the Chip Erase operation or Embedded Program Algorithm. Writing the Erase Suspend command during the Sector Erase time-out results in immediate termination of the time-out period and suspension of the erase operation. Any other command written during the Erase Suspend mode will be ignored except the Erase Resume command. Writing the Erase Resume command resumes the erase operation. The addresses are DON'T CARES when writing the Erase Suspend or Erase Resume command. When the Erase Suspend command is written during the Sector Erase operation, the device will take a maximum of "tSPD" to suspend the erase operation. When the device has entered the erase-suspended mode, the RY/BY output pin and the DQ7 bit will be at logic "1", and DQ6 will stop toggling. The user must use the address of the erasing sector for reading DQ6 and DQ7 to determine if the erase operation has been suspended. Further writes of the Erase Suspend command are ignored. When the erase operation has been suspended, the device defaults to the erase-suspend-read mode. Reading data in this mode is the same as reading from the standard read mode except that the data must be read from sectors that have not been erase-suspended. Successively reading from the erase-suspended sector while the device is in the erase-suspend-read mode will cause DQ2 to toggle. (See the section on DQ2.) After entering the erase-suspend-read mode, the user can program the device by writing the appropriate command sequence for Byte Program. This program mode is known as the erase-suspend-program mode. Again, programming in this mode is the same as programming in the regular Byte Program mode except that the data must be programmed to sectors that are not erase-suspended. Successively reading from the erasesuspended sector while the device is in the erase-suspend-program mode will cause DQ2 to toggle. The end of the erase-suspended program operation is detected by the RY/BY output pin, Data polling of DQ7, or by the Toggle Bit I (DQ6) which is the same as the regular Byte Program operation. Note that DQ7 must be read from the Byte Program address while DQ6 can be read from any address. To resume the operation of Sector Erase, the Resume command (30H) should be written. Any further writes of the Resume command at this point will be ignored. Another Erase Suspend command can be written after the chip has resumed erasing. 16 MBM29F017E 70/90/12 Extended Command (1) Fast Mode MBM29F017E has Fast Mode function. This mode dispenses with the initial two unclock cycles required in the standard program command sequence by writing Fast Mode command into the command register. In this mode, the required bus cycle for programming is two cycles instead of four bus cycles in standard program command. (Do not write erase command in this mode.) The read operation is also executed after exiting this mode. To exit this mode, it is necessary to write Fast Mode Reset command into the command register. (Refer to the Figure 23.) The VCC active current is required even CE = VIH during Fast Mode. (2) Fast Programming During Fast Mode, the programming can be executed with two bus cycles operation. The Embedded Program Algorithm is executed by writing program set-up command (A0H) and data write cycles (PA/PD). (Refer to the Figure 23.) (3) Extended Sector Group Protection In addition to normal sector group protection, the MBM29F017E has Extended Sector Group Protection as extended function. This function enable to protect sector group by forcing VID on RESET pin and write a command sequence. Unlike conventional procedure, it is not necessary to force VID and control timing for control pins. The only RESET pin requires VID for sector group protection in this mode. The extended sector group protection requires VID on RESET pin. With this condition, the operation is initiated by writing the setup command (60H) into the command register. Then, the sector group addresses pins (A20, A19, and A18) and (A6, A1, A0) = (0, 1, 0) should be set to the sector group to be protected (recommend to set VIL for the other addresses pins), and write extended sector group protection command (60H). A sector group is typically protected in 250 s. To verify programming of the protection circuitry, the sector group addresses pins (A20, A19, and A18) and (A6, A1, A0) = (0, 1, 0) should be set and write a command (40H). Following the command write, a logical "1" at device output DQ0 will produce for protected sector in the read operation. If the output data is logical "0", please repeat to write extended sector group protection command (60H) again. To terminate the operation, it is necessary to set RESET pin to VIH. (Refer to the Figures 16 and 24.) (4) CFI (Common Flash Memory Interface) The CFI (Common Flash Memory Interface) specification outlines device and host system software interrogation handshake which allows specific vendor-specified software algorithms to be used for entire families of devices. This allows device-independent, JEDEC ID-independent, and forward-and backwardcompatible software support for the specified flash device families. Refer to CFI specification in detail. The operation is initiated by writing the query command (98H) into the command register. Following the command write, a read cycle from specific address retrives device information. Refer to the CFI code table. To terminate operation, it is necessary to write the read/reset command sequence into the register. (See Table 9.) 17 MBM29F017E 70/90/12 Write Operation Status Table 7 Hardware Sequence Flags DQ7 DQ6 DQ5 DQ3 DQ2 DQ7 Toggle 0 0 1 0 Toggle 0 1 Toggle 1 1 0 0 Toggle Erase Suspend Read (Non-Erase Suspended Sector) Data Data Data Data Data Erase Suspend Program (Non-Erase Suspended Sector) DQ7 Toggle (Note 1) 0 0 1 (Note 2) DQ7 Toggle 1 0 1 0 Toggle 1 1 N/A DQ7 Toggle 1 0 N/A Status TM Embedded Program Algorithm Embedded EraseTM Algorithm In progress Erase Suspend Read (Erase Suspended Sector) Erase Suspended Mode Embedded ProgramTM Algorithm Exceeded Time Limits Embedded EraseTM Algorithm Erase Suspended Mode Erase Suspend Program (Non-Erase Suspended Sector) Notes: 1. Performing successive read operations from any address will cause DQ6 to toggle. 2. Reading the byte address being programmed while in the erase-suspend program mode will indicate logic "1" at the DQ2 bit. However, successive reads from the erase-suspended sector will cause DQ2 to toggle. 3. DQ0 and DQ1 are reserved pins for future use. 4. DQ4 is Fujitsu internal use only. DQ7 Data Polling The MBM29F017E device features Data Polling as a method to indicate to the host that the embedded algorithms are in progress or completed. During the Embedded Program Algorithm, an attempt to read the device will produce the complement of the data last written to DQ7. Upon completion of the Embedded Program Algorithm, an attempt to read the device will produce the true data last written to DQ7. During the Embedded EraseTM Algorithm, an attempt to read the device will produce a "0" at the DQ7 output. Upon completion of the Embedded Erase Algorithm an attempt to read the device will produce a "1" at the DQ7 output. The flowchart for Data Polling (DQ7) is shown in Figure 19. Data polling will also flag the entry into Erase Suspend. DQ7 will switch "0" to "1" at the start of the Erase Suspend mode. Please note that the address of an erasing sector must be applied in order to observe DQ7 in the Erase Suspend Mode. During Program in Erase Suspend, Data polling will perform the same as in regular program execution outside of the suspend mode. For chip erase, the Data Polling is valid after the rising edge of the sixth WE pulse in the six write pulse sequence. For sector erase, the Data Polling is valid after the last rising edge of the sector erase WE pulse. Data Polling must be performed at sector address within any of the sectors being erased and not a sector that is within a protected sector group. Otherwise, the status may not be valid. 18 MBM29F017E 70/90/12 Just prior to the completion of Embedded Algorithm operation DQ7 may change asynchronously while the output enable (OE) is asserted low. This means that the device is driving status information on DQ7 at one instant of time and then that byte's valid data at the next instant of time. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device has completed the Embedded Algorithm operations and DQ7 has a valid data, the data outputs on DQ0 to DQ6 may be still invalid. The valid data on DQ0 to DQ7 will be read on the successive read attempts. The Data Polling feature is only active during the Embedded Programming Algorithm, Embedded Erase Algorithm, Erase Suspend, erase-suspend-program mode, or sector erase time-out. (See Table 7.) See Figure 9 for the Data Polling timing specifications and diagram. DQ6 Toggle Bit I The MBM29F017E also features the "Toggle Bit I" as a method to indicate to the host system that the embedded algorithms are in progress or completed. During an Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from the device at any address will result in DQ6 toggling between one and zero. Once the Embedded Program or Erase Algorithm cycle is completed, DQ6 will stop toggling and valid data will be read on the next successive attempts. During programming, the Toggle Bit I is valid after the rising edge of the fourth WE pulse in the four write pulse sequence. For chip erase, and sector erase the Toggle Bit I is valid after the rising edge of the sixth WE pulse in the six write pulse sequence. For Sector Erase, the Toggle Bit I is valid after the last rising edge of the sector erase WE pulse. The Toggle Bit I is active during the sector erase time out. In programming, if the sector being written to is protected, the Toggle Bit I will toggle for about 2 s and then stop toggling without the data having changed. In erase, the device will erase all the selected sectors except for the ones that are protected. If all selected sectors are protected, the chip will toggle the Toggle Bit I for about 200 s and then drop back into read mode, having changed none of the data. Either CE or OE toggling will cause the DQ6 to toggle. In addition, an Erase Suspend/Resume command will cause DQ6 to toggle. See Figure 10 for the Toggle Bit I timing specifications and diagram. DQ5 Exceeded Timing Limits DQ5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under these conditions DQ5 will produce a "1". This is a failure condition which indicates that the program or erase cycle was not successfully completed. Data Polling DQ7, DQ6 is the only operating function of the device under this condition. The CE circuit will partially power down the device under these conditions (to approximately 2 mA). The OE and WE pins will control the output disable functions as described in Table 2. The DQ5 failure condition may also appear if a user tries to program a 1 to a location that is previously programmed to 0. In this case the device locks out and never completes the Embedded Algorithm operation. Hence, the system never reads a valid data on DQ7 bit and DQ6 never stops toggling. Once the device has exceeded timing limits, the DQ5 bit will indicate a "1." Please note that this is not a device failure condition since the device was incorrectly used. If this occurs, reset the device. 19 MBM29F017E 70/90/12 DQ3 Sector Erase Timer After the completion of the initial sector erase command sequence the sector erase time-out will begin. DQ3 will remain low until the time-out is complete. Data Polling and Toggle Bit I are valid after the initial sector erase command sequence. If Data Polling or the Toggle Bit I indicates the device has been written with a valid erase command, DQ3 may be used to determine if the sector erase timer window is still open. If DQ3 is high ("1") the internally controlled erase cycle has begun; attempts to write subsequent commands (other than Erase Suspend) to the device will be ignored until the erase operation is completed as indicated by Data Polling or Toggle Bit I. If DQ3 is low ("0"), the device will accept additional sector erase commands. To insure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3 were high on the second status check, the command may not have been accepted. Refer to Table 7: Hardware Sequence Flags. DQ2 Toggle Bit II This toggle bit II, along with DQ6, can be used to determine whether the device is in the Embedded EraseTM Algorithm or in Erase Suspend. Successive reads from the erasing sector will cause DQ2 to toggle during the Embedded EraseTM Algorithm. If the device is in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause DQ2 to toggle. When the device is in the erase-suspended-program mode, successive reads from the byte address of the non-erase suspended sector will indicate a logic "1" at the DQ2 bit. Table 8 Toggle Bit Status DQ7 DQ6 DQ2 DQ7 Toggles 1 Erase 0 Toggles Toggles Erase Suspend Read (1) (Erase-Suspended Sector) 1 1 Toggles DQ7 (2) Toggles 1 (2) Mode Program Erase Suspend Program Notes: 1. These status flags apply when outputs are read from a sector that has been erase-suspended. 2. These status flags apply when outputs are read from the byte address of the non-erase suspended sector. DQ6 is different from DQ2 in that DQ6 toggles only when the standard program or Erase, or Erase Suspend Program operation is in progress. The behavior of these two status bits, along with that of DQ7, is summarized as follows: For example, DQ2 and DQ6 can be used together to determine the erase-suspend-read mode (DQ2 toggles while DQ6 does not). See also Table 8 and Figure 11. Furthermore, DQ2 can also be used to determine which sector is being erased. When the device is in the erase mode, DQ2 toggles if this bit is read from the erasing sector. 20 MBM29F017E 70/90/12 RY/BY Ready/Busy The MBM29F017E provides a RY/BY open-drain output pin as a way to indicate to the host system that the Embedded Algorithms are either in progress or has been completed. If the output is low, the device is busy with either a program or erase operation. If the output is high, the device is ready to accept any read/write or erase operation. When the RY/BY pin is low, the device will not accept any additional program or erase commands with the exception of the Erase Suspend command. If the MBM29F017E is placed in an Erase Suspend mode, the RY/BY output will be high, by means of connecting with a pull-up resistor to VCC. During programming, the RY/BY pin is driven low after the rising edge of the fourth WE pulse. During an erase operation, the RY/BY pin is driven low after the rising edge of the sixth WE pulse. The RY/BY pin will indicate a busy condition during RESET pulse. Refer to Figure 12 for a detailed timing diagram. The RY/BY pin is pulled high in standby mode. Since this is an open-drain output, several RY/BY pins can be tied together in parallel with a pull-up resistor to VCC. RESET Hardware Reset The MBM29F017E device may be reset by driving the RESET pin to VIL. The RESET pin must be kept low (VIL) for at least "tRP". Any operation in progress will be terminated and the internal state machine will be reset to the read mode "tREADY" after the RESET pin is driven low. If a hardware reset occurs during a program operation, the data at that particular location will be indeterminate. When the RESET pin is low and the internal reset is complete, the device goes to standby mode and cannot be accessed. Also, note that all the data output pins are tri-stated for the duration of the RESET pulse. Once the RESET pin is taken high, the device requires tRH of wake up time until outputs are valid for read access. The RESET pin may be tied to the system reset input. Therefore, if a system reset occurs during the Embedded Program or Erase Algorithm, the device will be automatically reset to read mode and this will enable the system's microprocessor to read the boot-up firmware from the Flash memory. Data Protection The MBM29F017E is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. During power up the device automatically resets the internal state machine in the Read mode. Also, with its control register architecture, alteration of the memory contents only occurs after successful completions of specific multi-bus cycle command sequences. The device also incorporates several features to prevent inadvertent write cycles resulting from VCC power-up and power-down transitions or system noise. Low VCC Write Inhibit To avoid initiation of a write cycle during VCC power-up and power-down, a write cycle is locked out for VCC less than VLKO (min.). If VCC < VLKO, the command register is disabled and all internal program/erase circuits are disabled. Under this condition the device will reset to the read mode. Subsequent writes will be ignored until the VCC level is greater than VLKO. It is the users responsibility to ensure that the control pins are logically correct to prevent unintentional writes when VCC is above VLKO (min.). Write Pulse "Glitch" Protection Noise pulses of less than 5 ns (typical) on OE, CE, or WE will not initiate a write cycle. 21 MBM29F017E 70/90/12 Logical Inhibit Writing is inhibited by holding any one of OE = VIL, CE = VIH or WE = VIH. To initiate a write cycle CE and WE must be a logical zero while OE is a logical one. Power-Up Write Inhibit Power-up of the device with WE = CE = VIL and OE = VIH will not accept commands on the rising edge of WE. The internal state machine is automatically reset to the read mode on power-up. 22 MBM29F017E 70/90/12 Table 9 Description Query-unique ASCII string "QRY" Primary OEM Command Set 2h: AMD/FJ standard type Address for Primary Extended Table Alternate OEM Command Set (00h = not applicable) Address for Alternate OEM Extended Table VCC Min. (write/erase) D7-4: volt, D3-0: 100 mvolt VCC Max. (write/erase) D7-4: volt, D3-0: 100 mvolt VPP Min. voltage VPP Max. voltage Typical timeout per single byte/word write 2N S Typical timeout for Min. size buffer write 2N S Typical timeout per individual block erase 2N mS Typical timeout for full chip erase 2N mS Max. timeout for byte/word write 2N times typical Max. timeout for buffer write 2N times typical Max. timeout per individual block erase 2N times typical Max. timeout for full chip erase 2N times typical Device Size = 2N byte Flash Device Interface description Max. number of byte in multi-byte write = 2N Number of Erase Block Regions within device Common Flash Memory Interface Code A0 to A6 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh DQ0 to DQ7 51h 52h 59h 02h 00h 40h 00h 00h 00h 00h 00h 45h 1Ch 55h 1Dh 1Eh 1Fh 00h 00h 03h 20h 00h 21h 0Ah 22h 00h 23h 05h 24h 00h 25h 04h 26h 00h 27h 28h 29h 2Ah 2Bh 2Ch 15h 00h 00h 00h 00h 01h Description Erase Block Region 1 Information Query-unique ASCII string "PRI" Major version number, ASCII Minor version number, ASCII Address Sensitive Unlock 0h = Required 1h = Not Required Erase Suspend 0h = Not Supported 1h = To Read Only 2h = To Read & Write Sector Protection 0h = Not Supported X = Number of sectors in per group Sector Temporary Unprotection 00h = Not Supported 01h = Supported Sector Protection Algorithm Number of Sector for Bank 2 00h = Not Supported Burst Mode Type 00h = Not Supported Page Mode Type 00h = Not Supported ACC (Acceleration) Supply Minimum 00h = Not Supported, D7-4: volt, D3-0: 100 mvolt ACC (Acceleration) Supply Maximum 00h = Not Supported, D7-4: volt, D3-0: 100 mvolt Boot Type A0 to A6 2Dh 2Eh 2Fh 30h 40h 41h 42h 43h 44h 45h DQ0 to DQ7 46h 02h 47h 04h 48h 01h 49h 4Ah 04h 00h 4Bh 00h 4Ch 00h 4Dh 00h 4Eh 00h 4Fh 00h 1Fh 00h 00h 01h 50h 52h 49h 31h 31h 01h 23 MBM29F017E 70/90/12 ABSOLUTE MAXIMUM RATINGS Storage Temperature ........................................................................................-55C to +125C Ambient Temperature with Power Applied ........................................................-40C to +85C Voltage with Respect to Ground All pins except A9, OE, and RESET (Note 1).-2.0 V to +7.0 V VCC (Note 1) ......................................................................................................-2.0 V to +7.0 V A9, OE, and RESET (Note 2) ............................................................................-2.0 V to +13.5 V Notes: 1. Minimum DC voltage on input or I/O pins is -0.5 V. During voltage transitions, inputs may negative overshoot VSS to -2.0 V for periods of up to 20 ns. Maximum DC voltage on output and I/O pins is VCC +0.5 V. During voltage transitions, outputs may positive overshoot to VCC +2.0 V for periods up to 20 ns. 2. Minimum DC input voltage on A9, OE, and RESET pins are -0.5 V. During voltage transitions, A9, OE, and RESET pins may negative overshoot VSS to -2.0 V for periods of up to 20 ns. Maximum DC input voltage on A9, OE, and RESET are +13.0 V which may overshoot to 14.0 V for periods up to 20 ns. Voltage difference between input voltage and power supply. (VIN - VCC) do not exceed 9 V. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. RECOMMENDED OPERATING RANGES Ambient Temperature (TA) Ambient Temperature for MBM29F017E 70.................................................... -20C to +70C Ambient Temperature for MBM29F017E 90/12............................................... -40C to +85C VCC Supply Voltages VCC Supply Voltages for MBM29F017E 70...................................................... +4.75 V to +5.25 V VCC Supply Voltages for MBM29F017E 90/12................................................. +4.50 V to + 5.50 V Operating ranges define those limits between which the functionality of the device is guaranteed. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 24 MBM29F017E 70/90/12 MAXIMUM OVERSHOOT 20 ns +0.8 V 20 ns -0.5 V -2.0 V 20 ns Figure 1 Maximum Negative Overshoot Waveform 20 ns VCC +2.0 V VCC +0.5 V +2.0 V 20 ns Figure 2 20 ns Maximum Positive Overshoot Waveform 1 20 ns +14.0 V +13.0 V VCC +0.5 V 20 ns 20 ns Note : This waveform is applied for A9, OE, and RESET. Figure 3 Maximum Positive Overshoot Waveform 2 25 MBM29F017E 70/90/12 DC CHARACTERISTICS Parameter Symbol Parameter Description Test Conditions Min. Max. Unit ILI Input Leakage Current VIN = VSS to VCC, VCC = VCC Max. -1.0 +1.0 A ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC Max. -1.0 +1.0 A ILIT A9, OE, RESET Inputs Leakage Current VCC = VCC Max. A9, OE, RESET = 12.5 V -- 50 A ICC1 VCC Active Current (Note 1) CE = VIL, OE = VIH -- 40 mA ICC2 VCC Active Current (Note 2) CE = VIL, OE = VIH -- 60 mA VCC = VCC Max., CE = VIH RESET = VIH -- 1 mA VCC = VCC Max., CE = VCC 0.3 V, RESET = VCC 0.3 V -- 5 A VCC = VCC Max. RESET = VIL -- 1 mA VCC = VCC Max. RESET = VSS 0.3 V -- 5 A ICC3 ICC4 VCC Current (Standby) VCC Current (Standby, Reset) VIL Input Low Level -- -0.5 0.8 V VIH Input High Level -- 2.0 VCC+0.5 V VID Voltage for Autoselect and Sector Protection (A9, OE, RESET) (Note 3, 4) -- 11.5 12.5 V VOL Output Low Voltage Level IOL = 12.0 mA, VCC = VCC Min. -- 0.45 V IOH = -2.5 mA, VCC = VCC Min. 2.4 -- V VCC-0.4 -- V 3.2 4.2 V VOH1 Output High Voltage Level VOH2 VLKO Low VCC Lock-Out Voltage IOH = -100 A -- Notes: 1. The ICC current listed includes both the DC operating current and the frequency dependent component (at 6 MHz). The frequency component typically is 2 mA/MHz, with OE at VIH. 2. ICC active while Embedded Algorithm (program or erase) is in progress. 3. Applicable for only VCC applying. 4. (VID -VCC) do not exceed 9 V. 26 MBM29F017E 70/90/12 AC CHARACTERISTICS * Read Only Operations Characteristics Parameter Symbols Description 70 90 12 (Note1) (Note2) (Note2) Unit Test Setup JEDEC Standard tAVAV tRC Read Cycle Time tAVQV tACC Address to Output Delay tELQV tCE Chip Enable to Output Delay tGLQV tOE Output Enable to Output Delay tEHQZ tDF tGHQZ tAXQX -- -- Min. 70 90 120 ns CE = VIL OE = VIL Max. 70 90 120 ns OE = VIL Max. 70 90 120 ns -- Max. 30 35 50 ns Chip Enable to Output HIGH-Z -- Max. 20 20 30 ns tDF Output Enable to Output HIGH-Z -- Max. 20 20 30 ns tOH Output Hold Time From Addresses, CE or OE, whichever occurs first -- Min. 0 0 0 ns tREADY RESET Pin Low to Read Mode -- Max. 20 20 20 s Note: 1. Test Conditions: Output Load: 1 TTL gate and 30 pF Input rise and fall times: 5 ns Input pulse levels: 0.0 V to 3.0 V Timing measurement reference level Input: 1.5 V Output: 1.5 V Note: 2. Test Conditions: Output Load: 1 TTL gate and 100 pF Input rise and fall times: 5 ns Input pulse levels: 0.45 V to 2.4 V Timing measurement reference level Input: 0.8 V and 2.0 V Output: 0.8 V and 2.0 V 5.0 V IN3064 or Equivalent 2.7 k Device Under Test 6.2 k CL Diodes = IN3064 or Equivalent Figure 4 Test Conditions 27 MBM29F017E 70/90/12 * Write/Erase/Program Operations Parameter Symbols JEDEC 70 90 12 (Note1) (Note2) (Note2) Unit Description Standard tAVAV tWC Write Cycle Time Min. 70 90 120 ns tAVWL tAS Address Setup Time Min. 0 0 0 ns tWLAX tAH Address Hold Time Min. 45 45 50 ns tDVWH tDS Data Setup Time Min. 30 45 50 ns tWHDX tDH Data Hold Time Min. 0 0 0 ns -- tOES Output Enable Setup Time Min. 0 0 0 ns 0 0 0 ns tOEH Output Read Enable Hold Toggle Bit I and Data Polling Time Min. -- Min. 10 10 10 ns tGHWL tGHWL Read Recover Time Before Write Min. 0 0 0 ns tGHEL tGHEL Read Recover Time Before Write Min. 0 0 0 ns tELWL tCS CE Setup Time Min. 0 0 0 ns tWLEL tWS WE Setup Time Min. 0 0 0 ns tWHEH tCH CE Hold Time Min. 0 0 0 ns tEHWH tWH WE Hold Time Min. 0 0 0 ns tWLWH tWP Write Pulse Width Min. 35 35 50 ns tELEH tCP Write Pulse Width Min. 35 35 50 ns tWHWL tWPH Write Pulse Width High Min. 20 20 20 ns tEHEL tCPH Write Pulse Width High Min. 20 20 20 ns tWHWH1 tWHWH1 Byte Programming Operation Typ. 8 8 8 s tWHWH2 tWHWH2 Sector Erase Operation (Note 3) Typ. 1 1 1 sec Max. 8 8 8 sec -- tVCS VCC Setup Time Min. 50 50 50 s -- tVIDR Rise Time to VID (Note 4) Min. 500 500 500 ns -- tVLHT Voltage Transition Time (Note 4) Min. 4 4 4 s -- tWPP Write Pulse Width (Note 4) Min. 100 100 100 s -- tOESP OE Setup Time to WE Active (Note 4) Min. 4 4 4 s -- tCSP CE Setup Time to WE Active (Note 4) Min. 4 4 4 s -- tRB Recover Time from RY/BY Min. 0 0 0 ns (Continued) 28 MBM29F017E 70/90/12 (Continued) Parameter Symbols JEDEC 70 90 12 (Note1) (Note2) (Note2) Unit Description Standard -- tRP RESET Pulse Width Min. 500 500 500 ns -- tRH RESET Hold Time Before Read Min. 50 50 50 ns -- tBUSY Program/Erase Valid to RY/BY Delay Max. 70 90 120 ns -- tEOE Delay Time from Embedded Output Enable Max. 70 90 120 ns -- tTOW Erase Time-out Time Min. 50 50 50 s -- tSPD Erase Suspend Transition Time Max. 15 15 15 s Notes: 3. This does not include the preprogramming time. 4. This timing is for Sector Group Protection operation. 29 MBM29F017E 70/90/12 SWITCHING WAVEFORMS * Key to Switching Waveforms WAVEFORM INPUTS OUTPUTS Must Be Steady Will Be Steady May Change from H to L Will Be Changing from H to L May Change from L to H Will Be Changing from L to H "H" or "L" Any Change Permitted Changing, State Unknown Does Not Apply Center Line is HighImpedance "Off" State t RC A 0 to A 20 Addresses Stable t ACC CE t OE t DF OE t OEH WE t CE DQ 0 to DQ 7 High-Z Figure 5. 1 30 t OH Output Valid Read Operation Timing Diagram MBM29F017E 70/90/12 tRC A0 to A20 Addresses Stable tACC CE tRH tRP tRH tCE RESET tOH High-Z DQ0 to DQ7 Figure 5. 2 Output Valid Hardware Reset/Read Operation Timing Diagram 31 MBM29F017E 70/90/12 3rd Bus Cycle A 0 to A 20 Data Polling XXXH t WC PA t AS PA t AH t RC CE t CS t CH t CE OE t WP t WHWH1 t WPH t OE t GHWL WE t DS t OH t DH A 0H Data PD DQ 7 D OUT D OUT Notes: 1. PA is address of the memory location to be programmed. 2. PD is data to be programmed at byte address. 3. DQ7 is the output of the complement of the data written to the device. 4. DOUT is the output of the data written to the device. 5. Figure indicates last two bus cycles of four bus cycle sequence. Figure 6 32 Alternate WE Controlled Program Operation Timing Diagram MBM29F017E 70/90/12 3rd Bus Cycle A 0 to A 20 Data Polling PA XXXH t AS t WC PA t AH WE t WS t WH OE t GHEL t CP t CPH t WHWH1 CE t DS Data t DH A 0H PD DQ 7 D OUT Notes: 1. PA is address of the memory location to be programmed. 2. PD is data to be programmed at byte address. 3. DQ7 is the output of the complement of the data written to the device. 4. DOUT is the output of the data written to the device. 5. Figure indicates last two bus cycles of four bus cycle sequence. Figure 7 Alternate CE Controlled Program Operation Timing Diagram 33 MBM29F017E 70/90/12 A 0 to A 20 XXXH XXXH t WC t AS XXXH XXXH XXXH SA t AH CE t CS t CH OE t WP t GHWL t WPH WE t DS t DH AAH Data 55H 80H AAH 55H t VCS V CC Note: SA is the sector address for Sector Erase. Addresses = XXXH for Chip Erase. Figure 8 34 Chip/Sector Erase Operation Timing Diagram 10H/30H MBM29F017E 70/90/12 CE t CH t OE t DF OE t OEH WE t CE * DQ7 Data DQ7 = Valid Data DQ7 High-Z t WHWH1 or 2 DQ0 to DQ6 Data DQ0 to DQ6 = Output Flag DQ0 to DQ6 Valid Data High-Z t EOE * : DQ7 = Valid Data (The device has completed the Embedded operation.) Figure 9 Data Polling During Embedded Algorithm Operation Timing Diagram CE tOEH WE tOES tOEH OE * DQ0 to DQ7 Data DQ6 = Toggle DQ6 = Stop Toggling DQ6 = Toggle DQ0 to DQ7 Valid tOE * : DQ6 stops toggling (The device has completed the Embedded operation.) Figure 10 Toggle Bit I during Embedded Algorithm Operation Timing Diagram 35 MBM29F017E 70/90/12 Enter Embedded Erasing Erase Suspend WE Erase Enter Erase Suspend Program Erase Suspend Read Erase Resume Erase Suspend Program Erase Suspend Read Erase DQ6 DQ2 Toggle DQ2 and DQ6 with OE Note: DQ2 is read from the erase-suspended sector. Figure 11 DQ2 vs. DQ6 CE The rising edge of the last WE signal WE Entire programming or erase operations RY/BY tBUSY Figure 12 36 RY/BY Timing Diagram During Program/Erase Operation Erase Complete MBM29F017E 70/90/12 WE RESET tRP tREADY tRB RY/BY Figure 13 RESET, RY/BY Timing Diagram 37 MBM29F017E 70/90/12 A 20, A 19, A 18 SGAX SGAY A0 A1 A6 VID 5V A9 tVLHT VID 5V OE tVLHT tVLHT tVLHT tWPP WE tOESP tCSP CE Data 01H tOE tVCS VCC SGAX = Sector Group Address for initial sector SGAY = Sector Group Address for next sector Figure 14 38 Sector Group Protection Timing Diagram MBM29F017E 70/90/12 VCC tVIDR tVCS tVLHT VID 5V 5V RESET CE WE tVLHT Program or Erase Command Sequence tVLHT RY/BY Unprotection period Figure 15 Temporary Sector Group Unprotection Timing Diagram 39 MBM29F017E 70/90/12 VCC tVCS tVLHT RESET tVIDR tWC Add tWC SGAX SGAX SGAY A0 A1 A6 CE OE TIME-OUT tWP WE Data 60H 60H 40H 01H tOE SGAX : Sector Group Address to be protected SGAY : Next Sector Group Address to be protected TIME-OUT : Time-Out window = 250 s (min) Figure 16 40 Extended Sector Group Protection Timing Diagram 60H MBM29F017E 70/90/12 EMBEDDED ALGORITHMS Start Write Program Command Sequence (See Below) Data Polling Device Increment Address No Last Address ? Yes Programming Completed Program Command Sequence (Address/Command): XXXH/AAH XXXH/55H XXXH/A0H Program Address/Program Data Figure 17 Embedded ProgramTM Algorithm 41 MBM29F017E 70/90/12 EMBEDDED ALGORITHMS Start Write Erase Command Sequence (See Below) Data Polling or Toggle Bit I Successfully Completed Erasure Completed Chip Erase Command Sequence (Address/Command): Individual Sector/Multiple Sector Erase Command Sequence (Address/Command): XXXH/AAH XXXH/AAH XXXH/55H XXXH/55H XXXH/80H XXXH/80H XXXH/AAH XXXH/AAH XXXH/55H XXXH/55H XXXH/10H Sector Address/30H Sector Address/30H Additional sector erase commands are optional. Sector Address/30H Note: To insure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3 were high on the second status check, the command may not have been accepted. Figure 18 42 Embedded EraseTM Algorithm MBM29F017E 70/90/12 Start VA = Address for programming = Any of the sector addresses within the sector being erased during sector erase or multiple erases operation. = Any of the sector group addresses within the sector not being protected during sector erase or multiple sector erases operation. Read Byte (DQ0 to DQ7) Addr. = VA DQ7 = Data? Yes No No DQ5 = 1? Yes Read Byte (DQ0 to DQ7) Addr. = VA DQ7 = Data? Yes No Fail Pass Note: DQ7 is rechecked even if DQ5 = "1" because DQ7 may change simultaneously with DQ5. Figure 19 Data Polling Algorithm 43 MBM29F017E 70/90/12 Start Read Byte (DQ0 to DQ7) Addr. = "H" or "L" No DQ6 = Toggle ? Yes No DQ5 = 1 ? Yes Read Byte (DQ0 to DQ7) Addr. = "H" or "L" DQ6 = Toggle ? No Yes Fail Pass Note: DQ6 is rechecked even if DQ5 = "1" because DQ6 may stop toggling at the same time as DQ5 changing to "1". Figure 20 44 Toggle Bit I Algorithm MBM29F017E 70/90/12 Start Setup Sector Group Addr. (A20, A19, A18) PLSCNT = 1 OE = VID, A9 = VID, CE = VIL, RESET = VIH Increment PLSCNT Activate WE Pulse Time out 100 s WE = VIH, CE = OE = VIL, (A9 should remain VID) Read from Sector Group Addr. (A20, A19, A18) A1 = 1, A0 = A6 = 0 No No PLSCNT = 25? Data = 01H? Yes Yes Remove VID from A9 Write Reset Command Yes Protect Another Sector Group? No Device Failed Remove VID from A9 Write Reset Command Sector Group Protection Completed Figure 21 Sector Group Protection Algorithm 45 MBM29F017E 70/90/12 Start RESET = VID (Note 1) Perform Erase or Program Operations RESET = VIH Temporary Sector Group Unprotection Completed (Note 2) Notes: 1. All Protected sector groups unprotected. 2. All previously protected sector groups are protected once again. Figure 22 46 Temporary Sector Group Unprotection Algorithm MBM29F017E 70/90/12 FAST MODE ALGORITHM Start XXXH/AAH Set Fast Mode XXXH/55H XXXH/20H XXXH/A0H Program Address/Program Data Data Polling Device Verify Byte? No In Fast Program Yes Increment Address No Last Address ? Yes Programming Completed XXXH/90H Reset Fast Mode XXXH/F0H Figure 23 Embedded ProgramTM Algorithm for Fast Mode 47 MBM29F017E 70/90/12 Start RESET = VID Wait to 4 s Device is Operating in Temporary Sector Group Unprotection Mode No Extended Sector Group Protection Entry? Yes To Setup Sector Group Protection Write XXXH/60H PLSCNT = 1 To Sector Group Protection Write SGA/60H (A0 = VIL, A1 = VIH, A6 = VIL) Time Out 250 s Increment PLSCNT To Verify Sector Group Protection Write SGA/40H (A0 = VIL, A1 = VIH, A6 = VIL) Setup Next Sector Group Address Read from Sector Group Address (A0 = VIL, A1 = VIH, A6 = VIL) No No PLSCNT = 25? Yes Remove VID from RESET Write Reset Command Data = 01H? Yes Yes Protection Other Sector Group ? No Device Failed Remove VID from RESET Write Reset Command Sector Group Protection Completed Figure 24 48 Extended Sector Group Protection Algorithm MBM29F017E 70/90/12 ERASE AND PROGRAMMING PERFORMANCE Limits Parameter Unit Comments Min. Typ. Max. Sector Erase Time -- 1 8 sec Excludes 00H programming prior to erasure Byte Programming Time -- 8 150 s Excludes system-level overhead Chip Programming Time -- 16.8 40 sec Excludes system-level overhead 1,000,000 -- -- cycles Erase/Program Cycle TSOP(I) PIN CAPACITANCE Parameter Symbol Parameter Description Test Setup Typ. Max. Unit CIN Input Capacitance VIN = 0 T.B.D. T.B.D. pF COUT Output Capacitance VOUT = 0 T.B.D. T.B.D. pF CIN2 Control Pin Capacitance VIN = 0 T.B.D. T.B.D. pF Note: Test conditions TA = 25C, f = 1.0 MHz 49 MBM29F017E 70/90/12 ORDERING INFORMATION Standard Products Fujitsu standard products are available in several packages. The order number is formed by a combination of: MBM29F017 E 70 TN PACKAGE TYPE TN = 48-Pin Thin Small Outline Package (TSOP) Standard Pinout TR = 48-Pin Thin Small Outline Package (TSOP) Reverse Pinout SPEED OPTION See Product Selector Guide Device Revision DEVICE NUMBER/DESCRIPTION MBM29F017 16 Mega-bit (2 M x 8-Bit) CMOS Flash Memory 5.0 V-only Read, Write, and Erase 64 K Byte (32 Sectors) Valid Combinations Valid Combinations MBM29F017E 50 70 90 12 TN TR Valid Combinations list configurations planned to be supported in volume for this device. Consult the local Fujitsu sales office to confirm availability of specific valid combinations and to check on newly released combinations. MBM29F017E 70/90/12 PACKAGE DIMENSIONS *: Resin Protrusion. (Each Side:0.15(.006)MAX) 48-pin plastic TSOP(I) (FPT-48P-M19) LEAD No. 48 1 Details of "A" part INDEX 0.15(.006) MAX 0.35(.014) MAX "A" 0.15(.006) 0.25(.010) 25 24 20.000.20 (.787.008) * 18.400.20 (.724.008) * 12.000.20 (.472.008) 11.50REF (.460) +0.10 1.10 -0.05 +.004 .043 -.002 (Mounting height) 0.10(.004) 0.50(.0197) TYP 0.150.05 (.006.002) 19.000.20 (.748.008) C 1996 FUJITSU LIMITED F48029S-2C-2 0.05(0.02)MIN STAND OFF 0.200.10 (.008.004) 0.10(.004) M 0.500.10 (.020.004) Dimensions in mm(inches) (Continued) 51 MBM29F017E 70/90/12 (Continued) *: Resin Protrusion. (Each Side:0.15(.006)MAX) 48-pin plastic TSOP(I) (FPT-48P-M20) LEAD No. 48 1 Details of "A" part INDEX 0.15(.006) MAX 0.35(.014) MAX "A" 0.15(.006) 0.25(.010) 25 24 19.000.20 (.748.008) 0.500.10 (.020.004) 0.150.10 (.006.002) 0.10(.004) 0.200.10 (.008.004) 0.50(.0197) TYP 0.10(.004) M 0.05(0.02)MIN STAND OFF +0.10 * 18.400.20 (.724.008) 20.000.20 (.787.008) C 52 1996 FUJITSU LIMITED F48030S-2C-2 11.50(.460)REF 1.10 -0.05 +.004 .043 -.002 (Mounting height) * 12.000.20(.472.008) Dimensions in mm(inches) MBM29F017E 70/90/12 MEMO 53 MBM29F017E 70/90/12 MEMO 54 MBM29F017E 70/90/12 MEMO 55 MBM29F017E 70/90/12 FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-8588, Japan Tel: 81(44) 754-3763 Fax: 81(44) 754-3329 http://www.fujitsu.co.jp/ North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, USA Tel: (408) 922-9000 Fax: (408) 922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: (800) 866-8608 Fax: (408) 922-9179 http://www.fujitsumicro.com/ Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 D-63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122 http://www.fujitsu-ede.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220 http://www.fmap.com.sg/ F9908 FUJITSU LIMITED Printed in Japan 56 All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have an inhereut chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.