1PS8527A 06/01/06
Product Description
The PI74ALVCH16374 is particularly suitable for implementing
buffer registers, I/O ports, bidirectional bus drivers, and working
registers. This device can be used as two 8-bit flip-flops or one
16-bit flip-flop. On the positive transition of the Clock (CLK) input,
the Q outputs of the flip-flop take on the logic levels set up at the
data (D) inputs. OE can be used to place the eight outputs in either
a normal logic state (high or low logic levels) or a high-impedance
state. In that state, the outputs neither load nor drive the bus lines
significantly. The high-impedance state and the increased drive
provide the capability to drive bus lines without need for interface
or pullup components. OE does not affect internal operations of the
flip-flop. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power
down, OE should be tied to VCC through a pullup resistor; the
minimum value of the resistor is determined by the current-sinking
capability of the driver.
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1
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5
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2.5V 16-Bit Edge Triggered D-Type
Flip-Flop with 3-State Outputs
Logic Block Diagram
Product Features
• PI74AVC+16374 is designed for low-voltage operation,
VCC = 1.65V to 3.6V
• True ±24mA Balanced Drive @ 3.3V
• Compatible with Philips and T.I. AVC Logic family
•I
OFF supports partial power-down operation
• 3.6V I/O Tolerant inputs and outputs
• All outputs contain a patented DDC
(Dynamic DriveControl) circuit that reduces noise without
degrading propagation delay.
• Industrial operation at –40°C to +85°C
• Packaging (Pb-free & Green available):
– 48-pin 240-mil wide plastic TSSOP (A)
– 48-pin 173-mil wide plastic TVSOP (K)
PI74AVC+16374
1CLK
1Q1
1D
C1
1D1
To Seven Other Channels
1OE
1
48
47
2
2CLK
2Q1
1D
C1
2D1
To Seven Other Channels
25
36
13
24
2OE
06-0168
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PI74AVC+16374
2.5V 16-Bit Edge Triggered D-Type
Flip Flop with 3-State Outputs
1
2
3
4
5
6
7
8
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
32
31
30
29
28
27
26
25
1OE 1CLK
1Q1 1D1
1Q2 1D2
GND GND
1Q3 1D3
1Q4 1D4
V
1Q5 1D5
1Q6 1D6
GND GND
1Q7 1D7
1Q8 1D8
2Q1 2D1
2Q2 2D2
GND GND
2Q3 2D3
2Q4 2D4
2Q5 2D5
2Q6 2D6
GND GND
2Q7 2D7
2Q8 2D8
2OE 2CLK
CC
VCC
VCC
VCC
Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.)
Supply voltage range, VCC ............................................. –0.5V to +4.6V
Input voltage range, VI................................................... –0.5V to +4.6V
Voltage range applied to any output in the
high-impedance or power-off state, VO(1) ...................... –0.5V to +4.6V
Voltage range applied to any output in the
high or low state, VO(1,2) ......................................... –0.5V to VCC
+0.5V
Input clamp current, IIK (VI <0) .................................................... –50mA
Output clamp current, IOK (VO <0) .............................................. –50mA
Continuous output current, IO.................................................... ±50mA
Continuous current through each VCC or GND ......................... ±100mA
Package thermal impedance, θJA(3): package A .........................64°C/W
package K .........................48°C/W
Storage Temperature range, Tstg .................................... –65°C to 150°C
1. Input & output negative-voltage ratings may be
exceeded if the input and output curent rating are
observed.
2. Output positive-voltage rating may be exceeded up to
4.6V maximum if the output current rating is observed.
3. The package thermal impedance is calculated in accor-
dance with JESD 51.
Notes:
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
stupnIstuptuO
EOKLCDQ
L↑HH
L↑LL
LLroHXQ
0
HXX Z
Pin Name Description
OE 3-State Output Enable Inputs (Active LOW)
CLK Clock Input (Active HIGH)
Dx Data Inputs
Qx 3-State Outputs
GND Ground
VCC Power
Product Pin Description
T ruth T able(1)
Product Pin Configuration
Notes:
1. H = High Signal Level
L = Low Signal Level
X = Don’t Care or Irrelevant
Z = High Impedance
06-0168
3PS8527A 06/01/06
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PI74AVC+16374
2.5V 16-Bit Edge Triggered D-Type
Flip Flop with 3-State Outputs
Recommended Operating Conditions(1)
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VCC egatloVylppuS gnitarepO4.16.3
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VHI egatloVtupnIlevel-hgiH
VCC V2.1=V
CC
VCC V6.1otV4.1=Vx56.0 CC
VCC V59.1otV56.1=Vx56.0 CC
VCC V7.2otV3.2=7.1
VCC V6.3otV3=2
VLI egatloVtupnIlevel-woL
VCC V2.1=DNG
VCC V6.1otV4.1=Vx53.0 CC
VCC V59.1otV56.1=Vx53.0 CC
VCC V7.2otV3.2=7.0
VCC V6.3otV3=8.0
VIegatloVtupnI 06.3
VOegatloVtuptuO
etatSevitcA0V
CC
etatS-306.3
ISHO tnerructuptuolevel-hgiH
VCC V6.1otV4.1=4–
Am
VCC V59.1otV56.1=6–
VCC V7.2otV3.2=21–
VCC V6.3otV3=42–
ISLO tnerructuptuolevel-woL
VCC V6.1otV4.1=4
VCC V59.1otV56.1=6
VCC V7.2otV3.2=21
VCC V6.3otV3=42
ΔtΔetarllafroesirnoitisnarttupnIv V CC V6.3otV4.1=5V/sn
TAerutarepmetria-eerfgnitarepO 04–58C°
Notes:
1. All unused inputs must be held at VCC or GND to ensure proper device operation.
06-0168
4PS8527A 06/01/06
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PI74AVC+16374
2.5V 16-Bit Edge Triggered D-Type
Flip Flop with 3-State Outputs
sretemaraPsnoitidnoCtseT
)1(
V
CC
.niM.pyT.xaMstinU
V
HO
I
HO
001–= μAV6.3otV4.1V
CC
V2.0–
V
I
SHO
4–=m VA
HI
V19.0=V4.150.1
I
SHO
6–=m VA
HI
V70.1=V56.12.1
I
SHO
21–=m VA
HI
V7.1=V3.257.1
I
SHO
42–=m VA
HI
V2=V30.2
V
LO
I
SLO
001= μAV6.3otV4.12.0
I
SLO
4=m VA
LI
V94.0=V4.14.0
I
SLO
6=m VA
LI
V75.0=V56.154.0
I
SLO
21=m VA
LI
V7.0=V3.255.0
I
SLO
42=m VA
LI
V8.0=V38.0
I
I
V
I
V=
CC
DNGroV6.35.2±
Aμ
I
FFO
V
I
Vro
O
V6.3=0 01±
I
ZO
V
O
V=
CC
DNGroV6.301±
I
CC
V
I
V=
CC
IDNGro
O
0=V6.304
C
I
stupnIlortnoC
V
I
V=
CC
DNGro
V5.25.3
Fp
V3.35.3
stupnIataD
V5.26
V3.36
C
O
stuptuOV
O
V=
CC
DNGro
V5.25.6
V3.35.6
Notes:
1. Typical values are measured at TA = 25°C.
DC Electrical Characteristics (Over the Operating Range, TA
= –40°C +85°C)
06-0168
5PS8527A 06/01/06
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PI74AVC+16374
2.5V 16-Bit Edge Triggered D-Type
Flip Flop with 3-State Outputs
Switching Characteristics
(Over recommended operating free-air temperature range, unless otherwise noted, see Figures 1 thru 4)
Operating Characteristics, TA= 25°C
sretemaraPsnoitidnoCtseT
V
CC
V8.1= V51.0± V
CC
V5.2= V2.0± V
CC
V3.3= V3.0± stinU
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noitapissiDrewoPdpC
ecnaticapaC
delbanEstuptuO C
L
,Fp0=
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471898
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sretemaraP morF )tupnI( oT )tuptuO(
V
CC
V2.1= V
CC
V5.1= V1.0± V
CC
V8.1= V51.0± V
CC
V5.2= V2.0± V
CC
V3.3= V3.0± stinU
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sid
EOQ 4.85.24.93.28.712.45.19.3
V
CC
V2.1= V
CC
V5.1= V1.0± V
CC
V8.1= V51.0± V
CC
V5.2= V2.0± V
CC
V3.3= V3.0± stinU
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Timing Requirements
(Over recommended operating free-air temperature range, unless otherwise noted, see Figures 1 thru 4)
06-0168
6PS8527A 06/01/06
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PI74AVC+16374
2.5V 16-Bit Edge Triggered D-Type
Flip Flop with 3-State Outputs
PARAMETER MEASUREMENT INFORMATION
VCC = 1.2V and 1.5V ± 0.1V
Load Circuit
Voltage Waveforms
Propagation Delay Times Voltage Waveforms
Enable and Disable Times
Voltage Waveforms
Pulse Duration
tseT1S
tdp
tZLP t/ LZP
tZHP t/ HZP
nepO
Vx2 CC
DNG
Notes:
A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
• All input impulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50Ω, tR ≤ 2.0ns, tF ≤ 2.0ns.
• The outputs are measured one at a time with one transition per measurement.
• tPLZ and tPHZ are the same as tdis
• tPZL and tPZH are the same as ten
• tPLH and tPHL are the same as tpd
Figure 1. Load Circuit and Voltage Waveforms
2Ω
2Ω
2xVCC
Open
GND
S1
From Output
Under Test
CL = 15pF
(See Note A)
t
PZL
Output
Control
(Low Level
Enabling) 0V
V
CC
/2
V
CC
/2
V
CC
/2
V
CC
/2
t
PLZ
t
PHZ
V
OL
V
CC
0V
t
PZH
+0.1V
–0.1V
Output
Waveform 1
S1 at 2 x V
CC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
V
OH
V
OH
V
OL
V
CC
Input
t
PLH
t
PHL
0V
Output
V
OH
V
OL
V
CC
/2 V
CC
/2
V
CC
/2
V
CC
VCC/2
Input
t
W
V
CC
/2 V
CC
V
CC
/2
0V
Data
Input
t
su
t
h
VCC/2 VCC
VCC/2
0V
VCC
0V
Timing
Input VCC/2
Voltage Waveforms
Setup and Hold Times
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PI74AVC+16374
2.5V 16-Bit Edge Triggered D-Type
Flip Flop with 3-State Outputs
PARAMETER MEASUREMENT INFORMATION
VCC = 1.8V ±0.15V
Load Circuit
Voltage Waveforms
Propagation Delay Times Voltage Waveforms
Enable and Disable Times
Voltage Waveforms
Pulse Duration
tseT1S
tdp
tZLP t/ LZP
tZHP t/ HZP
nepO
Vx2 CC
DNG
Notes:
A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
• All input impulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50Ω, tR ≤ 2.0ns, tF ≤ 2.0ns.
• The outputs are measured one at a time with one transition per measurement.
• tPLZ and tPHZ are the same as tdis
• tPZL and tPZH are the same as ten
• tPLH and tPHL are the same as tpd
Figure 2. Load Circuit and Voltage Waveforms
2Ω
2Ω
2xVCC
Open
GND
S1
From Output
Under Test
CL = 15pF
(See Note A)
t
PZL
Output
Control
(Low Level
Enabling) 0V
V
CC
/2
V
CC
/2
V
CC
/2
V
CC
/2
t
PLZ
t
PHZ
V
OL
V
CC
0V
t
PZH
+0.1V
–0.1V
Output
Waveform 1
S1 at 2 x V
CC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
V
OH
V
OH
V
OL
V
CC
Input
t
PLH
t
PHL
0V
Output
V
OH
V
OL
V
CC
/2 V
CC
/2
V
CC
/2
V
CC
VCC/2
Input
t
W
V
CC
/2 V
CC
V
CC
/2
0V
Data
Input
t
su
t
h
VCC/2 VCC
VCC/2
0V
VCC
0V
Timing
Input VCC/2
Voltage Waveforms
Setup and Hold Times
1 kΩ
1 kΩ
0.15V
0.15V
30
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PI74AVC+16374
2.5V 16-Bit Edge Triggered D-Type
Flip Flop with 3-State Outputs
PARAMETER MEASUREMENT INFORMATION
VCC = 2.5V ± 0.2V
Load Circuit
Voltage Waveforms
Propagation Delay Times Voltage Waveforms
Enable and Disable Times
Voltage Waveforms
Pulse Duration
tseT1S
tdp
tZLP t/ LZP
tZHP t/ HZP
nepO
Vx2 CC
DNG
Notes:
A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
• All input impulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50Ω, tR ≤ 2.0ns, tF ≤ 2.0ns.
• The outputs are measured one at a time with one transition per measurement.
• tPLZ and tPHZ are the same as tdis
• tPZL and tPZH are the same as ten
• tPLH and tPHL are the same as tpd
Figure 3. Load Circuit and Voltage Waveforms
2Ω
2Ω
2xVCC
Open
GND
S1
From Output
Under Test
CL = 15pF
(See Note A)
t
PZL
Output
Control
(Low Level
Enabling) 0V
V
CC
/2
V
CC
/2
V
CC
/2
V
CC
/2
t
PLZ
t
PHZ
V
OL
V
CC
0V
t
PZH
+0.15V
–0.15V
Output
Waveform 1
S1 at 2 x V
CC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
V
OH
V
OH
V
OL
V
CC
Input
t
PLH
t
PHL
0V
Output
V
OH
V
OL
V
CC
/2 V
CC
/2
V
CC
/2
V
CC
VCC/2
Input
t
W
V
CC
/2 V
CC
V
CC
/2
0V
Data
Input
t
su
t
h
VCC/2 VCC
VCC/2
0V
VCC
0V
Timing
Input VCC/2
Voltage Waveforms
Setup and Hold Times
500Ω
500Ω
30
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PI74AVC+16374
2.5V 16-Bit Edge Triggered D-Type
Flip Flop with 3-State Outputs
PARAMETER MEASUREMENT INFORMATION
VCC = 3.3V ± 0.3V
Load Circuit
Voltage Waveforms
Propagation Delay Times Voltage Waveforms
Enable and Disable Times
Voltage Waveforms
Pulse Duration
tseT1S
t
dp
t
ZLP
t/
LZP
t
ZHP
t/
HZP
nepO
Vx2
CC
DNG
Notes:
A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
• All input impulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50Ω, tR ≤ 2.0ns, tF ≤ 2.0ns.
• The outputs are measured one at a time with one transition per measurement.
• tPLZ and tPHZ are the same as tdis
• tPZL and tPZH are the same as ten
• tPLH and tPHL are the same as tpd
Figure 4. Load Circuit and Voltage Waveforms
2Ω
2Ω
2xVCC
Open
GND
S1
From Output
Under Test
CL = 15pF
(See Note A)
t
PZL
Output
Control
(Low Level
Enabling) 0V
V
CC
/2
V
CC
/2
V
CC
/2
V
CC
/2
t
PLZ
t
PHZ
V
OL
V
CC
0V
t
PZH
+0.1V
–0.1V
Output
Waveform 1
S1 at 2 x V
CC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
V
OH
V
OH
V
OL
V
CC
Input
t
PLH
t
PHL
0V
Output
V
OH
V
OL
V
CC
/2 V
CC
/2
V
CC
/2
V
CC
VCC/2
Input
t
W
V
CC
/2 V
CC
V
CC
/2
0V
Data
Input
t
su
t
h
VCC/2 VCC
VCC/2
0V
VCC
0V
Timing
Input VCC/2
Voltage Waveforms
Setup and Hold Times
500Ω
500Ω
0.3V
0.3V
30
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PI74AVC+16374
2.5V 16-Bit Edge Triggered D-Type
Flip Flop with 3-State Outputs
Packaging Mechanical: 48-pin TSSOP (A)
Packaging Mechanical: 48-pin TVSOP (K)
.236
.244
.488
.496
.002
.006
SEATING PLANE
.007
.010
.0197
BSC
.004
.008
.319
1
48
12.4
12.6
6.0
6.2
0.50 0.17
0.27
8.1
0.05
0.15
0.09
0.20
X.XX
X.XX
DENOTES DIMENSIONS
IN MILLIMETERS
.018
.030
0.45
0.75
.047
1.20 Max
BSC
.378
.386
.047
.031
.041
SEATING
PLANE
.0051
.009
.016
BSC
1
48
.169
.177
9.60
9.80
4.30
4.50
0.40 0.13
0.23
0.80
1.05
X.XX
X.XX
DENOTES DIMENSIONS
IN MILLIMETERS
.002
.006
0.05
0.15
.0035
.008
0.09
0.20
.018
.030
0.45
0.75
.252
BSC
6.4
Max.
1.20
06-0168
11 PS8527A 06/01/06
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PI74AVC+16374
2.5V 16-Bit Edge Triggered D-Type
Flip Flop with 3-State Outputs
Notes:
• Thermal characteristics can be found on the company web site at www.pericom.com/packaging/
• E = Pb-free & Green
• Adding an X suffix = Tape/Reel
Ordering Information
edoCgniredrOepyTegakcaPnoitpircseDegakcaP
A47361+CLA47IPA POSSTcitsalpediwlim042,nip-65
EA47361+CLA47IPA POSSTcitsalpediwlim042,nip-65,neerG&eerf-bP
K47361+CLA47IPK POVSTcitsalpediwlim371,nip-65
EK47361+CLA47IPK POSVTcitsalpediwlim371,nip-65,neerG&eerf-bP
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