RT8108FGSP - Richtek - Product.Network

RT8108

DS8108-03 September 2011 www.richtek.com

Ordering Information

5V to 12V Single Synchronous Buck PWM Controller

General Description

The RT8108 series are single-phase synchronous buck

PWM DC/DC controllers designed to drive two

N-MOSFETs. They provide a highly accurate,

programmable output voltage precisely regulated to low

voltage requirement with an internal 0.6V or 0.8V reference.

The RT8108 series use a single feedback loop voltage mode

PWM control for fa st tra nsient response. The high driving

capability makes it suitable for large output current

applications. An oscillator with fixed frequency 200kHz /

300kHz / 500kHz reduces the component size of the

external inductor and capacitor for saving PCB board area

and cost.

The RT8108 series integrate complete protection functions

such a s OCP, OVP and OTP UVP into SOP-8 a nd SOP-8

(Exposed Pad) surfa ce mount pa ckages.

Features

zSingle IC Supply Voltage ( 5V to 12V)

zDrive T wo N-MOSFET s

zFixed Operating Frequency at 200kHz, 300kHz and

500kHz

zVoltage Mode PWM Control with External

Feedback Loop Compensation

zOver Current Protection by Sensing MOSFET RDS(ON)

zHardware Pin for On/Off Control

zFull 0 to 90% Duty Cycle

zFa st Tran sient Response

zRoHS Compliant and Halogen Free

Applications

zMother Boards and Desktop Servers

zGra phic Cards

zSwitching Power Supply

zGeneric DC/DC Power Regulator

Pin Configurations

(TOP VIEW)

SOP-8

BOOT

UGATE

GND

LGATE/OCSET

PHASE

COMP/SD

VCC

SOP-8 (Exposed Pad)

GND

BOOT

UGATE

GND

LGATE/OCSET

PHASE

COMP/SD

VCC

Note :

Richtek products are :

` RoHS compliant and compatible with the current require-

ments of IPC/JEDEC J-STD-020.

` Suitable for use in SnPb or Pb-free soldering processes.

RT8108 Package Type

S : SOP-8

SP : SOP-8 (Exposed Pad-Option 1)

Lead Plating System

G : Green (Halogen Free and Pb Free)

Frequency / VREF Options

A : 300k / 0.6V

B : 300k / 0.8V

C : 200k / 0.6V

D : 200k / 0.8V

E : 500k / 0.6V

F : 500k / 0.8V

RT8108

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Pin No. Pin Name Pin Function

SOP- 8 SOP-8

(Exposed Pad)

1 1 BOOT

Bootstrap Supply Pin for the Upper Gate Driver. Connect the

bootstrap capacitor between B OOT and PHASE pins.

2 2 UGATE Upper Gate Driv er Output. Connec t this pin to gate of the high side

power N-MOSFET.

3 3,

9 (E xp os ed P ad) GND

Both Signal and Power Ground for the IC. Tie this pin directly to the

low-side MOSFET source and ground plane with the lowest

impedance. The exposed pad must be soldered to a large PCB

and connected to GND for maximum power dissipation.

4 4 LGATE/OCSET

Low-Side Gate Drive. It also acts as over current setup pin by

adjusting the resistor connecting to GND.

5 5 VCC Con nec t this Pi n to a W e ll-De cou ple d 5V or 12V B ias Sup pl y. It is

al so the positi ve s upply for the lowe r gate driver.

6 6 FB Feedback of the Output Vol tage.

7 7 COMP/SD Feedback Compensation and Enable/Shutdown Control Pin.

8 8 PHASE

Connect this pin to the source of the upper MOSFET and the drain

of the lower MOSFET.

Functional Pin Description

Typical Application Circuit

VOUT

VCC

COMP

/SD

UGATE

RT8108x

LGATE/

OCSET

BOOT

PHASE

LOUT

VIN

COUT

CBOOTCHFCBULK

3.3V to 12V

CDCPL

VCC

5V or 12V

ROFFSET

GND

ROCSET

RBOOT

RUGATE

RT8108

DS8108-03 September 2011 www.richtek.com

Function Block Diagram

Internal

Regulator

POR and

Soft-Start

Gate Control

Logic

VCC

Oscillator

0.2V

5V int.

Sample

and Hold

DIS DIS

PWM

INHIBIT

PWM

Comparator

IOCSET

DBOOT

Fixed 200kHz / 300kHz / 500kHz

BOOT

UGATE

GND

LGATE/OCSET

PHASE

COMP/SD

VCC

-1

VREF

(0.6V / 0.8V)

Delay

RT8108

4DS8108-03 September 2011www.richtek.com

Electrical Characteristics

Parameter Symbol Test Conditions Min Typ Max Unit

Supply Input

Supply Input Vo ltage V CC 4.75 -- 13.2 V

Supply Current ICC UGATE, LGATE Open -- 2.5 10 mA

Shutdown Current ISHDN UGATE, LGATE Open -- 2 -- mA

Power-On Reset

PO R Thre shold VCC_RTH V

CC Rising 3.8 4 4.3 V

Po wer On Re se t Hysteresis VCC_HYS -- 0.4 -- V

To be continued

Recommended Operating Conditions (Note 4)

zSupply Input Voltage, VCC------------------------------------------------------------------------------ 5V ± 5%, 12V ± 10%

zJunction T emperature Range--------------------------------------------------------------------------- −40°C to 125°C

zAmbient T emperature Range--------------------------------------------------------------------------- −40°C to 85°C

Absolute Maximum Ratings (Note 1)

zSupply Input Voltage, VCC------------------------------------------------------------------------------ 16V

zBOOT to PHASE ----------------------------------------------------------------------------------------- 15V

zBOOT to GND

DC------------------------------------------------------------------------------------------------------------ −0.3V to VCC + 15V

<200ns ------------------------------------------------------------------------------------------------------ −0.3V to 42V

zPHASE to GND

DC------------------------------------------------------------------------------------------------------------ −0.5V to 15V

<200ns ------------------------------------------------------------------------------------------------------ −5V to 30V

zUGA TE V oltage ------------------------------------------------------------------------------------------- VPHASE − 0.3V to VBOOT + 0.3V

<200ns ------------------------------------------------------------------------------------------------------ VPHASE − 5V to VBOOT + 5V

zLGATE V oltage-------------------------------------------------------------------------------------------- GND − 0.3V to VCC + 0.3V

<200ns ------------------------------------------------------------------------------------------------------ GND− 5V to VCC + 5V

zOther Input or Output Voltages------------------------------------------------------------------------ GND − 0.3V to 7V

zPower Dissipation, PD @ TA = 25°C

SOP-8------------------------------------------------------------------------------------------------------- 0.909W

SOP-8 (Exposed Pad) ---------------------------------------------------------------------------------- 1.333W

zPa ckage Thermal Re sistance (Note 2)

SOP-8, θJA ------------------------------------------------------------------------------------------------- 110°C/W

SOP-8 (Exposed Pad), θJA ----------------------------------------------------------------------------- 75°C/W

SOP-8 (Exposed Pad), θJC ---------------------------------------------------------------------------- 28°C/W

zJunction T emperature------------------------------------------------------------------------------------ 150°C

zLead T emperature (Soldering, 10 sec.)-------------------------------------------------------------- 260°C

zStorage T emperature Range --------------------------------------------------------------------------- −65°C to 150°C

zESD Susceptibility (Note 3)

HBM (Human Body Mode) ----------------------------------------------------------------------------- 2kV

MM (Ma chine Mode) ------------------------------------------------------------------------------------- 200V

(VCC = 12V, TA = 25°C, unless otherwise specified)

RT8108

DS8108-03 September 2011 www.richtek.com

Note 1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.

These are stress ratings only, and functional operation of the device at these or any other conditions beyond those

indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect device reliability.

Note 2. θJA is measured in the natural convection at TA = 25°C on a high effective thermal conductivity test board (4 Layers, 2S2P)

of JEDEC 51-7 thermal measurement standard. The case point of θJC is on the exposed pad of the package.

Note 3. Devices are ESD sensitive. Handling precaution is recommended.

Note 4. The device is not guaranteed to function outside its operating conditions.

Parameter Symbol Test Conditions Min Typ Max Unit

Oscillato r RT8108A/B 250 300 350

RT8108C/D 170 200 230

PWM

Frequency RT8108E/F

FSW

425 500 575

kHz

Ramp Amplitu de ΔVOSC -- 1.5 -- VP-P

Referen ce

RT8108A/C/E 0.594 0.6 0.606

Reference

Voltage RT8108B/D/F VREF 0.792 0.8 0.808

PWM Controller

Open Loop DC Gain AO -- 88 -- dB

Gain Bandwidth GBW -- 15 -- MHz

fOSC = 200kHz / 300kHz -- 92 - - %

Maximum D uty DMAX fOSC = 500kHz -- 85 -- %

PWM Controller Gate Driver

Upper Gate Source IUGATEsr V

BOOT − VPHASE = 12V 1 1.2 -- A

Upper Gate S ink RUGATEsk V

UGATE − VPHASE = 0.1V, I = 50m A -- 2.25 4 Ω

Lower Gate Source ILGATEsr V

CC = 12V 1 1.2 -- A

Lower Gate Sink RLGATEsk V

LGATE = 0.1V, I = 50mA -- 1 2 Ω

Protection

Under Voltage Protection (UVP) VFB_UVP Sweep VFB 68 75 82 %

Ov er Vol tage Pro tection VFB_OVP Sweep VFB ( After P OR) 115 125 130 %

Ov er Vol tage Pro tection Vpre_OVP Sweep VFB ( Before POR) -- 130 -- %

LGATE OC Setti ng Cu rrent I OCSET 22 25 28 μA

Over Temperature Protection TOTP -- 165 -- °C

RT8108A/B 1 3 5

RT8108C/D 1 4 7

Soft-Start

Inter val RT8108E/F

TSS M easur e FB from 10% to 90%

0.7 2.5 4

COMP/SD Shutdown T hr eshold V SD -- -- 0.2 V

RT8108

6DS8108-03 September 2011www.richtek.com

Typical Operating Characteristics

Efficiency vs. Load Current

100

0 5 10 15 20 25 30

Load Cu rr ent (A)

Efficiency (%)

VIN = VCC = 12V

Reference Voltage vs. Temperature

0.597

0.598

0.599

0.600

0.601

0.602

0.603

0.604

0.605

-50 -25 0 25 50 75 100 125

Tempera tur e (°C)

Reference Voltage (V)

VIN = VCC = 12V, No Load

Output Voltage vs. Load Current

1.190

1.194

1.198

1.202

1.206

1.210

0 5 10 15 20 25

Load Cu rr ent (A)

Output Volt age (V)

VIN = VCC = 12V

Frequency vs. Temperature

150

200

250

300

350

400

-50 -25 0 25 50 75 100 125

Tempera ture (°C)

Fr equency (kHz) 11

VIN = VCC = 12V, No Load

Power On from VIN

Time (4ms/Div)

VIN

(10V/Div)

VIN = VCC = 12V, No Load

VOUT

(1V/Div)

UGATE

(20V/Div)

VCC

(10V/Div)

Power Off from VIN

Time (100ms/Div)

VIN

(10V/Div)

VIN = VCC = 12V, No Load

VOUT

(1V/Div)

UGATE

(20V/Div)

VCC

(10V/Div)

RT8108

DS8108-03 September 2011 www.richtek.com

Power On from COMP/SD

Time (1ms/Div)

VOUT

(1V/Div)

UGATE

(20V/Div)

VIN = VCC = 12V, No Load

VCOMP

(1V/Div)

LGATE

(10V/Div)

Power Off from COMP/SD

Time (20ms/Div)

VIN = VCC = 12V, No Load

VOUT

(1V/Div)

UGATE

(20V/Div)

VCOMP

(1V/Div)

LGATE

(10V/Div)

Load Transient Response

Time (10μs/Div)

ILOAD

(10A/Div)

VOUT_ac

(50mV/Div)

VIN = VCC = 12V, I LOAD = 15A to 0A

L = 1uH, COUT = 1640uF

UGATE

(20V/Div)

Load Transient Response

Time (10μs/Div)

ILOAD

(10A/Div)

VOUT_ac

(50mV/Div)

VIN = VCC = 12V, I LOAD = 0A to 15A

L = 1uH, COUT = 1640uF

UGATE

(20V/Div)

Time (10ms/Div)

VCC = 12V, IOCSET = 15A

VOUT

(1V/Div)

UGATE

(20V/Div)

(10A/Div)

LGATE

(10V/Div)

Over Current Protection Over Voltage Protection

Time (20ms/Div)

VIN = VCC = 12V, No Load

VOUT

(1V/Div)

UGATE

(20V/Div)

VFB

(1V/Div)

LGATE

(10V/Div)

RT8108

8DS8108-03 September 2011www.richtek.com

Application Information

Function Description

The RT8108 series are single-phase synchronous buck

PWM controllers with embedded MOSFET drivers. The

MOSFET drivers are designed with high-current driving

ca pability to support up to 12V+12V bootstra pped voltage

for high efficiency power conversion. The RT8108 series

utilize voltage-mode control scheme, which is implemented

with a voltage error amplifier to provide a simple control

loop. A fixed frequency oscillator (200kHz/300kHz/500kHz,

typical) is integrated to eliminate external component

count. The soft-start function is also integrated to eliminate

the external ti ming ca pa citor. The R T8108 series provide

full protection functions to protect the load. The feedba ck

voltage at the FB pin is monitored for over-voltage protection

and under-voltage protection. An internal 0.6V/0.8V

reference allows the output voltage to be precisely regulated

for low output voltage a pplications. An elaborately designed

control circuit allows the converter to power up with pre-

bia sed output voltage to avoid negative voltage da mage to

the load. The RT8108 series use RDS(ON) current-sensing

technique, which is lossless and cost-effective. Inductor

current information is monitored by the voltage across

RDS(ON) of the low-side MOSFET for over current protection.

Power-up

The power on reset (POR) circuit monitors the supply

voltage of the controller (VCC). If VCC exceeds the POR

rising threshold voltage, the controller is initiated. The

controller sets the over current protection threshold prior

to the beginning of soft start. If VCC falls below the POR

falling threshold during normal operation, all MOSFETs

stop switching a nd the controller is reset. The POR rising

and falling threshold has a hysteresis to prevent noise-

caused reset.

Soft-start

The RT8108 series provide soft-start function internally.

The soft-start function is used to prevent the large inrush

current while the converter is powered-up. An internal

current source charges the internal soft-start capacitor

such that the internal soft-start voltage ramps up in a

monotone. The FB voltage will tra ck the internal soft-start

voltage during the soft-start interval. After the internal soft-

start voltage exceeds the reference voltage, the FB voltage

no longer tracks the soft-start voltage but follows the

reference voltage. Therefore, the duty cycle of thr UGA TE

signal at power up is limited and so does the input current.

Power-up with Pre-biased Voltage

Generally , if the output voltage is not initially zero at power-

up, or the output capacitor is pre-charged, the voltage at

FB pin is not equal to zero. The controller will turn on the

low-side MOSFET to discharge the output ca pacitor , forcing

the feedback voltage to follow the reference voltage. Large

current is then drawn from the output capacitor while

discharging. The discharge current depends on the

inductance and the output capacitance. Output voltage may

oscillate and be negative.

The negative output voltage could da mage the loa d. The

RT8108 series implement elaborate control circuits to

prevent the negative voltage when the converter is powered-

up with pre-bia sed voltage on the output ca pacitor . Figure

1 shows the waveform that converter is powered-up at no

load with pre-biased output voltage. The output voltage rises

from its pre-charged initial value during soft-start without

being pulled down.

Figure 1. Power Up with Pre-Biased Output Voltage

COMP/SD Enable/Disable

The COMP/SD pin can also be used to enable or to disable

the controller. Pull down COMP/SD pin below the shutdown

level VSHDN can disable the controller. When the controller

is disabled, UGA TE signal goes low first and then LGA TE

Time (1ms/Div)

UGATE

(20V/Div)

VOUT

(1V/Div)

LGATE

(10V/Div)

VCOMP

(2V/Div)

RT8108

DS8108-03 September 2011 www.richtek.com

signal also goes low after a short delay time. In practical

applications, connect a small signal MOFSET to

COMP/SD pin to pull down the COMP/SD voltage to

implement the enable/disable function.

Over Voltage Protection (OVP)

The output voltage is scaled by the divider resistors and

fed back to the FB pin. The voltage on the FB pin will be

compared to the internal reference voltage VREF for voltage-

related protection functions, including over voltage

protection a nd under voltage protection. If the FB voltage

is higher than the OVP threshold during operation, OVP

will be triggered. When OVP is triggered, UGATE will go

low and LGATE will go high to discharge the output

ca pacitor. Once OVP is triggered, controller will be latched

unless VCC POR is detected again.

Besides, the RT8108 series also provide OVP even if VCC

is below the POR threshold. This can protect the load

even if the high-side MOSFET is shorted before the power-

on-reset. If the FB voltage is higher than the OVP threshold

while VCC rises but not exceeds the POR threshold, OVP

will be triggered. The LGA TE signal will go high to discharge

the output ca pa citor .

Under Voltage Protection (UVP)

The voltage on the FB pin is also monitored for under voltage

protection. If the FB voltage is lower than the UVP threshold

during normal operation, UVP will be triggered. When UVP

is triggered, both UGA TE and LGA TE go low. Unlike OVP,

UVP is not a latched protection. The controller will begin

soft start again after a specific period of time (~40ms).

Furthermore, the controller will enter the hiccup mode and

always try to restart if UVP situation is not removed. The

UVP is reset by detecting VCC POR again. Unlike OVP,

the output voltage is monitored for UVP only after soft-

start completes.

Over Current Protection (OCP)

The RT8108 series sense output current through low-side

MOSFET RDS(ON) for over current protection. When the

LGA TE is turned on, the controller monitors voltage across

the low-side MOSFET . The lossless RDS(ON) current sensing

technique is cost-effective, because no external component

is required. The RT8108 series utilize cycle-by-cycle peak

current sensing, the voltage across the low-side MOSFET

is sa mpled and held after low-side MOSFET is turned on.

This sampled and held voltage represents the inductor peak

current and is compared to the user-programmed protection

level.

Once the inductor current exceeds the protection level,

OCP will be triggered. When the OCP is triggered, both

UGA TE and LGA TE go low to stop the energy transferring

to the load. Like UVP, the OCP is a continuing hiccupped

protection. The soft start will be initiated again after a

specific period of ti me (4*Tss, typical). If OCP situation is

not removed, controller will always try to restart.

OCP Setting

The RT8108 series employ an elaborate topology for OCP

setting, which eliminates controller pin count. Connect a

resistor from LGA TE to GND to set the OCP level as shown

in Figure 2.

Figure 2. OCP Setting

When the VCC exceeds the POR threshold at power up,

LGA TE is internally floating and enters tri-state. An internal

current source IOCSET then flows through ROCSET to

determine the OCP threshold voltage. The voltage across

the ROCSET is stored as the over current level for OCP.

After that, the current source is switched off, a nd LGATE

leaves the tri-state and prepared for the soft-start. Therefore,

no extra pin is required to set the OCP threshold. The

internal current source IOC is only active for a short period

of time after VCC POR. The ROCSET can be determined

using the following equation.

DS(ON) MAX

OCSET OCSET

R = 2 x I ×

where IOCSET is 25uA (typical), IMAX represents the allowed

maximum inductor pea k current.

-1

Sample

& Hold

PHASE

LGATE

IOCSET

ROCSET

Delay

POR

RT8108

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MOSFET Drivers

The RT8108 series integrate high-current gate drivers for

MOSFETs to obtain high-efficiency power conversion in

synchronous buck topology . A dead time is used to prevent

the crossover conduction for the high-side and low-side

MOSFETs. Because both the two gate signals are off

during the dead time, the inductor current freewheels

through the body diode of the low-side MOSFET. The

freewheeling current a nd the forward voltage of the body

diode contribute to the power loss. The RT8108 series

employ a constant dead time control scheme to ensure

safe operation without sacrificing efficiency . Furthermore,

an elaborate logic circuit is implemented to prevent the

cross-conduction between MOSFETs.

For high output current applications, two or more power

MOSFET s are paralleled to have reduced RDS(ON). The gate

driver needs to provide more current to switch on/off these

paralleled MOSFETs. Gate driver with lower source/sink

current capability results in longer rising/ falling time in

gate signals, a nd theref ore the higher switching loss.

The RT8108 series employ embedded high-current gate

drivers to obtain high-efficiency power conversion. The

embedded drivers contribute to the ma jority of the controller

power dissipation. If no gate resistor is used, the power

dissipation of the controller can be approximately calculated

using the following equation.

PSW = FSW x (Qg_High-Side x VBOOT + Qg_Low-Side

x VDrive_Low-Side )

where VBOOT represents the voltage a cross the bootstra p

capacitor.

It is important to ensure the package can dissipate the

switching loss and have enough room for safe operation.

Inductor Selection

Inductor plays an importance role in the buck converter

because the energy from the input power rail is stored in it

and then released to the load. From the viewpoint of

eff iciency, the dc resista nce (DCR) of inductor should be

as small as possible because inductor carries current all

the time. Using inductor that has lower DCR can obtain

higher efficiency . In addition, because inductor cost most

of the board space, its size is also important. Low profile

inductors can save board space especially when the height

has limitation.

Additionally , larger inductance results in lower ripple current,

and therefore the lower power loss. However, the inductor

current rising time increases with inductance value. This

means the inductor will have a longer charging time before

its current rea ches the required output current. Since the

response time is increased, the transient response

performance will be decreased. Therefore, the inductor

design is a trade-off between performance, size and cost.

In general, inductance is designed such that the ripple

current ranges between 20% to 30% of full load current.

The inductance can be calculated using the following

equation.

IN OUT OUT

MIN SW OUT_Full Load IN

VV V

L = FkI V

−×

××

where k is 0.2 to 0.3.

Input Capacitor Selection

V oltage rating and current rating are the key parameters in

selecting input ca pa citor. The voltage rating must be 1.25

times greater than the maximum input voltage to ensure

enough room for safe operation. Generally , input ca pacitor

ha s a voltage rating of 1.5 times greater than the maximum

input voltage is a conservatively safe design.

The input capacitor is used to supply the input RMS

current, which ca n be a pproximately calculated using the

following equation.

OUT OUT

RMS OUT IN IN

I = I 1

⎛⎞

××−

⎜⎟

⎝⎠

Refer to the manufacturer's databook for RMS current rating

to select proper capacitor. Use more than one capacitor

with low equivalent series resista nce (ESR) in parallel to

form a ca pacitor bank is popular . Besides, placing cera mic

capacitor close to the drain of the high-side MOSFET is

helpful in reducing the input voltage ripple at heavy load.

Output Capacitor Selection

The output ca pacitor and the inductor form a low-pa ss filter

in the buck topology. The electrolytic capa citor is usually

used because it can provide large capacitance value. In

stea dy state condition, the output ca pa citor supplies only

AC ripple current to the load. The ripple current flows into/

RT8108

DS8108-03 September 2011 www.richtek.com

out of the ca pa citor results in ripple voltage, which ca n be

determined using the following equation.

ΔVOUT_ESR = ΔIL x ESR

In addition, the output voltage ripple is also influenced by

the switching frequency and the ca pacitance value.

OUT_C L OUT SW

V = I

8C F

ΔΔ×

××

The total output voltage ripple is the sum of VOUT_ESR and

VOUT_C.

If the specification for steady-state output voltage ripple is

known, the ESR can be determined using the above

equations.

Another para meter that has influence on the output voltage

undershoot is the equivalent series inductance (ESL). The

ra pid change in load current results in di/dt during transient.

Therefore, ESL contributes to part of the voltage

undershoot. Use capacitor that has low ESL to obtain better

tra n sient perf ormance. Generally, use several capa citors

connected in parallel can have better transient performance

tha n use single capacitor for the same total ESR.

Unlike the electrolytic ca pacitor , the ceramic capacitor ha s

relatively low ESR and can reduce the voltage deviation

during load transient. However, the ceramic capacitor ca n

only provide low capacitance value. Therefore, use a mixed

combination of electrolytic ca pacitor and ceramic capacitor

can also have better transient performance.

Feedback Loop Compensation

Figure 3 shows the voltage mode control loop for a buck

converter. The control loop consists of the modulator, output

LC filter and the compensator. The modulator is composed

of the PWM comparator and power MOSFETs. The PWM

comparator compares the error amplifier EA output (COMP)

with the oscillator (OSC) sawtooth wave to generate a PWM

signal. The MOSFETs is then switched on and off

according to the duty cycle of the PWM signal. The voltage

presented at PHASE node is a square wave of 0V to Vin.

The PHASE voltage is filtered by the output filter LOUT and

COUT to produce output voltage VOUT, which is fedba ck to

the inverting input of the error a mplifier. The output voltage

is then regulated according to the reference voltage VREF.

In order to achieve fast transient response and accurate

output regulation, an adequate compensator design is

necessary. The goal of the compensation network is to

provide adequate pha se margin (greater than 45 degrees)

and the highest 0dB crossing frequency. It is also

recommended to manipulate loop frequency response that

its gain crosses over 0dB at a slope of −20dB/dec.

Figure 3. Control Loop for V oltage Mode Buck Converter

OSC

ΔVOSC

ZFB

ZIN

VIN

Driver

REF

PWM

Comparator

COMP

REF

ZFB ZIN VOUT

COMP

R2 R3

ESR

PHASE

COUT

VOUT

LOUT

1) Modulator and Output LC filter

Referring to Figure 3, the modulator gain is the input voltage

VIN divided by the pea k to pea k oscillator voltage VOSC as

shown a s following Equation :

Gain OSC

Modu lator = VΔ

where ΔVOSC = 1.5V (typ.)

The output LC filter introduces a double pole to the transfer

function, creating −40dB/decade gain slope above its corner

frequency , with a phase lag of 180 degrees. The frequency

at the double-pole of LC filter is expressed as f ollows.

LC OUT OUT

f2L C

=××

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2) Compensator

Fugire 4 illustrates the type II compensator , which consists

of the error a mplifier and the impeda nce ZC and ZF.

-FB

VREF

COMP EA

R2 R1 VOUT

Figure 4. T ype II Compensator

Type II compensator provides two poles a nd one zero to

the system. The first pole is located at low frequency to

increa se the dc gain for regulation accuracy . The location

of the other pole a nd the zero is expressed as follows.

Figure 5 shows the Bode plot for the gain of system. The

compensation gain determined by ZC and ZF should be

designed to have high crossover frequency (bandwidth) with

sufficient phase margin. In order to make the gain crosses

over 0dB at a slope of −20dB/dec, pla ce the zero before

the LC double-pole frequency . Empirically , fz1 is placed at

75% of the LC double-pole frequency. Furthermore, the

bandwidth of the system is the factor that affects the

converter's transient performance. High ba ndwidth results

in fast transient response, but it often jeopardizes the

system stability . The bandwidth should be designed to be

less than 1/5 of the switching frequency. Properly adjust

R1 and R2 to change the mid-frequency gain to obtain the

required bandwidth. The pole at fp1 is usually placed at half

of the switching frequency to have sufficient pha se margin

and attenuation at high frequency.

Z1 1

f2R2C2

=××

P1 1

fC1 C2

2R2

C1 C2

=×

××+

Figure 5. System Gain Bode Plot

Frequency

10Hz 100Hz 1.0KHz 10KHz 100KHz 1.0MHz

vdb(vo) vdb(comp2) vdb(lo)

-40

-60

10 100 1k 10k 100k 1M

-20

-40

-60

Loop Gain

Compensation

Gain

Modulator

Gain

Frequency (Hz)

G a in (d B)

Layout Considerations

PCB layout is critical to high-current high-frequency

switching converter designs. A good layout can help the

controller to function properly and achieve expected

performa nce. On the other ha nd, PCB without a carefully

layout can radiate excessive noise, having more power

loss and even malfunction in the controller. In order to avoid

the above condition, the following general guidelines must

be followed in PCB layout.

`Power stage components should be pla ced first. Place

the input bulk capacitors close to the high-side power

MOSFET s, and then locate the output inductor and finally

the output capa citors.

`Place the cera mic capacitor physically close to the drain

of the high-side MOSFET. This can reduce the input

voltage drop when high-side MOSFET is turned on. If

more than one MOSFET is paralleled, ea ch should have

its own individual cera mic ca pacitor.

`Keep the high-current loops a s short as possible. During

high speed switching, the current transition between

MOSFETs usually causes di/dt voltage spike due to the

para sitic components on PCB trace. Therefore, making

the trace length between power MOSFET s and inductors

wide a nd short can reduce the voltage spike a nd EMI.

`Make MOSFET gate driver path as short as possible.

Since the gate driver uses narrow-width high-current

pulses to switch on/off the power MOSFET, the driver

path must be short to reduce the trace inductance. This

is especially important for low-side MOSFET, because

this ca n reduce the possibility of shoot-through.

In addition, the ESR of the output capacitor introduces a

zero to the transfer function, creating a +20dB/dec gain

slope with a pha se shift of 90 degree. The frequency of the

ESR zero is expressed as follows.

ESR OUT

f2ESRC

=××

RT8108

DS8108-03 September 2011 www.richtek.com

`Providing enough copper area around the power

MOSFETs to help heat dissi pation. Using thick copper

also reduces the trace resistance and inductance to have

better performance.

`The output ca pacitors should be placed physically close

to the load. This can minimize the trace parasitic

components and improve transient response.

`All small signal components should be located close to

the controller. The small signal components include the

feedback voltage divider resistors, compensator, function

setting components and high-frequency bypass

ca pacitors. The feedback voltage divider resistor and the

compensator must be placed close to FB pin and COMP

pin, because these pins are inherently noise-sensitive.

`Voltage feedback path must be kept away from the

switching nodes. The noisy switching node is, for

example, the interconnection between high-side

MOSFET, low-side MOSFET and inductor. The feedback

path must be kept away from this kind of noisy node to

avoid noise pick-up.

`A multi-layer PCB design is recommended. Make use

of one single layer as the ground and have separate

layers for power rail or signal that is suitable for PCB

design.

Figure 6. PCB Layout

RT8108

14 DS8108-03 September 2011www.richtek.com

Outline Dimension

8-Lead SOP Plastic Package

Dim ension s In M illimeters Dimen sions In Inches

Symbol Min Max Min Max

A 4.801 5.004 0.189 0.197

B 3.810 3.988 0.150 0.157

C 1.346 1.753 0.053 0.069

D 0.330 0.508 0.013 0.020

F 1.194 1.346 0.047 0.053

H 0.170 0.254 0.007 0.010

I 0.050 0.254 0.002 0.010

J 5.791 6.200 0.228 0.244

M 0.400 1.270 0.016 0.050

RT8108

DS8108-03 September 2011 www.richtek.com

Richtek Technology Corporation

Headquarter

5F, No. 20, Taiyuen Street, Chupei City

Hsinchu, Taiwan, R.O.C.

Tel: (8863)5526789 Fax: (8863)5526611

Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit design,

specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be guaranteed

by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek.

Richtek Technology Corporation

Taipei Office (Marketing)

5F, No. 95, Minchiuan Road, Hsintien City

Taipei County, Taiwan, R.O.C.

Tel: (8862)86672399 Fax: (8862)86672377

Email: marketing@richtek.com

EXPOSED THERMAL PAD

(Bottom of Package)

8-Lead SOP (Exposed Pad) Plastic Package

Dimensions In Millimeters Dimensions In Inches

Symbol Min Max Min Max

A 4.801 5.004 0.189 0.197

B 3.810 4.000 0.150 0.157

C 1.346 1.753 0.053 0.069

D 0.330 0.510 0.013 0.020

F 1.194 1.346 0.047 0.053

H 0.170 0.254 0.007 0.010

I 0.000 0.152 0.000 0.006

J 5.791 6.200 0.228 0.244

M 0.406 1.270 0.016 0.050

X 2.000 2.300 0.079 0.091

Option 1 Y 2.000 2.300 0.079 0.091

X 2.100 2.500 0.083 0.098

Option 2 Y 3.000 3.500 0.118 0.138