LTC2274
1
2274fb
TYPICAL APPLICATION
FEATURES
APPLICATIONS
DESCRIPTION
16-Bit, 105Msps Serial
Output ADC
The LTC
®
2274 is a 105Msps, 16-bit A/D converter with
a high speed serial interface. It is designed for digitizing
high frequency, wide dynamic range signals with an input
bandwidth of 700MHz. The input range of the ADC can
be optimized using the PGA front end. The output data is
serialized according to the JEDEC Serial Interface for Data
Converters specifi cation (JESD204).
The LTC2274 is perfect for demanding applications where
it is desirable to isolate the sensitive analog circuits from
the noisy digital logic. The AC performance includes a
77.7dB Noise Floor and 100dB spurious free dynamic range
(SFDR). Ultra low internal jitter of 80fs RMS allows under-
sampling of high input frequencies with excellent noise
performance. Maximum DC specs include ±4.5LSB INL
and ±1LSB DNL (no missing codes) over temperature.
The encode clock inputs, ENC+ and ENC–, may be driven
differentially or single-ended with a sine wave, PECL,
LVDS, TTL or CMOS inputs. A clock duty cycle stabilizer
allows high performance at full speed with a wide range
of clock duty cycles.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
n High Speed Serial Interface (JESD204)
n Sample Rate: 105Msps
n 77.7dBFS Noise Floor
n 100dB SFDR
n SFDR >82dB at 250MHz (1.5VP-P Input Range)
n PGA Front End (2.25VP-P or 1.5VP-P Input Range)
n 700MHz Full Power Bandwidth S/H
n Optional Internal Dither
n Single 3.3V Supply
n Power Dissipation: 1300mW
n Clock Duty Cycle Stabilizer
n Pin Compatible Family
105Msps: LTC2274
80Msps: LTC2273
65Msps: LTC2272
n 40-Pin 6mm × 6mm QFN Package
n Telecommunications
n Receivers
n Cellular Base Stations
n Spectrum Analysis
n Imaging Systems
n ATE
–
+
S/H
AMP CORRECTION
LOGIC
8B/10B
ENCODER
16-BIT
PIPELINED
ADC CORE
INTERNAL ADC
REFERENCE
GENERATOR
1.25V
COMMON MODE
BIAS VOLTAGE
CLOCK/DUTY
CYCLE
CONTROL
SCRAMBLER/
PATTERN
GENERATOR
PLL
20X
ENC+ENC–
VCM
ANALOG
INPUT
2274 TA01
SYNC+
SYNC–
OVDD
3.3V
1.2V TO 3.3V
3.3V FAM
ASIC OR FPGA
SENSE
CLOCK
2.2μF
PAT1 PAT0 SRR1 SRR0SCRAMSHDNMSBINVDITHPGA
0.1μF
0.1μF
0.1μF
VDD
GND
AIN +
AIN –
CMLOUT+
CMLOUT–
16 20
–
+
SERIALIZER SERIAL
RECEIVER
50Ω
50Ω
128k Point FFT, fIN = 4.93MHz,
–1dBFS, PGA = 0
FREQUENCY (MHz)
0
AMPLITUDE (dBFS)
10 20 30 40 50
2274 TA01b
–130
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
LTC2274
2
2274fb
PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS
Supply Voltage (VDD) ................................... –0.3V to 4V
Analog Input Voltage (Note 3) .......–0.3V to (VDD + 0.3V)
Digital Input Voltage ......................–0.3V to (VDD + 0.3V)
Digital Output Voltage ................ –0.3V to (OVDD + 0.3V)
Power Dissipation .............................................2000mW
Operating Temperature Range
LTC2274C ................................................ 0°C to 70°C
LTC2274I.............................................. –40°C to 85°C
Storage Temperature Range ................... –65°C to 150°C
Digital Output Supply Voltage (OVDD) .......... –0.3V to 4V
OVDD = VDD (Notes 1, 2)
3940 38 37 36 35 34 33 32 31
11 20
12 13 14 15
TOP VIEW
41
UJ PACKAGE
40-LEAD (6mm s 6mm) PLASTIC QFN
16 17 18 19
22
23
24
25
26
27
28
29
9
8
7
6
5
4
3
2
VDD
VDD
GND
AIN+
AIN–
GND
GND
GND
ENC+
ENC–
GND
SYNC–
SYNC+
GND
GND
OVDD
CMLOUT
+
CMLOUT
–
OVDD
GND
GND
VCM
SENSE
GND
MSBINV
PGA
SCRAM
PAT1
PAT0
FAM
GND
VDD
VDD
GND
DITH
ISMODE
SRR0
SRR1
SHDN
SHDN
21
30
10
1
TJMAX = 150°C, θJA = 22°C/W
EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC2274CUJ#PBF LTC2274CUJ#TRPBF LTC2274UJ 40-Lead (6mm × 6mm) Plastic QFN 0°C to 70°C
LTC2274IUJ#PBF LTC2274IUJ#TRPBF LTC2274UJ 40-Lead (6mm × 6mm) Plastic QFN –40°C to 85°C
LEAD BASED FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC2274CUJ LTC2274CUJ#TR LTC2274UJ 40-Lead (6mm × 6mm) Plastic QFN 0°C to 70°C
LTC2274IUJ LTC2274IUJ#TR LTC2274UJ 40-Lead (6mm × 6mm) Plastic QFN –40°C to 85°C
Consult LTC Marketing for parts specifi ed with wider operating temperature ranges. *The temperature grade is identifi ed by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifi cations, go to: http://www.linear.com/tapeandreel/
CONVERTER CHARACTERISTICS
SYMBOL CONDITIONS MIN TYP MAX UNITS
Integral Linearity Error Differential Analog Input (Note 5) TA = 25°C ±1.2 ±4 LSB
Integral Linearity Error Differential Analog Input (Note 5) l±1.5 ±4.5 LSB
Differential Linearity Error Differential Analog Input l±0.3 ±1 LSB
Offset Error (Note 6) l±1 ±8.5 mV
Offset Drift ±10 μV/°C
Gain Error External Reference l±0.2 ±1.5 %FS
Full-Scale Drift Internal Reference
External Reference ±30
±15 ppm/°C
ppm/°C
Transition Noise 3LSB
RMS
The l denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C. (Note 4)
LTC2274
3
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ANALOG INPUT
The l denotes denotes the specifi cations which apply over the full operating temperature range,
otherwise specifi cations are at TA = 25°C. (Note 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN Analog Input Range (AIN+ – AIN–)3.135V ≤ VDD ≤ 3.465V l1.5 or 2.25 VP-P
VIN, CM Analog Input Common Mode Differential Input (Note 7) l1 1.25 1.5 V
IIN Analog Input Leakage Current 0V ≤ AIN+, AIN– ≤ VDD (Note 10) l–1 1 μA
ISENSE SENSE Input Leakage Current 0V ≤ SENSE ≤ VDD (Note 11) –3 3 μA
CIN Analog Input Capacitance Sample Mode ENC+ < ENC–
Hold Mode ENC+ > ENC–6.7
1.8 pF
pF
tAP Sample-and-Hold
Acquisition Delay Time
1ns
tJITTER Sample-and-Hold
Acquisition Delay Time Jitter
80 fsRMS
CMRR Analog Input
Common Mode Rejection Ratio
1V < (AIN+ = AIN–) <1.5V 80 dB
BW-3dB Full Power Bandwidth RS ≤ 25Ω700 MHz
DYNAMIC ACCURACY
The l denotes the specifi cations which apply over the full operating temperature range,
otherwise specifi cations are at TA = 25°C. AIN = –1dBFS. (Note 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
SNR Signal-to-Noise Ratio 5MHz Input (2.25V Range, PGA = 0)
5MHz Input (1.5V Range, PGA = 1) 77.6
75.4 dBFS
dBFS
15MHz Input (2.25V Range, PGA = 0), TA = 25°C
15MHz Input (2.25V Range, PGA = 0)
15MHz Input (1.5V Range, PGA = 1)
l
76.5
76.2 77.5
77.2
75.3
dBFS
dBFS
dBFS
70MHz Input (2.25V Range, PGA = 0)
70MHz Input (1.5V Range, PGA = 1) 77.2
75.1 dBFS
dBFS
140MHz Input (2.25V Range, PGA = 0)
140MHz Input (1.5V Range, PGA = 1), TA = 25°C
140MHz Input (1.5V Range, PGA = 1) l
73.8
73.4
76.3
74.5
74.2
dBFS
dBFS
dBFS
170MHz Input (2.25V Range, PGA = 0)
170MHz Input (1.5V Range, PGA = 1) 75.9
74.3 dBFS
dBFS
SFDR Spurious Free Dynamic Range
2nd or 3rd Harmonic 5MHz Input (2.25V Range, PGA = 0)
5MHz Input (1.5V Range, PGA = 1) 100
100 dBc
dBc
15MHz Input (2.25V Range, PGA = 0), TA = 25°C
15MHz Input (2.25V Range, PGA = 0)
15MHz Input (1.5V Range, PGA = 1)
l
85
84 95
95
100
dBc
dBc
dBc
70MHz Input (2.25V Range, PGA = 0)
70MHz Input (1.5V Range, PGA = 1) 86
94 dBc
dBc
140MHz Input (2.25V Range, PGA = 0)
140MHz Input (1.5V Range, PGA = 1), TA = 25°C
140MHz Input (1.5V Range, PGA = 1) l
81
80
85
90
89
dBc
dBc
dBc
170MHz Input (2.25V Range, PGA = 0)
170MHz Input (1.5V Range, PGA = 1) 80
85 dBc
dBc
LTC2274
4
2274fb
The l denotes the specifi cations which apply over the full operating temperature range,
otherwise specifi cations are at TA = 25°C. AIN = –1dBFS unless otherwise noted. (Note 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
SFDR Spurious Free Dynamic Range 4th
Harmonic or Higher 5MHz Input (2.25V Range, PGA = 0)
5MHz Input (1.5V Range, PGA = 1) 100
100 dBc
dBc
15MHz Input (2.25V Range, PGA = 0)
15MHz Input (1.5V Range, PGA = 1)
l90 100
100 dBc
dBc
70MHz Input (2.25V Range, PGA = 0)
70MHz Input (1.5V Range, PGA = 1) 100
100 dBc
dBc
140MHz Input (2.25V Range, PGA = 0)
140MHz Input (1.5V Range, PGA = 1) l85 95
100 dBc
dBc
170MHz Input (2.25V Range, PGA = 0)
170MHz Input (1.5V Range, PGA = 1) 90
95 dBc
dBc
S/(N+D) Signal-to-Noise
Plus Distortion Ratio 5MHz Input (2.25V Range, PGA = 0)
5MHz Input (1.5V Range, PGA = 1) 77.5
75.3 dBFS
dBFS
15MHz Input (2.25V Range, PGA = 0), TA = 25°C
15MHz Input (2.25V Range, PGA = 0
15MHz Input (1.5V Range, PGA = 1)
l
76.3
75.9 77.4
77
75.2
dBFS
dBFS
dBFS
70MHz Input (2.25V Range, PGA = 0)
70MHz Input (1.5V Range, PGA = 1) 76.7
74.2 dBFS
dBFS
140MHz Input (2.25V Range, PGA = 0), TA = 25°C
140MHz Input (1.5V Range, PGA = 1)
140MHz Input (1.5V Range, PGA = 1) l
73.6
73.2
75.3
74.3
74
dBFS
dBFS
dBFS
170MHz Input (2.25V Range, PGA = 0)
170MHz Input (1.5V Range, PGA = 1) 73.4
73.4 dBFS
dBFS
SFDR Spurious Free Dynamic Range
at –25dBFS Dither “OFF” 5MHz Input (2.25V Range, PGA = 0)
5MHz Input (1.5V Range, PGA = 1) 105
105 dBFS
dBFS
15MHz Input (2.25V Range, PGA = 0)
15MHz Input (1.5V Range, PGA = 1) 105
105 dBFS
dBFS
70MHz Input (2.25V Range, PGA = 0)
70MHz Input (1.5V Range, PGA = 1) 105
105 dBFS
dBFS
140MHz Input (2.25V Range, PGA = 0)
140MHz Input (1.5V Range, PGA = 1) 100
100 dBFS
dBFS
170MHz Input (2.25V Range, PGA = 0)
170MHz Input (1.5V Range, PGA = 1) 100
100 dBFS
dBFS
SFDR Spurious Free Dynamic Range
at –25dBFS Dither “ON” 5MHz Input (2.25V Range, PGA = 0)
5MHz Input (1.5V Range, PGA = 1) 115
115 dBFS
dBFS
15MHz Input (2.25V Range, PGA = 0)
15MHz Input (1.5V Range, PGA = 1)
l97 115
115 dBFS
dBFS
70MHz Input (2.25V Range, PGA = 0)
70MHz Input (1.5V Range, PGA = 1) 115
115 dBFS
dBFS
140MHz Input (2.25V Range, PGA = 0)
140MHz Input (1.5V Range, PGA = 1) 110
110 dBFS
dBFS
170MHz Input (2.25V Range, PGA = 0)
170MHz Input (1.5V Range, PGA = 1) 105
105 dBFS
dBFS
DYNAMIC ACCURACY
LTC2274
5
2274fb
The l denotes the specifi cations which apply over
the full operating temperature range, otherwise specifi cations are at TA = 25°C. (Note 4)
COMMON MODE BIAS CHARACTERISTICS
PARAMETER CONDITIONS MIN TYP MAX UNITS
VCM Output Voltage IOUT = 0 1.15 1.25 1.35 V
VCM Output Tempco IOUT = 0 l40 ppm/°C
VCM Line Regulation 3.135V ≤ VDD ≤ 3.465V l1mV/V
VCM Output Resistance –1mA ≤ | IOUT | ≤ 1mA l2Ω
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Encode Inputs (ENC+, ENC–)
VID Differential Input Voltage (Note 7) l0.2 V
VICM Common Mode Input Voltage Internally Set
Externally Set (Note 7) 1.4 1.6 3.0 V
RIN Input Resistance (See Figure 2) 6 kΩ
CIN Input Capacitance 3pF
SYNC Inputs (SYNC+, SYNC–)
VSID SYNC Differential Input
Voltage (Note 7) l0.2 V
VSICM SYNC Common Mode Input
Voltage Internally Set
Externally Set (Note 7) 1.1 1.6 2.2 V
RSIN SYNC Input Resistance 16.5 kΩ
CSIN SYNC Input Capacitance 3pF
Logic Inputs (DITH, PGA, MSBINV, SCRAM, FAM, SHDN, SRR1, SRR0, ISMODE, PAT1, PAT0)
VIH High Level Input Voltage VDD = 3.3V l2V
VIL Low Level Input Voltage VDD = 3.3V l0.8 V
IIN Input Current VIN = 0V to VDD l±20 μA
CIN Input Capacitance 1.5 pF
High-Speed Serial Outputs (CMLOUT+, CMLOUT–)
VOH Output High Level Directly-Coupled 50Ω to OVDD
Directly-Coupled 100Ω Differential
AC-Coupled
OVDD
OVDD – 0.2
OVDD – 0.2
V
V
V
VOL Output Low Level Directly-Coupled 50Ω to OVDD
Directly-Coupled 100Ω Differential
AC-Coupled
OVDD – 0.4
OVDD – 0.6
OVDD – 0.6
V
V
V
VOCM Output Common Mode
Voltage Directly-Coupled 50Ω to OVDD
Directly-Coupled 100Ω Differential
AC-Coupled
OVDD – 0.2
OVDD – 0.4
OVDD – 0.4
V
V
V
ROUT Output Resistance Single-Ended Differential l35 50
100 65 Ω
Ω
The l denotes the specifi cations which apply over the
full operating temperature range, otherwise specifi cations are at TA = 25°C. (Note 4)
DIGITAL INPUTS AND DIGITAL OUTPUTS
LTC2274
6
2274fb
TIMING CHARACTERISTICS
The l denotes the specifi cations which apply over the full operating temperature
range, otherwise specifi cations are at TA = 25°C. (Note 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fSSampling Frequency (Note 9) l20 105 MHz
tCONV Conversion Period 1/fSs
tLENC Clock Low Time (Note 7) l3.1 4.762 25 ns
tHENC Clock High Time (Note 7) l3.1 4.762 25 ns
tAP Sample-and-Hold Aperture Delay 0.7 ns
tBIT
, UI Period of a Serial Bit tCONV/20 s
tJIT Total Jitter of CMLOUT± (P-P) BER = 1E–12 (Note 7) l0.35 UI
tR, tFDifferential Rise and Fall Time of CMLOUT± (20% to 80%) RTERM = 50Ω, CL = 2pF
(Note 7)
l50 110 ps
tSU SYNC to ENC Clock Setup Time (Note 7) l2ns
tHD ENC Clock to SYNC Hold Time (Note 7) l2.5 ns
tCS ENC Clock to SYNC Delay (Note 7) ltHD tCONV – tSU ns
LATPPipeline Latency 9 Cycles
LATSC Latency from SYNC Active to COMMA Out 3 Cycles
LATSD Latency from SYNC Release to DATA Out 2 Cycles
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND (unless otherwise
noted).
Note 3: When these pin voltages are taken below GND or above VDD, they
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA below GND or above VDD without latchup.
Note 4: VDD = 3.3V, fSAMPLE = 105MHz differential ENC+/ENC– = 2VP-P sine
wave with 1.6V common mode, input range = 2.25VP-P with differential
drive (PGA = 0), unless otherwise specifi ed.
Note 5: Integral nonlinearity is defi ned as the deviation of a code from
a “best fi t straight line” to the transfer curve. The deviation is measured
from the center of the quantization band.
Note 6: Offset error is the offset voltage measured from –1/2LSB when the
output code fl ickers between 0000 0000 0000 0000 and 1111 1111 1111
1111 in 2’s complement output mode.
Note 7: Guaranteed by design, not subject to test.
Note 8: VDD = 3.3V, fSAMPLE = 105MHz input range = 2.25VP-P with
differential drive.
Note 9: Recommended operating conditions.
Note 10: The dynamic current of the switched capacitors analog inputs
can be large compared to the leakage current and will vary with the sample
rate.
Note 11: Leakage current will have higher transient current at power up.
Keep drive resistance at or below 1k.
The l denotes the specifi cations which apply over the full operating temperature
range, otherwise specifi cations are at TA = 25°C. AIN = –1dBFS. (Note 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VDD Analog Supply Voltage l3.135 3.3 3.465 V
PSHDN Shutdown Power SHDN Pins = VDD 5mW
OVDD Output Supply Range CMLOUT Directly-Coupled 50Ω to OVDD (Note 7)
CMLOUT Directly-Coupled 100Ω Differential (Note 7)
CMLOUT AC-Coupled (Note 7)
l
l
l
1.2
1.4
1.4
VDD
VDD
VDD
V
V
V
IVDD Analog Supply Current DC Input l394 450 mA
IOVDD Output Supply Current CMLOUT Directly-Coupled, 50Ω to 0VDD
CMLOUT Directly-Coupled 100Ω Differential
CMLOUT AC-Coupled
8
16
16
mA
mA
mA
PDIS Power Dissipation DC Input l1300 1485 mW
POWER REQUIREMENTS
LTC2274
7
2274fb
N – 6
N – 10 N – 9 N – 8 N – 1 N
N – 5 N – 4 N + 3 N + 4
N – 9 N – 8 N – 7 N N + 1
tH
tCONV
LATP
tL
tAP
tBIT
NN + 1 N + 2 N + 8
N + 9
2274 TD01
N + 10
ANALOG INPUT
ENC+
INTERNAL
PARALLEL DATA
INTERNAL
8B/10B DATA
CMLOUT+/CMLOUT–
TIMING DIAGRAMS
N – 1 N
N + 1 N + 2
N + 3
N + 4 N + 5
N – 10 N – 9 N – 8 N – 7 K28.5 (x2) K28.5 (x2)
tCONV
tCS(MAX) LATSC
tHD
tCS(MIN)
tSU
ANALOG INPUT
ENC+
SYNC+
CMLOUT+/CMLOUT–
2274 TD02
N – 1 N
N + 1 N + 2
N + 3
N + 4
K28.5 (x2) K28.5 (x2) K28.5 (x2) N – 7 N – 6
tCONV
tCS(MAX) LATSD
tHD
tCS(MIN)
tSU
ANALOG INPUT
ENC+
CMLOUT+/CMLOUT–
2274 TD03
SYNC+
Analog Input to Serial Data Out Timing
SYNC+ Falling Edge to Comma (K28.5) Timing
SYNC+ Rising Edge to Data Timing
LTC2274
8
2274fb
TYPICAL PERFORMANCE CHARACTERISTICS
Differential Non-Linearity (DNL)
vs Output Code AC Grounded Input Histogram
128k Point FFT, fIN = 4.93MHz,
–1dBFS, PGA = 0
64k Point FFT, fIN = 14.8MHz,
–1dBFS, PGA = 0
64k Point FFT, fIN = 14.8MHz,
–10dBFS, PGA = 0
SFDR vs Input Level, fIN =
15MHz, PGA = 0, Dither “On”
64k Point 2-Tone FFT,
fIN = 14.2MHz and 15.8MHz,
–7dBFS, PGA = 0
Integral Non-Linearity (INL)
vs Output Code
SFDR vs Input Level, fIN =
15MHz, PGA = 0, Dither “Off”
OUTPUT CODE
0
INL ERROR (LSB)
16384 32768 49152
2274
G01
65536
–2.0
–1.5
–1.0
–0.5
0.0
0.5
1.0
1.5
2.0
OUTPUT CODE
0
DNL ERROR (LSB)
16384 32768 49152
2274
G02
65536
–1.0
–0.8
–0.6
–0.4
–0.2
0.0
0.2
0.4
0.6
0.8
1.0
OUTPUT CODE
32777
COUNT
32787 32797
2274
G03
32807
0
1000
2000
3000
4000
5000
6000
7000
8000
9000
10000
FREQUENCY (MHz)
0
AMPLITUDE (dBFS)
10 20 30 40 50
2274
G04
–130
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
FREQUENCY (MHz)
0
AMPLITUDE (dBFS)
10 20 30 40 50
2274
G05
–130
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
FREQUENCY (MHz)
0
AMPLITUDE (dBFS)
10 20 30 40 50
2274
G06
–130
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
FREQUENCY (MHz)
0
AMPLITUDE (dBFS)
10 20 30 40 50
2274
G09
–130
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
INPUT LEVEL (dBFS)
–80
SFDR (dBc AND dBFS)
–70 –60 –50 –40 –30 –20 –10 0
2274
G07
30
40
50
60
70
80
90
100
110
120
130
140
INPUT LEVEL (dBFS)
–80
SFDR (dBc AND dBFS)
–70 –60 –50 –40 –30 –20 –10 0
2274
G08
30
40
50
60
70
80
90
100
110
120
130
140
VDD = 3.3V, OVDD = 1.5V, TA = 25°C, FS = 105Msps,
unless otherwise noted.
LTC2274
9
2274fb
TYPICAL PERFORMANCE CHARACTERISTICS
64k Point 2-Tone FFT,
fIN = 14.2MHz and 15.8MHz,
–15dBFS, PGA = 0
64k FFT, fIN = 70.1MHz, –1dBFS,
PGA = 0
64k FFT, fIN = 70.1MHz, –1dBFS,
PGA = 1
128k Point FFT, fIN = 70.1MHz,
–20dBFS, PGA = 0, Dither “Off”
128k Point FFT, fIN = 70.1MHz,
–20dBFS, PGA = 0, Dither “On”
64k Point FFT, fIN = 140.2MHz,
–1dBFS, PGA = 1
SFDR vs Input Level,
fIN = 140MHz, PGA = 1,
Dither “Off”
SFDR vs Input Level,
fIN = 140MHz, PGA = 1,
Dither “On”
64k Point FFT, fIN = 170.2MHz,
–1dBFS, PGA = 1
FREQUENCY (MHz)
0
AMPLITUDE (dBFS)
10 20 30 40 50
2274
G10
–130
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
FREQUENCY (MHz)
0
AMPLITUDE (dBFS)
10 20 30 40 50
2274
G11
–130
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
FREQUENCY (MHz)
0
AMPLITUDE (dBFS)
10 20 30 40 50
2274
G12
–130
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
FREQUENCY (MHz)
0
AMPLITUDE (dBFS)
10 20 30 40 50
2274
G13
–130
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
FREQUENCY (MHz)
0
AMPLITUDE (dBFS)
10 20 30 40 50
2274
G14
–130
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
FREQUENCY (MHz)
0
AMPLITUDE (dBFS)
10 20 30 40 50
2274
G15
–130
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
INPUT LEVEL (dBFS)
–80
SFDR (dBc AND dBFS)
–70 –60 –50 –40 –30 –20 –10 0
2274
G16
30
40
50
60
70
80
90
100
110
120
130
140
INPUT LEVEL (dBFS)
–80
SFDR (dBc AND dBFS)
–70 –60 –50 –40 –30 –20 –10 0
2274
G17
30
40
50
60
70
80
90
100
110
120
130
140
FREQUENCY (MHz)
0
AMPLITUDE (dBFS)
10 20 30 40 50
2274
G18
–130
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
VDD = 3.3V, OVDD = 1.5V, TA = 25°C, FS = 105Msps,
unless otherwise noted.
LTC2274
10
2274fb
SAMPLE RATE (Msps)
0
IVDD (mA)
8040 120
2274
G25
290
300
310
320
330
340
350
360
370
380
390
400
410
420
TYPICAL PERFORMANCE CHARACTERISTICS
64k Point FFT, fIN = 250.2MHz,
–1dBFS, PGA = 1
SFDR (HD2 and HD3) vs
Input Frequency SNR vs Input Frequency
SNR and SFDR vs Sample Rate,
fIN = 5.1MHz
SNR and SFDR vs Supply Voltage
(VDD), fIN = 5.2MHz
SFDR vs Analog Input
Common Mode Voltage, 5MHz
and 70MHz, –1dBFS
IVDD vs Sample Rate, 5MHz Sine,
–1dBFS
FREQUENCY (MHz)
0
AMPLITUDE (dBFS)
10 20 30 40 50
2274
G19
–130
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
INPUT FREQUENCY (MHz)
0
SFDR (dBc)
400200
2274 G20
500300100
PGA = 1
PGA = 0
65
70
75
80
85
90
95
100
105
INPUT FREQUENCY (MHz)
0
SNR (dBFS)
400200
2274 G21
500300100
PGA = 0
PGA = 1
64
66
68
70
72
74
76
78
SAMPLE RATE (Msps)
20
SNR (dBFS) AND SFDR (dBC)
10060
2274 G22
1208040
SFDR
LIMIT
SNR
70
75
80
85
90
95
100
105
110
SUPPLY VOLTAGE (V)
2.8
SNR AND SFDR (dBFS)
3.2
2274 G23
3.43.0
SFDR
UPPER LIMIT
LOWER LIMIT
SNR
70
75
80
85
90
95
100
105
110
ANALOG INPUT COMMON MODE VOLTAGE (V)
0.50
SFDR (dBc)
0.75 1.00 1.25 1.50 1.75
2274
G02
2.00
60
65
70
75
80
85
90
95
100
105
110
5MHz
70MHz
VDD = 3.3V, OVDD = 1.5V, TA = 25°C, FS = 105Msps,
unless otherwise noted.
LTC2274
11
2274fb
TYPICAL PERFORMANCE CHARACTERISTICS
CMLOUT Dual-Dirac BER
Bathtub Curve, 400Mbps
CMLOUT Dual-Dirac BER
Bathtub Curve, 1.2Gbps
CMLOUT Dual-Dirac BER
Bathtub Curve, 2.1Gbps CMLOUT Eye Diagram 400Mbps
CMLOUT Eye Diagram 1.2Gbps CMLOUT Eye Diagram 2.1Gbps
VDD = 3.3V, OVDD = 1.5V, TA = 25°C, FS = 105Msps,
unless otherwise noted.
UNIT INTERVAL (UI)
0
BIT ERROR RATE (BER)
0.80.4
2274 G26
1.00.60.2
1.0E–14
1.0E–12
1.0E
–
10
1.0E–08
1.0E–06
1.0E–04
1.0E–02
1.0E+00
UNIT INTERVAL (UI)
0
BIT ERROR RATE (BER)
0.80.4
2274 G27
1.00.60.2
1.0E–14
1.0E–12
1.0E
–
10
1.0E–08
1.0E–06
1.0E–04
1.0E–02
1.0E+00
UNIT INTERVAL (UI)
0
BIT ERROR RATE (BER)
0.80.4
2274 G28
1.00.60.2
1.0E–14
1.0E–12
1.0E
–
10
1.0E–08
1.0E–06
1.0E–04
1.0E–02
1.0E+00
416.7ps/DIV
2274 G29
100mV/DIV
138.9ps/DIV
2274 G30
100mV/DIV
79.4ps/DIV
2274 G31
100mV/DIV
LTC2274
12
2274fb
PIN FUNCTIONS
VDD (Pins 1, 2, 12, 13 ): Analog 3.3V Supply. Bypass to
GND with 0.1μF ceramic chip capacitors.
GND (Pins 3, 6, 7, 8, 11, 14, 21, 26, 27, 30, 37, 40):
ADC Power Ground.
AIN+ (Pin 4): Positive Differential Analog Input.
AIN– (Pin 5): Negative Differential Analog Input.
ENC+ (Pin 9): Positive Differential Encode Input. The
sampled analog input is held on the rising edge of ENC+.
This pin is internally biased to 1.6V through a 6.2kΩ resistor.
Output data can be latched on the falling edge of ENC+.
ENC– (Pin 10): Negative Differential Encode Input. The
sampled analog input is held on the falling edge of ENC-.
This pin is internally biased to 1.6V through a 6.2kΩ
resistor. Bypass to ground with a 0.1uF capacitor for a
single-ended Encode signal.
DITH (Pin 15): Internal Dither Enable Pin. DITH = low
disables internal dither. DITH = high enables internal dither.
Refer to Internal Dither section of this data sheet for details
on dither operation.
ISMODE (Pin 16): Idle Synchronization mode. When IS-
MODE is not asserted, synchronization is performed with
a series of COMMAS (K28.5). When ISMODE is asserted,
a special Idle SYNC mode is enabled where synchroniza-
tion is performed by sending a COMMA (K28.5) followed
by the appropriate data code-group (D5.6 or D16.2) for
establishing a negative running disparity for the fi rst data
code-group after synchronization.
SRR0 (Pin 17): Sample Rate Range Select Bit0. Used with
the SRR1 pin to select the sample rate operating range.
SRR1 (Pin 18): Sample Rate Range Select Bit1. Used with
the SRR0 pin to select the sample rate operating range.
SHDN (Pins 19, 20): Shutdown Pins. A high level on both
pins will shut down the chip.
OVDD (Pins 22, 25): Positive Supply for the Output Drivers.
This supply range is 1.2V to VDD for directly coupled CML
outputs, or 1.4V to OVDD for AC-coupled or differentially
terminated CML outputs. Bypass to ground with 0.1μF
ceramic chip capacitor.
CMLOUT– (Pin 23): Negative High-Speed CML Output.
CMLOUT+ (Pin 24): Positive High-Speed CML Output.
SYNC+ (Pin 28): Sync Request Positive Input (Active
Low for Compatibility with JESD204). A low level on this
pin for at least two sample clock cycles will initiate frame
synchronization.
SYNC– (Pin 29): Sync Request Negative Input. A high
level on this pin for at least two sample clock cycles will
initiate frame synchronization. For single-ended operation,
bypass to ground with a 0.1μF capacitor and use SYNC+
as the SYNC point.
FAM (Pin 31): Frame Alignment Monitor Enable. A high
level enables the substitution of predetermined data at the
end of the frame with a K28.7 symbol for frame alignment
monitoring.
PAT0 (Pin 32): Pattern Select Bit0. Use with PAT1 to select
a test pattern for the serial interface.
PAT1 (Pin 33): Pattern Select Bit1. Use with PAT0 to select
a test pattern for the serial interface.
SCRAM (Pin 34): Enable Data Scrambling. A high level on
this pin will apply the polynomial 1 + x14 + x15 in scram-
bling each ADC data sample. The scrambling takes place
before the 8B/10B encoding.
PGA (Pin 35): Programmable Gain Amplifi er Control
Pin. Low selects a front-end gain of 1, input range of
2.25VP-P . High selects a front-end gain of 1.5, input range
of 1.5VP-P .
MSBINV (Pin 36): Invert the MSB. A high level will invert
the MSB to enable the 2’s complement format.
LTC2274
13
2274fb
CORRECTION
LOGIC
8B/10B
ENCODER
SCRAMBLER/
PATTERN
GENERATOR
PLL
20X CLK
VCM
22743 BD
SYNC+
SYNC–
PAT1 PAT0 SRR1 SRR0SCRAM
VDD
OVDD
GND
CMLOUT+
CMLOUT–
20
SERIALIZER
CONTROL LOGIC
MSBINV SHDNDITHPGA
CLOCK DRIVER
WITH DUTY CYCLE
CONTROL
2.5V
REFERENCE
ADC
REFERENCE
1x OR 2x
0.5x
REFERENCE
CONTROL
ENC–
ENC+
FAM
SENSE
16
–
+
DITHER SIGNAL
GENERATOR
S/H
AND PGA
AIN–
AIN+FIRST
STAGE
SECOND
STAGE
THIRD
STAGE
PIPELINED ADC STAGES
FOURTH
STAGE
FIFTH
STAGE
BLOCK DIAGRAM
Figure 1. Functional Block Diagram
SENSE (Pin 38): Reference Mode Select and External
Reference Input. Tie SENSE to VDD to select the internal
2.5V bandgap reference. An external reference of 2.5V or
1.25V may be used; both reference values will set a full
scale ADC range of 2.25V (PGA = 0).
VCM (Pin 39): 1.25V Output. Optimum voltage for input
common mode. Must be bypassed to ground with a
minimum of 2.2μF. Ceramic chip capacitors are recom-
mended.
GND (Exposed Pad) (Pin 41): ADC Power Ground. The
Exposed Pad on the bottom of the package needs to be
soldered to ground.
PIN FUNCTIONS
LTC2274
14
2274fb
DEFINITIONS
DYNAMIC PERFORMANCE TERMS
Signal-to-Noise Plus Distortion Ratio
The signal-to-noise plus distortion ratio [S/(N+D)] is the
ratio between the RMS amplitude of the fundamental input
frequency and the RMS amplitude of all other frequency
components at the ADC output. The output is band lim-
ited to frequencies above DC to below half the sampling
frequency.
Signal-to-Noise Ratio
The signal-to-noise (SNR) is the ratio between the RMS
amplitude of the fundamental input frequency and the RMS
amplitude of all other frequency components, except the
fi rst fi ve harmonics.
Total Harmonic Distortion
Total harmonic distortion is the ratio of the RMS sum
of all harmonics of the input signal to the fundamental
itself. The out-of-band harmonics alias into the frequency
band between DC and half the sampling frequency. THD
is expressed as:
THD = –20Log (√(V22 + V32 + V42 + ... VN2)/V1)
where V1 is the RMS amplitude of the fundamental fre-
quency and V2 through VN are the amplitudes of the second
through nth harmonics.
Intermodulation Distortion
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce intermodulation distortion (IMD) in addition to
THD. IMD is the change in one sinusoidal input caused
by the presence of another sinusoidal input at a different
frequency.
If two pure sine waves of frequencies fa and fb are applied
to the ADC input, nonlinearities in the ADC transfer function
can create distortion products at the sum and difference
frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc.
For example, the 3rd order IMD terms include (2fa + fb),
(fa + 2fb), (2fa - fb) and (fa - 2fb). The 3rd order IMD is
defi ned as the ratio of the RMS value of either input tone
to the RMS value of the largest 3rd order IMD product.
Spurious Free Dynamic Range (SFDR)
The ratio of the RMS input signal amplitude to the RMS
value of the peak spurious spectral component expressed
in dBc. SFDR may also be calculated relative to full scale
and expressed in dBFS.
Full Power Bandwidth
The full power bandwidth is that input frequency at which
the amplitude of the reconstructed fundamental is reduced
by 3dB for a full scale input signal.
Aperture Delay Time
The time from when a rising ENC+ equals the ENC– voltage
to the instant that the input signal is held by the sample-
and-hold circuit.
Aperture Delay Jitter
The variation in the aperture delay time from conversion
to conversion. This random variation will result in noise
when sampling an AC input. The signal to noise ratio due
to the jitter alone will be:
SNRJITTER = –20log (2π • fIN • tJITTER)
SERIAL INTERFACE TERMS
8B/10B Encoding
A data encoding method designed to make an 8-bit data
word (octet) more suitable for serial transmission. The
resulting 10-bit word (code-group) has two fundamental
strengths: 1) The receiver does not require a high-speed
clock to capture the data. This is because the output
code-groups are run-length limited, ensuring that there
are enough transitions in the bit stream for the receiver
to lock onto the data and recover the high-speed clock.
2) AC coupling is permitted because the code-groups are
generated in a way that ensures the data stream is DC
balanced (see Running Disparity).
A table of the 256 possible input octets with the resulting
10-bit code-groups is documented in IEEE Std 802.3-2002
part3 Table 36-1. The name associated with each of the
256 data code-groups is formatted Dx.y, with x ranging
from 0 to 31 and y ranging from 0 to 7. Table 36-2 of
LTC2274
15
2274fb
DEFINITIONS
the standard defi nes an additional set of 12 special code-
groups for non-data characters such as commas. Special
code-group names begin with K instead of D. A complete
8B/10B description is found in Clause 36.2 of IEEE Std
802.3-2002 part3.
Current Mode Logic (CML)
A technique used to implement differential high-speed logic.
CML employs differential pairs (usually n-type) to steer
current into resistive loads. It is possible to implement any
logic function using CML. The output swing and offset is
dependant on the bias current, the load resistance, and
termination resistance.
This product family uses CML drivers to transmit high-
speed serial data to the outside world. The output driver
bias current is typically 16mA, generating a signal swing
potential of 400mVP-P (800mVP-P diff.) across the com-
bined internal and external termination resistance of 25Ω
on each output.
Code-Group
The 10-bit output from an 8B/10B encoder or the 10-bit
input to the 8B/10B decoder.
Comma
A special 8B/10B code-group containing the binary se-
quence “0011111” or “1100000”. Commas are used for
frame alignment and synchronization because a comma
sequence cannot be generated by any combination of
normal code-groups (unless a bit error occurs). There are
three special code-groups that contain a comma, K28.1,
K28.5, and K28.7.
For brevity, each of these three special code-groups are
often called a comma, but in the strictest sense it is the
fi rst 7 bits of these code-groups that are designated a
comma.
DC Balanced Signal
A specially conditioned signal that may be AC coupled with
minimal degradation to the signal. DC balance is achieved
when the average number of 1’s and 0’s are equal, eliminat-
ing the undesirable effects of DC wander on the receive
side of the coupling capacitor. When 8B/10B coding is
used, DC balance is achieved by following disparity rules
(see Running Disparity).
De-Scrambler
A logic block that restores scrambled data to its pre-
scrambled state. A self aligning de-scrambler is based on
the same pseudo random bit sequence as the scrambler,
so it requires no alignment signals. In this product family
the scrambler is based on the 1 + x14 + x15 polynomial,
and the self aligning process results in an initial loss of
one ADC sample.
Frame
A group of octets or code-groups that make up one
complete word. For this product family, a frame consists
of two complete octets or code-groups, and constitutes
one ADC sample.
Frame Alignment Monitoring (FAM)
After initial frame synchronization has been established,
frame alignment monitoring enables the receiver to verify
that code-group alignment is maintained without the loss
of data. This is done by substituting a K28.7 comma for the
last code-group of the frame when certain conditions are
met. The receiver uses this comma as a position marker
within the frame for alignment verifi cation. After decoding
the data, the receiver replaces the K28.7 comma with the
original data.
Idle Frame Synchronization Mode (ISMODE)
A special synchronization mode where idle ordered sets
are used to establish initial frame synchronization instead
of K28.5 commas.
An Idle Ordered Set is defi ned in the IEEE Std 802.3-2002
part3, Clause 36.2.4.12. In general, it is a K28.5 comma
followed by either a D5.6 or a D16.2. If the running dispar-
ity after the transmission of the K28.5 comma is positive,
LTC2274
16
2274fb
DEFINITIONS
a D16.2 will be transmitted after the comma, otherwise
a D5.6 will be transmitted. The result is that the ending
disparity of an idle ordered set will always be negative.
Initial Frame Synchronization
The process of communicating frame synchronization
information to the receiver upon the request of the receiver.
For JESD204 compliance, K28.5 commas are transmitted
as the preamble. Once the preamble has been detected
the receiver terminates the synchronization request, and
the preamble transmission continues until the end of the
frame. The receiver designates the fi rst normal data word
after the preamble to be the start of the data frame.
Octet
The 8-bit input to an 8B/10B encoder, or the 8-bit output
from an 8B/10B decoder.
Run-Length Limited (RLL)
The act of limiting the number of consecutive 1’s or 0’s
in a data stream by encoding the data prior to serial
transmission.
This process guarantees that there will be an adequate
number of transitions in the serial data for the receiver
to lock onto with a phase-locked loop and recover the
high-speed clock.
Running Disparity
In order to maintain DC balance there are two possible
8B/10B output code-groups for each input octet. The
running disparity is calculated to determine which of the
two code-groups should be transmitted to maintain DC
balance.
The disparity of a code-group is analyzed in two segments
called sub-blocks. Sub-block1 consists of the fi rst six bits
of a code-group and sub-block2 consists of the last four
bits of a code-group. When a sub-block is more heavily
weighted with 1’s the running disparity is positive, and when
it is more heavily weighted with 0’s the running disparity
is negative. When the number of 1’s and 0’s are equal in a
sub-block, the running disparity remains unchanged.
The polarity of the current running disparity determines
which code-group should be transmitted to maintain DC
balance. For a complete description of disparity rules, refer
to IEEE Std 802.3-2002 part3, Clause 36.2.4.4.
Pseudo Random Bit Sequence (PRBS)
A data sequence having a random nature over a fi nite
interval. The most commonly used PRBS test patterns
may be described by a polynomial in the form of 1 + xm +
xn and have a random nature for the length of up to 2n – 1
bits, where n indicates the order of the PRBS polynomial
and m plays a role in maximizing the length of the random
sequence.
Scrambler
A logic block that applies a pseudo random bit sequence
to the input octets to minimize the tonal content of the
high-speed serial bit stream.
LTC2274
17
2274fb
APPLICATIONS INFORMATION
CONVERTER OPERATION
The core of the LTC2274 is a CMOS pipelined multi-step
converter with a front-end PGA. As shown in Figure 1, the
converter has fi ve pipelined ADC stages. A sampled analog
input will result in a digitized value nine clock cycles later
(see the Timing Diagram section). The analog input (AIN+,
AIN–) is differential for improved common mode noise im-
munity and to maximize the input range. Additionally, the
differential input drive will reduce even order harmonics
of the sample and hold circuit. The encode clock input
(ENC+, ENC–) is also differential for improved common
mode noise immunity.
Each pipelined stage shown in Figure 1 contains an ADC,
a reconstruction DAC, and an error residue amplifi er. The
function of each stage is to produce a digital representation
of its input voltage along with the resulting analog error
residue. The ADC of each stage provides the quantization,
and the residue is produced by taking the difference between
the input voltage and the output of the reconstruction DAC.
The residue is amplifi ed by the residue amplifi er and passed
on to the next stage. The successive stages of the pipeline
operate on alternating phases of the clock so that when
odd stages are outputting their residue, the even stages
are acquiring that residue and vice versa.
The pipelined ADC of the LTC2274 has two phases of
operation determined by the state of the differential
ENC+/ENC– input pins. For brevity, the text will refer to
ENC+ greater than ENC– as ENC high and ENC+ less than
ENC– as ENC low.
When ENC is low, the analog input is sampled differentially
onto the input sample-and-hold capacitors, inside the “S/H
& PGA” block of Figure 1. On the rising edge of ENC, the
voltage on the sample capacitors is held. While ENC is
high, the held input voltage is buffered by the S/H amplifi er
which drives the fi rst pipelined ADC stage. The fi rst stage
acquires the output of the S/H amplifi er during the high
phase of ENC. On the falling edge of ENC, the fi rst stage
produces its residue which is acquired by the second stage.
The process continues to the end of the pipeline.
Each ADC stage following the fi rst has additional error
correction range to accommodate fl ash and amplifi er offset
errors. Results from all of the ADC stages are digitally
delayed such that the results can be properly combined
in the correction logic before being encoded, serialized,
and sent to the output buffer.
LTC2274
18
2274fb
APPLICATIONS INFORMATION
SAMPLE/HOLD OPERATION AND INPUT DRIVE
Sample/Hold Operation
Figure 2 shows an equivalent circuit for the LTC2274 CMOS
differential sample and hold. The differential analog inputs
are sampled directly onto sampling capacitors (CSAMPLE)
through NMOS transistors. The capacitors shown attached
to each input (CPARASITIC) are the summation of all other
capacitance associated with each input.
During the sample phase when ENC is low, the NMOS
transistors connect the analog inputs to the sampling
capacitors and they charge to, and track, the differential
input voltage. On the rising edge of ENC, the sampled
input voltage is held on the sampling capacitors. During
the hold phase when ENC is high, the sampling capacitors
are disconnected from the input and the held voltage is
passed to the ADC core for processing. As ENC transitions
for high to low, the inputs are reconnected to the sampling
capacitors to acquire a new sample. Since the sampling
capacitors still hold the previous sample, a charging glitch
proportional to the change in voltage between samples will
be seen at this time. If the change between the last sample
and the new sample is small, the charging glitch seen at
the input will be small. If the input change is large, such
as the change seen with input frequencies near Nyquist,
then a larger charging glitch will be seen.
Common Mode Bias
The ADC sample-and-hold circuit requires differential drive
to achieve specifi ed performance. Each input should swing
±0.5625V for the 2.25V range (PGA = 0) or ±0.375V for
the 1.5V range (PGA = 1), around a common mode volt-
age of 1.25V. The VCM output pin (Pin 39) is designed to
provide the common mode bias level. VCM can be tied
directly to the center tap of a transformer to set the DC
input level or as a reference level to an op amp differential
driver circuit. The VCM pin must be bypassed to ground
close to the ADC with 2.2μF or greater.
Input Drive Impedance
As with all high performance, high speed ADCs the dy-
namic performance of the LTC2274 can be infl uenced
by the input drive circuitry, particularly the second and
third harmonics. Source impedance and input reactance
can infl uence SFDR. At the falling edge of ENC the
sample-and-hold circuit will connect the 4.9pF sampling
capacitor to the input pin and start the sampling period.
The sampling period ends when ENC rises, holding the
sampled input on the sampling capacitor. Ideally, the
input circuitry should be fast enough to fully charge
the sampling capacitor during the sampling period
1/(2FENCODE); however, this is not always possible and the
incomplete settling may degrade the SFDR. The sampling
glitch has been designed to be as linear as possible to
minimize the effects of incomplete settling.
For the best performance it is recommended to have a
source impedance of 100Ω or less for each input. The
source impedance should be matched for the differential
inputs. Poor matching will result in higher even order
harmonics, especially the second.
CSAMPLE
4.9pF
VDD
VDD
LTC2274
AIN+
2274 F02
CSAMPLE
4.9pF
VDD
AIN–
ENC–
ENC+
1.6V
6k
1.6V
6k
CPARASITIC
1.8pF
CPARASITIC
1.8pF
RPARASITIC
3Ω
RON
20Ω
RON
20Ω
RPARASITIC
3Ω
Figure 2. Equivalent Input Circuit
LTC2274
19
2274fb
APPLICATIONS INFORMATION
INPUT DRIVE CIRCUITS
Input Filtering
A fi rst order RC lowpass fi lter at the input of the ADC can
serve two functions: limit the noise from input circuitry and
provide isolation from ADC S/H switching. The LTC2274
has a very broadband S/H circuit, DC to 700MHz; it can
be used in a wide range of applications; therefore, it is not
possible to provide a single recommended RC fi lter.
Figures 3, 4a and 4b show three examples of input RC
fi ltering at three ranges of input frequencies. In general
it is desirable to make the capacitors as large as can be
tolerated—this will help suppress random noise as well
as noise coupled from the digital circuitry. The LTC2274
does not require any input fi lter to achieve data sheet
specifi cations; however, no fi ltering will put more stringent
noise requirements on the input drive circuitry.
Transformer Coupled Circuits
Figure 3 shows the LTC2274 being driven by an RF trans-
former with a center-tapped secondary. The secondary
center tap is DC biased with VCM, setting the ADC input
signal at its optimum DC level. Figure 3 shows a 1:1 turns
ratio transformer. Other turns ratios can be used; however,
as the turns ratio increases so does the impedance seen by
the ADC. Source impedance greater than 50Ω can reduce
the input bandwidth and increase high frequency distor-
tion. A disadvantage of using a transformer is the loss of
low frequency response. Most small RF transformers have
poor performance at frequencies below 1MHz.
Center-tapped transformers provide a convenient means
of DC biasing the secondary; however, they often show
poor balance at high input frequencies, resulting in large
2nd order harmonics.
Figure 4a shows transformer coupling using a transmis-
sion line balun transformer. This type of transformer has
much better high frequency response and balance than
fl ux coupled center tap transformers. Coupling capacitors
are added at the ground and input primary terminals to
allow the secondary terminals to be biased at 1.25V. Figure
4b shows the same circuit with components suitable for
higher input frequencies.
0.1μF
AIN+
AIN–
4.7pF
2.2μF
4.7pF
4.7pF
VCM
LTC2274
ANALOG
INPUT
0.1μF
0.1μF
T1
1:1
T1 = MA/COM ETC1-1-13
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
EXCEPT 2.2μF
2274 F04a
5Ω10Ω
25Ω
25Ω 10Ω 5Ω
Figure 4a. Using a Transmission Line Balun Transformer.
Recommended for Input Frequencies from 100MHz to 250MHz
0.1μF
AIN+
AIN–
2.2μF
2.2pF
2.2pF
VCM
LTC2274
ANALOG
INPUT
0.1μF
0.1μF
T1
1:1
T1 = MA/COM ETC1-1-13
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
EXCEPT 2.2μF
2274 F04b
5Ω
25Ω
25Ω 5Ω
Figure 4b. Using a Transmission Line Balun Transformer.
Recommended for Input Frequencies from 250MHz to 500MHz
Figure 3. Single-Ended to Differential Conversion
Using a Transformer. Recommended for Input
Frequencies from 5MHz to 150MHz
35Ω
50Ω
35Ω
10Ω
10Ω
5Ω
5Ω
0.1μF
AIN+
AIN–
8.2pF
2.2μF
8.2pF
8.2pF
VCM
LTC2274
T1
T1 = MA/COM ETC1-1T
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
EXCEPT 2.2μF
2274 F03
LTC2274
20
2274fb
APPLICATIONS INFORMATION
Direct Coupled Circuits
Figure 5 demonstrates the use of a differential amplifi er to
convert a single ended input signal into a differential input
signal. The advantage of this method is that it provides
low frequency input response; however, the limited gain
bandwidth of any op amp or closed-loop amplifi er will de-
grade the ADC SFDR at high input frequencies. Additionally,
wideband op amps or differential amplifi ers tend to have
high noise. As a result, the SNR will be degraded unless
the noise bandwidth is limited prior to the ADC input.
Reference Operation
Figure 6 shows the LTC2274 reference circuitry consisting
of a 2.5V bandgap reference, a programmable gain ampli-
fi er and control circuit. The LTC2274 has three modes of
reference operation: Internal Reference, 1.25V external
reference or 2.5V external reference. To use the internal
reference, tie the SENSE pin to VDD. To use an external
reference, simply apply either a 1.25V or 2.5V reference
voltage to the SENSE input pin. Both 1.25V and 2.5V applied
to SENSE will result in a full scale range of 2.25VP-P (PGA
= 0). A 1.25V output VCM is provided for a common mode
bias for input drive circuitry. An external bypass capacitor is
required for the VCM output. This provides a high frequency
low impedance path to ground for internal and external
circuitry. This is also the compensation capacitor for the
reference; it will not be stable without this capacitor. The
minimum value required for stability is 2.2μF.
The internal programmable gain amplifi er provides the
internal reference voltage for the ADC. This amplifi er has
very stringent settling requirements and is not accessible
for external use.
The SENSE pin can be driven ±5% around the nominal 2.5V
or 1.25V external reference inputs. This adjustment range
can be used to trim the ADC gain error or other system
gain errors. When selecting the internal reference, the
SENSE pin should be tied to VDD as close to the converter
as possible. If the sense pin is driven externally it should
be bypassed to ground as close to the device as possible
with 1μF (or larger) ceramic capacitor.
PGA Pin
The PGA pin selects between two gain settings for
the ADC front-end. PGA = 0 selects an input range of
2.25VP-P; PGA = 1 selects an input range of 1.5VP-P
. The
2.25V input range has the best SNR; however, the distor-
tion will be higher for input frequencies above 100MHz.
For applications with high input frequencies, the low
input range will have improved distortion; however, the
SNR will be 2.4dB worse. See the Typical Performance
Characteristics section of this datasheet.
Figure 5. DC Coupled Input with Differential Amplifi er
––
++
AIN+
AIN–
2.2μF
12pF
12pF
VCM
LTC2274
ANALOG
INPUT
2274 F05
CM
AMPLIFIER = LTC6600-20,
LTC1993, ETC.
HIGH SPEED
DIFFERENTIAL
AMPLIFIER 25Ω
25Ω
1x OR 2x
1.25V
SENSE
VCM BUFFER
INTERNAL
ADC
REFERENCE
RANGE
SELECT
AND GAIN
CONTROL
2.5V
BANDGAP
REFERENCE
2.2μF
TIE TO VDD TO USE
INTERNAL 2.5V
REFERENCE
OR INPUT FOR
EXTERNAL 2.5V
REFERENCE
OR INPUT FOR
EXTERNAL 1.25V
REFERENCE
2274 F06
LTC2274
Figure 6. Reference Circuit
LTC2274
21
2274fb
APPLICATIONS INFORMATION
2274 F10
ENC–
ENC+
3.3V
3.3V
D0
Q0
Q0
LTC2274
130Ω130Ω
83Ω83Ω
MC100LVELT22
Figure 10. ENC Drive Using a CMOS to PECL Translator
Figure 9. Single-Ended ENC Drive,
Not Recommended for Low Jitter
2274 F09
ENC–
1.6V
VTHRESHOLD = 1.6V ENC+
0.1μF
LTC2274
Figure 7. A 2.25V Range ADC with
an External 2.5V Reference
VCM
SENSE
1.25V
3.3V
2.2μF
2.2μF
1μF
2274 F07
LTC2274
2, 3 6
4, 5, 7, 8
LTC6652-2.5
Figure 8a. Equivalent Encode Input Circuit
Figure 8b. Transformer Driven Encode
VDD
VDD
LTC2274
2274 F08a
VDD
ENC–
ENC+
1.6V
1.6V
6k
6k
TO INTERNAL
ADC CLOCK
DRIVERS
50Ω 100Ω
8.2pF
0.1μF
0.1μF
0.1μF
T1
T1 = MA/COM ETC1-1-13
RESISTORS AND CAPACITORS
ARE 0402 PACKAGE SIZE
50Ω
LTC2274
2274 F08b
ENC–
ENC+
LTC2274
22
2274fb
APPLICATIONS INFORMATION
Driving the Encode Inputs
The noise performance of the LTC2274 can depend on
the encode signal quality as much as for the analog input.
The encode inputs are intended to be driven differentially,
primarily for noise immunity from common mode noise
sources. Each input is biased through a 6k resistor to a
1.6V bias. The bias resistors set the DC operating point
for transformer coupled drive circuits and can set the logic
threshold for single-ended drive circuits.
Any noise present on the encode signal will result in ad-
ditional aperture jitter that will be RMS summed with the
inherent ADC aperture jitter.
In applications where jitter is critical (high input frequen-
cies), take the following into consideration:
1. Differential drive should be used.
2. Use as large an amplitude possible. If using trans-
former coupling, use a higher turns ratio to increase the
amplitude.
3. If the ADC is clocked with a fi xed frequency sinusoidal
signal, fi lter the encode signal to reduce wideband
noise.
4. Balance the capacitance and series resistance at both
encode inputs such that any coupled noise will appear
at both inputs as common mode noise.
The encode inputs have a common mode range of 1.2V
to VDD. Each input may be driven from ground to VDD for
single-ended drive.
Maximum and Minimum Conversion Rates
The maximum conversion rate is 105Msps for the
LTC2274.
The lower limit of the LTC2274 sample rate is determined
by the PLL minimum operating frequency of 20Msps.
For the ADC to operate properly, the internal CLK signal
should have a 50% duty cycle. A duty cycle stabilizer cir-
cuit has been implemented on chip to facilitate non-50%
ENC duty cycles.
Data Format
The MSBINV pin selects the ADC data format. A low level
selects offset binary format (code 0 corresponds to –FS, and
code 65535 corresponds to +FS). A high level on MSBINV
selects 2’s complement format (code –32768 corresponds
to –FS and code 32767 corresponds to +FS.
Shutdown
A high level on both SHDN pins will shutdown the ADC
and the serial interface and place the chip in a low cur-
rent state.
Internal Dither
The LTC2274 is a 16-bit ADC with a very linear transfer
function; however, at low input levels even slight imperfec-
tions in the transfer function will result in unwanted tones.
Small errors in the transfer function are usually a result
of ADC element mismatches. An optional internal dither
mode can be enabled to randomize the input location on
the ADC transfer curve, resulting in improved SFDR for
low signal levels.
As shown in Figure 11, the output of the sample-and-hold
amplifi er is summed with the output of a dither DAC. The
dither DAC is driven by a long sequence pseudo-random
number generator; the random number fed to the dither
DAC is also subtracted digitally from the ADC result. If the
dither DAC is precisely calibrated to the ADC, very little
of the dither signal will be seen at the output. The dither
signal that does leak through will appear as white noise.
The dither DAC is calibrated to result in less than 0.5dB
elevation in the noise fl oor of the ADC, as compared to
the noise fl oor with dither off.
LTC2274
23
2274fb
APPLICATIONS INFORMATION
SERIALIZED DATA FRAME
Prior to serialization, the ADC data is encoded into the
8B/10B format, which is DC balanced, and run-length
limited. The receiver is required to lock onto the data
and recover the clock with the use of a PLL. The 8B/10B
format requires that the ADC data be broken up into 8-bit
blocks (octets), which is encoded into 10-bit code groups
applying the 8B/10B rules (refer to IEEE Std 802.3-2002
Part 3, for a complete 8B/10B description).
Figure 12 illustrates the generation of one complete 8B/10B
frame. The 8 most signifi cant bits of the ADC are assigned
to the fi rst half of the frame, and the remaining 8 bits
to the second half of the frame. Next, the two resulting
octets are optionally scrambled and encoded into their
corresponding 8B/10B code. Finally, the two 10-bit code
groups are serialized and transmitted beginning with Bit
0 of code group 1.
+–
AIN–
AIN+
S/H
AMP
DIGITAL
SUMMATION
8b10b
ENCODER
MULTIBIT DEEP
PSEUDO-RANDOM
NUMBER
GENERATOR
16-BIT
PIPELINED
ADC CORE
PRECISION
DAC
CLOCK/DUTY
CYCLE
CONTROL
ENC
DITHER ENABLE
HIGH = DITHER ON
LOW = DITHER OFF
DITH
ENC
ANALOG
INPUT
2274 F11
LTC2274
CMLOUT+
CMLOUT–
SERIALIZER
Figure 11. Functional Equivalent Block Diagram of Internal Dither Circuit
Figure 12. Evolution of One Transmitted Frame (Compare to IEEE Std 802.3-2002 Part 3, Figure 36-3)
BIT
15
BIT
0
BIT
1
BIT
2
BIT
3
BIT
4
BIT
5
BIT
6
BIT
7
BIT
8
BIT
9
BIT
10
BIT
11
BIT
12
BIT
13
BIT
14
BIT
7
BIT
0
BIT
1
BIT
2
BIT
3
BIT
4
BIT
5
BIT
6
HABCDEFG
BIT
7
BIT
0
BIT
1
BIT
2
BIT
3
BIT
4
BIT
5
BIT
6
HABCD
FIRST OCTET
ADC OUTPUT WORDMSB LSB
OCTET
ASSIGNMENT
OPTIONAL
SCRAMBLER
8B/10B
ENCODER
EFG
BIT
2
BIT
9
BIT
8
BIT
7
BIT
6
BIT
5
BIT
4
BIT
3
BIT
0
BIT
1
cjhgf
FIRST SCRAMBLED OCTET
8B/10B CODE GROUP 1
BIT 0 OF CODE GROUP 1 IS TRANSMITTED FIRST
iedab
BIT
7
BIT
0
BIT
1
BIT
2
BIT
3
BIT
4
BIT
5
BIT
6
HBACDEFG
BIT
7
BIT
0
BIT
1
BIT
2
BIT
3
BIT
4
BIT
5
BIT
6
HBACD
SECOND OCTET
EFG
BIT
2
BIT
9
BIT
8
BIT
7
BIT
6
BIT
5
BIT
4
BIT
3
BIT
0
BIT
1
chjgf
SECOND SCRAMBLED OCTET
8B/10B CODE GROUP 2
iedab
ONE FRAME
SERIAL OUT 2274 F12
LTC2274
24
2274fb
APPLICATIONS INFORMATION
Initial Frame Synchronization
In the absence of a frame clock, it is necessary to deter-
mine the start of each frame through a synchronization
process. To establish frame synchronization, Figures 14
and 15 illustrate the following sequence:
• The receiver issues a synchronization request via the
synchronization interface.
• If the synchronization request is active for more than
one ENC clock cycle, the LTC2274 will transmit a
synchronization preamble. When the ISMODE pin is
low the transmitted preamble will consist of consecu-
tive K28.5 comma symbols in conformance with the
JESD204 specifi cation. When the ISMODE pin is high,
a series of idle ordered sets will be transmitted. The
idle ordered sets consist of a K28.5 comma followed by
either D5.6 or D16.2 as defi ned in IEEE Std 802.3-2002
part3, Clause 36.2.4.12.
• The receiver searches for the expected preamble and
waits for the correct reception of an adequate number
of preamble characters.
• The receiver deactivates the synchronization request.
• Upon detecting the deactivation of the synchroniza-
tion request, the LTC2274 continues to transmit the
synchronization preamble until the end of the frame.
• At the start of the next frame, the LTC2274 will begin
transmitting data characters.
• The receiver designates the fi rst data character received
after the preamble transmission to be the start of the
frame. The fi rst octet of the frame contains the most
signifi cant byte of the ADC’s output word.
Figure 13. Timing Relationship of Analog Sample to Serial Data Out
N – 6
N – 10 N – 9 N – 8 N – 1 N
N – 5 N – 4 N + 3 N + 4
N – 9 N – 8 N – 7 N N + 1
tH
tCONV
LATP
tL
tAP
tBIT
NN + 1 N + 2 N + 8
N + 9
2274 F13
N + 10
ANALOG INPUT
ENC+
INTERNAL
PARALLEL DATA
INTERNAL
8B/10B DATA
SERIAL DATA OUT
LTC2274
25
2274fb
APPLICATIONS INFORMATION
Figure 14a. SYNC+ Low Transition to Comma Output Timing (ISMODE is Low)
Figure 14b. SYNC+ High Transition to Data Output Timing (ISMODE is Low)
N – 1 N
N + 1 N + 2
N + 3
N + 4 N + 5
N – 10 N – 9 N – 8 N – 7 K28.5 (x2) K28.5 (x2)
tCONV
tCS(MAX) LATSC
tHD
tCS(MIN)
tSU
ANALOG INPUT
ENC+
SYNC+
SERIAL DATA OUT
2274 F14a
N – 1 N
N + 1 N + 2
N + 3
N + 4
K28.5 (x2) K28.5 (x2) K28.5 (x2) N – 7 N – 6
tCONV
tCS(MAX) LATSD
tHD
tCS(MIN)
tSU
ANALOG INPUT
ENC+
SERIAL DATA OUT
2274 F14b
SYNC+
LTC2274
26
2274fb
SYNC
REQUEST?
START
IS ISMODE
ENABLED?
NEGATIVE
DISPARITY?
DATA TRANSMISSION
FLOW (SEE FIGURE 18)
TRANSMIT K28.5
AS CODE GROUP 1
WAIT FOR NEXT
FRAME CLOCK
TRANSMIT K28.5
AS CODE GROUP 2
TRANSMIT K28.5
AS CODE GROUP 1
TRANSMIT D5.6
AS CODE GROUP 2
TRANSMIT K28.5
AS CODE GROUP 1
TRANSMIT D16.2
AS CODE GROUP 2
NO YES
NO YES
NO
(DISPARITY NOT OK)
(NEGATIVE DISPARITY)
(NEGATIVE DISPARITY)
(DISPARITY IS OK)
(POSITIVE DISPARITY)
(NEGATIVE DISPARITY)
2274 F15
YES
APPLICATIONS INFORMATION
Figure 15. Initial Synchronization Flow Diagram
Scrambling
To avoid spectral interference from the serial data output,
an optional data scrambler is added between the ADC
data and the 8B/10B encoder to randomize the spectrum
of the serial link. The scrambler is enabled by setting the
SCRAM pin to a high logic level. The polynomial used for
the scrambler is 1 + x14 + x15, which is a pseudo-random
pattern repeating itself every 215–1. Figure 16 illustrates
the LTC2274 implementation of this polynomial in parallel
form.
The scrambled data is converted into two valid 8B/10B
code groups, constituting a complete frame. The 8B/10B
code groups are then serialized and transmitted.
The receiver is required to deserialize the data, decode
the code-groups into octets and descramble them back
to the original octets using the self-aligning descrambler
shown in Figure 17. This descrambler is shown in 16-bit
parallel form, which is an effi cient implementation of the
(1 + x14 + x15) polynomial, operating at the frame clock
rate (ADC sample rate).
LTC2274
27
2274fb
APPLICATIONS INFORMATION
Figure 16. LTC2274 16-Bit 1 + x14 + x15 Parallel Scrambler
SS0
SAMPLE_CLK
D0
SECOND
OCTET
FROM
ADC
TO 8B/10B
ENCODER
FIRST
OCTET
SECOND
SCRAMBLED
OCTET
FIRST
SCRAMBLED
OCTET
SS1D1
D2
QD
C
FF
SS2
D3 SS3
SS4D4
SS5D5
D6 SS6
D7 SS7
SF0D8
SF1D9
D10 SF2
D11 SF3
SF4D12
SF5D13
D13 SF6
D15
MSB
SF7
MSB
QD
C
FF
QD
C
FF
QD
C
FF
QD
C
FF
QD
C
FF
QD
C
FF
QD
C
FF
QD
C
FF
QD
C
FF
QD
C
FF
QD
C
FF
QD
C
FF
QD
C
FF
QD
C
FF
2274 F16
LTC2274
28
2274fb
APPLICATIONS INFORMATION
Figure 17. Required 16-Bit 1 + x14 + x15 Parallel Descrambler
FRAME_CLK
LSB
D0
SS0
DQ
CFF
D1
SS1
DQ
CFF
D2
SS2
DQ
CFF
D3
SS3
DQ
CFF
D4
SS4
DQ
CFF
D5
SS5
DQ
CFF
D6
SS6
DQ
CFF
D7
SS7
DQ
CFF
D8
SF0
DQ
CFF
D9
SF1
DQ
CFF
D10
SF2
DQ
CFF
D11
SF3
DQ
CFF
D12
SF4
DQ
CFF
D13
SF5
DQ
CFF
D14
SF6
SF7
MSB
DQ
CFF
D15
MSB
SECOND
SCRAMBLED
OCTET
FROM
8B/10B
DECODER
DESCRAMBLED
ADC DATA
FIRST
SCRAMBLED
OCTET
2274 F17
LTC2274
29
2274fb
APPLICATIONS INFORMATION
Frame Alignment Monitoring
After the initial synchronization has been established, it may
be desirable to periodically verify that frame alignment is
being maintained. The receiver may issue a synchroniza-
tion request at any time, but data will be lost during the
resynchronization interval.
To verify frame alignment without the loss of data, frame
alignment monitoring is enabled by setting the FAM pin
to a high level. In this mode, predetermined data in the
second code group of the frame is substituted with the
control character K28.7. The receiver is required to detect
the K28.7 character and replace it with the original data. In
this way, the second code group may be discerned from
the fi rst, and the receiver is able to periodically verify the
frame alignment without the loss of data (refer to Table 1
and the fl ow diagram of Figure 18). There are two frame
alignment monitoring modes summarized in Table 1.
FAM mode 1 is implemented when FAM is high, and
SCRAM is low:
• When the data in the second code group of the current
frame equals the data in the second code group of the
previous frame, the LTC2274 will replace the second
code group with the control character K28.7 before
serialization. However, if a K28.7 symbol was already
transmitted in the previous frame, the actual code group
will be transmitted.
• Upon receiving a K28.7 symbol, the receiver is required
to replace it with the data decoded at the same position
of the previous frame.
FAM mode 2 is implemented when FAM is high and
SCRAM is high:
• When the data in the second code group of the current
frame equals D28.7, the LTC2274 will replace this data
with K28.7 before serialization.
• Upon receiving a K28.7 symbol, the receiver is required
to replace it with D28.7.
With FAM enabled the receiver is required to search for
the presence of K28.7 symbols in the data stream. If two
successive K28.7 symbols are detected at the same posi-
tion other than the assumed end of frame, the receiver will
realign its frame boundary to the new position.
Table 1. Frame Alignment Monitoring Modes
SCRAM PIN DDSYNC PIN ACTION
FAM Mode 1 Low High The second code group is replaced with K28.7 if
it is equal to the 2nd Code Group of the previous
frame
FAM Mode 2 High High The second code group is replaced with K28.7 if
it is equal to D28.7
FAM OFF X Low No K28.7 substitutions will take place
LTC2274
30
2274fb
APPLICATIONS INFORMATION
Table 2. Sample Rate Ranges
SRR1 SRR0 SAMPLE RATE RANGE
0 x 20Msps < FS ≤ 35Msps
1 0 30Msps < FS ≤ 65Msps
1 1 60Msps < FS ≤ 105Msps
Figure 18. Data Transmission Flow Diagram
PLL Operation
The PLL has been designed to accommodate a wide range
of sample rates. The SRR0 and SRR1 pins are used to
confi gure the PLL for the intended sample rate range.
Table 2 summarizes the sample clock ranges available
to the user.
Serial Test Patterns
To facilitate testing of the serial interface, three test patterns
are selectable via pins PAT0 and PAT1. The available test
patterns are described in Table 3. A K28.5 comma may be
used as a fourth test pattern by requesting synchronization
through the SYNC+/SYNC– pins.
IS FAM
ENABLED?
IS SCRAM
ENABLED?
IS CODE
GROUP 2 =
D28.7?
TRANSMIT
CODE GROUP 1
TRANSMIT
CODE GROUP 2
TRANSMIT
CODE GROUP 2
TRANSMIT K28.7
AS CODE GROUP 2
NO YES (FRAME ALIGNMENT MONITORING IS ENABLED)
(DATA SCRAMBLING IS ENABLED)NO YES
NO YES
IS CODE
GROUP 2 =
CODE GROUP 2
OF LAST
FRAME?
TRANSMIT
CODE GROUP 2
NO YES
WAS K28.7
TRANSMITTED
IN LAST
FRAME?
TRANSMIT K28.7
AS CODE GROUP 2
TRANSMIT
CODE GROUP 2
NO YES
2274 F18
TRANSMIT
CODE GROUP 1
GENERATE 8B/10B
CODE-GROUPS 1 AND 2
START
SCRAMBLE ADC DATA
IF SCRAM IS ENABLED
END
Table 3. Test Patterns
PAT1 PAT0 TEST PATTERNS
0 0 ADC Data
0 1 1010101010 Pattern
(8B/10B Code Group D21.5)
1 0 1+ x9 + x11 Pseudo Random Pattern
1 1 1+ x14 + x15 Pseudo Random Pattern
LTC2274
31
2274fb
APPLICATIONS INFORMATION
High Speed CML Outputs
The CML outputs must be terminated for proper opera-
tion. The OVDD supply voltage and the termination voltage
determine the common mode output level of the CML
outputs. For proper operation of the CML driver, the output
common mode voltage should be greater than 1V.
The directly-coupled termination mode of Figure 19a is
recommended when the receiver termination voltage is
within the range of 1.2V to 3.3V. When the CML outputs
are directly-coupled to the 50Ω termination resistors, the
OVDD supply voltage serves as the receiver termination
voltage, and the output common mode voltage will be
approximately 200mV lower than OVDD.
The directly-coupled differential termination of Figure 19b
may be used in the absence of a receiver termination voltage
within the required range. In this case, the common mode
voltage is shifted down to approximately 400mV below
OVDD, requiring an OVDD in the range of 1.4V to 3.3V.
If the serial receiver’s common mode input requirements
are not compatible with the directly-coupled termination
modes, the DC balanced 8B/10B encoded data will permit
the addition of DC blocking capacitors as shown in Figure
19c. In this AC-coupled mode, the termination voltage is
determined by the receiver’s requirements. The coupling
capacitors should be selected appropriately for the intended
operating bit-rate, usually between 1nF to 10nF. In the AC-
coupled mode, the output common mode voltage will be
approximately 400mV below OVDD, so the OVDD supply
voltage should be in the range of 1.4V to 3.3V.
Grounding and Bypassing
The LTC2274 require a printed circuit board with a
clean unbroken ground plane; a multilayer board with an
internal ground plane is recommended. The pinout of the
LTC2274 has been optimized for a fl owthrough layout so
that the interaction between inputs and digital outputs is
minimized. Layout for the printed circuit board should
ensure that digital and analog signal lines are separated as
much as possible. In particular, care should be taken not
to run any digital track alongside an analog signal track
or underneath the ADC.
High quality ceramic bypass capacitors should be used
at the VDD, VCM, and OVDD pins. Bypass capacitors must
be located as close to the pins as possible. The traces
connecting the pins and bypass capacitors must be kept
short and should be made as wide as possible.
The LTC2274 differential inputs should run parallel and
close to each other. The input traces should be as short
as possible to minimize capacitance and to minimize
noise pickup.
Heat Transfer
Most of the heat generated by the LTC2274 is transferred
from the die through the bottom-side exposed pad. For
good electrical and thermal performance, the exposed
pad must be soldered to a large grounded pad on the PC
board. It is critical that the exposed pad and all ground
pins are connected to a ground plane of suffi cient area
with as many vias as possible.
LTC2274
32
2274fb
APPLICATIONS INFORMATION
Figure 19a. CML Termination, Directly-Coupled Mode (Preferred)
Figure 19b. CML Termination, Directly-Coupled Differential Mode
2274 F19a
50Ω50Ω50Ω 50Ω
DATA+
DATA–
GND
SERIAL CML DRIVER SERIAL CML RECEIVER
1.2V TO 3.3V
50Ω
TRANSMISSION LINE
50Ω
TRANSMISSION LINE
16mA
CMLOUT+
OVDD
CMLOUT–
2274 F19b
100Ω
50Ω 50Ω
DATA+
DATA–
GND
SERIAL CML DRIVER SERIAL CML RECEIVER
1.4V TO 3.3V
50Ω
TRANSMISSION LINE
50Ω
TRANSMISSION LINE
16mA
CMLOUT+
OVDD
CMLOUT–
LTC2274
33
2274fb
APPLICATIONS INFORMATION
Figure 19c. CML Termination, AC-Coupled Mode
2274 F19c
50Ω50Ω
0.01μF
0.01μF
50Ω 50Ω
DATA+
DATA–
GND
SERIAL CML DRIVER SERIAL CML RECEIVER
1.4V TO 3.3V VTERM
50Ω
TRANSMISSION LINE
50Ω
TRANSMISSION LINE
16mA
CMLOUT+
OVDD
CMLOUT–
LTC2274
34
2274fb
TYPICAL APPLICATIONS
Silkscreen Top
Top Side
LTC2274
35
2274fb
TYPICAL APPLICATIONS
Inner Layer 2
Inner Layer 3
LTC2274
36
2274fb
TYPICAL APPLICATIONS
Inner Layer 4
Inner Layer 5
LTC2274
37
2274fb
TYPICAL APPLICATIONS
Bottom Side
Silkscreen Bottom
LTC2274
38
2274fb
TYPICAL APPLICATIONS
CML ADC
ASSEMBLY TYPE U1 U3 DATA RATE SAMPLE RATE C1 C2, C3 L1 R5, R19 T3 INPUT FREQUENCY
DC1151A-C LTC2274CU TLK2501 1.5GHz TO 2.5GHz 105Msps 4.7pF 8.2pF 56nH 86.6Ω MABA-007159 1MHz TO 70MHz
DC1151A-D LTC2274CU TLK2501 1.5GHz TO 2.5GHz 105Msps 1.8pF 3.9pF 18nH 43.2Ω WBC1-1LB 70MHz TO 140MHz
DC1151A-E LTC2273CU TLK2501 1.5GHz TO 2.5GHz 80Msps 4.7pF 8.2pF 56nH 86.6Ω MABA-007159 1MHz TO 70MHz
DC1151A-F LTC2273CU TLK2501 1.5GHz TO 2.5GHz 80Msps 1.8pF 3.9pF 18nH 43.2Ω WBC1-1LB 70MHz TO 140MHz
DC1151A-G LTC2272CU TLK1501 0.6GHz TO 1.5GHz 65Msps 4.7pF 8.2pF 56nH 86.6Ω MABA-007159 1MHz TO 70MHz
DC1151A-H LTC2272CU TLK1501 0.6GHz TO 1.5GHz 65Msps 1.8pF 3.9pF 18nH 43.2Ω WBC1-1LB 70MHz TO 140MHz
J8
CLKOUT
2274 TA02
U1
LTC2274CUJ
GND
GND
GND
GND
GND
GND
GND
GND
OGND
OGND
OGND
OGND
GND
TP3
EXT REF
FAMON
1
3
31
SCRAM 34
MSBINV 36
PAT1 33
PAT0 32
DITH 15
ISMODE 16
PLL0 17
PLL1 18
PDADC 19
PDSER
FAM
SCRAM
MSBINV
PAT1
PAT0
DITH
ISMODE
PLL0
PLL1
PDADC
PDSER
20
ENC–
10
ENC+
9
SENSE
38
VCM
39
PGA
VCM
PGA 35
AIN–
5
AIN+
4
1
2
3
5
4SYNC+28
SYNC–29
CMLOUT–23
CMLOUT+24
2
6
12
7
13
811143740
22
21
VDD
VDD
VDD
VDD
OVDD
OVDD
3.3V
3.3V 2.5V
OVDD
25
26 27 30
GND
41
C13
0.1μF
C26
0.1μF
L4
FERRITE BEAD
BLM1866470SN1D
C12
0.1μF
C14
0.01μF
C26A
1nF
C27A
1nF
C32
0.01μF
C15
0.01μF
R1
10Ω
R18
1000Ω
L1*
R2
10Ω
R16
10Ω
T3*
T1
MABAES0060
T2
MABA-007159-000000
R17
10Ω
R15
OPTIONAL
C1*
R6
100Ω
R3
68.1Ω
R4
68.1Ω
1
2
3
5
4
C16
202μF
C20
0.01μF
C6
0.1μF
3
2
1
4
5
R9
4.99Ω
R10
4.99Ω
C8
8.2pF
R7
4.99Ω
R8
4.99Ω
C11
0.1μF
C4
0.1μF
R11
100Ω
••••
•
•
C9
0.1μF
C10
0.1μF
R51
68.1Ω
R52
68.1Ω
R19*
C3* C2*
R5*
J2
SIG IN
J5
ENCODE
C5
0.1μF
R34
34Ω
SUM
SBTC-2-10L+
PORT1
NC PORT2
GND
GND
3
1
42
2
3.3V
3.3V
2.5V
VDD
SENSE
R55
OPTIONAL
R56
0Ω
TP4
GND
5
6
4
3
12
GND
NC7SVU04P5X
NC7SP17P5X
SW1
MAIN
SYNC
EVQPPDA25
VCC
35
R35
49.9Ω
R33
10k
R32
10k
C30
0.1μF
IN
LT1763CDE
OUT
IN
BYP
11
SHDN
8
NC
1
NC
4
NC
9
NC
12
10
6
2
OUT 3
SENSE 5
713
R36
10k
R22
1000Ω
R31
4.32k
C18
10μF
0805
C17
4.7μF
0805
C19
0.01μF
IN
LT1763CDE-2.5
OUT
IN
BYP
GND
GP
GND
GP
11
SHDN
8
NC
1
NC
4
NC
9
NC
12
10
6
2
OUT 3
SENSE 5
713
R11
10k
C33
10μF
0805
2.5V
OVDD
OVDD
C34
0.01μF
L3
FERRITE BEAD
BLM1866470SN1D ADC
3.3V
3.3V
EX_3.3V
TP1
EX_3.3V
TP2
GND
*U3
TX_EN
51
20
LOOPEN 21
TX_ER 22
VDD 23
ENABLE 24
LCKREFN 25
PRBSEN 26
TESTEN 27
GND 28
RX_ER/PRBS_PASS 29
RX_DV/LOS 30
DINRXP
54
DINRXN
53
GNDA
52
RXD0
50
RXD1
49
RXD2
48
VDD
47
RXD3
46
RXD4
45
RXD5
44
RXD6
43
GND
42
RXD7
41
RX_CLK
40
RXD8
39
RXD9
38
VDD
37
RXD10
36
RXD11
35
RXD12
34
RXD13
33
GND
32
RXD14
31
RXD15
PBUS0
PBUS1
PBUS2
PBUS3
PBUS4
PBUS5
PBUS6
PBUS7
PBUS8
PBUS9
PBUS10
PBUS11
PBUS12
PBUS13
PBUS14
PBUS15
R23B
33Ω
R23C
33Ω
R24A
33Ω
R24B
33Ω
R24C
33Ω
R24D
33Ω
R23D
33Ω
R25A
33Ω
R25B
33Ω
R25C
33Ω
R25D
33Ω
R26A
33Ω
R26B
33Ω
R27C
33Ω
R27D
33Ω
R26C
33Ω
R26D
33Ω
C36
0.01μF
VDDA
57
RREF
56
VDDA
55
DOUTTXP
60
DOUTTXN
59
GNDA
58
GNDA
61
J7
CMLOUT+
C26B
1nF
C27B
1nF
J6
CMLOUT–
R20
200Ω
R12
49.9k
R13
49.9k
R21
825Ω
C21
0.01μF
C22
0.01μF
TXD0
62
TXD1
63
TXD2
64
VDD
1
TXD3
2
TXD4
3
TXD5
4
GND
5
TXD6
6
TXD7
7
GTX_CLK
8
VDD
9
TXD8
10
TXD9
11
TXD10
12
GND
13
TXD11
14
TXD12
15
TXD13
16
TXD14
17
GND
18
TXD15
19
DITH
1
OFF
ISMODE
2
PLL0
3
PLL1
4
8765
PDADC
1
OFF
PDSER
2
FAM
3
SCRAM
4
8765
PAT0
1
OFF
S2 S3 S4
PAT1
2
PGA
3
MSBINV
4
8765
L2
FERRITE BEAD
BLM1866470SN1D
C23
0.01μF
C25
0.01μF
C24
0.01μF
D2
DATA GOOD
JP2
RUN
SHDN
R44
1k
R14
33.2Ω
3.3V
INT_SYNC
SYNC
OPTIONAL
C
NC7SZ332PSX
A
YB
4
6
3
VCC GND
52
1
C28
0.01μF
42
R32
10Ω
C25
0.01μF
R43
10k
R46
10k
R28
825Ω
R29
825Ω
D1
SYNC ERR
C37
0.01μF
2.5V
1
3
2
PFC8574TS
A0 6
A1 7
A2 9
SCL 2
SDA
SCL
SDA
3.3V
4
INT 1
NC
3
NC
8
NC
13
NC
18
VSS
15
PAT0
20
PAT1
19
PGA
17
MSBINV
16
PDADC
14
PDSER
12
FAM
11
SCRAM
10
P7
P6
P5
P4
P3
P2
P1
P0
VDD
5
PFC8574TS
A0 6
A1 7
A2 9
SCL 2
SDA
SCL
SDA
3.3V
3.3V
4
INT 1
NC
3
NC
8
NC
13
NC
18
VSS
15
20 19 17
RX_ER
16
PLL1
14
PLL0
12
ISMODE
11
DITH
10
P7
P6
P5
P4
P3
P2
P1
P0
VDD
5
3.3V
HEADER
OPTIONAL
12
10
14
8
6
4
2
PAT1
PAT0
PGA
SCRAM
FAM
PDSER
PDADC
SYNC
INT_SYNC
MSBINV
DITH
ISMODE
PLL0
PLL1
11
9
13
7
5
3
1
R53
1k
R54
OPTIONAL
21
19
17
15
13
11
9
7
5
3
1
41
39
37
35
33
31
29
27
25
23
61
59
57
55
53
51
49
47
45
43
81
79
77
75
73
71
69
67
65
63
99
97
95
93
91
89
87
85
83
22
20
18
16
14
12
10
8
6
4
2
42
40
38
36
34
32
30
28
26
24
62
60
58
56
54
52
50
48
46
44
82
80
78
76
74
72
70
68
66
64
100
PBUS8
98
96
94
92
90
88
86
PBUS5
PBUS6
PBUS7
PBUS14
RX_ER
PBUS15
PBUS0
PBUS1
PBUS2
PBUS3
PBUS4
PBUS9
PBUS10
PBUS11
PBUS12
PBUS13
84
2.5V
R47
OPTIONAL
R45
10k
NC7WB66K8X
1B
2B
GND VCC
1A
1
OE1
7
2A
5
OE2
36
2
SDA
SCL
4
8
R48
OPTIONAL
R49
OPTIONAL
R39
1000Ω
R50
OPTIONAL
3.3V
2.5V
3.3V
24LC025-I/ST WP
A0
VSS VCC
A2
A1 1
4
8
SDA
SCL
SDASCL
7
3
2
5
6
24LC32A-I/ST WP
A0
VSS VCC
A2
A1 1
4
8
SDA
SCL
WP
SDA
SCL
7
3
2
5
6
WP
C35
0.01μF
R37
4750Ω
R38
4750Ω
R40
4750Ω
82pF
*VERSION TABLE
LTC2274
39
2274fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
PACKAGE DESCRIPTION
UJ Package
40-Lead Plastic QFN (6mm × 6mm)
(Reference LTC DWG # 05-08-1728 Rev Ø)
6.00 p 0.10
(4 SIDES)
NOTE:
1. DRAWING IS A JEDEC PACKAGE OUTLINE VARIATION OF (WJJD-2)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
PIN 1 TOP MARK
(SEE NOTE 6)
PIN 1 NOTCH
R = 0.45 OR
0.35 s 45o
CHAMFER
0.40 p 0.10
4039
1
2
BOTTOM VIEW—EXPOSED PAD
4.50 REF
(4-SIDES)
4.42 p0.10
4.42 p0.10
4.42 p0.05
4.42 p0.05
0.75 p 0.05 R = 0.115
TYP
0.25 p 0.05
0.50 BSC
0.200 REF
0.00 – 0.05
(UJ40) QFN REV Ø 0406
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.70 p0.05
4.50 p0.05
(4 SIDES)
5.10 p0.05
6.50 p0.05
0.25 p0.05
0.50 BSC
PACKAGE OUTLINE
R = 0.10
TYP
LTC2274
40
2274fb
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2008
LT 0609 REV B • PRINTED IN USA
RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
LTC1993-2 High Speed Differential Op Amp 800MHz BW, 70dBc Distortion at 70MHz, 6dB Gain
LTC1994 Low Noise, Low Distortion Fully Differential Input/
Output Amplifi er/Driver Low Distortion: –94dBc at 1MHz
LTC2215 16-Bit, 65Msps, Low Noise ADC 700mW, 81.5dB SNR, 100dB SFDR, 64-Pin QFN
LTC2216 16-Bit, 80Msps, Low Noise ADC 970mW, 81.3dB SNR, 100dB SFDR, 64-Pin QFN
LTC2217 16-Bit, 105Msps, Low Noise ADC 1190mW, 81.2dB SNR, 100dB SFDR, 64-Pin QFN
LTC2202 16-Bit, 10Msps, 3.3V ADC, Lowest Noise 140mW, 81.6dB SNR, 100dB SFDR, 48-Pin QFN
LTC2203 16-Bit, 25Msps, 3.3V ADC, Lowest Noise 220mW, 81.6dB SNR, 100dB SFDR, 48-Pin QFN
LTC2204 16-Bit, 40Msps, 3.3V ADC 480mW, 79dB SNR, 100dB SFDR, 48-Pin QFN
LTC2205 16-Bit, 65Msps, 3.3V ADC 590mW, 79dB SNR, 100dB SFDR, 48-Pin QFN
LTC2206 16-Bit, 80Msps, 3.3V ADC 725mW, 77.9dB SNR, 100dB SFDR, 48-Pin QFN
LTC2207 16-Bit, 105Msps, 3.3V ADC 900mW, 77.9dB SNR, 100dB SFDR, 48-Pin QFN
LTC2208 16-Bit, 130Msps, 3.3V ADC, LVDS Outputs 1250mW, 77.7dB SNR, 100dB SFDR, 64-Pin QFN
LTC2209 16-Bit, 160Msps, ADC, LVDS Outputs 1.45W, 77.1dB SNR, 100dB SFDR, 64-Pin QFN
LTC2220 12-Bit, 170Msps ADC 890mW, 67.5dB SNR, 9mm × 9mm QFN Package
LTC2220-1 12-Bit, 185Msps, 3.3V ADC, LVDS Outputs 910mW, 67.7dB SNR, 80dB SFDR, 64-Pin QFN
LTC2224 12-Bit, 135Msps, 3.3V ADC, High IF Sampling 630mW, 67.6dB SNR, 84dB SFDR, 48-Pin QFN
LTC2249 14-Bit, 80Msps ADC 230mW, 73dB SNR, 5mm × 5mm QFN Package
LTC2250 10-Bit, 105Msps ADC 320mW, 61.6dB SNR, 5mm × 5mm QFN Package
LTC2251 10-Bit, 125Msps ADC 395mW, 61.6dB SNR, 5mm × 5mm QFN Package
LTC2252 12-Bit, 105Msps ADC 320mW, 70.2dB SNR, 5mm × 5mm QFN Package
LTC2253 12-Bit, 125Msps ADC 395mW, 70.2dB SNR, 5mm × 5mm QFN Package
LTC2254 14-Bit, 105Msps ADC 320mW, 72.5dB SNR, 5mm × 5mm QFN Package
LTC2255 14-Bit, 125Msps, 3V ADC, Lowest Power 395mW, 72.5dB SNR, 88dB SFDR, 32-Pin QFN
LTC2284 14-Bit, Dual, 105Msps, 3V ADC, Low Crosstalk 540mW, 72.4dB SNR, 88dB SFDR, 64-Pin QFN
LTC2299 Dual 14-Bit, 80Msps ADC 230mW, 71.6dB SNR, 5mm x 5mm QFN Package
LTC5512 DC-3GHz High Signal Level
Downconverting Mixer DC to 3GHz, 21dBm IIP3, Integrated LO Buffer
LTC5515 1.5 GHz to 2.5GHz Direct Conversion Quadrature
Demodulator High IIP3: 20dBm at 1.9GHz, Integrated LO Quadrature Generator
LTC5516 800MHz to 1.5GHz Direct Conversion Quadrature
Demodulator High IIP3: 21.5dBm at 900MHz, Integrated LO Quadrature Generator
LTC5517 40MHz to 900MHz Direct Conversion Quadrature
Demodulator High IIP3: 21dBm at 800MHz, Integrated LO Quadrature Generator
LTC5522 600MHz to 2.7GHz High Linearity Downconverting
Mixer 4.5V to 5.25V Supply, 25dBm IIP3 at 900MHz,
NF = 12.5dB, 50Ω Single-Ended RF and LO Ports
LTC5527 400MHz to 3.7GHz High Signal Level
Downconverting Mixer 4.5V to 5.25V Supply, 23.5dBm IIP3 at 1900MHz, ICC = 78mA,
Conversion Gain = 2dB
LTC5579 1.5GHz to 3.8GHz High Linearity Upconverting
Mixer 3.3V Supply, 27.3dBm OIP3 at 2.14GHz, Conversion Gain = 2.6dB at 2.14GHz
LTC6400-20 1.8GHz Low Noise, Low Distortion Differential ADC
Driver for 300MHz IF Fixed Gain 10V/V, 2.1nV√Hz Total Input Noise, 3mm × 3mm QFN-16 Package
