CY7C199CN
256 K (32 K × 8) Static RAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document #: 001-06435 Rev. *F Revised May 4, 2011
Features
■Fast access time: 15 ns and 20 ns
■Wide voltage range: 5.0V ± 10% (4.5V to 5.5V)
■complementary metal oxide semiconductor (CMOS) for
optimum speed and power
■Transistor transistor logic (TTL) compatible inputs and outputs
■2.0 V data retention
■Low CMOS standby power
■Automated power down when deselected
■Available in Pb-free 28-pin Thin Small Outline Package (TSOP)
I, 28-pin Molded Small Outline J-Lead (SOJ) and 28-pin DIP
packages
General Description [1]
The CY7C199CN is a high performance CMOS Asynchronous
SRAM organized as 32K by 8 bits that supports an asynchronous
memory interface. The device features an automatic power
down feature that reduces power consumption when deselected.
See the “Truth Table” on page 4 in this data sheet for a complete
description of read and write modes.
The CY7C199CN is available in Pb-free 28-pin TSOP I, 28-pin
Molded SOJ and 28-pin DIP package(s).
Logic Block Diagram
Product Portfolio
–15 –20 Unit
Maximum access time 15 20 ns
Maximum operating current 80 75 mA
Maximum CMOS standby current (low power) 500 500 A
Row Decoder
RAM Array
Column Decoder
Input Buffer
Sense Amps
AX
Power
Down
Circuit
I/Ox
OE
WE
CE
X
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CY7C199CN
Document #: 001-06435 Rev. *F Page 2 of 18
Contents
Pin Layout and Specifications ........................................ 3
Pin Description ................................................................. 4
Truth Table ........................................................................ 4
Maximum Ratings .............................................................4
Operating Range ............................................................... 4
Capacitance ........................................................................................ 5
Thermal Resistance ........................................................................ 5
DC Electrical Characteristics ..........................................5
AC Test Loads ..................................................................6
AC Test Conditions ..........................................................6
AC Electrical Characteristics ..................................................... 7
Data Retention Characteristics ................................................. 7
Timing Waveforms ........................................................... 8
Data Retention Waveform ...........................................8
Read Cycle 1 ............................................................... 8
Read Cycle 2 ............................................................... 9
Write Cycle 1 (WE controlled) ..............................................10
Write Cycle 2 (CE controlled) ...............................................11
Write Cycle 3 (WE controlled, OE low) .............................12
Ordering Information ...................................................... 13
Ordering Code Definitions ......................................... 13
Package Diagrams .......................................................... 14
Acronyms ........................................................................ 17
Document Conventions ................................................. 17
Units of Measure ....................................................... 17
Document History Page ................................................. 18
Sales, Solutions, and Legal Information ...................... 18
Worldwide Sales and Design Support ....................... 18
Products .................................................................... 18
PSoC Solutions ......................................................... 18
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Document #: 001-06435 Rev. *F Page 3 of 18
Pin Layout and Specifications
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
IO0
IO1
IO2
VSS IO3
IO4
IO5
IO6
IO7
CE
A0
OE
A1
A2
A3
A4
WE
VCC 1
2
3
4
5
6
7
8
9
10
11
12
13
14 15
16
17
18
19
20
21
22
23
24
25
26
27
28
28 DIP
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
IO0
IO1
IO2
VSS IO3
IO4
IO5
IO6
IO7
CE
A0
OE
A1
A2
A3
A4
WE
V CC 1
2
3
4
5
6
7
8
9
10
11
12
13
14 15
16
17
18
19
20
21
22
23
24
25
26
27
28
28 SOJ
OE
A1
A2
A3
A4
WE
VCC
A5
A6
A7
A8
A9
A10
A11 A12
A13
A14
IO0
IO1
IO2
VSS
IO3
IO4
IO5
IO6
IO7
CE
A0
1
2
3
4
5
6
7
8
9
10
11
12
13
14 15
16
17
18
19
20
21
22
23
24
25
26
27
28
28 TSOP I (8 x 13.4 mm)
Note
1. For best practices recommendations, refer to the Cypress application note System Design Guidelines on www.cypress.com.
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Document #: 001-06435 Rev. *F Page 4 of 18
Pin Description
Pin Type Description DIP SOJ TSOP I
AXInput Address inputs 1, 2, 3, 4, 5, 6, 7, 8, 9,
10, 21, 23, 24, 25, 26
1, 2, 3, 4, 5, 6, 7, 8, 9, 10,
21, 23, 24, 25, 26
2, 3, 4, 5, 8, 9, 10, 11, 12,
13, 14, 15, 16, 17, 28
CE Control Chip rnable 20 20 27
IOXInput or Output Data input outputs 11, 12, 13, 15, 16, 17,
18, 19
11, 12, 13, 15, 16, 17, 18,
19
18, 19, 20, 22, 23, 24, 25, 26
OE Control Output rnable 22 22 1
VCC Supply Power (5.0V) 28 28 7
VSS Supply Ground 14 14 21
WE Control Write enable 27 27 6
Truth Table
CE OE WE IOx Mode Power
H X X High-Z Deselect/Power down Stand by (ISB)
L L H Data Out Read Active (ICC)
L X L Data In Write Active (ICC)
L H H High-Z Selected, Outputs disabled Active (ICC)
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested.
Parameter Description Value Unit
TSTG Storage temperature –65 to +150 °C
TAMB Ambient temperature with power applied (that is, case temperature) –55 to +125 °C
VCC Core Supply voltage relative to VSS –0.5 to +7.0 V
VIN, VOUT DC voltage applied to any pin relative to VSS –0.5 to VCC + 0.5 V
IOUT Output short-circuit current 20 mA
VESD Static discharge voltage (in accordance with MIL-STD-883, Method 3015) > 2001 V
ILU Latch-up current > 200 mA
Operating Range
Range Ambient Temperature (TA)Voltage Range (VCC)
Commercial 0 °C to 70 °C 5.0 V ± 10%
Industrial –40 °C to 85 °C 5.0 V ± 10%
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DC Electrical Characteristics
Over the Operating Range (–15, –20) [2]
Parameter Description Condition
–15 –20
Unit
Min Max Min Max
VIH Input HIGH voltage 2.2 VCC + 0.3 2.2 VCC + 0.3 V
VIL Input LOW voltage –0.5 0.8 –0.5 0.8 V
VOH Output HIGH voltage VCC = Min, IOH = –4.0 mA 2.4 –2.4 – V
VOL Output LOW voltage VCC = Min, IOL = 8.0 mA –0.4 –0.4 V
ICC VCC Operating supply
current
VCC = Max, IOUT = 0 mA,
f = Fmax = 1/tRC
–80 –75 mA
ISB1 Automatic CE power
down current TTL
inputs
Max VCC, CE VIH,
VIN VIH or VIN VIL, f = Fmax
–30 –30 mA
L – 10 –10 mA
ISB2 Automatic CE Power
down current CMOS
Inputs
Max VCC, CE VCC – 0.3 V,
VIN VCC – 0.3 V, or VIN 0.3 V, f = 0
–10 –10 mA
L – 500 –500 A
IOZ Output leakage current GND VI VCC, output disabled –5 +5 –5 +5 A
IIX Input leakage current GND VI VCC –5 +5 –5 +5 A
Capacitance [3]
Parameter Description Conditions Max Unit
CIN Input capacitance TA = 25°C, f = 1 MHz, VCC = 5.0 V 8pF
COUT Output capacitance 8
Thermal Resistance [3]
Parameter Description Conditions TSOP I SOJ DIP Unit
JA Thermal resistance
(junction to ambient)
Still air, soldered on a 3 × 4.5
square inch, two–layer printed
circuit board
88.6 79 69.33 °C/W
JC Thermal resistance
(junction to case)
21.94 41.42 31.62
Note
2. VIL (min) = –2.0 V for pulse durations of less than 20 ns.
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Document #: 001-06435 Rev. *F Page 6 of 18
AC Test Loads
AC Test Conditions
Parameter Description Nom Unit
C1 Capacitor 1 30 pF
C2 Capacitor 2 5
R1 Resistor 1 480
R2 Resistor 2 255
R3 Resistor 3 480
R4 Resistor 4 255
RTH Resistor Thevenin 167
VTH Voltage Thevenin 1.73 V
VCC
VSS
Rise Time
1 V/ns
Fall Time
1 V/ns
All Input P ulses
90%
10%
90%
10%
V
Output
R1
R2C1
CC V
Output
R3
C2
CC
R4
Output Loads Output Loads
for tHZOE,t
HZCE
&t
HZWE
* including scope and jig capacitance
(B)*
(A)*
Rth
T
V
Thevenin Equivalent
Note
3. Tested initially and after any design or process change that may affect these parameters.
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Document #: 001-06435 Rev. *F Page 7 of 18
AC Electrical Characteristics [4]
Parameter Description
–15 –20
Unit
Min Max Min Max
tRC Read cycle time 15 –20 –ns
tAA Address to data valid –15 –20 ns
tOHA Data hold from address change 3–3–ns
tACE CE to data valid –15 –20 ns
tDOE OE to data valid –7–9ns
tLZOE OE to Low-Z [5] 0–0–ns
tHZOE OE to High-Z [5, 6] –7–9ns
tLZCE CE to Low-Z [5] 3–3–ns
tHZCE CE to High-Z [5, 6] –7–9ns
tPU CE to Power Up 0–0–ns
tPD CE to Power Down –15 –20 ns
tWC Write Cycle Time [7] 15 –20 –ns
tSCE CE to write end 10 –15 –ns
tAW Address setup to write end 10 –15 –ns
tHA Address hold from write end 0–0–ns
tSA Address setup to write start 0–0–ns
tPWE WE pulse width 9 – 15 –ns
tSD Data setup to write end 9 – 10 –ns
tHD Data hold from write end 0–0–ns
tHZWE WE LOW to High-Z [5, 6] –7–10 ns
tLZWE WE HIGH to Low-Z [5] 3–3–ns
Data Retention Characteristics [8]
Parameter Description Condition Min Max Unit
VDR VCC for data retention 2.0 – V
ICCDR Data retention current VCC = VDR = 2.0 V, CE VCC – 0.3 V,
VIN VCC – 0.3 V or VIN 0.3 V
–150 A
tCDR Chip deselect to data
retention time
0 – ns
tROperation recovery time 200 –s
Notes
4. Test Conditions are based on a transition time of 3 ns or less and timing reference levels of 1.5 V, and input pulse levels of 0 to 3.0 V.
5. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
6. tHZOE, tHZCE, tHZWE are specified as in part (b) of the “” on page 5. Transitions are measured ± 200 mV from steady state voltage.
7. The internal memory write time is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of these
signals can terminate the write. The input data setup and hold timing must be referenced to the leading edge of the signal that terminates the write.
8. L-version only.
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Document #: 001-06435 Rev. *F Page 8 of 18
Timing Waveforms
Data Retention Waveform
Figure 1. Read Cycle 1 [9, 10]
Notes
9. Device is continuously selected. OE = VIL = CE.
10. WE is HIGH for read cycle.
CE
DATA RETENTION MODE
tCDR tR
VCC
Address
Data Out Previous Data Valid Data Valid
tRC
tAA
tOHA
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Document #: 001-06435 Rev. *F Page 9 of 18
Figure 2. Read Cycle 2 [11, 12]
Timing Waveforms (continued)
Notes
11. This cycle is OE controlled and WE is HIGH read cycle.
12. Address valid before or similar with CE transition LOW.
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Figure 3. Write Cycle 1 (WE controlled) [13, 14, 15]
Figure 4. Write Cycle 2 (CE controlled) [14, 16, 17]
Timing Waveforms (continued)
Address
CE
WE
Data In/Out
tWC
Data-In Valid
tSCE
tSA
tAW
tPWE
tHA
tHD
tSD
OE
tHZOE
Undefined
see footnotes
Address
CE
WE
Data In/Out
tWC
Data-In Valid
tSCE
tSA
tAW
tHA
tHD
tSD
High Z High Z
Notes
13. This cycle is WE controlled, OE is HIGH during write.
14. Data in and/or out is high impedance if OE = VIH.
15. During this period the IOs are in output state and input signals must not be applied.
16. This cycle is CE controlled.
17. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.
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Document #: 001-06435 Rev. *F Page 11 of 18
Figure 5. Write Cycle 3 (WE controlled, OE low) [18]
Timing Waveforms (continued)
Address
CE
WE
Data
In Out
tWC
Data In Valid
tSCE
tSA
tAW
tPWE
tHA
tHD
tSD
tHZWE tLZWE
Undefined
see footnotes
Undefined
See Footnotes
Note
18. The cycle is WE controlled, OE LOW. The minimum write cycle time is the sum of tHZWE and tSD.
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Document #: 001-06435 Rev. *F Page 12 of 18
Ordering Information
Contact local sales representative regarding availability of these parts.
Speed
(ns) Ordering Code Package
Diagram Package Type Power Option Operating
Range
15 CY7C199CN-15PXC 51-85014 28 DIP (6.9 x 35.6 x 3.5 mm), Pb-free Standard Commercial
CY7C199CN-15VXC 51-85031 28-Pin (300-Mil) Molded SOJ, Pb-free Standard Commercial
CY7C199CNL-15VXI 51-85031 28-Pin (300-Mil) Molded SOJ, Pb-free Low Power Industrial
20 CY7C199CN-20ZXI 51-85071 28 TSOP I (8 x 13.4 mm), Pb-free Standard Industrial
Ordering Code Definitions
Temperature Range: X = C or I
C = Commercial; I = Industrial
Package Type: XX = VX or PX or ZX
VX = 28-lead Molded SOJ (Pb-free)
PX = 28-lead DIP (Pb-free)
ZX = 28-lead TSOP I (Pb-free)
Speed: XX = 15 ns or 20 ns
L = low power
CN = 0.25 µm Technology
99 = 256 K bit density with datawidth × 8 bits
1 = Fast Asynchronous SRAM family
Technology Code: C = CMOS
7 = SRAM
CY = Cypress
CCY 1 - XX XX799 CN XL
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Package Diagrams
Figure 6. 28-pin TSOP I (8 x 13.4 mm), 51-85071
51-85071 *I
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Figure 7. 28-pin (300 Mil) Molded SOJ, 51-85031
Package Diagrams (continued)
51-85031 *D
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Figure 8. 28-pin (300 Mil) PDIP, 51-85014
Package Diagrams (continued)
51-85014 *E
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Acronyms Document Conventions
Units of Measure
Acronym Description
CE chip enable
CMOS Complementary metal oxide semiconductor
I/O Input/output
OE output enable
SRAM Static random access memory
SOJ Small Outline J-Lead
TSOP Thin Small Outline Package
VFBGA Very Fine-Pitch Ball Grid Array
Symbol Unit of Measure
ns nano seconds
VVolts
µA micro Amperes
mA milli Amperes
mV milli Volts
mW milli Watts
MHz Mega Hertz
pF pico Farad
°C degree Celcius
WWatts
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Document History Page
Document Title: CY7C199CN, 256 K (32 K × 8) Static RAM
Document Number: 001-06435
Revision ECN. Submission
Date
Orig. of
Change Description of Change
** 430363 See ECN NXR New Data Sheet
*A 684342 See ECN VKN Added Automotive-A Information
Updated Ordering Information Table
*B 839904 See ECN VKN Added tDOE spec for Automotive-A part in AC Electrical characteristics
table
*C 2896044 03/19/2010 NXR Updated Ordering Information Table
Updated Package Diagram
*D 3108898 12/13/2010 PRAS Added Ordering Code Definitions.
*E 3198636 03/17/11 PRAS Dislodged Automotive device information to 001-67737
Updated template and styles.
*F 3246329 05/04/2011 PRAS Addtional information on ISB1, ISB2 with respect to L parts
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Document #: 001-06435 Rev. *F Revised May 4, 2011 Page 18 of 18
All products and company names mentioned in this document may be the trademarks of their respective holders.
CY7C199CN
© Cypress Semiconductor Corporation, 2006-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
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