LTC2446/LTC2447
1
24467fa
FEATURES
DESCRIPTIO
U
APPLICATIO S
U
TYPICAL APPLICATIO
U
■
Flow
■
Weight Scales
■
Pressure
■
Direct Temperature Measurement
■
Gas Chromatography
■
Five Selectable Differential Reference Inputs
■
Four Differential/Eight Single-Ended Inputs
■
4-Way MUX for Multiple Ratiometric
Measurements
■
Up to 8kHz Output Rate
■
Up to 4kHz Multiplexing Rate
■
Selectable Speed/Resolution:
2µV
RMS
Noise at 1.76kHz Output Rate
200nV
RMS
Noise at 13.8Hz Output Rate with
Simultaneous 50/60Hz Rejection
■
Guaranteed Modulator Stability and Lock-Up
Immunity for any Input and Reference Conditions
■
0.0005% INL, No Missing Codes
■
Autosleep Enables 20µA Operation at 6.9Hz
■
<5µV Offset (4.5V < V
CC
< 5.5V, – 40°C to 85°C)
■
Differential Input and Differential Reference with
GND to V
CC
Common Mode Range
■
No Latency Mode, Each Conversion is Accurate Even
After a New Channel is Selected
■
Internal Oscillator—No External Components
■
LTC2447 Includes MUXOUT/ADCIN for External
Buffering or Gain
■
Tiny QFN 5mm x 7mm Package
24-Bit High Speed
8-Channel ∆Σ ADCs with
Selectable Multiple Reference Inputs
The LTC
®
2446/LTC2447 4-terminal switching enables
multiplexed ratiometric measurements. Four sets of se-
lectable differential inputs coupled with four sets of differ-
ential reference inputs allow multiple RTDs, bridges and
other sensors to be digitized by a single converter. A fifth
differential reference input can be selected for any input
channel not requiring ratiometric measurements (ther-
mocouples, voltages, current sense, etc.). The flexible
input multiplexer allows single-ended or differential in-
puts coupled with a slaved reference input or a universal
reference input.
A proprietary delta-sigma architecture results in absolute
accuracy (offset, full-scale, linearity) of 15ppm, noise as
low as 200nV
RMS
and speeds as high as 8kHz. Through a
simple 4-wire interface, ten speed/resolution combina-
tions can be selected. The first conversion following a
speed, resolution, channel change or reference change is
valid since there is no settling time between conversions,
enabling scan rates of up to 4kHz. Additionally, a 2x mode
can be selected for any speed-enabling output rates up to
8kHz with one cycle of latency.
, LTC and LT are registered trademarks of Linear Technology Corporation.
LTC2446 Speed vs RMS Noise
Multiple Ratiometric Measurement System
CONVERSION RATE (Hz)
1
0.1
RMS NOISE (µV)
1
10
100
10 100
24467 TA02
1000 10000
2.8µV AT 880Hz
280nV AT 6.9Hz
(50/60Hz REJECTION)
V
CC
= 5V
V
REF
= 5V
V
IN+
= V
IN–
= 0V
2x SPEED MODE
NO LATENCY MODE
VARIABLE SPEED/
RESOLUTION 24-BIT
∆Σ ADC
+
–
19-INPUT
4-OUTPUT
MUX
•
•
•
REF
+
V
CC
LTC2446
IN
+
IN
–
REF
–
CS
SDI
SDO
SCK
24467 TA01
Protected by U.S. Patents, including 6140950, 6169506, 6208279, 6411242, 6639526
LTC2446/LTC2447
2
24467fa
13 14 15 16
TOP VIEW
39
UHF PACKAGE
38-LEAD (5mm × 7mm) PLASTIC QFN
17 18 19
38 37 36 35 34 33 32
24
25
26
27
28
29
30
31
8
7
6
5
4
3
2
1GND
BUSY
EXT
GND
GND
GND
COM
CH0
CH1
VREF01–
VREF01+
CH2
GND
REFG–
REFG+
VCC
NC
NC
NC
NC
VREF67+
VREF67–
CH7
CH6
SCK
SDO
CS
FO
SDI
GND
GND
CH3
VREF23–
VREF23+
CH4
CH5
VREF45–
VREF45+
23
22
21
20
9
10
11
12
ORDER PART
NUMBER
ABSOLUTE AXI U RATI GS
W
WW
U
PACKAGE/ORDER I FOR ATIO
UUW
(Notes 1, 2)
Supply Voltage (V
CC
) to GND.......................–0.3V to 6V
Analog Input Pins Voltage
to GND .................................... –0.3V to (V
CC
+ 0.3V)
Reference Input Pins Voltage
to GND .................................... –0.3V to (V
CC
+ 0.3V)
Digital Input Voltage to GND ........ –0.3V to (V
CC
+ 0.3V)
LTC2446CUHF
LTC2446IUHF
QFN PART
MARKING*
2446
Digital Output Voltage to GND ..... –0.3V to (V
CC
+ 0.3V)
Operating Temperature Range
LTC2446C/LTC2447C .............................. 0°C to 70°C
LTC2446I/LTC2447I ........................... – 40°C to 85°C
Storage Temperature Range ................. – 65°C to 125°C
T
JMAX
= 125°C, θ
JA
= 34°C/W
EXPOSED PAD (PIN 39) IS GND
MUST BE SOLDERED TO PCB
*The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for parts specified with wider operating temperature ranges.
ORDER PART
NUMBER
LTC2447CUHF
LTC2447IUHF
QFN PART
MARKING*
2447
13 14 15 16
39
TOP VIEW
UHF PACKAGE
38-LEAD (5mm × 7mm) PLASTIC QFN
17 18 19
38 37 36 35 34 33 32
24
25
26
27
28
29
30
31
8
7
6
5
4
3
2
1GND
BUSY
EXT
GND
GND
GND
COM
CH0
CH1
VREF01–
VREF01+
CH2
GND
REFG–
REFG+
VCC
MUXOUTN
ADCINN
ADCINP
MUXOUTP
VREF67+
VREF67–
CH7
CH6
SCK
SDO
CS
FO
SDI
GND
GND
CH3
VREF23_
VREF23+
CH4
CH5
VREF45–
VREF45+
23
22
21
20
9
10
11
12
T
JMAX
= 125°C, θ
JA
= 34°C/W
EXPOSED PAD (PIN 39) IS GND
MUST BE SOLDERED TO PCB
Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
LTC2446/LTC2447
3
24467fa
ELECTRICAL CHARACTERISTICS
PARAMETER CONDITIONS MIN TYP MAX UNITS
Resolution (No Missing Codes) 0.1V ≤ V
REF
≤ V
CC
, –0.5 • V
REF
≤ V
IN
≤ 0.5 • V
REF
, (Note 5) ●24 Bits
Integral Nonlinearity V
CC
= 5V, REF
+
= 5V, REF
–
= GND, V
INCM
= 2.5V, (Note 6) ●5 15 ppm of V
REF
REF
+
= 2.5V, REF
–
= GND, V
INCM
= 1.25V, (Note 6) 3 ppm of V
REF
Offset Error 2.5V ≤ REF
+
≤ V
CC
, REF
–
= GND, ●2.5 5 µV
GND ≤ IN
+
= IN
–
≤ V
CC
(Note 12)
Offset Error Drift 2.5V ≤ REF
+
≤ V
CC
, REF
–
= GND, 20 nV/°C
GND ≤ IN
+
= IN
–
≤ V
CC
Positive Full-Scale Error REF
+
= 5V, REF
–
= GND, IN
+
= 3.75V, IN
–
= 1.25V ●10 50 ppm of V
REF
REF
+
= 2.5V, REF
–
= GND, IN
+
= 1.875V, IN
–
= 0.625V ●10 50 ppm of V
REF
Positive Full-Scale Error Drift 2.5V ≤ REF
+
≤ V
CC
, REF
–
= GND, 0.2 ppm of V
REF
/°C
IN
+
= 0.75REF
+
, IN
–
= 0.25 • REF
+
Negative Full-Scale Error REF
+
= 5V, REF
–
= GND, IN
+
= 1.25V, IN
–
= 3.75V ●10 50 ppm of V
REF
REF
+
= 2.5V, REF
–
= GND, IN
+
= 0.625V, IN
–
= 1.875V ●10 50 ppm of V
REF
Negative Full-Scale Error Drift 2.5V ≤ REF
+
≤ V
CC
, REF
–
= GND, 0.2 ppm of V
REF
/°C
IN
+
= 0.25 • REF
+
, IN
–
= 0.75 • REF
+
Total Unadjusted Error 5V ≤ V
CC
≤ 5.5V, REF
+
= 2.5V, REF
–
= GND, V
INCM
= 1.25V 15 ppm of V
REF
5V ≤ V
CC
≤ 5.5V, REF
+
= 5V, REF
–
= GND, V
INCM
= 2.5V 15 ppm of V
REF
REF
+
= 2.5V, REF
–
= GND, V
INCM
= 1.25V, (Note 6) 15 ppm of V
REF
Input Common Mode Rejection DC 2.5V ≤ REF
+
≤ V
CC
, REF
–
= GND, 120 dB
GND ≤ IN
–
= IN
+
≤ V
CC
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
IN
+
Absolute/Common Mode IN
+
Voltage ●GND – 0.3V V
CC
+ 0.3V V
IN
–
Absolute/Common Mode IN
–
Voltage ●GND – 0.3V V
CC
+ 0.3V V
V
IN
Input Differential Voltage Range ●–V
REF
/2 V
REF
/2 V
(IN
+
– IN
–
)
REF
+
Absolute/Common Mode REF
+
Voltage ●0.1 V
CC
V
REF
–
Absolute/Common Mode REF
–
Voltage ●GND V
CC
– 0.1V V
V
REF
Reference Differential Voltage Range ●0.1 V
CC
V
(REF
+
– REF
–
)
C
S(IN+)
IN
+
Sampling Capacitance 2 pF
C
S(IN–)
IN
–
Sampling Capacitance 2 pF
C
S(REF+)
REF
+
Sampling Capacitance 2 pF
C
S(REF–)
REF
–
Sampling Capacitance 2 pF
I
DC_LEAK(IN+, IN–,
Leakage Current, Inputs and Reference CS = V
CC
, IN
+
= GND, IN
–
= GND, ●–15 1 15 nA
REF+, REF–)
REF
+
= 5V, REF
–
= GND
I
SAMPLE(IN+, IN–,
Average Input/Reference Current Varies, See Applications Section nA
REF+, REF–)
During Sampling
t
OPEN
MUX Break-Before-Make 50 ns
QIRR MUX Off Isolation V
IN
= 2V
P-P
DC to 1.8MHz 120 dB
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 3)
A ALOG I PUT A
U
D REFERE CE
UUU
LTC2446/LTC2447
4
24467fa
TI I G CHARACTERISTICS
UW
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
CC
Supply Voltage ●4.5 5.5 V
I
CC
Supply Current
Conversion Mode CS = 0V (Note 7) ●811 mA
Sleep Mode CS = V
CC
(Note 7) ●830 µA
The ● denotes specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. (Note 3)
POWER REQUIRE E TS
WU
The ● denotes specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
IH
High Level Input Voltage 4.5V ≤ V
CC
≤ 5.5V ●2.5 V
CS, F
O
V
IL
Low Level Input Voltage 4.5V ≤ V
CC
≤ 5.5V ●0.8 V
CS, F
O
V
IH
High Level Input Voltage 4.5V ≤ V
CC
≤ 5.5V (Note 8) ●2.5 V
SCK
V
IL
Low Level Input Voltage 4.5V ≤ V
CC
≤ 5.5V (Note 8) ●0.8 V
SCK
I
IN
Digital Input Current 0V ≤ V
IN
≤ V
CC
●–10 10 µA
CS, F
O
, EXT, SOI
I
IN
Digital Input Current 0V ≤ V
IN
≤ V
CC
(Note 8) ●–10 10 µA
SCK
C
IN
Digital Input Capacitance 10 pF
CS, F
O
C
IN
Digital Input Capacitance (Note 8) 10 pF
SCK
V
OH
High Level Output Voltage I
O
= –800µA●V
CC
– 0.5V V
SDO, BUSY
V
OL
Low Level Output Voltage I
O
= 1.6mA ●0.4V V
SDO, BUSY
V
OH
High Level Output Voltage I
O
= –800µA (Note 9) ●V
CC
– 0.5V V
SCK
V
OL
Low Level Output Voltage I
O
= 1.6mA (Note 9) ●0.4V V
SCK
I
OZ
Hi-Z Output Leakage ●–10 10 µA
SDO
DIGITAL I PUTS A D DIGITAL OUTPUTS
UU
The ● denotes specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
f
EOSC
External Oscillator Frequency Range ●0.1 20 MHz
t
HEO
External Oscillator High Period ●25 10000 ns
t
LEO
External Oscillator Low Period ●25 10000 ns
t
CONV
Conversion Time OSR = 256 ●0.99 1.13 1.33 ms
OSR = 32768 ●126 145 170 ms
External Oscillator (Notes 10, 13) ●
40 • OSR +170
f
EOSC
(kHz)
ms
f
ISCK
Internal SCK Frequency Internal Oscillator (Note 9) ●0.8 0.9 1 MHz
External Oscillator (Notes 9, 10) f
EOSC
/10 Hz
LTC2446/LTC2447
5
24467fa
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
D
ISCK
Internal SCK Duty Cycle (Note 9) ●45 55 %
f
ESCK
External SCK Frequency Range (Note 8) ●20 MHz
t
LESCK
External SCK Low Period (Note 8) ●25 ns
t
HESCK
External SCK High Period (Note 8) ●25 ns
t
DOUT_ISCK
Internal SCK 32-Bit Data Output Time Internal Oscillator (Notes 9, 11) ●41.6 35.3 30.9 µs
External Oscillator (Notes 9, 10) ●320/f
EOSC
s
t
DOUT_ESCK
External SCK 32-Bit Data Output Time (Note 8) ●32/f
ESCK
s
t
1
CS ↓ to SDO Low Z (Note 12) ●025ns
t
2
CS ↑ to SDO High Z (Note 12) ●025ns
t
3
CS ↓ to SCK ↓(Note 9) 5 µs
t
4
CS ↓ to SCK ↑(Notes 8, 12) ●25 ns
t
KQMAX
SCK ↓ to SDO Valid ●25 ns
t
KQMIN
SDO Hold After SCK ↓(Note 5) ●15 ns
t
5
SCK Setup Before CS ↓●50 ns
t
6
SCK Hold After CS ↓●50 ns
t
7
SDI Setup Before SCK ↑(Note 5) ●10 ns
t
8
SDI Hold After SCK ↑(Note 5) ●10 ns
The ● denotes specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 3)
TI I G CHARACTERISTICS
WU
GND (Pins 1, 4, 5, 6, 31, 32, 33): Ground. Multiple
ground pins internally connected for optimum ground
current flow and V
CC
decoupling. Connect each one of
these pins to a common ground plane through a low
impedance connection. All seven pins must be connected
to ground for proper operation.
BUSY (Pin 2): Conversion in Progress Indicator. This pin
is HIGH while the conversion is in progress and goes LOW
indicating the conversion is complete and data is ready. It
remains LOW during the sleep and data output states. At
the conclusion of the data output state, it goes HIGH
indicating a new conversion has begun.
EXT (Pin 3): Internal/External SCK Selection Pin. This pin
is used to select internal or external SCK for outputting/
inputting data. If EXT is tied low, the device is in the
external SCK mode and data is shifted out of the device
under the control of a user applied serial clock. If EXT is
tied high, the internal serial clock mode is selected. The
device generates its own SCK signal and outputs this on
the SCK pin. A framing signal BUSY (Pin 2) goes low
indicating data is being output.
COM (Pin 7): The common negative input (IN
–
) for all
single ended multiplexer configurations. The voltage on
CH0-CH7 and COM pins can have any value between GND
UU
U
PI FU CTIO S
Note 1: Absolute Maximum Ratings are those values beyond which the life
of the device may be impaired.
Note 2: All voltage values are with respect to GND.
Note 3: V
CC
= 4.5V to 5.5V unless otherwise specified.
V
REF
= REF
+
– REF
–
, V
REFCM
= (REF
+
+ REF
–
)/2; REF
+
is the positive
reference input, REF
–
is the negative reference input; V
IN
= IN
+
– IN
–
,
V
INCM
= (IN
+
+ IN
–
)/2.
Note 4: F
O
pin tied to GND or to external conversion clock source with
f
EOSC
= 10MHz unless otherwise specified.
Note 5: Guaranteed by design, not subject to test.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 7: The converter uses the internal oscillator.
Note 8: The converter is in external SCK mode of operation such that the
SCK pin is used as a digital input. The frequency of the clock signal driving
SCK during the data output is f
ESCK
and is expressed in Hz.
Note 9: The converter is in internal SCK mode of operation such that the
SCK pin is used as a digital output. In this mode of operation, the SCK pin
has a total equivalent load capacitance of C
LOAD
= 20pF.
Note 10: The external oscillator is connected to the F
O
pin. The external
oscillator frequency, f
EOSC
, is expressed in Hz.
Note 11: The converter uses the internal oscillator. F
O
= 0V.
Note 12: Guaranteed by design and test correlation.
Note 13: There is an internal reset that adds an additional 1µs (typ) to the
conversion time.
LTC2446/LTC2447
6
24467fa
contains an enable bit which determines if a new channel/
speed is selected. If this bit is low the following conversion
remains at the same speed and selected channel. The
serial data input is applied to the device under control of
the serial clock (SCK) during the data output cycle. The
first conversion following a new channel/speed is valid.
F
O
(Pin 35): Frequency Control Pin. Digital input that
controls the internal conversion clock. When F
O
is con-
nected to V
CC
or GND, the converter uses its internal
oscillator running at 9MHz. The conversion rate is deter-
mined by the selected OSR such that t
CONV
(ms) = (40 •
OSR + 170)/f
OSC
(kHz). The first digital filter null is located
at 8/t
CONV
, 7kHz at OSR = 256 and 55Hz (Simultaneous 50/
60Hz) at OSR = 32768. This pin may be driven with a
maximum external clock of 10.24MHz resulting in a maxi-
mum 8kHz output rate (OSR = 64, 2x Mode).
CS (Pin 36): Active Low Chip Select. A LOW on this pin
enables the SDO digital output and wakes up the ADC.
Following each conversion the ADC automatically enters
the sleep mode and remains in this low power state as long
as CS is HIGH. A LOW-to-HIGH transition on CS during the
Data Output aborts the data transfer and starts a new
conversion.
SDO (Pin 37): Three-State Digital Output. During the data
output period, this pin is used as serial data output. When
the chip select CS is HIGH (CS = V
CC
) the SDO pin is in a
high impedance state. During the conversion and sleep
periods, this pin is used as the conversion status output.
The conversion status can be observed by pulling CS
LOW. This signal is HIGH while the conversion is in
progress and goes LOW once the conversion is complete.
SCK (Pin 38): Bidirectional Digital Clock Pin. In internal
serial clock operation mode, SCK is used as a digital output
for the internal serial interface clock during the data output
period. In the external serial clock operation mode, SCK is
used as the digital input for the external serial interface
clock during the data output period. The serial clock
operation mode is determined by the logic level applied to
the EXT pin.
Exposed Pad (Pin 39): Ground. The exposed pad on the
bottom of the package must be soldered to the PCB ground.
For Prototyping purposes, this pin may remain floating.
– 0.3V to V
CC
+ 0.3V. Within these limits, the two selected
inputs (IN
+
and IN
–
) provide a bipolar input range (V
IN
=
IN
+
– IN
–
) from –0.5 • V
REF
to 0.5 • V
REF
. Outside this input
range, the converter produces unique over-range and
under-range output codes.
CH0 to CH7 (Pins 8, 9, 12, 13, 16, 17, 20, 21): Analog
Inputs. May be programmed for Single-ended or Differen-
tial mode.
VREF01+ (Pin 11), VREF01– (Pin 10) VREF23+ (Pin 15),
VREF23– (Pin 14), VREF45+ (Pin 19), VREF45– (Pin 18),
VREF67+ (Pin 23), VREF67– (Pin 22): Differential Reference
Inputs. The voltage on these pins can be anywhere
between 0V and VCC as long as the positive reference
input (VEF01+, VREF23+, VREF45+, VREF67+) is greater than
the corresponding negative reference input (VREF01–,
VREF23–, VREF45–, VREF67–) by at least 100mV.
NC (Pins 24, 25, 26, 27): LTC2446 No Connect. These
pins can either be tied to ground or left floating.
MUXOUTP (Pin 24): LTC2447 Positive Input Channel
Multiplexer Output. Used to drive the input to an external
buffer/amplifier for the selected positive input signal (IN
+
).
ADCINP (Pin 25): LTC2447 Positive ADC Input. Tie to
output of buffer/amplifier driven by MUXOUTP.
ADCINN (Pin 26): LTC2447 Negative ADC Input. Tie to
output of buffer/amplifier driven by MUXOUTN.
MUXOUTN (Pin 27): LTC2447 Negative Input Channel
Multiplexer Output. Used to drive the input to an external
buffer/amplifier for the selected negative input signal
(IN–).
V
CC
(Pin 28): Positive Supply Voltage. Bypass to GND with
a 10µF tantalum capacitor in parallel with a 0.1µF ceramic
capacitor as close to the part as possible.
V
REFG+
(Pin 29), V
REFG–
(Pin 30): Global Reference Input.
This differential reference input can be used for any input
channel selected through a single bit in the digital input word.
SDI (Pin 34): Serial Data Input. This pin is used to select
the speed, 1x or 2x mode, resolution, input channel and
reference input for the next conversion cycle. At initial
power-up, the default mode of operation is CH0-CH1,
V
REF01
, OSR of 256, and 1x mode. The serial data input
PI FU CTIO S
UUU
LTC2446/LTC2447
7
24467fa
TEST CIRCUITS
FU CTIO AL BLOCK DIAGRA
UU
W
Figure 1. Functional Block Diagram
APPLICATIO S I FOR ATIO
WUUU
CONVERTER OPERATION
Converter Operation Cycle
The LTC2446/LTC2447 are multichannel, multireference
high speed, delta-sigma analog-to-digital converters with
an easy to use 3- or 4-wire serial interface (see Figure 1).
Their operation is made up of three states. The converter
operating cycle begins with the conversion, followed by
the low power sleep state and ends with the data output/
input (see Figure 2). The 4-wire interface consists of serial
data input (SDI), serial data output (SDO), serial clock
(SCK) and chip select (CS). The interface, timing, opera-
tion cycle and data out format is compatible with Linear’s
entire family of ∆Σ converters.
Initially, the LTC2446/LTC2447 perform a conversion.
Once the conversion is complete, the device enters the Figure 2. LTC2446/LTC2447 State Transition Diagram
AUTOCALIBRATION
AND CONTROL
DIFFERENTIAL
3RD ORDER
∆Σ MODULATOR
DECIMATING FIR
ADDRESS
INTERNAL
OSCILLATOR
SERIAL
INTERFACE
GND
V
CC
CH0
CH1 •
•
•
•
•
•
CH7
COM
IN
+
REF
+
REF
–
IN
–
INPUT/REFERENCE MUX
SDO
SCK
V
REFG+
V
REFG–
V
REF67+
V
REF67–
V
REF01+
V
REF01–
CS
SDI
F
O
(INT/EXT)
24467 F01
CONVERT
SLEEP
NO
YES
CHANNEL SELECT
REFERENCE SELECT
SPEED SELECT
DATA OUTPUT
POWER UP
IN
+
=CH0, IN
–
=CH1
REF
+
= V
REFO1+
,
REF
–
= V
REF01–
OSR=256,1X MODE
24467 F02
CS = LOW
AND
SCK
1.69k
SDO
24467 TA03
Hi-Z TO V
OH
V
OL
TO V
OH
V
OH
TO Hi-Z
C
LOAD
= 20pF
1.69k
SDO
24467 TA04
Hi-Z TO V
OL
V
OH
TO V
OL
V
OL
TO Hi-Z
C
LOAD
= 20pF
V
CC
LTC2446/LTC2447
8
24467fa
sleep state. While in this sleep state, power consumption
is reduced below 10µA. The part remains in the sleep state
as long as CS is HIGH. The conversion result is held
indefinitely in a static shift register while the converter is
in the sleep state.
Once CS is pulled LOW, the device begins outputting the
conversion result. There is no latency in the conversion
result while operating in the 1x mode. The data output cor-
responds to the conversion just performed. This result is
shifted out on the serial data out pin (SDO) under the con-
trol of the serial clock (SCK). Data is updated on the falling
edge of SCK allowing the user to reliably latch data on the
rising edge of SCK (see Figure 3). The data output state is
concluded once 32 bits are read out of the ADC or when CS
is brought HIGH. The device automatically initiates a new
conversion and the cycle repeats.
Through timing control of the CS, SCK and EXT pins, the
LTC2446/LTC2447 offer several flexible modes of opera-
tion (internal or external SCK). These various modes do
not require programming configuration registers; more-
over, they do not disturb the cyclic operation described
above. These modes of operation are described in detail in
the Serial Interface Timing Modes section.
Ease of Use
The LTC2446/LTC2447 data output has no latency, filter
settling delay or redundant data associated with the
conversion cycle while operating in the 1x mode. There
is a one-to-one correspondence between the conversion
and the output data. Therefore, multiplexing multiple
analog voltages and references is easy. Speed/resolution
adjustments may be made seamlessly between two
conversions without settling errors.
The LTC2446/LTC2447 perform offset and full-scale cali-
brations every conversion cycle. This calibration is trans-
parent to the user and has no effect on the cyclic operation
described above. The advantage of continuous calibration
is extreme stability of offset and full-scale readings with re-
spect to time, supply voltage change and temperature drift.
Power-Up Sequence
The LTC2446/LTC2447 automatically enter an internal
reset state when the power supply voltage V
CC
drops
APPLICATIO S I FOR ATIO
WUUU
below approximately 2.2V. This feature guarantees the
integrity of the conversion result and of the serial inter-
face mode selection.
When the V
CC
voltage rises above this critical threshold,
the converter creates an internal power-on-reset (POR)
signal with a duration of approximately 0.5ms. The POR
signal clears all internal registers. The conversion imme-
diately following a POR is performed on the input channel
IN
+
= CH0, IN
–
= CH1, REF
+
= V
REF01+
, REF
–
V
REF01–
at an
OSR = 256 in the 1x mode. Following the POR signal, the
LTC2446/LTC2447 start a normal conversion cycle and
follow the succession of states described above. The first
conversion result following POR is accurate within the
specifications of the device if the power supply voltage is
restored within the operating range (4.5V to 5.5V) before
the end of the POR time interval.
Reference Voltage Range
These converters accept truly differential external refer-
ence voltages. Each set of five reference inputs may be
independently driven to any common mode voltage over
the entire supply range of the device (GND to VCC). For
correct converter operation, each positive reference pin
REF+ (VREF01+, VREF23+, VREF45+, VREF67+, VREFG+) must
be more positive than its corresponding negative refer-
ence pin REF– (VREF01–, VREF23–, VREF45–, VREF67–,
VREFG–) by at least 100mV.
The LTC2446/LTC2447 can accept a differential reference
from 0.1V to V
CC
on each set of reference input pins. The
converter output noise is determined by the thermal noise
of the front-end circuits, and as such, its value in micro-
volts is nearly constant with reference voltage. A decrease
in reference voltage will not significantly improve the
converter’s effective resolution. On the other hand, a
reduced reference voltage will improve the converter’s
overall INL performance.
Input Voltage Range
The analog input is truly differential with an absolute/
common mode range for the CH0-CH7 and COM input
pins extending from GND – 0.3V to V
CC
+ 0.3V. Outside
these limits, the ESD protection devices begin to turn on
and the errors due to input leakage current increase
rapidly. Within these limits, the LTC2446/LTC2447
LTC2446/LTC2447
9
24467fa
c
onvert the bipolar differential input signal, V
IN
= IN
+
–
IN
–
(where IN
+
and IN
–
are the selected input channels),
from –FS = –0.5 • V
REF
to +FS = 0.5 • V
REF
where V
REF
=
REF
+
– REF
–
(REF
+
and REF
–
are the selected references).
Outside this range, the converter indicates the overrange
or the underrange condition using distinct output codes.
MUXOUT/ADCIN
There are two differences between the LTC2446 and the
LTC2447. The first is the RMS noise performance. For a
given OSR, the LTC2447 noise level is approximately √2
times lower (0.5 effective bits)than that of the LTC2446.
The second difference is the LTC2447 includes MUXOUT/
ADCIN pins. These pins enable an external buffer or gain
block to be inserted between the selected input channel of
the multiplexer and the input to the ADC. Since the buffer
is driven by the output of the multiplexer, only one circuit
is required for all 8 input channels. Additionally, the
transparent calibration feature of the LTC244X family
automatically removes the offset errors of the external
buffer.
In order to achieve optimum performance, the MUXOUT
and ADCIN pins should not be shorted together. In appli-
cations where the MUXOUT and ADCIN need to be shorted
together, the LTC2446 should be used because the
MUXOUT and ADCIN are internally connected for opti-
mum performance.
Output Data Format
The LTC2446/LTC2447 serial output data stream is 32 bits
long. The first 3 bits represent status information indicat-
ing the sign and conversion state. The next 24 bits are the
conversion result, MSB first. The remaining 5 bits are sub
LSBs beyond the 24-bit level that may be included in
averaging or discarded without loss of resolution. In the
case of ultrahigh resolution modes, more than 24 effective
bits of performance are possible (see Table 4). Under
these conditions, sub LSBs are included in the conversion
result and represent useful information beyond the 24-bit
level. The third and fourth bit together are also used to
indicate an underrange condition (the differential input
voltage is below –FS) or an overrange condition (the
differential input voltage is above +FS).
Bit 31 (first output bit) is the end of conversion (EOC)
indicator. This bit is available at the SDO pin during the
conversion and sleep states whenever the CS pin is LOW.
This bit is HIGH during the conversion and goes LOW
when the conversion is complete.
Bit 30 (second output bit) is a dummy bit (DMY) and is
always LOW.
Bit 29 (third output bit) is the conversion result sign indi-
cator (SIG). If V
IN
is >0, this bit is HIGH. If V
IN
is <0, this
bit is LOW.
Bit 28 (fourth output bit) is the most significant bit (MSB)
of the result. This bit in conjunction with Bit 29 also
provides the underrange or overrange indication. If both
Bit 29 and Bit 28 are HIGH, the differential input voltage is
above +FS. If both Bit 29 and Bit 28 are LOW, the
differential input voltage is below –FS.
The function of these bits is summarized in Table 1.
Table 1. LTC2446/LTC2447 Status Bits
BIT 31 BIT 30 BIT 29 BIT 28
INPUT RANGE EOC DMY SIG MSB
V
IN
≥ 0.5 • V
REF
0011
0V ≤ V
IN
< 0.5 • V
REF
0010
–0.5 • V
REF
≤ V
IN
< 0V 0001
V
IN
< – 0.5 • V
REF
0000
Bits 28-5 are the 24-bit conversion result MSB first.
Bit 5 is the least significant bit (LSB).
Bits 4-0 are sub LSBs below the 24-bit level. Bits 4-0 may
be included in averaging or discarded without loss of
resolution.
Data is shifted out of the SDO pin under control of the serial
clock (SCK), see Figure 3. Whenever CS is HIGH, SDO
remains high impedance and SCK is ignored.
In order to shift the conversion result out of the device, CS
must first be driven LOW. EOC is seen at the SDO pin of the
device once CS is pulled LOW. EOC changes real time from
HIGH to LOW at the completion of a conversion. This
signal may be used as an interrupt for an external
microcontroller. Bit 31 (EOC) can be captured on the first
APPLICATIO S I FOR ATIO
WUUU
LTC2446/LTC2447
10
24467fa
MSB
BIT 28 BIT 27 BIT 26 BIT 25 BIT 24 BIT 23 BIT 22 BIT 21 BIT 20 BIT 19 BIT 0
LSB Hi-Z
24467 F03
SIG
BIT 29
“0”
BIT 30
EOC
Hi-Z
CS
SCK
SDI
SDO
BUSY
BIT 31
1 0 EN SGL GLBL A1 A0 OSR3 OSR2 OSR1 OSR0 TWOXODD
1234567891011121314 32
+FS, the conversion result is clamped to the value corre-
sponding to the +FS + 1LSB. For differential input voltages
below –FS, the conversion result is clamped to the value
corresponding to –FS – 1LSB.
SERIAL INTERFACE PINS
The LTC2446/LTC2447 transmit the conversion results
and receive the start of conversion command through a
synchronous 3- or 4-wire interface. During the conver-
sion and sleep states, this interface can be used to assess
the converter status and during the data output state it is
used to read the conversion result and program the
speed, resolution and input channel.
rising edge of SCK. Bit 30 is shifted out of the device on the
first falling edge of SCK. The final data bit (Bit 0) is shifted
out on the falling edge of the 31st SCK and may be latched
on the rising edge of the 32nd SCK pulse. On the falling
edge of the 32nd SCK pulse, SDO goes HIGH indicating the
initiation of a new conversion cycle. This bit serves as EOC
(Bit 31) for the next conversion cycle. Table 2 summarizes
the output data format.
As long as the voltage on the IN
+
and IN
–
pins is maintained
within the –0.3V to (V
CC
+ 0.3V) absolute maximum
operating range, a conversion result is generated for any
differential input voltage V
IN
from –FS = –0.5 • V
REF
to
+FS = 0.5 • V
REF
. For differential input voltages greater than
Table 2. LTC2446/LTC2447 Output Data Format
Differential Input Voltage Bit 31 Bit 30 Bit 29 Bit 28 Bit 27 Bit 26 Bit 25 … Bit 0
V
IN
* EOC DMY SIG MSB
V
IN
* ≥ 0.5 • V
REF
** 0 0110 0 0…0
0.5 • V
REF
** – 1LSB 0 0101 1 1…1
0.25 • V
REF
** 0 0101 0 0…0
0.25 • V
REF
** – 1LSB 0 0100 1 1…1
0 0 0100 0 0…0
–1LSB 0 0011 1 1…1
–0.25 • V
REF
** 0 0011 0 0…0
–0.25 • V
REF
** – 1LSB 00010 1 1…1
–0.5 • V
REF
** 0 0010 0 0…0
V
IN
* < –0.5 • V
REF
** 0 0001 1 1…1
*The differential input voltage V
IN
= IN
+
– IN
–
. **The differential reference voltage V
REF
= REF
+
– REF
–
.
APPLICATIO S I FOR ATIO
WUUU
Figure 3. SDI Speed/Resolution, Channel Selection, and Data Output Timing
LTC2446/LTC2447
11
24467fa
Serial Clock Input/Output (SCK)
The serial clock signal present on SCK (Pin 38) is used to
synchronize the data transfer. Each bit of data is shifted out
the SDO pin on the falling edge of the serial clock.
In the Internal SCK mode of operation, the SCK pin is an
output and the LTC2446/LTC2447 create their own serial
clock. In the External SCK mode of operation, the SCK pin
is used as input. The internal or external SCK mode is
selected by tying EXT (Pin 3) LOW for external SCK and
HIGH for internal SCK.
Serial Data Output (SDO)
The serial data output pin, SDO (Pin 37), provides the
result of the last conversion as a serial bit stream (MSB
first) during the data output state. In addition, the SDO pin
is used as an end of conversion indicator during the
conversion and sleep states.
When CS (Pin 36) is HIGH, the SDO driver is switched to
a high impedance state. This allows sharing the serial
interface with other devices. If CS is LOW during the
convert or sleep state, SDO will output EOC. If CS is LOW
during the conversion phase, the EOC bit appears HIGH on
the SDO pin. Once the conversion is complete, EOC goes
LOW. The device remains in the sleep state until the first
rising edge of SCK occurs while CS = LOW.
Chip Select Input (CS)
The active LOW chip select, CS (Pin 36), is used to test the
conversion status and to enable the data output transfer as
described in the previous sections.
In addition, the CS signal can be used to trigger a new
conversion cycle before the entire serial data transfer has
been completed. The LTC2446/LTC2447 will abort any
serial data transfer in progress and start a new conversion
cycle anytime a LOW-to-HIGH transition is detected at the
CS pin after the converter has entered the data output
state.
Serial Data Input (SDI)
The serial data input (SDI, Pin 34) is used to select the
speed/resolution input channel and reference of the
LTC2446/LTC2447. SDI is programmed by a serial input
data stream under the control of SCK during the data
output cycle, see Figure 3.
Initially, after powering up, the device performs a conver-
sion with IN
+
= CH0, IN
–
= CH1, REF
+
= V
REF01+
, REF
–
=
V
REF01–
, OSR = 256 (output rate nominally 880Hz), and 1x
speed mode (no Latency). Once this first conversion is
complete, the device enters the sleep state and is ready to
output the conversion result and receive the serial data input
stream programming the speed/resolution, input channel
and reference for the next conversion. At the conclusion of
each conversion cycle, the device enters this state.
In order to change the speed/resolution, reference or input
channel, the first 3 bits shifted into the device are 101. This
is compatible with the programming sequence of the
LTC2414/LTC2418/LTC2444/LTC2445/LTC2448/
LTC2449. If the sequence is set to 000 or 100, the follow-
ing input data is ignored (don’t care) and the previously
selected speed/resolution, channel and reference remain
valid for the next conversion. Combinations other than 101,
100, and 000 of the 3 control bits should be avoided.
If the first 3 bits shifted into the device are 101, then the
following 5 bits select the input channel/reference for the
following conversion (see Table 3). The next 5 bits select
the speed/resolution and mode 1x (no Latency) 2x (double
output rate with one conversion latency), see Table 4. If
these 5 bits are set to all 0’s, the previous speed remains
selected for the next conversion. This is useful in applica-
tions requiring a fixed output rate/resolution but need to
change the input channel or reference. In this case, the
timing and input sequence is compatible with the LTC2414/
LTC2418.
When an update operation is initiated (the first 3 bits are
101) the next 5 bits are the channel/reference address. The
first bit, SGL, determines if the input selection is differen-
tial (SGL = 0) or single-ended (SGL = 1). For SGL = 0, two
adjacent channels can be selected to form a differential
input. For SGL = 1, one of 8 channels is selected as the
positive input. The negative input is COM for all single
ended operations. The global V
REF
bit (GLBL) is used to
determine which reference is selected. GLBL = 0 selects
the individual reference slaved to a given channel. Each set
of channels has a corresponding differential input refer-
ence. If GLBL = 1, a global reference V
REFG+
/V
REFG–
is
selected. The global reference input may be used for any
input channel selected. Table 3 shows a summary of input/
reference selection. The remaining bits (ODD, A1, A0)
determine which channel is selected.
APPLICATIO S I FOR ATIO
WUUU
LTC2446/LTC2447
12
24467fa
Table 3. Channel Selection for the LTC2446/LTC2447
MUX ADDRESS CHANNEL INPUT REFERENCE INPUT
ODD/
SGL SIGN GLBL A1 A0 0 1 2 3 4 5 6 7 COM 01
+
01
–
23
+
23
–
45
+
45
–
67
+
67
–
G
+
G
–
*0 0 0 0 0 IN
+
IN
–
REF
+
REF
–
00001 IN
+
IN
–
REF
+
REF
–
00010 IN
+
IN
–
REF
+
REF
–
00011 IN
+
IN
–
REF
+
REF
–
01000IN
–
IN
+
REF
+
REF
–
01001 IN
–
IN
+
REF
+
REF
–
01010 IN
–
IN
+
REF
+
REF
–
01011 IN
–
IN
+
REF
+
REF
–
10000IN
+
IN
–
REF
+
REF
–
10001 IN
+
IN
–
REF
+
REF
–
10010 IN
+
IN
–
REF
+
REF
–
10011 IN
+
IN– REF
+
REF
–
11000 IN
+
IN
–
REF
+
REF
–
11001 IN
+
IN
–
REF
+
REF
–
11010 IN
+
IN
–
REF
+
REF
–
11011 IN
+
IN
–
REF
+
REF
–
00100IN
+
IN
–
REF
+
REF
–
00101 IN
+
IN
–
REF
+
REF
–
00110 IN
+
IN
–
REF
+
REF
–
00111 IN
+
IN
–
REF
+
REF
–
01100IN
–
IN
+
REF
+
REF
–
01101 IN
–
IN
+
REF
+
REF
–
01110 IN
–
IN
+
REF
+
REF
–
01111 IN
–
IN
+
REF
+
REF
–
10100IN
+
IN
–
REF
+
REF
–
10101 IN
+
IN
–
REF
+
REF
–
10110 IN
+
IN
–
REF
+
REF
–
10111 IN
+
IN
–
REF
+
REF
–
11100 IN
+
IN
–
REF
+
REF
–
11101 IN
+
IN
–
REF
+
REF
–
11110 IN
+
IN
–
REF
+
REF
–
11111 IN
+
IN
–
REF
+
REF
–
*Default at power up
APPLICATIO S I FOR ATIO
WUUU
LTC2446/LTC2447
13
24467fa
APPLICATIO S I FOR ATIO
WUUU
Table 4. LTC2446/LTC2447 Speed/Resolution Selection
CONVERSION RATE
INTERNAL EXTERNAL RMS RMS
9MHz 10.24MHz NOISE NOISE ENOB ENOB
OSR3 OSR2 OSR1 OSR0 TWOX CLOCK CLOCK LTC2446 LTC2447 LTC2446 LTC2447 OSR LATENCY
00000 Keep Previous Speed/Resolution
000103.52kHz 4kHz 23µV23µV 17 17 64 None
001001.76kHz 2kHz 4.4µV 3.5µV 20.1 20.1 128 None
00110880Hz 1kHz 2.8µV2µV 20.8 21.3 256 None
01000440Hz 500Hz 2µV 1.4µV 21.3 21.8 512 None
01010220Hz 250Hz 1.4µV1µV 21.8 22.4 1024 None
01100110Hz 125Hz 1.1µV 750nV 22.1 22.9 2048 None
0111055Hz 62.5Hz 720nV 510nV 22.7 23.4 4096 None
1000027.5Hz 31.25Hz 530nV 375nV 23.2 24 8192 None
1001013.75Hz 15.625Hz 350nV 250nV 23.8 24.4 16384 None
111106.875Hz 7.8125Hz 280nV 200nV 24.1 24.6 32768 none
00001 Keep Previous Speed/Resolution
000117.04kHz 8kHz 23µV23µV 17 17 64 1 Cycle
001013.52kHz 4kHz 4.4µV 3.5µV 20.1 20.1 128 1 Cycle
001111.76kHz 2kHz 2.8µV2µV 20.8 21.3 256 1 Cycle
01001880Hz 1kHz 2µV 1.4µV 21.3 21.8 512 1 Cycle
01011440Hz 500Hz 1.4µV1µV 21.8 22.4 1024 1 Cycle
01101220Hz 250Hz 1.1µV 750nV 22.1 22.9 2048 1 Cycle
01111110Hz 125Hz 720nV 510nV 22.7 23.4 4096 1 Cycle
1000155Hz 62.5Hz 530nV 375nV 23.2 24 8192 1 Cycle
1001127.5Hz 31.25Hz 350nV 250nV 23.8 24.4 16384 1 Cycle
1111113.75Hz 15.625Hz 280nV 200nV 24.1 24.6 32768 1 Cycle
LTC2446/LTC2447
14
24467fa
Speed Multiplier Mode
In addition to selecting the speed/resolution, a speed
multiplier mode is used to double the output rate while
maintaining the selected resolution. The last bit of the 5-bit
speed/resolution control word (TWOX, see Table 4) deter-
mines if the output rate is 1x (no speed increase) or 2x
(double the selected speed).
While operating in the 1x mode, the device combines two
internal conversions for each conversion result in order to
remove the ADC offset. Every conversion cycle, the offset
and offset drift are transparently calibrated greatly simpli-
fying the user interface. The conversion result has no
latency. The first conversion following a newly selected
speed/resolution and/or input/reference is valid. This is
identical to the operation of the LTC2440, LTC2444,
LTC2445, LTC2448, LTC2449, LTC2414 and LTC2418.
While operating in the 2x mode, the device performs a
running average of the last two conversion results. This
automatically removes the offset and drift of the device
while increasing the output rate by 2x. The resolution
(noise) remains the same as the 1x mode. If a new
channel/reference is selected, the conversion result is
valid for all conversions after the first conversion (one
cycle latency). If a new speed/resolution is selected, the
first conversion result is valid but the resolution (noise) is
a function of the running average. All subsequent conver-
sion results are valid. If the mode is changed from either
1x to 2x or 2x to 1x without changing the resolution or
channel, the first conversion result is valid.
If an external buffer/amplifier circuit is used for the
LTC2447, the 2x mode can be used to increase the settling
time of the amplifier between readings. While operating in
the 2x mode, the multiplexer output (input to the external
buffer/amplifier) is switched at the end of each conversion
cycle. Prior to concluding the data out/in cycle, the analog
multiplexer output is switched. This occurs at the end of
the conversion cycle (just prior to the data output cycle)
for auto calibration. The time required to read the conver-
sion enables more settling time for the external buffer/
amplifier. The offset/offset drift of the external amplifiers
are automatically removed by the converter’s auto calibra-
tion sequence for both the 1x and 2x speed modes.
While operating in the 1x mode, if a new input channel/
reference is selected the multiplexer is switched on the
falling edge of the 14th SCK (once the complete data input
word is programmed). The remaining data output se-
quence time can be used to allow the external buffer/
amplifier to settle.
BUSY
The BUSY output (Pin 2) is used to monitor the state of
conversion, data output and sleep cycle. While the part is
converting, the BUSY pin is HIGH. Once the conversion is
complete, BUSY goes LOW indicating the conversion is
complete and data out is ready. The part now enters the
LOW power sleep state. BUSY remains LOW while data is
shifted out of the device and SDI is shifted into the device.
It goes HIGH at the conclusion of the data input/output
cycle indicating a new conversion has begun. This rising
edge may be used to flag the completion of the data read
cycle.
SERIAL INTERFACE TIMING MODES
The LTC2446/LTC2447’s 3- or 4-wire interface is SPI and
MICROWIRE compatible. This interface offers several flex-
ible modes of operation. These include internal/external
serial clock, 3- or 4-wire I/O, single cycle conversion and
autostart. The following sections describe each of these
serial interface timing modes in detail. In all these cases,
the converter can use the internal oscillator (F
O
= LOW) or
an external oscillator connected to the F
O
pin. Refer to
Table 5 for a summary.
Table 5. LTC2446/LTC2447 Interface Timing Modes
CONVERSION DATA CONNECTION
SCK CYCLE OUTPUT AND
CONFIGURATION SOURCE CONTROL CONTROL WAVEFORMS
External SCK, Single Cycle Conversion External CS and SCK CS and SCK Figures 4, 5
External SCK, 3-Wire I/O External SCK SCK Figure 6
Internal SCK, Single Cycle Conversion Internal CS ↓CS ↓Figures 7, 8
Internal SCK, 3-Wire I/O, Continuous Conversion Internal Continuous Internal Figure 9
APPLICATIO S I FOR ATIO
WUUU
LTC2446/LTC2447
15
24467fa
External Serial Clock, Single Cycle Operation
(SPI/MICROWIRE Compatible)
This timing mode uses an external serial clock to shift out
the conversion result and a CS signal to monitor and
control the state of the conversion cycle, see Figure 4.
The serial clock mode is selected by the EXT pin. To select
the external serial clock mode, EXT must be tied low.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
While CS is pulled LOW, EOC is output to the SDO pin.
EOC = 1 (BUSY = 1) while a conversion is in progress and
EOC = 0 (BUSY = 0) if the device is in the sleep state.
Independent of CS, the device automatically enters the low
power sleep state once the conversion is complete.
When the device is in the sleep state (EOC = 0), its
conversion result is held in an internal static shift regis-
ter. The device remains in the sleep state until the first
rising edge of SCK is seen. Data is
shifted out the SDO pin
on each falling edge of SCK. This enables external circuitry
to latch the output on the rising edge of SCK. EOC can be
latched on the first rising edge of SCK and the last bit of
the conversion result can be latched on the 32nd rising
edge of SCK. On the 32nd falling edge of SCK, the device
begins a new conversion. SDO goes HIGH (EOC = 1) and
BUSY goes HIGH indicating a conversion is in progress.
At the conclusion of the data cycle, CS may remain LOW
and EOC monitored as an end-of-conversion interrupt.
Alternatively, CS may be driven HIGH setting SDO to Hi-Z
and BUSY monitored for the completion of a conversion.
Figure 4. External Serial Clock, Single Cycle Operation
APPLICATIO S I FOR ATIO
WUUU
MSB
BIT 28 BIT 27 BIT 26 BIT 25 BIT 24 BIT 23 BIT 22 BIT 21 BIT 20 BIT 19 BIT 0
LSB Hi-Z
24467 F04
SIG
BIT 29
“0”
BIT 30
EOC
Hi-Z
CS
SCK
(EXTERNAL)
SDI
SDO
BUSY
BIT 31
1 0 EN SGL GLBL A1 A0 OSR3 OSR2 OSR1 OSR0 TWOXODD
1234567891011121314 32
CONVERSION SLEEP DATA OUTPUT CONVERSION
TEST EOC TEST EOC
V
CC
F
O
REF67
+
REF67
–
CH0
CH1
CH2
CH7
COM
REFG
+
REFG
–
REF01
+
REF01
–
SCK
SDI
SDO
CS
GND
28
29
30
11
10
35
24
23
8
9
12
22
7
38
37
1,4,5,6,31,32,33
36
34
USER SELECTABLE
REFERENCES
0.1V TO V
CC
ANALOG
INPUTS .
.
.
.
.
.
2
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
1µF
4.5V TO 5.5V
LTC2446
4-WIRE
SPI INTERFACE
BUSY
LTC2446/LTC2447
16
24467fa
output sequence is aborted prior to the 13th rising edge of
SCK, the new input data is ignored, and the previously
selected speed/resolution and channel are used for the
next conversion cycle.
This is useful for systems not
requiring all 32 bits of output data, aborting an invalid
conversion cycle or synchronizing the start of a conver-
sion. If a new channel is being programmed, the rising
edge of CS must come after the 14th falling edge of SCK
in order to store the data input sequence.
CS
SCK
(EXTERNAL)
SDI
SDO
BUSY
12345615
MSB
BIT 28 BIT 27 BIT 26 BIT 25
SIG
BIT 29
“0”
BIT 30
EOC
Hi-Z Hi-Z
BIT 31
24467 F05
CONVERSION SLEEP
SLEEP
DATA OUTPUT DATA OUTPUT
CONVERSION
CONVERSION
TEST EOC
DON'T CARE DON'T CARE
DON'T CARE
VCC FO
REF67+
REF67–
CH0
CH1
CH2
CH7
COM
REFG+
REFG–
REF01+
REF01–
SCK
SDI
SDO
CS
GND
28
29
30
11
10
35
24
23
8
9
12
22
7
38
37
1,4,5,6,31,32,33
36
34
USER SELECTABLE
REFERENCES
0.1V TO VCC
ANALOG
INPUTS .
.
.
.
.
.
2
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
1µF
4.5V TO 5.5V
LTC2446
4-WIRE
SPI INTERFACE
BUSY
As described above, CS may be pulled LOW at any time in
order to monitor the conversion status on the SDO pin.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
CS HIGH anytime between the fifth falling edge and the
32nd falling edge of SCK, see Figure 5. On the rising edge
of CS, the device aborts the data output state and imme-
diately initiates a new conversion.
Thirteen serial input
data bits are required in order to properly program the
speed/resolution and input/reference channel. If the data
APPLICATIO S I FOR ATIO
WUUU
Figure 5. External Serial Clock, Reduced Output Data Length
LTC2446/LTC2447
17
24467fa
APPLICATIO S I FOR ATIO
WUUU
External Serial Clock, 3-Wire I/O
This timing mode utilizes a 3-wire serial I/O interface. The
conversion result is shifted out of the device by an exter-
nally generated serial clock (SCK) signal, see Figure 6. CS
may be permanently tied to ground, simplifying the user
interface or isolation barrier. The external serial clock
mode is selected by tying EXT LOW.
Since CS is tied LOW, the end-of-conversion (EOC) can be
continuously monitored at the SDO pin during the convert
and sleep states. Conversely, BUSY (Pin 2) may be used
to monitor the status of the conversion cycle. EOC or BUSY
may be used as an interrupt to an external controller
Figure 6. External Serial Clock, CS = 0 Operation (3-Wire)
indicating the conversion result is ready. EOC = 1
(BUSY = 1) while the conversion is in progress and
EOC = 0 (BUSY = 0) once the conversion enters the low
power sleep state. On the falling edge of EOC/BUSY, the
conversion result is loaded into an internal static shift
register. The device remains in the sleep state until the
first rising edge of SCK. Data is shifted out the SDO pin
on each falling edge of SCK enabling external circuitry to
latch data on the rising edge of SCK. EOC can be latched
on the first rising edge of SCK. On the 32nd falling edge
of SCK, SDO and BUSY go HIGH (EOC = 1) indicating a
new conversion has begun.
CS
SCK
(EXTERNAL)
SDI
SDO
BUSY
24467 F06
CONVERSION SLEEP DATA OUTPUT CONVERSION
MSB
BIT 28 BIT 27 BIT 26 BIT 25 BIT 24 BIT 23 BIT 22 BIT 21 BIT 20 BIT 19 BIT 0
LSB
SIG
BIT 29
“0”
BIT 30
EOC
BIT 31
1 0 EN SGL GLBL A1 A0 OSR3 OSR2 OSR1 OSR0 TWOXODD
1234567891011121314 32
DON'T CAREDON'T CARE
V
CC
F
O
REF67
+
REF67
–
CH0
CH1
CH2
CH7
COM
REFG
+
REFG
–
REF01
+
REF01
–
SCK
SDI
SDO
CS
GND
28
29
30
11
10
35
24
23
8
9
12
22
7
38
37
1,4,5,6,31,32,33
36
34
USER SELECTABLE
REFERENCES
0.1V TO V
CC
ANALOG
INPUTS
.
.
.
.
.
.
2
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
1µF
4.5V TO 5.5V
LTC2446
3-WIRE
SPI INTERFACE
BUSY
LTC2446/LTC2447
18
24467fa
Internal Serial Clock, Single Cycle Operation
This timing mode uses an internal serial clock to shift out
the conversion result and a CS signal to monitor and
control the state of the conversion cycle, see Figure 7.
In order to select the internal serial clock timing mode, the
EXT pin must be tied HIGH.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
Once CS is pulled LOW, SCK goes LOW and EOC is output
to the SDO pin. EOC = 1 while a conversion is in progress
and EOC = 0 if the device is in the sleep state. Alternatively,
BUSY (Pin 2) may be used to monitor the status of the
conversion in progress. BUSY is HIGH during the conver-
Figure 7. Internal Serial Clock, Single Cycle Operation
sion and goes LOW at the conclusion. It remains LOW until
the result is read from the device.
When testing EOC, if the conversion is complete (EOC = 0),
the device will exit the sleep state and enter the data output
state if CS remains LOW. In order to prevent the device
from exiting the low power sleep state, CS must be pulled
HIGH before the first rising edge of SCK. In the internal
SCK timing mode, SCK goes HIGH and the device begins
outputting data at time t
EOCtest
after the falling edge of CS
(if EOC = 0) or t
EOCtest
after EOC goes LOW (if CS is LOW
during the falling edge of EOC). The value of t
EOCtest
is
500ns. If CS is pulled HIGH before time t
EOCtest
, the device
remains in the sleep state. The conversion result is held in
the internal static shift register.
APPLICATIO S I FOR ATIO
WUUU
MSB
BIT 28 BIT 27 BIT 26 BIT 25 BIT 24 BIT 23 BIT 22 BIT 21 BIT 20 BIT 19 BIT 0
LSB Hi-Z
244676 F07
SIG
BIT 29
“0”
BIT 30
EOC
Hi-Z
CS
SCK
SDI
SDO
BUSY
BIT 31
1 0 EN SGL GLBL A1 A0 OSR3 OSR2 OSR1 OSR0 TWOXODD
1234567891011121314 32
CONVERSION SLEEP DATA OUTPUT CONVERSION
TEST EOC TEST EOC
DON'T CARE DON'T CARE
<t
EOC(TEST)
V
CC
F
O
REF67
+
REF67
–
CH0
CH1
CH2
CH7
COM
REFG
+
REFG
–
REF01
+
REF01
–
SCK
SDI
SDO
CS
GND
28
29
30
11
10
35
24
23
8
9
12
22
7
38
37
1,4,5,6,31,32,33
36
34
USER SELECTABLE
REFERENCES
0.1V TO V
CC
ANALOG
INPUTS
.
.
.
.
.
.
2
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
1µF
4.5V TO 5.5V
LTC2446
4-WIRE
SPI INTERFACE
BUSY
LTC2446/LTC2447
19
24467fa
If CS remains LOW longer than t
EOCtest
, the first rising
edge of SCK will occur and the conversion result is serially
shifted out of the SDO pin. The data output cycle begins on
this first rising edge of SCK and concludes after the 32nd
rising edge. Data is shifted out the SDO pin on each falling
edge of SCK. The internally generated serial clock is output
to the SCK pin. This signal may be used to shift the
conversion result into external circuitry. EOC can be
latched on the first rising edge of SCK and the last bit of the
conversion result on the 32nd rising edge of SCK. After the
32nd rising edge, SDO goes HIGH (EOC = 1), SCK stays
HIGH and a new conversion starts.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
CS HIGH anytime between the first and 32nd rising edge
APPLICATIO S I FOR ATIO
WUUU
Figure 8. Internal Serial Clock, Reduced Data Output Length
of SCK, see Figure 8. On the rising edge of CS, the device
aborts the data output state and immediately initiates a
new conversion. This is useful for systems not requiring
all 32 bits of output data, aborting an invalid conversion
cycle, or synchronizing the start of a conversion. Thirteen
serial input data bits are required in order to properly
program the speed/resolution and input channel. If the
data output sequence is aborted prior to the 13th rising
edge of SCK, the new input data is ignored, and the
previously selected speed/resolution and channel are used
for the next conversion cycle.
If a new channel is being
programmed, the rising edge of CS must come after the
14th falling edge of SCK in order to store the data input
sequence.
CS
SCK
SDI
SDO
BUSY
12345615
MSB
BIT 28 BIT 27 BIT 26 BIT 25
SIG
BIT 29
“0”
BIT 30
EOC
Hi-Z Hi-Z
BIT 31
24467 F08
CONVERSION SLEEP
SLEEP
DATA OUTPUT DATA OUTPUT
CONVERSION
CONVERSION
TEST EOC
DON'T CARE DON'T CARE DON'T CARE
<tEOC(TEST)
<tEOC(TEST)
VCC FO
REF67+
REF67–
CH0
CH1
CH2
CH7
COM
REFG+
REFG–
REF01+
REF01–
SCK
SDI
SDO
CS
GND
28
29
30
11
10
35
24
23
8
9
12
22
7
38
37
1,4,5,6,31,32,33
36
34
USER SELECTABLE
REFERENCES
0.1V TO VCC
ANALOG
INPUTS
.
.
.
.
.
.
2
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
1µF
4.5V TO 5.5V
LTC2446
4-WIRE
SPI INTERFACE
BUSY
LTC2446/LTC2447
20
24467fa
APPLICATIO S I FOR ATIO
WUUU
Figure 9. Internal Serial Clock, Continuous Operation
Internal Serial Clock, 3-Wire I/O,
Continuous Conversion
This timing mode uses a 3-wire, all output (SCK and SDO)
interface. The conversion result is shifted out of the device
by an internally generated serial clock (SCK) signal, see
Figure 9. CS may be permanently tied to ground, simplify-
ing the user interface or isolation barrier. The internal
serial clock mode is selected by tying EXT HIGH.
During the conversion, the SCK and the serial data output
pin (SDO) are HIGH (EOC = 1) and BUSY = 1. Once the
conversion is complete, SCK, BUSY and SDO go LOW
(EOC = 0) indicating the conversion has finished and the
device has entered the low power sleep state. The part
remains in the sleep state a minimum amount of time
(≈500ns) then immediately begins outputting data. The
data output cycle begins on the first rising edge of SCK and
ends after the 32nd rising edge. Data is shifted out the SDO
pin on each falling edge of SCK. The internally generated
serial clock is output to the SCK pin. This signal may be
used to shift the conversion result into external circuitry.
EOC can be latched on the first rising edge of SCK and the
last bit of the conversion result can be latched on the 32nd
rising edge of SCK. After the 32nd rising edge, SDO goes
HIGH (EOC = 1) indicating a new conversion is in progress.
SCK remains HIGH during the conversion.
CS
SCK
SDI
SDO
BUSY
24467 F09
CONVERSION
SLEEP
DATA OUTPUT CONVERSION
MSB
BIT 28 BIT 27 BIT 26 BIT 25 BIT 24 BIT 23 BIT 22 BIT 21 BIT 20 BIT 19 BIT 0
LSB
SIG
BIT 29
“0”
BIT 30
EOC
BIT 31
1 0 EN SGL GLBL A1 A0 OSR3 OSR2 OSR1 OSR0 TWOXODD
1234567891011121314 32
DON'T CAREDON'T CARE
V
CC
F
O
REF67
+
REF67
–
CH0
CH1
CH2
CH7
COM
REFG
+
REFG
–
REF01
+
REF01
–
SCK
SDI
SDO
CS
GND
28
29
30
11
10
35
24
23
8
9
12
22
7
38
37
1,4,5,6,31,32,33
36
34
USER SELECTABLE
REFERENCES
0.1V TO V
CC
ANALOG
INPUTS
.
.
.
.
.
.
2
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
1µF
4.5V TO 5.5V
LTC2446
3-WIRE
SPI INTERFACE
BUSY
LTC2446/LTC2447
21
24467fa
Figure 11. LTC2446/LTC2447
Normal Mode Rejection (Internal Oscillator)
Figure 10. LTC2446/LTC2447
Normal Mode Rejection (Internal Oscillator)
APPLICATIO S I FOR ATIO
WUUU
Table 6. OSR vs Notch Frequency (fN) (with Internal Oscillator
Running at 9MHz)
OSR NOTCH (f
N
)
64 28.16kHz
128 14.08kHz
256 7.04kHz
512 3.52kHz
1024 1.76kHz
2048 880Hz
4096 440Hz
8192 220Hz
16384 110Hz
32768* 55Hz
*Simultaneous 50/60Hz rejection
Normal Mode Rejection and Antialiasing
One of the advantages delta-sigma ADCs offer over con-
ventional ADCs is on-chip digital filtering. Combined with
a large oversampling ratio, the LTC2446/LTC2447 signifi-
cantly simplify antialiasing filter requirements.
The LTC2446/LTC2447’s speed/resolution is determined
by the over sample ratio (OSR) of the on-chip digital filter.
The OSR ranges from 64 for 3.5kHz output rate to 32,768
for 6.9Hz (in 1x mode) output rate. The value of OSR and
the sample rate f
S
determine the filter characteristics of the
device. The first NULL of the digital filter is at f
N
and
multiples of f
N
where f
N
= f
S
/OSR, see Figure 10 and Table
6. The rejection at the frequency f
N
±14% is better than
80dB, see Figure 11.
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
0
–60
–40
0
180
24467 F10
–80
–100
60 120 240
–120
–140
–20
NORMAL MODE REJECTION (dB)
SINC4 ENVELOPE
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
47
–140
NORMAL MODE REJECTION (dB)
–130
–120
–110
–100
51 55 59 63
24467 F11
–90
–80
49 53 57 61
If F
O
is grounded, f
S
is set by the on-chip oscillator at
1.8MHz ±5% (over supply and temperature variations). At
an OSR of 32,768, the first NULL is at f
N
= 55Hz and the no
latency output rate is f
N
/8 = 6.9Hz. At the maximum OSR,
the noise performance of the device is 280nV
RMS
(LTC2446) and 200nV
RMS
(LTC2447) with better than
80dB rejection of 50Hz ±2% and 60Hz ±2%. Since the OSR
is large (32,768) the wide band rejection is extremely large
and the antialiasing requirements are simple. The first
multiple of f
S
occurs at 55Hz • 32,768 = 1.8MHz, see
Figure 12.
The first NULL becomes f
N
= 7.04kHz with an OSR of 256
(an output rate of 880Hz) and F
O
grounded. While the
NULL has shifted, the sample rate remains constant. As a
result of constant modulator sampling rate, the linearity,
Figure 12. LTC2446/LTC2447
Normal Mode Rejection (Internal Oscillator)
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
0
–60
–40
0
24467 F12
–80
–100
1000000 2000000
–120
1.8MHz
–140
–20
NORMAL MODE REJECTION (dB)
REJECTION > 120dB
LTC2446/LTC2447
22
24467fa
offset and full-scale performance remain unchanged as
does the first multiple of f
S
.
The sample rate f
S
and NULL f
N
, may also be adjusted by
driving the F
O
pin with an external oscillator. The sample
rate is f
S
= f
EOSC
/5, where f
EOSC
is the frequency of the
clock applied to F
O
. Combining a large OSR with a reduced
sample rate leads to notch frequencies f
N
near DC while
maintaining simple antialiasing requirements. A 100kHz
clock applied to F
O
results in a NULL at 0.6Hz plus all
harmonics up to 20kHz, see Figure 13. This is useful in
applications requiring digitalization of the DC component
of a noisy input signal and eliminates the need of placing
a 0.6Hz filter in front of the ADC.
Figure 13. LTC2446/LTC2447 Normal
Mode Rejection (External Oscillator at 90kHz)
APPLICATIO S I FOR ATIO
WUUU
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
0
–40
–20
0
8
24467 F13
–60
–80
246 10
–100
–120
–140
NORMAL MODE REJECTION (dB)
multiplexer. The unique no latency architecture allows
seamless changes in both input channel and reference
while the absolute accuracy ensures excellent matching
between both analog input channels and reference chan-
nels. Any set of inputs (differential or single-ended) can
perform a conversion with one of two references. For
Bridges, RTDs and other ratiometric devices, each set of
channels can perform a conversion with respect to a
unique reference voltage. For Thermocouples, voltage
sense, current sense and other absolute sensors, each set
of channels can perform a conversion with respect to a
single global reference voltage (see Figure 15). This allows
users to measure both multiple absolute and multiple ratio
metric sensors with the same device in such applications
as flow, gas chromatography, multiple RTDs or bridges,
or universal data acquisition.
Average Input Current
The LTC2446 switches the input and reference to a 2pF
capacitor at a frequency of 1.8MHz. A simplified equivalent
circuit is shown in Figure 16. The sample capacitor for the
LTC2447 is 4pF, and its average input current is externally
buffered from the input source.
The average input and reference currents can be ex-
pressed in terms of the equivalent input resistance of the
sample capacitor, where: Req = 1/(f
SW
• Ceq).
An external oscillator operating from 100kHz to 20MHz
can be implemented using the LTC1799 (resistor set
SOT-23 oscillator), see Figure 14. By floating pin 4 (DIV)
of the LTC1799, the output oscillator frequency is:
f MHz k
R
OSC SET
=⎛
⎝
⎜⎞
⎠
⎟
10 10
10
••
The normal mode rejection characteristic shown in
Figure 13 is achieved by applying the output of the LTC1799
(with R
SET
= 100k) to the F
O
pin on the LTC2446/LTC2447
with SDI tied HIGH (OSR = 32768).
Multiple Ratiometric and Absolute Measurements
The LTC2446/LTC2447 combine a high precision, high
speed delta-sigma converter with a versatile front-end
Figure 14. Simple External Clock Source
24467 F14
0.1µF
LTC1799
OUT
DIV SET
GND
V
+
R
SET
NC
V
CC
F
O
REF67
+
REF67
–
CH0
CH1
CH2
CH7
COM
REFG
+
REFG
–
REF01
+
REF01
–
SCK
SDI
SDO
CS
GND
28
29
30
11
10
35
24
23
8
9
12
22
7
38
37
1,4,5,6,31,32,33
36
34
USER SELECTABLE
REFERENCES
0.1V TO V
CC
ANALOG
INPUTS .
.
.
.
.
.
2
1µF
4.5V TO 5.5V
LTC2446
4-WIRE
SPI INTERFACE
BUSY
LTC2446/LTC2447
23
24467fa
APPLICATIO S I FOR ATIO
WUUU
Figure 15. Versatile 4-Way Multiplexer Measures Multiple Ratiometric/Absolute Sensors
Figure 16. LTC2446 Input Structure
When using the internal oscillator, f
SW
is 1.8MHz and the
equivalent resistance is approximately 110kΩ.
Input Bandwidth and Frequency Rejection
The combined effect of the internal SINC4 digital filter and
the digital and analog autocalibration circuits determines
the LTC2446/LTC2447 input bandwidth and rejection
characteristics. The digital filter’s response can be ad-
justed by setting the oversample ratio (OSR) through the
SPI interface or by supplying an external conversion clock
to the fo pin.
Table 7 lists the properties of the LTC2446/LTC2447 with
various combinations of oversample ratio and clock fre-
quency. Understanding these properties is the key to fine
tuning the characteristics of the LTC2446/LTC2447 to the
application.
V
REFG+
10µF
V
REFO1+
V
REFO1–
RTD CH0
CH1
LTC2446
V
REF
V
CC
V
REF23+
V
REF23–
IN
+
VARIABLE SPEED
RESOLUTION
24-BIT ∆Σ ADC
REF
+
IN
–
REF
–
RTD
RATIOMETRIC
ABSOLUTE
vs V
REFG
BRIDGE
CH2
CH3
V
REF45+
V
REF45–
CH4
CH5
COM
V
REFG
24467 F15
CH6
CH7
CS
+
–
SDI
SDO
SCK
V
REF
+
V
IN
+
V
CC
R
SW
(TYP)
500Ω
I
LEAK
I
LEAK
V
CC
I
LEAK
I
LEAK
V
CC
R
SW
(TYP)
500ΩC
EQ
5pF
(TYP)
(C
EQ
= 2pF
SAMPLE CAP
+ PARASITICS)
R
SW
(TYP)
500Ω
I
LEAK
I
IN
+
V
IN
–
I
IN
–
I
REF
+
I
REF
–
24467 F16
I
LEAK
V
CC
I
LEAK
I
LEAK
SWITCHING FREQUENCY
f
SW
= 1.8MHz INTERNAL OSCILLATOR
f
SW
= f
EOSC
/5 EXTERNAL OSCILLATOR
V
REF
–
R
SW
(TYP)
500Ω
MUX
MUX
LTC2446/LTC2447
24
24467fa
Maximum Conversion Rate
The maximum conversion rate is the fastest possible rate
at which conversions can be performed.
First Notch Frequency
This is the first notch in the SINC
4
portion of the digital filter
and depends on the f
o
clock frequency and the oversample
ratio. Rejection at this frequency and its multiples (up to the
modulator sample rate of 1.8MHz) exceeds 120dB. This is
8 times the maximum conversion rate.
Effective Noise Bandwidth
The LTC2446/LTC2447 has extremely good input noise
rejection from the first notch frequency all the way out to
the modulator sample rate (typically 1.8MHz). Effective
noise bandwidth is a measure of how the ADC will reject
wideband input noise up to the modulator sample rate. The
example on the following page shows how the noise
rejection of the LTC2446/LTC2447 reduces the effective
noise of an amplifier driving its input.
Example:
If an amplifier (e.g. LT1219) driving the input of an
LTC2446/LTC2447 has wideband noise of 33nV/√Hz,
band-limited to 1.8MHz, the total noise entering the
ADC input is:
33nV/√Hz • √1.8MHz = 44.3µV.
APPLICATIO S I FOR ATIO
WUUU
When the ADC digitizes the input, its digital filter rejects the
wideband noise from the input signal. The noise reduction
depends on the oversample ratio which defines the effec-
tive bandwidth of the digital filter.
At an oversample of 256, the noise bandwidth of the ADC
is 787Hz which reduces the total amplifier noise to:
33nV/√Hz • √787Hz = 0.93µV.
The total noise is the RMS sum of this noise with the 2µV
noise of the ADC at OSR=256.
√(0.93µV)
2
+ (2uV)
2
= 2.2µV.
Increasing the oversample ratio to 32768 reduces the
noise bandwidth of the ADC to 6.2Hz which reduces the
total amplifier noise to:
33nV/√Hz • √6.2Hz = 82nV.
The total noise is the RMS sum of this noise with the 200nV
noise of the ADC at OSR = 32768.
√(82nV)
2
+ (200nV)
2
= 216nV.
In this way, the digital filter with its variable oversampling
ratio can greatly reduce the effects of external noise
sources.
Table 7. Performance vs Over-Sample Ratio
MAXIMUM FIRST NOTCH EFFECTIVE –3dB
OVER- CONVERSION RATE FREQUENCY NOISE BW POINT (Hz)
SAMPLE *RMS *RMS ENOB INTERNAL INTERNAL INTERNAL INTERNAL
RATIO NOISE NOISE (V
REF
= 5V) 9MHz EXTERNAL 9MHz EXTERNAL 9MHz EXTERNAL 9MHz EXTERNAL
(OSR) LTC2446 LTC2447 LTC2446 LTC2447 CLOCK f
O
CLOCK f
O
CLOCK f
O
CLOCK f
O
64 23µV23µV 17 17 3515.6 f
O
/2560 28125 f
O
/320 3148 f
O
/5710 1696 f
O
/5310
128 4.5µV 3.5µV 20.1 20 1757.8 f
O
/5120 14062.5 f
O
/640 1574 f
O
/2860 848 f
O
/10600
256 2.8µV2µV 20.8 21.3 878.9 f
O
/10240 7031.3 f
O
/1280 787 f
O
/1140 424 f
O
/21200
512 2µV 1.4µV 21.3 21.8 439.5 f
O
/20480 3515.6 f
O
/2560 394 f
O
/2280 212 f
O
/42500
1024 1.4µV1µV 21.8 22.4 219.7 f
O
/40960 1757.8 f
O
/5120 197 f
O
/4570 106 f
O
/84900
2048 1.1µV 750nV 22.1 22.9 109.9 f
O
/81920 878.9 f
O
/1020 98.4 f
O
/9140 53 f
O
/170000
4096 720nV 510nV 22.7 23.4 54.9 f
O
/163840 439.5 f
O
/2050 49.2 f
O
/18300 26.5 f
O
/340000
8192 530nV 375nV 23.2 24 27.5 f
O
/327680 219.7 f
O
/4100 24.6 f
O
/36600 13.2 f
O
/679000
16384 350nV 250nV 23.8 24.4 13.7 f
O
/655360 109.9 f
O
/8190 12.4 f
O
/73100 6.6 f
O
/1358000
32768 280nV 200nV 24.1 24.6 6.9 f
O
/1310720 54.9 f
O
/16380 6.2 f
O
/146300 3.3 f
O
/2717000
*ADC noise increases by approximately √2 when OSR is decreased by a factor of 2 for OSR 32768 to OSR 256. The ADC noise at OSR 128 and OSR 64 include effects from internal modulator
quantization noise.
LTC2446/LTC2447
25
24467fa
Automatic Offset Calibration of External
Buffers/Amplifiers
The LTC2447 enables an external amplifier to be inserted
between the multiplexer output and the ADC input. This
enables one external buffer/amplifier circuit to be shared
between all nine analog inputs (eight single-ended or four
differential). The LTC2447 performs an internal offset
calibration every conversion cycle in order to remove the
offset and drift of the ADC. This calibration is performed
through a combination of front end switching and digital
processing. Since the external amplifier is placed between
the multiplexer and the ADC, it is inside the correction
loop. This results in automatic offset correction and offset
drift removal of the external amplifier.
The LT1368 is an excellent amplifier for this function.
It has rail-to-rail inputs and outputs, and it operates on a
single 5V supply. Its open-loop gain is 1M and its input
bias current is 10nA. It also requires at least a 0.1µF load
capacitor for compensation. It is this feature that sets
it apart from other amplifiers—the load capacitor
APPLICATIO S I FOR ATIO
WUUU
–
+
–
+
5V
0V
1/2 LT1368
1/2 LT1368
1
2
3
4
5
6
7
8
*LT1368 REQUIRES 0.1µF
OUTPUT COMPENSATION
CAPACITOR
MUX
MUXOUTN
MUXOUTP
ADCINP
ADCINN
9
24467 F17
(EXTERNAL AMPLIFIERS)
LTC2447
CH0-CH6/
COM
MUX
10
FIVE
DIFFERENTIAL
REFERENCE
INPUTS
SDI
SCK
SDO
CS
0.1µF*
OFFSETS AND 1/f NOISE
OF EXTERNAL SIGNAL
CONDITIONING CIRCUITS
ARE AUTOMATICALLY
CANCELLED
0.1µF*
HIGH
SPEED
∆Σ ADC
REF+
REF–
Figure 17. External Buffers Provide High Impedance Inputs and Amplifier Offsets are Cancelled
attenuates sampling glitches from the LTC2447 ADCIN
terminal, allowing it to achieve full performance of the
ADC with high impedance at the multiplexer inputs.
Another benefit of the LT1368 is that it can be powered
from supplies equal to or greater than that of the ADC.
This can allow the inputs to span the entire absolute
maximum of GND – 0.3V to VCC + 0.3V. Using a positive
supply of 7.5V to 10V and a negative supply of –2.5 to
–5V gives the amplifier plenty of headroom over the
LTC2447 input range.
Interfacing Sensors to the LTC2447
Figure 18 shows a few of the ways that the multiple
reference inputs of the LTC2447 greatly simplify sensor
interfacing. Each of the four references is fully differential
and has a differential range of 100mV to 5V. This opens up
many possibilities for sensing voltages and currents,
eliminating much of the analog signal conditioning cir-
cuitry required for interfacing to conventional ADCs.
LTC2446/LTC2447
26
24467fa
APPLICATIO S I FOR ATIO
WUUU
Figure 18a is a standard 350Ω, voltage excited strain gauge
with sense wires for the excitation voltage. REF01
+
and
REF01
–
sense the excitation voltage at the gauge, compen-
sating for voltage drop along the high current excitation
supply wires. This can be a significant error, as the exci-
tation current is 14mA when excited with 5V. Reference
loading capacitors at the ADC are necessary to average the
reference current during sampling. Both ADC inputs are
always close to mid-reference, and hence close to mid-
supply when using 5V excitation.
Figure 18b is a novel way to interface the LTC2447 to a bridge
that is specified for constant current excitation. The Fujikura
FPM-120PG is a 120psig pressure sensor that is not
trimmed for absolute accuracy, but is temperature compen-
sated for low drift when excited by a constant current source.
The LTC2447’s fully differential reference allows sensing
the excitation current with a resistor in series with the bridge
excitation. Changes in ambient temperature and supply
voltage will cause the current to vary, but the LTC2447
compensates by using the current sense voltage as its
reference. The input common mode will be slightly higher
than mid-reference, but still far enough away from the
positive supply to eliminate concerns about the buffer
amplifier’s headroom.
Figure 18c is an Omega 44018 linear output thermistor. Two
fixed resistors linearize the output from the thermistors. The
recommended 5700Ω series resistor is broken up into two
2850Ω resistors to give a differential output centered
around mid-reference. This ensures that the buffer ampli-
fiers have enough headroom at the negative supply. Note
that the excitation is 3V, the maximum recommended by
the manufacturer to prevent self-heating errors. The
LTC2447 senses this reference voltage.
Figure 18d shows a standard 100Ω platinum RTD. This
circuit shows how to use the LTC2447 to make a direct
resistance measurement, where the output code is the RTD
resistance divided by the reference resistance. A 500Ω
sense resistor allows measurement of resistance up to
250Ω. (A standard α = 0.00385 RTD has a resistance of
247.09Ω at 400°C.)
The LTC2446 multiplexes rail-to-rail inputs directly to the
ADC modulator and is suitable for low impedance resistive
sources such as 100Ω RTDs and 350Ω strain gauges that
are located close to the ADC. In applications where the
source resistance is high or the source is located more
than 5cm to 10cm from the ADC, the LTC2447 (with an
LT1368 buffer) is appropriate. The LTC2447 automatically
removes offset, drift and 1/f noise of the LT
®
1368. One
consideration for single supply applications is that both
ADC inputs should always be at least 100mV from the
LT1368’s supply rails. All of the applications shown in
Figure 18 are designed to keep both analog inputs far
enough away from ground and V
CC
so that the LT1368 can
operate on the same 5V supply as the LTC2447. Although
the LT1368 has rail-to-rail inputs and outputs, these
amplifiers still need some degree of headroom to work at
the resolution level of the LTC2447. For input signals
running rail-to-rail, the supply voltage of the LT1368 can
be increased in order to provide the extra headroom.
The LTC2446/LTC2447 reference have no such limitations
—they are truly rail-to-rail, and will even operate up to
300mV outside the supply rails. Reference terminals may
be connected directly to the ground plane or to a reference
voltage that is decoupled to the ground plane with a 1µF or
larger capacitor without any degradation of performance
provided the connection is less than 5cm from the LTC2446/
LTC2447. If the reference terminals are sensing a point
more than 5cm to 10cm away from the ADC, the reference
pins should be decoupled to the ground plane with 1µF
capacitors.
The reference terminals can also sense a resistive source
with a resistance up to 500Ω located close to the LTC2446/
LTC2447, however parasitic capacitance must be kept to
a minimum. If the sense point is more than 5cm from the
ADC, then it should be buffered. The LT1368 is also an
outstanding reference buffer. While offsets are not cancelled
as in the ADC input circuit, the 200mV offset and 2mV/°C
drift will not degrade the performance of most sensors. The
LT1369 is a quad version of the LT1368, and can serve as
the input buffer for an LTC2447 and two reference buffers.
LTC2446/LTC2447
27
24467fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
U
PACKAGE DESCRIPTIO
UHF Package
38-Lead Plastic QFN (5mm × 7mm)
(Reference LTC DWG # 05-08-1701)
5.00 ± 0.10
(2 SIDES)
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE
OUTLINE M0-220 VARIATION WHKD
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
PIN 1
TOP MARK
(SEE NOTE 6)
0.40 ± 0.10
37
1
2
38
BOTTOM VIEW—EXPOSED PAD
5.15 ± 0.10
(2 SIDES)
7.00 ± 0.10
(2 SIDES)
0.75 ± 0.05
R = 0.115
TYP
0.25 ± 0.05
(UH) QFN 1203
0.50 BSC
0.200 REF
0.200 REF
0.00 – 0.05
RECOMMENDED SOLDER PAD LAYOUT
3.15 ± 0.10
(2 SIDES) 0.18
0.18
0.23
0.435
0.00 – 0.05
0.75 ± 0.05
0.70 ± 0.05
0.50 BSC
5.20 ± 0.05 (2 SIDES)
3.15 ± 0.05
(2 SIDES)
4.10 ± 0.05
(2 SIDES)
5.50 ± 0.05
(2 SIDES)
6.10 ± 0.05 (2 SIDES)
7.50 ± 0.05 (2 SIDES)
0.25 ± 0.05
PACKAGE
OUTLINE
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
LTC2446/LTC2447
28
24467fa
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2004
LT/LT 0905 REV A • PRINTED IN USA
RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
LT1236A-5 Precision Bandgap Reference, 5V 0.05% Max, 5ppm/°C Drift
LT1461 Micropower Series Reference, 2.5V 0.04% Max, 3ppm/°C Max Drift
LTC1799 Resistor Set SOT-23 Oscillator Single Resistor Frequency Set
LTC2053 Rail-to-Rail Instrumentation Amplifier 10µV Offset with 50nV/°C Drift, 2.5µV
P-P
Noise 0.01Hz to 10Hz
LTC2412 2-Channel, Differential Input, 24-Bit, No Latency ∆Σ ADC 0.16ppm Noise, 2ppm INL, 200µA
LTC2415 1-Channel, Differential Input, 24-Bit, No Latency ∆Σ ADC 0.23ppm Noise, 2ppm INL, 2x Speedup
LTC2414/LTC2418 4-/8-Channel, Differential Input, 24-Bit, No Latency ∆Σ ADC 0.2ppm Noise, 2ppm INL, 200µA
LTC2430/LTC2431 1-Channel, Differential Input, 20-Bit, No Latency ∆Σ ADC 0.56ppm Noise, 3ppm INL, 200µA
LTC2436-1 2-Channel, Differential Input, 16-Bit, No Latency ∆Σ ADC 800nV
RMS
Noise, 0.12LBS INL, 0.006LBS Offset, 200µA
LTC2440 1-Channel, Differential Input, High Speed/Low Noise, 2µV
RMS
Noise at 880Hz, 200nV
RMS
Noise at 6.9Hz,
24-Bit, No Latency ∆Σ ADC 0.0005% INL, Up to 3.5kHz Output Rate
LTC2444/LTC2445 8-/16-Channel, Differential Input, High Speed/Low Noise, 2µV
RMS
Noise at 1.76kHz, 200nV
RMS
Noise at 13.8Hz,
LTC2448/LTC2449 24-Bit, No Latency ∆Σ ADC 0.0005% INL, Up to 8kHz Output Rate
APPLICATIO S I FOR ATIO
WUUU
Figure 18. Muxed Inputs/References Enable Multiple Ratiometric Measurements with the Same Device
GND
5V
5V
(18b) Full-Bridge, Current Sense
375Ω
CH3
+–
FULL-SCALE OUTPUT = 60mV TO 140mV
SELECT FOR V > 2 • 140mV
AT MAXIMUM BRIDGE RESISTANCE
FUJIKURA FPM-120PG
(4k TO 6k IMPEDANCE)
CH2
V
REF23+
V
REF23–
GND
5V
5V
OMEGA 44018
LINEAR
THERMISTOR
COMPOSITE
THERMISTOR
(18a) Full-Bridge, Voltage Sense
(18d) Half-Bridge, Current Sense(18c) Half-Bridge, Voltage Sense
CH0
1µF
1µF
350Ω
LOAD CELL
+–
FULL-SCALE OUTPUT = 10mV
CH1
V
REF01+
V
REF45+
CH5
CH4
V
REF45–
2850Ω
V
REF01–
1µF
LT1790-3
GND
GND
2850Ω
12.4k
T2 T1
100Ω RTD
CH7
CH6
V
REF67–
24467 F18
V
REF67+
R
ILIM
GND
500Ω
SENSOR
100Ω AT 0°C
247.09Ω AT 400°C
