Si9168
Vishay Siliconix
New Product
Document Number: 70899
S-00022—Rev. A, 10-Jan--00 www.siliconix.com FaxBack 408-970-5600
1
Synchronous Buck or Boost Controller for 2-Cell Li+ Battery
Operated Portable Communication Devices
Voltage Mode Control
5-V to 10-V Input Voltage Range for VDD
5-V to 12.6-V Input Voltage Range for VS – Boost
Programmable PWM/PSM Control
– Up to 2-MHz Switching Frequency in PWM
– Synchronous Rectification in PWM
– Less than 350-A IDD in PSM
Very High Efficiencies In Buck or Boost Modes
Low Dropout Operation at 100% Duty Cycle In Buck
Mode
Integrated UVLO and POR
Integrated Soft-Start
Synchronization
Logic Controlled Micropower Shutdown Current <2 A
Fast Line and Load Transient Response
Available in 16-Lead TSSOP Package
Cellular Telephones
Wireless Modems
Portable Instruments
Notebook and Palmtop Computers
PDA’s
Battery Operated Devices
The Si9168 is a synchronous buck or boost controller for 2-cell
Li+ battery operated portable communication devices.
Designed for use with external high-frequency MOSFETs, the
Si9168 is ideal for providing power to various power amplifiers
such as TDMA, CDMA, GSM, or PCS. For ultra-high efficiency,
converters are designed to operate in synchronous rectified
PWM mode under full load, while transforming into externally
controlled pulse skipping mode (PSM) under light load
conditions. All these features are provided by Si9168 without
sacrificing system integration requirements of fitting these
circuits into ever demanding smaller space. The Si9168 is
capable of switching up to 2 MHz to minimize the size of the
output inductor and capacitor , in order to decrease the overall
converter footprint. The programmability to design a buck or
boost converter with this IC makes it convenient to power
either the high voltage (7.2-V) or low voltage (4-V) PAs.
The Si9168 is available in TSSOP-16 pin package and
specified to operate over the industrial temperature range of
–25C to 85C.
1.3 V 10 V
SMPS
1.3 V
V oltage Reference
Shutdown
Control
SD
VOUT
(1.3 10 V)
VREF
(1.3 V)
5 V 12.6 V
SMPS
1.3 V
V oltage Reference
Shutdown
Control
SD
VOUT
(5 12.6 V)
VREF
(1.3 V)
Buck Mode Boost Mode
VIN
(5 – 10 V)
VIN
(5 – 10 V)
Si9168
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2Document Number: 70899
S-00022—Rev. A, 10-Jan--00
Voltages Referenced to AGND
VDD 13.2 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VSS–VDD 2 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PWM/PSM, SYNC, SD, VREF, ROSC, COMP, FB, Mode–0.3 V to VDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VO.–0.3 V to VS + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PGND ."0.3V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltages Referenced to PGND
VS. 13.2 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DH, DL–0.3 V to VS + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peak Output Current (DH, DL)1 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage Temperature .–65 to 150C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Junction Temperature 150C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Dissipation (Package)a
16-Pin TSSOP (Q Suffix)b925 mW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Impedance (QJA)
16-Pin TSSOP 135C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Notes
a. Device mounted with all leads soldered or welded to PC board.
b. Derate 7.4 mW/C above 25C.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only , and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
Voltages Referenced to AGND
VDD 5 V to 10 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FOSC 200 kHz to 2 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ROSC .25 kW to 300 kW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PWM/PSM, SYNC, SD, Mode 0 V to VDD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VREF 0.1 mF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltages Referenced to PGND
VS 5.0 V to 10 V (Buck). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VS 5.0 V to 12.6 V (Boost). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Test Conditions
Unless Otherwise S
p
ecified
Limits
–25C to 85C
Parameter Symbol
Unless
Otherwise
Specified
5 V v VDD, VS v 10 V MinaTypbMaxaUnit
Reference
Output V oltage
VREF
IREF = 0 A 1.268 1.3 1.332
V
Output
Voltage
V
REF VDD = 7.2 V, 25C 1.280 1.3 1.320
V
VREF Current IREF –500 mA
Power Supply Rejection PSRR 60 dB
UVLO
Under V oltage Lockout
(Turn-On) VUVLO/LH 4.3 4.5 4.7 V
Hysteresis VHYS 0.2
Soft-Start Time
SS Time tSS 3ms
SD, SYNC, PWM/PSM
Logic High VIH 2.4
V
Logic Low VIL 0.8
V
Input Current IL–1.0 1.0 mA
Mode
Logic High VIH 70% VDD
V
Logic Low VIL 30% VDD
V
Input Current IL–1.0 1.0 mA
Si9168
Vishay Siliconix
New Product
Document Number: 70899
S-00022—Rev. A, 10-Jan--00 www.siliconix.com FaxBack 408-970-5600
3
Limits
–25C to 85C
Test Conditions
Unless Otherwise Specified
5 V v VDD, VS v 10 V
Parameter UnitMaxa
Typb
Mina
Test Conditions
Unless Otherwise Specified
5 V v VDD, VS v 10 V
Symbol
Oscillator
Maximum Frequency FMAX 2MHz
Accuracy 1% External Resistor –20 20
%
Maximum Duty Cycle
(Buck, Non LDO Mode) DMAX FSW = 2 MHZ 75 80 %
Maximum Duty Cycle (Boost)
MAX
ROSC = 130 kW, VDD = 5 V, VS = 12.6 V 65 71
SYNC Range FSYNC/FOSC 1.2 1.5
SYNC Low Pulse Width 50
SYNC High Pulse Width 50 ns
SYNC tr, tf tr, tf50
Error Amplifier
Input Bias Current IBIAS VFB = 1.4 V –1 1 mA
Open Loop V oltage Gain AVOL 50 60 dB
Offset Voltage VOS –10 10 mV
Unity Gain BW BW 2 MHz
Output Current (Source)
IEA
VFB = 1.05 V –2 –1
mA
Output Current (Sink)
I
EA VFB = 1.55 V 1 3
mA
Power Supply Rejection PSRR 60 dB
PSM Modulator
Switch On Time t ON
VDD
=
7.2 V, VOUT
=
3.3 V, Buck Mode
180
ns
Switch Off Blanking Time tOFF
V
DD =
7
.
2
V
,
V
OUT =
3
.
3
V
,
Buck
Mode
330
ns
Output Drive (DH and DL)
Output High Voltage VOH VS = 7.2 V, IOUT = –20 mA 7.08 7.14
V
Output Low Voltage VOL VS = 7.2 V, IOUT = 20 mA 0.06 0.12
V
Peak Output Source ISOURCE
VS
=
7.2 V, DH
=
DL = VS/2
–1000 –500
mA
Peak Output Sink ISINK
V
S =
7
.
2
V
,
D
H =
D
L =
V
S
/2
500 1000
mA
Break-Before-Make tBBM VS = VDD = 10 V 40 ns
Supply
Normal Mode
I
VDD = 7.2 V, fOSC = 2 MHz 1100
A
PSM Mode IDD VDD = 7.2 V 350 mA
Shutdown Mode VDD = 7.2 V, SD = 0 V 2.0
Notes
a. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
b. T ypical values are for DESIGN AID ONL Y, not guaranteed or subject to production testing.
c. Guaranteed by design and characterization, not subject to production testing.
Si9168
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New Product
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4Document Number: 70899
S-00022—Rev. A, 10-Jan--00
1.7
1.8
1.9
2.0
2.1
2.2
–50 0 50 100
Temperature (C)
Frequency vs. Temperature
Frequency (MHz)
VDD = 7.2 V
ROSC = 25 kW
70
74
78
82
86
90
94
98
400 600 800 1000 1200 1400 1600 1800 2000 2200
Max Duty Cycle vs. Frequency (Buck Mode)
1.28
1.284
1.288
1.292
1.296
1.300
1.304
1.308
1.312
1.316
1.320
–50 –25 0 25 50 75 100
VREF vs. Temperature
Temperature (C)
(V)VREF
1.29
1.292
1.294
1.296
1.298
1.300
1.302
1.304
1.306
1.308
1.310
4 6 8 10 12 14
VREF vs. VDD
VDD – (V)
(V)VREF
% Max Duty Cycle
Frequency (kHz)
VIN = 7.2 V
100
1000
10000
10 100 1000
ROSC (kW)
Frequency vs. ROSC
Frequency (kHz)
42
46
50
54
58
62
66
70
74
400 600 800 1000 1200 1400 1600 1800 2000 2200
Max Duty Cycle vs. Frequency (Boost Mode)
% Max Duty Cycle
Frequency (kHz)
VIN = 7.2 V
VDD = 7.2 V
Si9168
Vishay Siliconix
New Product
Document Number: 70899
S-00022—Rev. A, 10-Jan--00 www.siliconix.com FaxBack 408-970-5600
5
50
60
70
80
90
100
10 100 1000 10000
200
400
600
800
1000
1200
1400
4 6 8 10 12 14
200
400
600
800
1000
1200
1400
4 6 8 10 12 14
PWM Supply Current vs. VDD (Buck Mode) PWM Supply Current vs. VDD (Boost Mode)
VDD – (V) VDD – (V)
(I DD (mA)
(I DD (mA)
50
100
150
200
250
300
4 6 8 10 12 14
50
100
150
200
250
300
4 6 8 10 12 14
PSM Supply Current vs. VDD (Buck Mode) PSM Supply Current vs. VDD (Boost Mode)
VDD – (V) VDD – (V)
(I DD (mA)
(I DD (mA)
Efficiency —Boost, VOUT = 7.2 V
Load Current (mA)
Efficiency (%)
PSM: 7.0 VIN
PSM: 5.4 VIN
PSM: 6.0 VIN
PWM: 5.4 VIN
PWM: 6.0 VIN
PWM: 7.0 VIN
FOSC = 1.6 MHz FOSC = 1.6 MHz
50
60
70
80
90
100
10 100 1000 10000
Efficiency —Buck, VOUT = 3.6 V
Load Current (mA)
Efficiency (%)
PSM = 5 VIN
PWM = 5 VIN
PWM = 7.2 VIN
PSM = 7.2 VIN
PSM = 8.4 VIN
PWM = 8.4 VIN
16
15
14
13
1
2
3
4
12
11
10
9
5
6
7
8
MODE VS
DLN/C
PGND DH
SD PWM/PSM
VOSYNC
VDD GND
ROSC VREF
COMP FB
TSSOP-16
Top View
Si9168BQ
Si9168
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New Product
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6Document Number: 70899
S-00022—Rev. A, 10-Jan--00
Part Number Temperature Range Package
Si9168BQ-T1 –25 to 85CTape and Reel
Eval Kit Temperature Range Board Type
Si9168DB –25 to 85CSurface Mount
Pin Number Name Function
1 MODE Determines the converter topology. Connect to AGND for buck or VDD for boost.
2 DLThe gate drive output for the low-side n-channel MOSFET for buck and boost converter
3 PGND Power ground for output drive stage
4 SD Logic low shuts down the IC completely and decreases the current consumption of IC to <2 A.
5 VODirect output voltage sense
6 VDD Input supply voltage for the analog circuit. VDD voltage should be the ac filtered voltage of VSS. Input voltage range
is 5 V to 10 V.
7 ROSC External resistor to determine the switching frequency.
8 COMP Error amplifier output for external compensation network.
9 FB Output voltage feedback connected to the inverting input of an error amplifier .
10 VREF 1.3-V reference voltage. Connected internally to non-inverting error amplifier input. Decouple with 0.1-F ceramic
capacitor.
11 GND Low power controller ground
12 SYNC Externally controlled synchronization signal. Logic high to low transition forces the clock synchronization. If not used,
the pin must be connected to VDD, or logic high.
13 PWM/PSM Logic high = PWM mode, logic low = PSM mode. In PSM mode, synchronous rectification drive is disabled.
14 DHThe gate drive output for the high-side p-channel MOSFET for buck and boost converter
15 N/C Not used.
16 VSSupply voltage for the output driver section. Voltage range is 5 V to 10 V (Buck), 5 to 12.6 V (Boost).
Si9168
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New Product
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FIGURE 1.
Reference
Threshold
Generator
Soft-Start
Timer
Oscillator
COSC
UVLO POR Bias
Generator
System Monitor
Drivers
PWMIN
PSMIN
PWM/PFM
Select
PWMIN
PSMIN
PWM
Modulator
PSM
Modulator
0.5 V
1.0 V
Ramp
VREF
VO
FB
COMP
SYNC
ROSC
MODE
PWM/PSM
GND
VDD SD
DL
Negative Return
and
Substrate
Positive Supply
1.3 V
PGND
DH
VS
Start-Up
The UVLO circuit prevents the controller output driver and
oscillator circuit from turning on, if the voltage on VDD pin is less
than 4.5 V. With typical UVLO hysteresis of 0.2 V, the
controller is continuously powered on until the VDD voltage
drops below 4.3 V. This hysteresis prevents the converter
from oscillating during the start-up phase and unintentionally
locking up the system. Once the VDD voltage exceeds the
UVLO threshold, and with no other shutdown condition
detected, an internal power-on-reset timer is activated while
most circuitry, except the output driver, are turned on. After the
POR time-out of about 1 ms, the internal soft-start capacitor is
allowed to charge. When the soft-start capacitor voltage
reaches 0.5 V, the PWM circuit is enabled. Thereafter, the
constant current charging of the soft-start capacitor will force
the converter output voltage to rise gradually without
overshooting. To prevent negative undershoot, the
synchronous switch is tri-stated until the duty cycle reaches
about 10%. See start-up timing diagram. In tri-state, the
high-side p-channel MOSFET is turned off by pulling up the
gate voltage (DH) to VS potential. The low-side n-channel
MOSFET is turned off by pulling down the gate voltage (DL) to
PGND potential. Note that Si9168 will always soft starts in the
PWM mode regardless of the voltage level on the PWM/PSM
pin.
Shutdown
Si9168 is designed to conserve as much battery life as
possible by decreasing current consumption of IC during
normal operation as well as the shutdown mode. With logic low
level on the SD pin, current consumption of the Si9168
decreases to less than 2 A by shutting off most of the circuits.
The logic high enables the controller and starts up as
described in “Start-Up” section above.
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PWM Mode
With PWM/PSM mode pin in logic high condition, Si9168
operates in constant frequency (PWM) mode. As the load and
input voltage vary, switching frequency remain constant. The
switching frequency is programmed by the ROSC value as
shown by the oscillator curve. In the PWM mode, the
synchronous drive is always enabled, even when the output
current reaches 0 A. In continuous current mode, the transfer
function of the converter remain constant providing fast
transient response. If the converter operates in discontinuous
current mode, overall loop gain decreases and transient
response time can be 10 times longer than if the converter
remain in continuous current mode. This transient response
time advantage can significantly decrease the hold-up
capacitors needed on the output of dc-dc converter to meet the
transient voltage regulation. Therefore, the PWM/PSM pin is
available to dynamically program the controller. If the
synchronous rectifier switch is not used, the converter may not
operate in PWM mode if the load current is low enough to force
the converter into pulse skipping mode.
The maximum duty cycle of the Si9168 can reach 100% in
buck mode. The duty cycle will continue to increase as the
input voltage decreases until it reaches 100%. This allows the
system designers to extract out the maximum stored energy
from the battery. Once the controller delivers 100% duty cycle,
the converter operates like a saturated linear regulator. At
100% duty cycle, synchronous rectification is completely
turned off. At up to 80% duty cycle at 2-MHz switching
frequency, the controller maintains perfect output voltage
regulation. If the input voltage drops below the level where the
converter requires greater than 80% duty cycle, the controller
will deliver 100% duty cycle. This instantaneous jump in duty
cycle is due to fixed BBM time and the internal propagation
delays. In order to maintain regulation, the controller might
fluctuate its duty cycle back and forth from 100% to something
lower than 80% during this input voltage range. If the input
voltage drops further, the controller will remain on for 100%
duty cycle. If the input voltage increases to a point where it’s
requiring less than 80% duty cycle, synchronous rectification
is once again activated.
The maximum duty cycle under boost mode is internally limited
to 75% to prevent inductor saturation. If the converter is turned
on for 100% duty cycle, the inductor never gets a chance to
discharge its energy and eventually saturate. In boost mode, the
synchronous rectifier is always turned on for minimum or greater
duration as long as the switch has been turned on. The controller
will deliver 0% duty cycle, if the input voltage is greater than the
programmed output voltage. Because of fixed BBM time, the
controller will not transition smoothly from minimum controllable
duty cycle to 0% duty cycle. For example, controller may
decrease its duty cycle from 5% to 0% abruptly, instead of the
gradual decrease seen from 75% to 5%.
Pulse Skipping Mode
The gate charge losses produced from the Miller capacitance
of MOSFETs are the dominant power dissipation parameter
during light load (i.e. < 200 mA). Therefore, less gate switching
will improve overall converter efficiency. This is exactly why
the Si9168 is designed with pulse skipping mode. If the
PWM/PSM pin is connected to logic low level, converter
operates in pulse skipping modulation (PSM) mode. During
the pulse skipping mode, quiescent current of the controller is
decreased to approximately 350 A, instead of 900 A during
the PWM mode. This is accomplished by turning off most of the
internal control circuitry and utilizing a simple constant on-time
control with the feedback comparator. The controller is
designed to have a constant on-time and a minimum off-time
acting as the feedback comparator blanking time. If the output
voltage drops below the desired level, the main switch is first
turned on and then off. If the applied on-time is insuf ficient to
provide the desired voltage, the controller will force another on
and off sequence, until the desired voltage is accomplished.
If the applied on-time forces the output to exceed the desired
level, as typically found in the light load condition, the converter
stays off. The excess energy is delivered to the output slowly ,
forcing the converter to skip pulses as needed to maintain
regulation. The on-time and off-time are set internally based
on the inductor used (2-H typical) and the maximum load
current. Therefore, with this control method, duty cycles
ranging from 0 to 100% are possible depending on whether the
boost or buck mode is chosen.
Reference
The reference voltage for the Si9168 is set at 1.3 V. The
reference voltage is internally connected to the non-inverting
inputs of the error amplifier. The REF pin requires a 0.1-F
decoupling capacitor.
Error Amplifier
The error amplifier gain-bandwidth product and slew rate are
critical parameters which determines the transient response of
converter. The transient response is function of both small and
large signal responses. The small signal response is
determined by the feedback compensation network while the
large signal is determined by the error amplifier dv/dt and the
inductor di/dt slew rate. Besides the inductance value, the
error amplifier determines the converter response time. In
order to minimize the response time, Si9168 is designed with
a 2-MHz error amplifier gain-bandwidth product to generate
the widest converter bandwidth and a 3.5-V/sec slew rate for
ultra-fast large signal response.
Oscillator
The oscillator is designed to operate up to 2-MHz minimum.
The 2-MHz operating frequency allows the converter to
minimize the inductor and capacitor size, improving the power
density of the converter. Even with a 2-MHz switching
frequency, quiescent current is only 1100 A (max) with the
unique power saving circuit design. The switching frequency
is easily programmed by attaching a resistor to the ROSC pin.
See oscillator frequency versus Rosc curve to select the
proper timing values for the desired operating frequency . The
tolerance on the operating frequency is "20% with a 1%
tolerance resistor.
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Document Number: 70899
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9
Synchronization
The synchronization to external clock is easily accomplished
by connecting the external clock into the SYNC pin. The logic
high to low transition synchronizes the clock. The external
clock frequency must be within 1.2 to 1.5 times the internal
clock frequency.
Break-Before-Make Timing
A proper BBM time is essential in order to prevent
shoot-through current and to maintain high efficiency. The
break-before-make time is set internally at 20 to 60 ns @
VS = 7.2 V. The high- and low-side gate drive voltages are
monitored and when the gate-to-source voltage reaches 3.5 V
above or below the initial starting voltage, 20- to 60-ns BBM
time is set before the other gate drive transitions to its proper
state. The maximum and minimum duty cycle is limited by the
BBM time. Since the BBM time is fixed, controllable maximum
duty cycle will vary depending on the switching frequency.
Output Driver Stage
The DH pin is designed to drive the main switch MOSFET and
DL pin is designed to drive the synchronous rectifier MOSFET.
The driver stage is sized to sink and source peak currents up
to 1000 mA with VS = 7.2 V. The ringing from the gate drive
output trace inductance can produce negative voltage on the
DH and DL respect to PGND. The gate drive circuit is capable
of withstanding these negative voltages without any functional
defects.
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10 Document Number: 70899
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FIGURE 2. 1.5-A Buck Regulator Using the Si9168BQ
R1*
51 W
C3
0.1 mF
C2
10 mF
10 V
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Si9168BQ
U1
2, 3
VIN
5-10 V
VOUT
3.6 V
1.5 A
C4
330 pF
C8
0.1 mF
C6
1 nF C7
56 pF
C5
0.1 mF
6, 7
8
1
4
C1
22 mF
16 V
R5
75 kW
R8*
5.6 W
R9*
5.6 W
5
R6
8.2 kW
Q1B
Si6803DQ
Q1A
Si6803DQ
R2
200 W
R3
22 kW
R4
12.4 kW
L1, 4.7 mH
IHLP2525
D1
MBR0520T1
C9
0.1 mF
MODE
DL
PGND
SD
VOUT
VDD
ROSC
COMP
VS
NC
DH
PWM/PSM
GND
VREF
FB
SYNC
COM
COM
PWM/PSM to VIN for PWM mode;
PWM/PSM to GND for PSM mode.
SD to VIN for converter enable mode;
SD to GND for shutdown mode.
* = Optional
C1
10 mF
16 V
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
U1
VIN
5-7.2 V
C2
47 mF
16 V C3
0.1 mF
Q1
SI9803DY
C4
560 pF
C8
0.1 mF
C6
5.6 nF C7
220 pF
C5
0.1 mF
4
R1*
51 W
R5
75 kW
1, 2, 3
R6
4.7 kW
R3
56.2 kW
R2
1 kW
R4
12.4 kW
5, 6, 7, 8
3
4
1, 2, 5, 6
Q2
Si3442DV
D1
B130LB
L1, 4.7 mH
IHLP2525
Si9168
VOUT
7.2 V
2.5 A
MODE
DL
PGND
SD
VOUT
VDD
ROSC
COMP
VS
NC
DH
PWM/PSM
GND
VREF
FB
SYNC
COM
COM
PWM/PSM to VIN for PWM mode;
PWM/PSM to GND for PSM mode.
SD to VIN for converter enable mode;
SD to GND for shutdown mode.
* = Optional
FIGURE 3. Si9168BQ Boost Regulator Application
Legal Disclaimer Notice
Vishay
Document Number: 91000 www.vishay.com
Revision: 08-Apr-05 1
Notice
Specifications of the products displayed herein are subject to change without notice. Vishay Intertechnology, Inc.,
or anyone on its behalf, assumes no responsibility or liability for any errors or inaccuracies.
Information contained herein is intended to provide a product description only. No license, express or implied, by
estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Vishay's
terms and conditions of sale for such products, Vishay assumes no liability whatsoever, and disclaims any express
or implied warranty, relating to sale and/or use of Vishay products including liability or warranties relating to fitness
for a particular purpose, merchantability, or infringement of any patent, copyright, or other intellectual property right.
The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications.
Customers using or selling these products for use in such applications do so at their own risk and agree to fully
indemnify Vishay for any damages resulting from such improper use or sale.
Vishay Siliconix
Package Information
Document Number: 74417
23-Oct-06
www.vishay.com
1
Symbols
DIMENSIONS IN MILLIMETERS
Min Nom Max
A - 1.10 1.20
A1 0.05 0.10 0.15
A2 - 1.00 1.05
B 0.22 0.28 0.38
C - 0.127 -
D 4.90 5.00 5.10
E 6.10 6.40 6.70
E1 4.30 4.40 4.50
e-0.65-
L 0.50 0.60 0.70
L1 0.90 1.00 1.10
y--0.10
θ10°3°6°
ECN: S-61920-Rev. D, 23-Oct-06
DWG: 5624
TSSOP: 16-LEAD
PAD Pattern
www.vishay.com Vishay Siliconix
Revision: 02-Sep-11 1Document Number: 63550
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
RECOMMENDED MINIMUM PAD FOR TSSOP-16
0.281
(7.15)
Recommended Minimum Pads
Dimensions in inches (mm)
0.171
(4.35)
0.055
(1.40)
0.012
(0.30)
0.026
(0.65)
0.014
(0.35)
0.193
(4.90)
Legal Disclaimer Notice
www.vishay.com Vishay
Revision: 12-Mar-12 1Document Number: 91000
Disclaimer
ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE
RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.
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