Qualcomm Technologies, Inc. WCD9335 Audio Codec Device Specification LM80-P2751-29 Rev. A February 8, 2018 For additional information or to submit technical questions, go to: https://www.96boards.org/product/dragonboard820c/ Qualcomm Snapdragon and Qualcomm Snapdragon Voice Activation are products of Qualcomm Technologies, Inc. Other Qualcomm products referenced herein are products of Qualcomm Technologies, Inc. or its other subsidiaries. DragonBoard, Qualcomm, and Snapdragon are trademarks of Qualcomm Incorporated, registered in the United States and other countries. Other product and brand names may be trademarks or registered trademarks of their respective owners. Use of this document is subject to the license set forth in Exhibit 1. Qualcomm Technologies, Inc. 5775 Morehouse Drive San Diego, CA 92121 U.S.A. (c) 2018 Qualcomm Technologies, Inc. All rights reserved. Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1 1.2 1.3 1.4 1.5 1.6 2 Pad definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.1 2.2 3 Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Summary of key features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 WCD9335 detailed functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Supply voltage summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Terms and acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 I/O parameter definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Pad descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.1 3.2 3.3 3.4 3.5 3.6 3.7 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC power characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.1 Peak current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital logic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Audio inputs and Tx processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.1 Analog input through digital serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.2 DMIC input through digital serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . Audio outputs and Rx processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.1 Digital serial interface through earpiece analog output . . . . . . . . . . . . . . . . . . 3.6.2 Digital serial interface through HPH output . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.3 Digital serial interface through stereo hi-fi differential line outputs . . . . . . . . . 3.6.4 Digital serial interface through single-ended line output . . . . . . . . . . . . . . . . . Digital I/Os and digital processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7.1 SLIMbus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 22 23 23 23 23 24 25 27 27 29 31 32 33 34 3.7.2 Inter-IC sound (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.8 LM80-P2751-29 Rev. A 3.7.3 Inter-integrated circuit (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7.4 Digital microphone PDM interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7.5 Master clock (MCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7.6 SoundWire . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Support circuits - analog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 36 37 37 39 2 WCD9335 Audio Codec Device Specification Contents 3.8.1 Microphone bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 4 Device marking and ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 4.1 5 Carrier, storage, & handling information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5.1 5.2 5.3 6 Carrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.1 Tape and reel information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.1 Bagged storage conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.2 Out-of-bag duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.1 Baking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.2 Electrostatic discharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 43 44 44 44 44 44 45 PCB mounting guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6.1 7 Device ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 4.1.1 Specification-compliant devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 RoHS compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Device reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 7.1 LM80-P2751-29 Rev. A Reliability qualifications summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3 WCD9335 Audio Codec Device Specification Contents Figures Figure 1-1 Figure 1-2 Figure 2-1 Figure 3-1 Figure 3-2 Figure 3-3 Figure 3-4 Figure 4-1 Figure 4-2 Figure 5-1 Figure 5-2 LM80-P2751-29 Rev. A WCD9335 high-level block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 WCD9335 detailed functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 WCD9335 pad assignments (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Received clock signal constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 WCD9335 digital microphone PDM interface timing . . . . . . . . . . . . . . . . . . . . . . . . 36 PHY timing - clock output/input and data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 PHY timing - clock output/input and data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 113 FOWPSP (4.17 x 3.91 x 0.65 mm) package outline drawing . . . . . . . . . . . . . . 41 Device identification code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Carrier tape drawing with part orientation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Tape handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4 WCD9335 Audio Codec Device Specification Contents Tables Table 1-1 Summary of WCD9335 device features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 1-2 Terms and acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 2-1 I/O description (pad type) parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 2-2 Pad descriptions - analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 2-3 Pad descriptions - analog outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 2-4 Pad descriptions - digital I/Os (other than host interfaces) . . . . . . . . . . . . . . . . . . . . . Table 2-5 Pad descriptions - host digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 2-6 Pad descriptions - support circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 2-7 Pad descriptions - do not connect pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 2-8 Pad descriptions - power supply pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 2-9 Pad descriptions - ground pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 3-1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 3-2 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 3-3 Power supply peak current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 3-4 Digital I/O characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 3-5 Analog input through digital serial interface performance . . . . . . . . . . . . . . . . . . . . . Table 3-6 Digital microphone input through digital serial interface performance . . . . . . . . . . . Table 3-7 Serial interface through mono EAR output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 3-8 Serial interface through HPH output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 3-9 Serial interface through stereo-differential line outputs . . . . . . . . . . . . . . . . . . . . . . . Table 3-10 Serial interface through stereo line output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 3-11 Clock input timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 3-12 Data output timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 3-13 Data input timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 12 16 17 17 18 18 19 20 20 20 21 22 23 23 24 25 27 29 31 32 34 34 34 Table 3-14 Supported I2S standards and exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 3-15 Master transmitter with data rate of 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 3-16 Slave receiver with clock rate of 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 3-17 Supported I2C standards and exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 3-18 Digital microphone timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 3-19 Master clock (MCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 3-20 PHY timing parameters (1.8 V systems) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 3-21 Microphone bias performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 7-1 Silicon reliability results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 7-2 Package reliability results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LM80-P2751-29 Rev. A 35 36 37 38 39 47 48 5 WCD9335 Audio Codec Device Specification Revision history Revision Date A February 2018 LM80-P2751-29 Rev. A Description Initial release 6 1 Introduction 1.1 Device description This document contains a description of the chipset capabilities. Not all features are available, nor are all features supported in the software. NOTE Enabling some features may require additional licensing fees. The WCD9335 is a stand-alone high fidelity (hi-fi) audio codec IC that supports the Qualcomm Technologies, Inc. (QTI) multimedia solutions, including the APQ8096SGE chipset. The key WCD9335 functions include the following: Serial low-power interchip media bus (SLIMbus) for access to all on-chip digital audio channels; inter-IC sound (I2S) accesses fewer paths, but maintains compatibility with earlier integrated circuits (ICs). SoundWire interface for driving WSA8810 or WSA8815 speaker amplifiers Six analog input ports and seven analog output ports Six audio analog-to-digital converters (ADCs) and seven digital-to-analog converters (DACs) Six digital microphone inputs (three clock/data pairs) Multibutton headset control (MBHC) for smart accessory detection Digital processing includes the following: Microphone activity detection (MAD) detecting audio, ultrasound, and beacon activity Qualcomm(R) Voice Activation subsystem Active noise cancellation (ANC) Integrated analog support reduces bill of materials (BOM) and area: Microphone bias outputs (x4) 1.2 Summary of key features WCD9335 features are listed in Table 1-1. Lower cost, smaller footprint while enabling high-percentage digital content Ultra low-power voice activation engine for keyword detection and user identification Low-power, high-performance ultrasound support, including analog microphone (MIC) and line output LM80-P2751-29 Rev. A 7 WCD9335 Audio Codec Device Specification Introduction Hi-fi audio recording and playback - 109 dB ADC and 130 dB DAC signal-to-noise ratio (SNR) 32-bit/384 kHz, 44.1 kHz processing Supports external smart speaker amplifiers such as WSA8810/WSA8815 with 2-wire SoundWire signaling to provide configuration flexibility and reduce printed circuit board (PCB) design complexity. Class-H headphone amplifier - 122 dB dynamic range and -105 dB THD+N MBHC, including an additional pad to support both tip and ground insertion/removal Ground reference pad for line outputs to improve signal integrity for docking stations. Only two external supplies are required; all other required voltages are generated by the WCD9335 support circuits. Highly integrated 4.17 x 3.91 mm fan out wafer-level picoscale package (FOWPSP) See Section 1.5 for a complete list of the WCD9335 features. [ ,QWHUIDFHURXWHU UHJLVWHUV '0,&,) [ 0%+& [ :6$ :6$ VSHDNHUDPSV $'& $QDORJDXGLR LQSXWV [ 'LJLWDO SURFHVVLQJ 6RXQGZLUH,) $QDORJDXGLR RXWSXWV [ [ +RVWGLJLWDO LQWHUIDFHV '$& '\QDPLFUDQJH HQKDQFHPHQW (DUSLHFH 6WHUHR KHDGSKRQHV +RVW ,& 6/,0EXV5[7[ ,65[ ,67[ , &VODYH 'LVFUHWH,2V 6XSSRUWFLUFXLWV 0,&ELDV [ /LQHRXWSXWV Figure 1-1 LM80-P2751-29 Rev. A WCD9335 high-level block diagram 8 WCD9335 Audio Codec Device Specification Introduction A M IC 4 _ IN M ADC A M IC 5 _ IN P A M IC 5 _ IN M ADC A M IC 6 _ IN P ADC A M IC 6 _ IN M O p t io n a l c o n n e c t io n to J A C K H S _ D E T M BH C _H S D ET_L M BH C _H S D ET_G D M IC 3 _ D A T A D M IC 3 _ C L K JTA G D M IC 2 _ D A T A D M IC 2 _ C L K PDM _DATA H eadset A n a lo g o u tp u ts EAROP EAROM H PH _L H PH _R EF H PH _R H S v o ic e m ic to e x te rn a l h e a d p h o n e a m p lif ie r f o r h ig h p e r f o r m a n c e p la y b a c k t o P M I 8 9 9 4 H a p t ic s d r iv e r Figure 1-2 LM80-P2751-29 Rev. A T X _ I2 S _ W S T X _ I2 S _ S C K R X _ I2 S _ S D 0 R X _ I2 S _ S D 1 R X _ I2 S _ W S R X _ I2 S _ S C K 1 .8 V DAC DAC R x d ig it a l p r o c e s s in g L IN E _ O U T 2 _ M L IN E _ O U T 3 1 .8 V engine 1 .8 V control V S W _ S ID O V A U X _ S ID O V O U T _ A _ S ID O V O U T _ D _ S ID O VD D_A_LV , VDD_M X VD D_A_LV VDD_CO RE GNDs Pow er M anagem ent PA_VPOS VDD_BUCK G ND_BUCK 1 .8 V VSW _BUCK VOUT_BUCK DAC PA_VNEG V SW _FLYB K DAC FLYBK_VN EG _O U T DAC G N D _C C O M P FLYBK_VN EG _D AC L IN E _ O U T 2 _ P L IN E _ O U T 4 Host IC T X _ I2 S _ S D 0 T X _ I2 S _ S D 1 VDD_M X V D D _ S ID O G N D _ S ID O L IN E _ O U T 1 _ P L IN E _ O U T 1 _ M L IN E _ O U T _ R E F O p t io n a l lin e o u t p u t S o u n d w ir e in t e r f a c e Processing D i g i t a l I/ O s E a r p ie c e S L IM B U S _ D A T A 1 S L IM B U S _ C L K V D D _ IO P D M _C LK speaker am ps S L IM B U S _ D A T A 2 V D D _TX D M IC 1 _ C L K W SA8810/ W SA8815 P M IC IC VDD_RX D M IC 1 _ D A T A Sidetone IIR S V A m ic /v o ic e m ic s f o r F lu e n c e P r o / s u r r o u n d s o u n d r e c o r d in g MODE0 J T D I, J T D O , J T M S , J T C K , J T R S T D M IC in t e r f a c e s ANC V o ic e m ic s f o r F lu e n c e P r o / s u r r o u n d s o u n d r e c o r d in g Status & MBHC Rx I2S JAC K H S_D ET T x d ig it a l p r o c e s s in g M C LK M C LK 2 IN T R 2 IN T R 1 R F_PA_O N R ESET_N MODE1 1 .8 V Tx I2S O p t io n a l in p u t f o r a n a lo g m ic A M IC 4 _ IN P Support circuits O p t io n a l in p u t f o r a n a lo g m ic D ig ita l p r o c e s s in g interface ADC A M IC 3 _ IN M SLIMbus A M IC 3 _ IN P I2 C _ S D A C lo c k s interface ADC H S A N C m ic Host digital interfaces ADC A M IC 2 _ IN P A M IC 2 _ IN M Interface router & registers A M IC 1 _ IN M H S v o ic e m ic H S A N C m ic W C D 9335 A M IC 1 _ IN P interface A n a lo g in p u ts O p t io n a l in p u t f o r a n a lo g m ic I2 C _ S C L I/F I2C 1.3 WCD9335 detailed functional block diagram CCOMP V B A T _ A D C _ IN DAC V D D _ M IC _ B IA S DAC M I C b ia s M IC _ B IA S x (x 4 ) LD O _H M IC B _ C F IL T _ R E F VBAT V PH _PW R _BBY P M IC _ B IA S x (x 4 ) WCD9335 detailed functional block diagram 9 WCD9335 Audio Codec Device Specification Introduction 1.4 Supply voltage summary The following supplies are required: Primary phone power (VPH_PWR) Regulated 1.8 V from power management The on-chip circuits generate all other voltages required by the WCD9335. 1.5 Features The features of the WCD9335 device are listed in Table 1-1. Table 1-1 Summary of WCD9335 device features Feature WCD9335 capabilities System Hi-fi audio Qualcomm Voice Activation subsystem Recording path: 110 dB dynamic range and -103 dB THD + N Playback path: 130 dB dynamic range and -109 dB THD + N Microphone activity detection (MAD) to detect audio and beacon activity Codec processing engine (CPE) with 304 kB on-chip RAM Provides keyword detection and user identification in the codec with less than 0.85 mA power at battery (100% speech occupancy). Look-ahead buffer provides more consistent and coherent interaction to users. Digital I/Os SLIMbus slave Two data lanes; 16 transmit (Tx) ports + 8 receive (Rx) ports + control Tx sample rates: 8, 16, 32, 48, 96, and 192 kHz Rx sample rates: 8, 16, 32, 44.1, 48, 96, 192, and 384 kHz Bit resolution: 12, 16, 20, 24, and 32 Framer device to support framer handover to codec Isochronous mode Push/pull transport protocols Four Tx ports + four Rx ports Tx sample rates: 8, 16, 32, 48, 96, and 192 kHz Rx sample rates: 8, 16, 32, 44.1, 48, 96, and 192 kHz Bit resolution: 16 and 32 SoundWire interface to WSA8810/WSA8815 Multichannel, audio, and control use two lines (one clock and one data) Digital microphone ports Six; three clock lines; nine supported frequencies from 600 kHz to 6.144 MHz Interrupts Multiple hardware interrupts multiplexed behind two interrupt pads Two stereo master and slave I2S LM80-P2751-29 Rev. A 10 WCD9335 Audio Codec Device Specification Introduction Feature WCD9335 capabilities Tx processing Analog audio input ports Six ports that support differential and single-ended configurations. There are three operational modes: Hi-fi Programmable gain from 0-24 dB in 1.5 dB steps Standard Programmable gain from 0-30 dB in 1.5 dB steps 0.9 Vrms input referred noise, 100 dB SNR, and -107 THD at 21 dB gain 1.4 Vrms input referred noise, 96 dB SNR, and -102 THD at 21 dB gain Ultra low power Programmable gain from 0-30 dB in 1.5 dB steps 2.7 Vrms input referred noise, 90 dB SNR, and -95 THD at 21 dB gain Capless inputs: Input multiplexing allows routing any AMIC input to any decimator Integrated IEC diodes on AMIC2_INP, AMIC3_INP, and AMIC4_INP ADCs Six audio ADCs Concurrency Nine concurrent Tx decimation paths to support voice and audio applications Digital controls Gain: -84 dB to +40 dB in 0.5 dB increments DC blocking corner frequency: 4 Hz, 75 Hz, and 100 Hz Decimation filters Nine decimation filters for concurrent Tx paths Passband ripple: 0.005 dB Rx processing Analog audio output ports Seven - earpieces, stereo headphone, four line outputs (two differentials, two single-ended or four single-ended) Integrated IEC diodes on EAROP, EAROM, HPH_L, HPH_R, and HPH_REF pads Class-H differential earpiece output 120 mW (typical) into 32 ; 150 mW (minimum) into 16 or 10.67 Class-H stereo single-ended headphone outputs; capless; 16 or 32 Two differentials and two single-ended line outputs Digital audio to WSA SoundWire interface DACs Seven DACs and nine dedicated interpolators High-performance DACs for differential line outputs (to external headphone amplifiers) Headphone: 1 Vrms; 122 dB dynamic range, -105 dB THD+N, and 16 Vpp click and pop in Class-H mode Line outputs: 2 Vrms; 130 dB dynamic range and -109 THD+N (differential) Concurrency Nine concurrent Rx paths Frequency response High pass filter (HPF) cutoff of 0.48 Hz with 0.0025 dB droop at 20 Hz to meet Dolby requirements Nine interpolation filters with passband ripple of 0.0025 dB (HPF disabled) Performance Mixing LM80-P2751-29 Rev. A Digital mixing at the input of each DAC path Digital mixing on inputs to IIRs with independent gain control HD audio mixing path added to all interpolators 11 WCD9335 Audio Codec Device Specification Introduction Feature WCD9335 capabilities Dynamic range enhancement DRE provides Hi-Fi audio quality for headphone and line-output PAs Protection and suppression Overcurrent protection Click-and-pop suppression Multiple sample rates Any path can use any of these sampling rates: 8, 16, 32, 44.1, 48, 96, 192, and 384 kHz Concurrent PCM rates Independent rates on each path to support voice and music concurrently Additional digital processing and paths Active noise cancellation - Multibutton headset control (MBHC) Moisture detection Mechanical plug insertion and removal detection on both tip and ground detection pad with pop noise reduction Accessory plug type (3-pole, 4-pole - CTIA or OMTP, and 5-pole) detection Detection for up to eight buttons (send/end, volume, and play control) Headset impedance detection with 5% from 3 up to 2 k All mixed channels operate at the same sample rate No gain changes occur as a result of mixing channels Five-stage IIR filters Sample-rate converters Echo cancellation (EC) Master clocks supported: 24.576, 19.2, 12.288, and 9.6 MHz (default) Four voltage sources for powering analog and digital microphones Programmable from 1.0 V to 2.85 V SmartBoost Feedback signal to the companion WSA boost for efficient power control Feedback speaker protection Receives I/V sense signals from companion WSA devices and transmits them to the audio processing in the APQ chipset Always-on power Supports headset-insert/button-detect and Snapdragon Voice Activation while in low-power sleep mode Sidetone paths and processing Clock circuits Support circuits Microphone biasing Fabrication technology and package Package Small, thermally efficient 113 FOWPSP; 4.17 x 3.91 x 0.65 mm; 0.35 mm pitch 1.6 Terms and acronyms Table 1-2 defines terms and acronyms commonly used throughout this document. Table 1-2 Terms and acronyms Term or acronym LM80-P2751-29 Rev. A Definition ADC Analog-to-digital converter AMIC Analog microphone 12 WCD9335 Audio Codec Device Specification Introduction Term or acronym BOM Bill of materials BPF Band pass filter bps Bits per second CPE Codec processing engine DAC Digital-to-analog converter DMIC Digital microphone EC Echo cancellation ESD FOWPSP FOWLP Electrostatic discharge Fan out wafer-level picoscale package Fan out wafer level package Hi-fi High fidelity HPF High pass filter HPH Headphone HR Hundred reel HV High voltage I2C Interintegrated circuit I2S Inter-IC sound IEC International Electrotechnical Commission JTAG Joint Test Action Group (ANSI/ICEEE Std. 1149.1-1990) LDO Low dropout (linear regulator) LPF Low pass filter LV MBHC MGB MIC or mic Low voltage Multibutton headset control Master bandgap (voltage reference) Microphone MSL Moisture sensitivity level NVM Nonvolatile memory OEM Original equipment manufacturer OSR Oversampling ratio PA Power amplifier PCB Printed circuit board PDM Pulse density modulation RoHS Restriction of hazardous substances SIDO Single inductor dual output SIMO Single inductor multiple outputs SLIMbus LM80-P2751-29 Rev. A Definition Serial low-power interchip media bus 13 WCD9335 Audio Codec Device Specification Introduction Term or acronym SMPS Switched-mode power supply SMT Surface-mount technology SNR Signal-to-noise ratio Sn/Ag/Cu SPKR Also known as SAC. Tin-silver-copper is a lead-free (Pb-free) alloy commonly used for electronic solder Speaker SR Short reel TR Tape and reel WCD WSP codec device WLP Wafer-level package WSA WSP smart amplifier WSP Wafer-scale package XO LM80-P2751-29 Rev. A Definition Crystal oscillator 14 2 Pad definitions The WCD9335 is available in the 113 FOWPSP; a high-level view of its pad assignments is shown in Figure 2-1. 1 2 GND_ SIDO DNC 3 VBAT_ ADC_IN 10 MIC_ BIAS3 9 VSW_ SIDO 16 VDD_ SIDO 17 MIC_ BIAS4 25 MIC_ BIAS2 LDO_H 39 VOUT_ A_SIDO 47 GND_ TX 54 AMIC6 _INM 61 AMIC6 _INP 69 AMIC5 _INP 76 AMIC4 _INP 84 AMIC3 _INP Analog audio outputs 28 57 GND GND 72 MCLK MCLK2 80 81 GND GND 101 LINE_ OUT2_P Digital IOs 88 MODE0 94 LINE_ OUT1_M Host digital interfaces HPH_R 111 EAROM HPH_L DNC 68 RX_I2S _WS 75 VSW_ BUCK 82 VOUT_ BUCK 83 VDD_ BUCK 90 GND_ BUCK 97 PA_ VPOS 98 VSW_ FLYBK 105 FLYBK_ VNEG_ OUT 104 PA_ VNEG 110 Support circuits 67 I2C_ SDA 96 VDD_ RX 103 EAROP 109 LINE_ OUT1_P 60 GND 89 MBHC_ HSDET_L HPH_REF 95 GND_ RX 102 59 74 79 53 VDD_ IO GND JTRST MODE1 87 JTDO 52 VDD_ CORE 66 I2C_ SCL 73 RF_PA _ON 38 TX_I2S _SD1 45 JTMS JTCK GND 71 30 37 VDD_ MX 51 65 23 TX_I2S _WS GND 44 58 DMIC2 _DATA 64 22 VDD_ CORE 36 DMIC3 _CLK 43 DMIC1 _CLK 8 GND 15 RX_I2S _SD0 29 RX_I2S _SD1 50 DMIC1 _DATA 56 108 LINE_ OUT3 21 VDD_ IO 35 VDD_ CORE INTR2 86 LINE_ OUT2_M 100 LINE_ OUT4 Analog audio inputs LM80-P2751-29 Rev. A GND 93 LINE_ OUT_REF 107 AMIC1 _INP Figure 2-1 CCOMP 85 AMIC3 _INM 99 AMIC1 _INM GND 49 7 TX_I2S _SD0 14 RX_I2S _SCK GND 42 VDD_ CORE INTR1 78 MBHC_ HSDET_G 92 AMIC2 _INM 106 41 70 AMIC5 _INM 13 VDD_ MX 27 SLIMBUS _DATA1 48 6 JTDI 20 DMIC3 _DATA 34 SLIMBUS _CLK 63 GND_ CCOMP 77 AMIC4 _INM 91 AMIC2 _INP 26 55 VDD_ A_LV 62 VDD_ TX 12 SLIMBUS _DATA2 RESET_N 40 VDD_ MIC_BIAS 5 DMIC2 _CLK 19 TX_I2S _SCK 33 MICB_ CFILT_ REF 32 46 VOUT_ D_SIDO 11 PDM _CLK 18 MIC_ BIAS1 24 GND_ SIDO 31 VAUX_ SIDO 4 PDM _DATA 112 FLYBK_ VNEG_ DAC Power 113 DNC Ground WCD9335 pad assignments (top view) 15 WCD9335 Audio Codec Device Specification Pad definitions 2.1 I/O parameter definitions Table 2-1 I/O description (pad type) parameters Symbol Description Pad attribute AI Analog input AO Analog output B Bidirectional digital with CMOS input DI Digital input (CMOS) DO Digital output (CMOS) Z High-impedance (Hi-Z) output VDD_IO is used for digital I/O pads. 2.2 Pad descriptions Descriptions of all pads are presented in the following tables, organized by functional group: Table 2-2 Analog inputs Table 2-3 Analog outputs Table 2-4 Digital I/Os (other than host interfaces) Table 2-5 Host digital interfaces Table 2-6 Support circuits Table 2-7 Do not connect pads Table 2-8 Power supply pads Table 2-9 Ground pads LM80-P2751-29 Rev. A 16 WCD9335 Audio Codec Device Specification Table 2-2 Pad descriptions - analog inputs Pad # 1. Pad name Pad type11 Functional description 107 AMIC1_INP AI Analog microphone 1 input, differential plus 99 AMIC1_INM AI Analog microphone 1 input, differential minus 91 AMIC2_INP AI Analog microphone 2 input, differential plus 92 AMIC2_INM AI Analog microphone 2 input, differential minus 84 AMIC3_INP AI Analog microphone 3 input, differential plus 85 AMIC3_INM AI Analog microphone 3 input, differential minus 76 AMIC4_INP AI Analog microphone 4 input, differential plus 77 AMIC4_INM AI Analog microphone 4 input, differential minus 69 AMIC5_INP AI Analog microphone 5 input, differential plus 70 AMIC5_INM AI Analog microphone 5 input, differential minus 61 AMIC6_INP AI Analog microphone 6 input, differential plus 54 AMIC6_INM AI Analog microphone 6 input, differential minus 89 MBHC_HSDET_L AI MBHC mechanical insertion/removal tip-detection pad 78 MBHC_HSDET_G AI Secondary MBHC mechanical insertion/removal ground-detection pad See Table 2-1 for parameter and acronym definitions. Table 2-3 Pad descriptions - analog outputs Pad # 1. Pad definitions Pad name Pad type11 Functional description 102 EAROP AO Earpiece amplifier output, differential plus 110 EAROM AO Earpiece amplifier output, differential minus 111 HPH_L AO Headphone left output 103 HPH_R AO Headphone right output 88 HPH_REF AI Capless headphone ground reference of the PA 109 LINE_OUT1_P AO Audio line output 1, differential plus 94 LINE_OUT1_M AO Audio line output 1, differential minus 101 LINE_OUT2_P AO Audio line output 2, differential plus 86 LINE_OUT2_M AO Audio line output 2, differential minus 108 LINE_OUT3 AO Audio line output 3, single-ended 100 LINE_OUT4 AO Audio line output 4, single-ended 93 LINE_OUT_REF AI Audio line outputs 3 and 4 ground reference See Table 2-1 for parameter and acronym definitions. LM80-P2751-29 Rev. A 17 WCD9335 Audio Codec Device Specification Table 2-4 Pad definitions Pad descriptions - digital I/Os (other than host interfaces) Pad # Pad name Pad type11 Functional description Digital microphone (DMIC) interfaces 50 DMIC1_DATA DI Data for digital microphones 1 and 2 43 DMIC1_CLK DO Clock for digital microphones 1 and 2 58 DMIC2_DATA DI Data for digital microphones 3 and 4 5 DMIC2_CLK DO Clock for digital microphones 3 and 4 20 DMIC3_DATA DI Data for digital microphones 5 and 6 36 DMIC3_CLK DO Clock for digital microphones 5 and 6 SoundWire port 1. 4 PDM_DATA B SoundWire data for WSA8810/WSA8815 smart speaker amplifier 11 PDM_CLK DO SoundWire clock for WSA8810/WSA8815 smart speaker amplifier See Table 2-1 for parameter and acronym definitions. Table 2-5 Pad descriptions - host digital interfaces Pad # Pad name Pad type11 Functional description SLIMbus bidirectional audio 12 SLIMBUS_DATA2 B Bidirectional (Rx/Tx) SLIMbus data bit 2 27 SLIMBUS_DATA1 B Bidirectional (Rx/Tx) SLIMbus data bit 1 34 SLIMBUS_CLK B Bidirectional (Rx/Tx) SLIMbus clock Interintegrated circuit (I2C) port 67 I2C_SDA B I2C serial data 66 I2C_SCL B I2C serial clock I2S bus - Rx direction 14 RX_I2S_SCK B I2S bit clock, Rx direction 68 RX_I2S_WS B I2S word select, Rx direction 29 RX_I2S_SD1 DI I2S serial data line 1, Rx direction 15 RX_I2S_SD0 DI I2S serial data line 0, Rx direction I2S bus - Tx direction 19 TX_I2S_SCK B I2S bit clock, Tx direction 23 TX_I2S_WS B I2S word select, Tx direction 38 TX_I2S_SD1 DO I2S serial data line 1, Tx direction 7 TX_I2S_SD0 DO I2S serial data line 0, Tx direction Clock circuits 71 MCLK AI Master clock input 72 MCLK2 AI Master clock input 2 LM80-P2751-29 Rev. A 18 WCD9335 Audio Codec Device Specification Table 2-5 Pad definitions Pad descriptions - host digital interfaces (cont.) Pad # Pad name Pad type11 Functional description Discrete status and control signals 1. 26 RESET_N DI WCD9335 IC-level reset 73 RF_PA_ON DI Indicates that GSM RF power amplifier is about to burst 41 INTR1 DO Interrupt output 1 56 INTR2 DO Interrupt output 2 87 MODE0 DI Digital interface mode selection (SLIMbus or I2S) bit 0 79 MODE1 DI Digital interface mode selection (SLIMbus or I2S) bit 1 See Table 2-1 for parameter and acronym definitions. Table 2-6 Pad descriptions - support circuits Pad # Pad name Pad type11 Functional description SIDO buck 9 VSW_SIDO AI, AO SIDO buck switching node 31 VAUX_SIDO AI, AO SIDO buck auxiliary voltage node 39 VOUT_A_SIDO AO SIDO output voltage for analog circuits 46 VOUT_D_SIDO AO SIDO output voltage for digital circuits Buck SMPS 75 VSW_BUCK AI, AO Buck SMPS switching node 82 VOUT_BUCK AO Buck SMPS output node 1 SIMO flyback 105 FLYBK_VNEG_OUT AO Flyback SIMO negative output for PAs 112 FLYBK_VNEG_DAC AO Flyback SIMO negative output for DACs 98 VSW_FLYBK AI, AO Flyback SIMO switching node Low-dropout (LDO) linear regulator 32 LDO_H AO Internal-circuitry LDO high-voltage output load capacitor Microphone bias voltage sources 18 MIC_BIAS1 AO Microphone bias output voltage 1 25 MIC_BIAS2 AO Microphone bias output voltage 2 10 MIC_BIAS3 AO Microphone bias output voltage 3 17 MIC_BIAS4 AO Microphone bias output voltage 4 33 MICB_CFILT_REF AI Microphone bias shared reference ground of the circuits Bandgap voltage reference decoupling 48 CCOMP AO Bandgap reference circuit compensation capacitor AI Input to VBAT ADC Battery voltage monitor 3 VBAT_ADC_IN LM80-P2751-29 Rev. A 19 WCD9335 Audio Codec Device Specification Table 2-6 Pad definitions Pad descriptions - support circuits (cont.) Pad # Pad type11 Pad name Functional description JTAG interface 1. 51 JTCK DI JTAG clock 6 JTDI DI JTAG data input 45 JTDO DO JTAG data output 44 JTMS DI JTAG mode select 74 JTRST DI JTAG reset See Table 2-1 for parameter and acronym definitions. Table 2-7 Pad descriptions - do not connect pads Pad # Pad name 1, 113 DNC Table 2-8 Functional description Do not connect; connected internally, do not connect externally Pad descriptions - power supply pads Pad # Pad name Functional description 104 PA_VNEG Negative supply for PAs 97 PA_VPOS Positive supply for PAs 55 VDD_A_LV Power for analog low-voltage circuits 83 VDD_BUCK Power for buck SMPS 22, 35, 42, 52 VDD_CORE Power for core digital circuits 13, 37 VDD_MX Power for on-chip memory 40 VDD_MIC_BIAS Power for the LDO and microphone bias circuits 21, 53 VDD_IO Power for digital I/O pads 96 VDD_RX Power for analog audio output (Rx) circuits 16 VDD_SIDO Power for the SIDO buck 62 VDD_TX Power for analog audio input (Tx) circuits Table 2-9 Pad descriptions - ground pads Pad # Pad name Functional description 8, 28, 30, 49, 57, 59, 60, 64, 65, 80, 81, 106 GND Ground 90 GND_BUCK Ground for buck SMPS circuits 63 GND_CCOMP Ground for bandgap reference circuits 95 GND_RX Ground for analog audio input (Rx) circuits 2, 24 GND_SIDO Ground for SIDO buck 47 GND_TX Ground for analog audio input (Tx) circuits LM80-P2751-29 Rev. A 20 3 Electrical specifications 3.1 Absolute maximum ratings Absolute maximum ratings (Table 3-1) reflect the worst-case conditions that WCD9335 devices are exposed to during testing. They are limiting values to be considered individually when all other parameters are within their specified operating ranges. Functional operation and specification compliance at any absolute maximum condition, or after exposure to any of these conditions, are not guaranteed or implied. Exposure can shorten the life of the device. Table 3-1 Absolute maximum ratings Parameter Description Minimum Maximum Units Power supply voltages VDD_MIC_BIAS Power for the LDO and microphone bias circuits -0.30 4.80 V VDD_RX Power for analog audio output (Rx) circuits -0.30 2.16 V VDD_TX Power for analog audio input (Tx) circuits -0.30 2.16 V VDD_BUCK Power for buck SMPS -0.30 2.16 V VDD_SIDO Power for the SIDO buck -0.30 2.16 V VDD_IO Power for digital I/O pads -0.30 2.16 V VDD_A_LV Power for analog low-voltage circuits -0.30 1.30 V VDD_MX Power for on-chip memory -0.30 1.30 V VDD_CORE Power for core digital circuits -0.30 1.30 V VIN_DIG Any digital input, nonpower -0.30 2.15 V VIN_ANA Any analog input, nonpower -0.30 2.90 V VBAT_ADC_IN Input to VBAT ADC -0.30 4.80 V Signal pads LM80-P2751-29 Rev. A 21 WCD9335 Audio Codec Device Specification Electrical specifications 3.2 Operating conditions Operating conditions include parameters that are under the control of the design team: power supply voltage, power distribution impedances, and thermal conditions (Table 3-2). The WCD9335 meets all performance specifications listed in Section through Section 3.7.6, when used within the operating conditions, unless otherwise noted in those sections (provided the absolute maximum ratings have never been exceeded). Table 3-2 Operating conditions Parameter Description Minimum Typ Maximum Units Power supply voltages VDD_MIC_BIAS Power for the LDO and microphone bias circuits 3.15 3.80 4.60 V VDD_RX Power for analog audio output (Rx) circuits 1.70 1.80 1.90 V VDD_TX Power for analog audio input (Tx) circuits 1.70 1.80 1.90 V VDD_BUCK Power for buck SMPS 1.70 1.80 1.90 V VDD_SIDO Power for the SIDO buck 1.70 1.80 1.90 V VDD_IO Power for digital I/O pads 1.70 1.80 1.90 V Internally generated input voltage VDD_A_LV Power for analog low-voltage circuits 1.0 1.10 1.21 V VDD_MX Power for on-chip memory 1.0 1.10 1.21 V VDD_CORE Power for core digital circuits 0.88 1.10 1.21 V Input to VBAT ADC 2.50 3.80 4.60 V Operating temperature (case) -30 - 85 C Signal pads VBAT_ADC_IN Thermal condition Tc LM80-P2751-29 Rev. A 22 WCD9335 Audio Codec Device Specification Electrical specifications 3.3 DC power characteristics 3.3.1 Peak current Table 3-3 Power supply peak current Parameter Conditions Minimum Typ Maximum Units VDD_MIC_BIAS - - - 15 mA VDD_RX - - - 25 mA VDD_TX - - - 25 mA VDD_BUCK - - - 650 mA VDD_SIDO - - - 200 mA VDD_IO Total for two pads - - 10 mA VDD_A_LV Included in VDD_SIDO - - 15 mA VDD_MX Included in VDD_SIDO, total for two pads - - 10 mA VDD_CORE Included in VDD_SIDO, total for four pads - - 40 mA 3.4 Digital logic characteristics Table 3-4 Digital I/O characteristics Parameter Conditions Minimum Typ Maximum Units VIH High-level input voltage - 0.65 * VDDX - 1.1 * VDDX V VIL Low-level input voltage - 0 - 0.35 * VDDX V VOH High-level output voltage - 0.90 * VDDX - VDDX V VOL Low-level output voltage - 0 - 0.10 * VDDX V CIN Digital input capacitance - - - 5 pF 3.5 Audio inputs and Tx processing Unless otherwise stated: All Tx performance parameters are measured with 1.02 kHz sine wave input signal, differential or single-ended inputs, Fs = 48 kHz, 24-bit data, and MCLK = 9.6 MHz or 12.288 MHz. SNR is measured by taking the ratio of the output level with input signal level of 0 dBV and 1.02 kHz sine wave to the output level with inputs grounded over a bandwidth of 20 Hz-20 kHz. LM80-P2751-29 Rev. A 23 WCD9335 Audio Codec Device Specification 3.5.1 Electrical specifications Analog input through digital serial interface Table 3-5 specifies the performance of the following Tx path: Any analog input pre-amp ADC digital serial interface. NOTE Table 3-5 Only hi-fi mode specification is listed. Lower power consumption modes are supported. Analog input through digital serial interface performance Parameter Conditions Min Typ Max Units Microphone amplifier gain = 0 dB (minimum gain) Input-referred noise A-weighted; inputs grounded; bandwidth 20 Hz-20 kHz - 3.3 - Vrms SNR A-weighted - 109 - dB THD + N ratio Analog input = 0 dBV; bandwidth 20 Hz-20 kHz - -103 - dB Analog input = -1 dBV; bandwidth 20 Hz-20 kHz - -98 - dB Analog input = -60 dBV; bandwidth 20 Hz-20 kHz; A-weighted - -50 - dB Microphone amplifier gain = 21 dB (typical gain) Input-referred noise A-weighted; inputs grounded; bandwidth 20 Hz-20 kHz - 0.9 - Vrms SNR A-weighted - 100 - dB THD + N ratio Analog input = -21 dBV; bandwidth 20 Hz-20 kHz - -90 - dB Analog input = -22 dBV; bandwidth 20 Hz-20 kHz - -90 - dB Analog input = -81 dBV; bandwidth 20 Hz-20 kHz; A-weighted - -34 - dB Analog input = -22 dBV; bandwidth 20 Hz-20 kHz - -107 - dB THD General requirements Absolute gain error Hi-fi mode - -0.1 - dB Full scale input signal Measure differential input level that gives 0 dBFS output level; gain = 0 dB - 0.1 - dBV Power supply rejection (VDD_TX) 0 < f < 1 kHz; 100 mVpp sine wave imposed on the power supply; analog input = 0 Vrms Terminate inputs with 0 ; gain = 0 dB - 113 - dB 1 kHz < f < 5 kHz; 100 mVpp sine wave imposed on the power supply; analog input = 0 Vrms Terminate inputs with 0 ; gain = 0 dB - 107 - dB 5 kHz < f < 20 kHz; 100 mVpp sine wave imposed on the power supply; analog input = 0 Vrms Terminate inputs with 0 ; gain = 0 dB - 94 - dB Input impedance - 1 - - M Input capacitance Analog pad - - 30 pF LM80-P2751-29 Rev. A 24 WCD9335 Audio Codec Device Specification Table 3-5 Electrical specifications Analog input through digital serial interface performance (cont.) Parameter Conditions Min Typ Max Units Rx-to-Tx crosstalk attenuation Tx path measurement with -5 dBFS Rx path signal; separate Tx input and Rx output grounds - 105 - dB Interchannel isolation 20 < f < 20 kHz; one input terminated with 1 k and the other input gets 1 kHz at -5 dBFS. Measure the digital output of the terminated channel; separate Tx inputs grounds - 93 - dB 3.5.2 DMIC input through digital serial interface Table 3-6 specifies the performance of the following Tx path: Any digital microphone input digital serial interface. Table 3-6 Digital microphone input through digital serial interface performance Parameter Conditions Minimum Typ Maximum Units Frequency response (from digital microphone input to SB/I2S PCM output, all sample rates) Frequency response LM80-P2751-29 Rev. A See Table 3-7 for the frequency response from digital microphone input to SB/I2S PCM output for all the sampling rates. 25 WCD9335 Audio Codec Device Specification Table 3-6 Electrical specifications Digital microphone input through digital serial interface performance (cont.) Parameter Conditions Minimum Typ Maximum Units System clock = 9.6 MHz decimated output rates: 8 kHz, 16 kHz, 32 kHz, and 48 kHz - 600 - kHz System clock = 9.6 MHz decimated output rates: 8 kHz, 16 kHz, 32 kHz, and 48 kHz - 1.2 - MHz System clock = 9.6 MHz decimated output rates: 8 kHz, 16 kHz, 32 kHz, 48 kHz, 96 kHz, and 192 kHz - 2.4 - MHz System clock = 9.6 MHz decimated output rates: 8 kHz, 16 kHz, 32 kHz, 48 kHz, 96 kHz, and 192 kHz - 3.2 - MHz System clock = 9.6 MHz decimated output rates: 8 kHz, 16 kHz, 32 kHz, 48 kHz, 96 kHz, and 192 kHz - 4.8 - MHz System clock = 12.288 MHz decimated output rates: 8 kHz, 16 kHz, 32 kHz, and 48 kHz - 768 - kHz System clock = 12.288 MHz decimated output rates: 8 kHz, 16 kHz, 32 kHz, and 48 kHz - 1.536 - MHz System clock = 12.288 MHz decimated output rates: 8 kHz, 16 kHz, 32 kHz, 48 kHz, 96 kHz, and 192 kHz - 2.048 - MHz System clock = 12.288 MHz decimated output rates: 8 kHz, 16 kHz, 32 kHz, 48 kHz, 96 kHz, and 192 kHz - 3.072 - MHz System clock = 12.288 MHz decimated output rates: 8 kHz, 16 kHz, 32 kHz, 48 kHz, 96 kHz, and 192 kHz - 4.096 - MHz System clock = 12.288 MHz decimated output rates: 8 kHz, 16 kHz, 32 kHz, 48 kHz, 96 kHz, and 192 kHz - 6.144 - MHz Input capacitance - - 1 5 pF Board capacitance - - 10 50 pF Clock rate LM80-P2751-29 Rev. A 26 WCD9335 Audio Codec Device Specification Electrical specifications 3.6 Audio outputs and Rx processing Unless otherwise stated: All Rx performance parameters are measured with 1.02 kHz sine wave input signal, Fs = 48 kHz, 24-bit data and MCLK = 9.6 MHz or 12.288 MHz Receive noise is measured with no dither added to the input signal 3.6.1 Digital serial interface through earpiece analog output Table 3-7 specifies the performance of the following Rx path: digital serial input mono DAC mono EAR output with 32 , load unless otherwise specified. Table 3-7 Serial interface through mono EAR output Parameter Conditions Minimum Typ Maximum Units A-weighted; input = -999 dBFS, 6 dB gain mode - 8.4 - Vrms A-weighted; input = -999 dBFS, 0 dB gain mode - 5 - Vrms SNR Ratio of full-scale output to output noise level, A-weighted, 6 dB gain - 107 - dB THD + N ratio PCMI = 0 dBFS, 20 Hz-20 kHz, 6 dB gain - -91 - dB PCMI = -1 dBFS, 20 Hz-20 kHz, 6 dB gain - -90 - dB PCMI = -60 dBFS, 20 Hz-20 kHz, 6 dB gain, A-weighted - -38 - dB A-weighted; input = -999 dBFS, 6 dB gain mode - 8.4 - Vrms A-weighted; input = -999 dBFS, 0 dB gain mode - 5 - Vrms SNR Ratio of full-scale output to output noise level, A-weighted, 6 dB gain - 107 - dB THD + N ratio PCMI = 0 dBFS, 20 Hz-20 kHz, 6 dB gain - -96 - dB PCMI = -1 dBFS, 20 Hz-20 kHz, 6 dB gain - -95 - dB PCMI = -60 dBFS, 20 Hz-20 kHz, 6 dB gain, A-weighted - -40 - dB Full-scale output voltage Input = 0 dBFS, PA gain = 6 dB - 1.96 - Vrms Input = 0 dBFS, PA gain = 0 dB - 0.99 - Vrms Output power PA gain = 6 dB, 32 , THD+N 1% - 120 - mW Output load Supported output load 10 32 - EAR output; 8/16 kHz; 16 bits Receive noise EAR output; 48 kHz; 16 bits Receive noise Other characteristics LM80-P2751-29 Rev. A 27 WCD9335 Audio Codec Device Specification Table 3-7 Electrical specifications Serial interface through mono EAR output (cont.) Parameter Conditions Minimum Typ Maximum Units Tx-to-Rx crosstalk attenuation Rx path measurement with -5 dBFS Tx path signal; separate Tx input and Rx output grounds - 101 - dB Power supply rejection 0 < f < 1 kHz; 100 mVpp sine wave imposed on the power supply; PCMI = -999 dBFS - 101 - dB 1 kHz < f < 5 kHz; 100 mVpp sine wave imposed on the power supply; PCMI = 999 dBFS - 95 - dB 5 kHz < f < 20 kHz; 100 mVpp sine wave imposed on the power supply; PCMI = 999 dBFS - 80 - dB Disabled output impedance Measured externally with the amplifier disabled - 38 - k Output capacitance The differential output load capacitance that EAR PA can support including any PCB trace, EMI, ESD, and transducer capacitances. - - 500 pF Output DC offset Input = -999 dBFS, measured between differential output - 0.73 - mV Turn on/off click-and-pop level A-weighted, 6 dB gain - 0.5 - mVpp LM80-P2751-29 Rev. A 28 WCD9335 Audio Codec Device Specification 3.6.2 Electrical specifications Digital serial interface through HPH output Table 3-8 specifies the performance of the following Rx path: digital serial input stereo DAC stereo Class H HPH with 16 load, unless otherwise specified. Table 3-8 Serial interface through HPH output Parameter Conditions Minimum Typ Maximum Units A-weighted; input = -999 dBFS Standard mode Hi-fi mode Low-power mode - - - 0.89 0.77 1.04 - - - Vrms Vrms Vrms Ratio of full-scale output to output noise level, A-weighted Standard mode - 121 - dB Hi-fi mode Low-power mode - - 122 119 - - dB dB PCMI = 0 dBFS; 20 Hz-20 kHz Standard mode Hi-fi mode Low-power mode - - - -97 -98 -92 - - - dB dB dB PCMI = -1 dBFS; 20 Hz-20 kHz Standard mode Hi-fi mode Low-power mode - - - -96 -97 -92 - - - dB dB dB PCMI = -60 dBFS; 20 Hz-20 kHz, A-weighted Standard mode Hi-fi mode Low-power mode - - - -41 -41 -41 - - - dB dB dB A-weighted; input = -999 dBFS Standard mode Hi-fi mode Low-power mode - - - 0.89 0.77 1.04 - - - Vrms Vrms Vrms Ratio of full-scale output to the output noise level, A-weighted Standard mode Hi-fi mode Low-power mode - - - 121 122 119 - - - dB dB dB HPH; 48 kHz/44.1 kHz/16-bits Receive noise SNR THD + N ratio HPH; 48 kHz/44.1 kHz/192 kHz/24-bits; 384 kHz/32-bits Receive noise SNR LM80-P2751-29 Rev. A 29 WCD9335 Audio Codec Device Specification Table 3-8 Electrical specifications Serial interface through HPH output (cont.) Parameter Minimum Typ Maximum Units PCMI = 0 dBFS; 20 Hz- 20 kHz Standard mode Hi-fi mode - - -104 -105 - - dB dB Low-power mode - -93 - dB PCMI = -1 dBFS; 20 Hz- 20 kHz Standard mode Hi-fi mode Low-power mode - - - -104 -105 -95 - - - dB dB dB PCMI = -60 dBFS; 20 Hz- 20 kHz; A-weighted Standard mode Hi-fi mode Low-power mode - - - -61 -62 -60 - - - dB dB dB Full-scale output voltage Input = 0 dBFS; 16 or 32 load - 1 - Vrms Output power Input = 0 dBFS, 16 load - 62.5 - mW Input = 0 dBFS, 32 load - 31.25 - mW Output load Supported output load 4 16 - Tx-to-Rx crosstalk attenuation Rx path measurement with -5 dBFS Tx path signal, separate Tx input, and the Rx output grounds - 118 - dB Inter-channel isolation Measured channel output = -999 dBFS; second DAC channel output = -5 dBFS; separate GND for HPH_L and HPH_R 1 kHz 20 kHz - - 105 97 - - dB dB -0.3 - 0.3 dB - 0 - degree Power supply 0 kHz < f < 1 kHz; 100 mVpp sine wave rejection (VDD_RX or imposed on the power supply; VDD_BUCK) PCMI = -999 dBFS - 109 - dB 1 kHz < f < 5 kHz; 100 mVpp sine wave imposed on the power supply; PCMI = -999 dBFS - 99 - dB 5 kHz < f < 20 kHz; 100 mVpp sine wave imposed on the power supply; PCMI = -999 dBFS - 77 - dB Measured externally, with the amplifier disabled - 9.2 - THD + N ratio Conditions Other characteristics Inter-channel gain error Delta between the left and right channels; input = 1 kHz at -20 dBFS Inter-channel phase error Delta between the left and right channels; input = 1 kHz at -20 dBFS Disabled output impedance LM80-P2751-29 Rev. A 30 WCD9335 Audio Codec Device Specification Table 3-8 Electrical specifications Serial interface through HPH output (cont.) Parameter Conditions Minimum Typ Maximum Units Output capacitance Single-ended output load capacitance that HPH PA can support including any PCB trace, EMI, ESD, and transducer capacitances - - 1000 pF Output DC offset Measured between HPH_L or HPH_R and ground - 0 - mV Turn on/off click-and-pop level A-weighted, 16 , 32 , or 10 k load Standard mode Class-H hi-fi mode Low-power mode - - - 16 16 17 - - - Vpp Vpp Vpp 3.6.3 Digital serial interface through stereo hi-fi differential line outputs Table 3-9 specifies the performance of the following Rx path: digital serial input stereo DAC stereo hi-fi differential line outputs with 600 load on the positive output and 200 load on the negative output, unless otherwise specified. Table 3-9 Serial interface through stereo-differential line outputs Parameter Conditions Minimum Typ Maximum Units Line output differential; 48 kHz/44.1 kHz/192 kHz/24 bits; 384 kHz/32-bits Receive noise A-weighted; input = -999 dBFS - 0.58 - Vrms SNR Ratio of full-scale output to output noise level; A-weighted - 130 - dB THD + N ratio PCMI = 0 dBFS; 20 Hz-20kHz - -109 - dB PCMI = -1 dBFS; 20 Hz-20 kHz - -109 - dB PCMI = -60; dBFS 20 Hz-20 kHz, A-weighted - -70 - dB Full-scale output voltage Input = 0 dBFS - 1.97 - Vrms Output load Supported output load (at each output pad) 200 - - Tx-to-Rx crosstalk attenuation Rx path measurement with -5 dBFS Tx path signal. f = 1 kHz; separate Tx input and Rx output grounds - 119 - dB Other characteristics LM80-P2751-29 Rev. A 31 WCD9335 Audio Codec Device Specification Table 3-9 Electrical specifications Serial interface through stereo-differential line outputs (cont.) Parameter Minimum Typ Maximum Units Power supply rejection 0 kHz < f < 1 kHz; 100 mVpp sine wave imposed on the power supply; PCMI = -999 dBFS - 110 - dB 1 kHz < f < 5 kHz; 100 mVpp sine wave imposed on the power supply; PCMI = -999 dBFS - 102 - dB 5 kHz < f < 20 kHz; 100 mVpp sine wave imposed on the power supply; PCMI = -999 dBFS - 93 - dB Disabled output impedance Measured externally from each pad to GND, with the amplifier disabled - 15.2 - Output capacitance Differential output load capacitance that the line PA can support, including any PCB trace, EMI, ESD, and input capacitances of external circuits - - 100 pF Turn on/off click and pop level A-weighted - 0.028 - mVpp 3.6.4 Conditions Digital serial interface through single-ended line output Table 3-10 specifies the performance of the following Rx path: digital serial input stereo DAC single-ended line output in Class-AB mode with 1 k load, unless otherwise specified. . Table 3-10 Serial interface through stereo line output Parameter Conditions Minimum Typ Maximum Units Line out SE; 48 kHz/44.1 kHz/16-bits Receive noise A-weighted; input = -999 dBFS - 1.16 - Vrms SNR Ratio of full-scale output to output noise level, A-weighted - 119 - dB THD + N ratio PCMI = 0 dBFS; 20 Hz-20 kHz - -96 - dB PCMI = -1 dBFS; 20 Hz-20 kHz - -95 - dB PCMI = -60 dBFS; 20 Hz-20 kHz; A-weighted - -41 - dB Line out SE; 48 kHz/44.1 kHz/192 kHz/24-bits Receive noise A-weighted; input = -999 dBFS - 1.16 - Vrms SNR Ratio of full-scale output to output noise level, A-weighted - 119 - dB THD + N ratio PCMI = 0 dBFS; 20 Hz-20 kHz - -99 - dB PCMI = -1 dBFS; 20 Hz-20 kHz - -99 - dB PCMI = -60 dBFS; 20 Hz-20 kHz; A-weighted - -59 - dB Other characteristics LM80-P2751-29 Rev. A 32 WCD9335 Audio Codec Device Specification Table 3-10 Electrical specifications Serial interface through stereo line output (cont.) Parameter Conditions Minimum Typ Maximum Units Full-scale output voltage Input = 0 dBFS - 1 - Vrms Output load Supported output load 1 - - k Tx-to-Rx crosstalk attenuation Rx path measurement with 5 dBFS Tx path signal, separate Tx input, and Rx output grounds - 114 - dB Inter-channel isolation 20 < f < 20 kHz, measured channel output = -999 dBFS, second DAC channel output = -5 dBFS, separate GND on line outputs - 111 - dB Power supply rejection 0 kHz < f < 1 kHz; 100 mVpp sine wave imposed on the power supply; PCMI = -999 dBFS - 112 - dB 1 kHz < f < 5 kHz; 100 mVpp sine wave imposed on the power supply; PCMI = -999 dBFS - 100 - dB 5 kHz < f < 20 kHz; 100 mVpp sine wave imposed on the power supply; PCMI = -999 dBFS - 83 - dB Disabled output impedance Measured externally, with the amplifier disabled - 14.5 - Output capacitance Single-ended output load capacitance that the line PA can support including any PCB trace, EMI, ESD, and input capacitances of external circuits - - 100 pF Turn on/off click-and-pop level A-weighted - 0.2 - mVpp 3.7 Digital I/Os and digital processing Digital logic characteristics are defined in Section 3.4. The supported industry standards are identified in the following subsections. LM80-P2751-29 Rev. A 33 WCD9335 Audio Codec Device Specification 3.7.1 Electrical specifications SLIMbus Figure 3-1 Table 3-11 Received clock signal constraints Clock input timing requirements Symbol Parameter Conditions Minimum Typ Maximum Units TCLKIH CLK input high time IOL = 1 mA 12 - - ns VCLKIL CLK input low time IOH = 1 mA 12 - - ns SRCLKI Clock input slew rate Load = 15 pF or 75 pF 0.02 x VDD - - V/ns Table 3-12 Data output timing characteristics Symbol Parameter Conditions SRDATA Data output slew rate TDV Time for data output valid IOH = 1 mA Table 3-13 20% < VO < 80% Minimum Typ Maximum Units - - 0.5 x VDD V/ns - - 12 ns Data input timing requirements Symbol Parameter Conditions Minimum Typ Maximum Units TH Data input hold time - 2 - - ns TSETUP Data input setup time - 3 - - ns NOTE 3.7.2 The WCD9335 SLIMbus is compliant to the clock and data specifications, as specified in the MIPI Alliance Specification for Serial Low-power Inter-chip Media Bus (SLIMbus) Version 1.01.01. Inter-IC sound (I2S) Table 3-14 Supported I2S standards and exceptions Applicable standards Phillips I2S Bus Specifications, revised June 5, 1996 LM80-P2751-29 Rev. A Feature exceptions WCD9335 variations No external controller support None 34 WCD9335 Audio Codec Device Specification Table 3-15 Electrical specifications Master transmitter with data rate of 16 MHz Parameter Conditions Minimum Typ Maximum Unit Clock period T I2S requirement: min T = 62.5 - 62.5 - ns Clock high t(hc) I2S requirement: min > 0.35 T - - - ns Clock low t(lc) I2S requirement: min > 0.35 T - - - ns Delay t(dtr) I2S requirement: max < 0.8 T - - 15.6 ns Hold time t(htr) I2S requirement: min > 0 3.2 - - ns Table 3-16 Slave receiver with clock rate of 16 MHz Parameter Conditions Minimum Typ Maximum Unit Clock period T I2S requirement: min T = 62.5 - 62.5 - ns Clock high t(hc) I2S requirement: min < 0.35 T - - - ns Clock low t(lc) I2S requirement: min < 0.35 T - - - ns Setup time t(sr) I2S requirement: min < 0.2 T 15.6 - - ns Hold time t(htr) I2S requirement: min < 0 0 - - ns 3.7.3 Inter-integrated circuit (I2C) Table 3-17 Supported I2C standards and exceptions Applicable standards I2C Specification, version 6.0, October 4 April 2014 (Phillips Semiconductor document number 9398 393 40011) LM80-P2751-29 Rev. A Feature exceptions - WCD9335 variations None 35 WCD9335 Audio Codec Device Specification 3.7.4 Electrical specifications Digital microphone PDM interface Mbias Vs 0.1 F Sel WCD9335 clk Data2 Dmic L Vs 0.1 F Sel Dmic R clk Data1 Select (Sel) Mode Internal Signal Vs Right (Data1) DMIC 1 GND Left (Data2) DMIC 2 Vs Right (Data3) DMIC 3 GND Left (Data4) DMIC 4 Vs Right (Data5) DMIC 5 GND Left (Data6) DMIC 6 TCLK DMIC_CLK TLH TRH DMIC_DATA Figure 3-2 Table 3-18 Data Right(Data 1,3,5) Data Left(Data 2,4,6) TRSU TLSU WCD9335 digital microphone PDM interface timing Digital microphone timing Parameter Minimum Typ Maximum Unit DMIC clock period (TCLK) 163 - 1666 ns DMIC clock duty cycle 45 - 55 % Data left setup time to DMIC clock rising edge (TLSU) 10 - - ns Data left hold time from DMIC clock rising edge (TLH) 0 - - ns Data right setup time to DMIC clock falling edge (TRSU) 10 - - ns Data right hold time from DMIC clock falling edge (TRH) 0 - - ns LM80-P2751-29 Rev. A 36 WCD9335 Audio Codec Device Specification 3.7.5 Electrical specifications Master clock (MCLK) Table 3-19 Master clock (MCLK) Parameter Minimum Typ Maximum Units Frequency 11 9.6 9.6 24.576 Rise/fall time - 10 20 ns Duty cycle 45 50 55 % MHz 1. The codec supports 9.6 MHz, 19.2 MHz, 12.288 MHz, or 24.576 MHz frequency. NOTE 3.7.6 Recommendation G.711: The nominal value recommended for the sampling rate is 8000 samples per second. The tolerance on that rate should be 50 ppm. SoundWire WCD9335 SoundWire PHY timing parameters as specified in Table 3-20 are compliant to clock and data specifications as specified in the MIPI Alliance Specification for SoundWire Version 0.8, Revision 04. See Figure 3-3 and Figure 3-4. 1/f T_slew_CLK T_High_CLK T_slew_CLK T_Low_CLK VOH_CLK VTPCLKmax VTPCLKmin/ VTNCLKmax VTNCLKmin VOL_CLK T_ISetupmin T_IHoldmin T_ISetupmin T_IHoldmin VIHmin VILmin Figure 3-3 LM80-P2751-29 Rev. A PHY timing - clock output/input and data input 37 WCD9335 Audio Codec Device Specification Electrical specifications VTPCLKmax VTPCLKmin/ VTNCLKmax T_OV VTNCLKmin T_DZ T_OV T_ZD VOHmin VOLmax Figure 3-4 Table 3-20 PHY timing - clock output/input and data input PHY timing parameters (1.8 V systems) Name Description Minimum Typ Maximum Units VOH_CLK Voltage level for clock high output 0.8 x VDD - - V VOL_CLK Voltage level for clock low output - - 0.2 x VDD V VTPCLK Voltage threshold for positive-going clock edges 0.9 - 1.17 V VTNCLK Voltage threshold for negative-going clock edges 0.63 - 0.9 V T_slew_CLK Slew time for positive or negative clock edge on clock output 2 - 5.4 ns T_High_CLK Duration of high half-period on clock output 35.3 - - ns T_Low_CLK Duration of low half-period on clock output 35.3 - - ns DC_Out_Clock Duty cycle generated at clock output 46 - 54 % DC_In_Clock Duty cycle received at clock input 45 - 55 % T_Slew_Data Slew time for data output changing from low to high or high to low 2 - - ns T_DZ Time to disable data output after positive or negative edge on clock input - - 4 ns T_ZD Time to enable data output after positive or negative edge on clock input 7.9 - - ns T_OV Time for data output to remain stable or valid after positive or negative edge on clock input - - 27.6 ns LM80-P2751-29 Rev. A 38 WCD9335 Audio Codec Device Specification Name Electrical specifications Description Minimum Typ Maximum Units 6.7 - - ns T_OH Time for data output to remain stable after positive or negative edge on clock input t_ISetup_min Minimum setup time demanded by a data input before a positive or negative edge on clock input - - 0 ns t_IHold_min Minimum hold time demanded by a data input after to a positive or negative edge on clock input - - 4 ns t_Keeper_Settle Time to bus-keeper generating the correct value on the data output after a continuously stable data value has been presented on the data input - - 2.5 ns Frequency Clock output frequency 0.6 -11 12.288 MHz 1. When MCLK = 12.288 MHz, SoundWire clock = 768 kHz, 1.536 MHz, 3.072 MHz, 6.144 MHz, or 12.288 MHz. When MCLK = 9.6 MHz, SoundWire clock = 600 kHz, 1.2 MHz, 2.4 MHz, 4.8 MHz, or 9.6 MHz. 3.8 Support circuits - analog 3.8.1 Microphone bias NOTE Table 3-21 Microphone bias performances are measured with 0.1 uF load capacitance and output voltage of 2.85 V. Microphone bias performance Parameter Output voltage normal operation error Load current Output noise Power supply rejection ratio Load capacitance LM80-P2751-29 Rev. A Conditions 3 mA microphone load Output current that the MIC bias output can source - 100 mVpp applied to VDD_MIC_BIAS input; 1.5 mA microphone load 20 Hz 200 Hz to 1 kHz 2 kHz 10 kHz 20 kHz Capacitances directly at the MIC bias output Minimum Typ Maximum Units 1 -50 1.8 - 2.85 50 V mV 0.005 - 6 mA - 2.5 - V 93 113 100 90 78 - - - - - - - - - - dB dB dB dB dB 0.025 0.1 0.5 F 39 4 Device marking and ordering information The WCD9335 is available in the 113 FOWPSP that includes ground pads for improved grounding, mechanical strength, and thermal continuity. The 113 FOWPSP has a 4.17 x 3.91 x 0.65 mm body with a maximum height of 0.65 mm. A simplified version of the 113 FOWPSP outline drawing is shown in Figure 4-1. LM80-P2751-29 Rev. A 40 WCD9335 Audio Codec Device Specification Figure 4-1 NOTE LM80-P2751-29 Rev. A Device marking and ordering information 113 FOWPSP (4.17 x 3.91 x 0.65 mm) package outline drawing This is a simplified outline drawing. 41 WCD9335 Audio Codec Device Specification Device marking and ordering information 4.1 Device ordering information 4.1.1 Specification-compliant devices Use the identification code shown in Figure 4-2 to order the device. 'HYLFH,' FRGH $$$$$$$ 6\PERO GHILQLWLRQ 3URGXFW QDPH ([DPSOH :&' Figure 4-2 LM80-P2751-29 Rev. A 3 &RQILJ FRGH &&& '''''' 1XPEHU 3DFNDJH RISDGV W\SH (( 6KLSSLQJ SDFNDJH )2:363 +565 RU75 55 6 3URGXFW 6RXUFH YHUVLRQ FRGH Device identification code 42 5 Carrier, storage, & handling information 5.1 Carrier 5.1.1 Tape and reel information All carrier tape systems conform to EIA-481 standards. A simplified sketch of the WCD9335 tape carrier is shown in Figure 5-1, including the proper part orientation, maximum number of devices per reel, and key dimensions. Tape width Pin A1 faces feed holes Taping direction Tape feed: Units per reel: Figure 5-1 LM80-P2751-29 Rev. A Pocket pitch Single 100 for HR 500 for SR 2000 for TR Reel diameter: 178 mm Tape width: 12 mm Hub diameter: 55 mm 8 mm Pocket pitch: Carrier tape drawing with part orientation 43 WCD9335 Audio Codec Device Specification Carrier, storage, & handling information Tape-handling recommendations are shown in Figure 5-2. Handle only at the edges Figure 5-2 Tape handling 5.2 Storage 5.2.1 Bagged storage conditions The WCD9335 devices delivered in tape and reel carriers must be stored in sealed, moisture barrier, antistatic bags. 5.2.2 Out-of-bag duration The out-of-bag duration is the time a device can be on the factory floor before being installed onto a PCB. 5.3 Handling Tape handling was discussed in Section 5.1.1. Other (IC-specific) handling guidelines are presented in this section. Unlike traditional IC devices, the die within a fan-out wafer-level package (WLP) is not protected by an overmold and substrate; hence, these devices are relatively fragile. NOTE To avoid damage to the die due to improper handling, follow these recommendations: * Do not use tweezers; a vacuum tip is recommended for handling the devices. * Carefully select a pickup tool for use during the SMT process. * Do not touch the device when reworking or tuning the components located near the device. 5.3.1 Baking Baking is not required if material is stored in a 30C/60% RH condition. LM80-P2751-29 Rev. A 44 WCD9335 Audio Codec Device Specification 5.3.2 Carrier, storage, & handling information Electrostatic discharge Electrostatic discharge (ESD) occurs naturally in laboratory and factory environments. An established high-voltage potential is always at risk of discharging to a lower potential. If this discharge path is through a semiconductor device, destructive damage can occur. Develop and use the ESD countermeasures and handling methods to control the factory environment at each manufacturing site. You must handle products according to the ESD Association standard: ANSI/ESD S20.20-1999, Protection of Electrical and Electronic Parts, Assemblies, and Equipment. LM80-P2751-29 Rev. A 45 6 PCB mounting guidelines 6.1 RoHS compliance The device complies with the requirements of the EU restriction of hazardous substances (RoHS) directive. Its tin-silver-copper (Sn/Ag/Cu) solder balls use SAC405 composition. LM80-P2751-29 Rev. A 46 7 Device reliability 7.1 Reliability qualifications summary Table 7-1 Silicon reliability results Tests, standards, and conditions Sample size Result 370 Pass < 1000 DPPM HTOL in FIT (l) failure in billion device hours HTOL: JESD22-A108-A (Total samples from three different wafer lots) 370 Pass < 50 FIT Mean time to failure (MTTF) t = 1/l in million hours 370 > 20 ESD - Human-body model (HBM) rating JESD22-A114-F (Total samples from one wafer lot) 3 2000 V ESD - Charged-device model (CDM) rating JESD22-C101-D (Total samples from one wafer lot) 3 500 V Latch-up (I-test): EIA/JESD78A Trigger current: 100 mA; temperature: 85C (Total samples from one wafer lot) 6 Pass Latch-up (Vsupply overvoltage): EIA/JESD78A Trigger voltage: Each VDD pin, stress at 1.5 x Vdd max per device specification; temperature: 85C (Total samples from one wafer lot) 6 Pass ELFR in DPPM HTOL: JESD22-A108-A (Total samples from three different wafer lots) (Total samples from three different wafer lots) LM80-P2751-29 Rev. A 47 WCD9335 Audio Codec Device Specification Table 7-2 Device reliability Package reliability results Assembly source SCS Sample size Assembly source Nanium Sample size Result Moisture resistance test (MRT): J-STD-020E Reflow at 260 +0/-5C (Total samples from three different assembly lots at each SAT) 480 480 Pass Temperature cycle: JESD22-A104-D Temperature: -55C to 125C; number of cycles: 1000 Soak time at minimum/maximum temperature: 8-10 minutes Cycle rate: 2 cycles per hour (CPH) Preconditioning: JESD22-A113-F MSL1, reflow temperature: 260C+0/-5C (Total samples from three different assembly lots at each SAT) 240 240 Pass Unbiased highly accelerated stress test (UHAST): JESD22-A118-B Stress condition: 130C/85% RH, 96 hrs Preconditioning: JESD22-A113-F MSL: 1, reflow temperature: 260 +0/-5C (Total samples from three different assembly lots at each SAT) 240 240 Pass High-temperature storage life: JESD22-A103-C Temperature 150C, 1000 hours (Total samples from three different assembly lots at each SAT) 240 240 Pass Solder ball shear: JESD22-B117 15 15 Pass Flammability UL-STD-94 Flammability test - not required Note: ICs are exempt from flammability requirements due to their size per UL/EN 60950-1, as long as they are mounted on materials rated V-1 or better. Most PWBs onto which ICs are mounted are rated V-0 (better than V-1). - - See Note Physical dimensions: JESD22-B100-A Case outline drawing: Qualcomm internal document (Total samples from three different assembly lots at each SAT) 60 60 Pass Tests, standards, and conditions LM80-P2751-29 Rev. A 48 EXHIBIT 1 PLEASE READ THIS LICENSE AGREEMENT ("AGREEMENT") CAREFULLY. THIS AGREEMENT IS A BINDING LEGAL AGREEMENT ENTERED INTO BY AND BETWEEN YOU (OR IF YOU ARE ENTERING INTO THIS AGREEMENT ON BEHALF OF AN ENTITY, THEN THE ENTITY THAT YOU REPRESENT) AND Qualcomm Technologies, Inc. ("QTI" "WE" "OUR" OR "US"). THIS IS THE AGREEMENT THAT APPLIES TO YOUR USE OF THE DESIGNATED AND/OR ATTACHED DOCUMENTATION AND ANY UPDATES OR IMPROVEMENTS THEREOF (COLLECTIVELY, "MATERIALS"). BY USING OR COMPLETING THE INSTALLATION OF THE MATERIALS, YOU ARE ACCEPTING THIS AGREEMENT AND YOU AGREE TO BE BOUND BY ITS TERMS AND CONDITIONS. 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