[AK4497]
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1. General Description
The AK4497 is a new generation Premium 32-bit 2ch DAC with VELVET SOUNDTM technology,
achieving industry’s leading level low distortion characteristics and wide dynamic range. The AK4497
integrates a newly developed switched capacitor filter “OSR Doubler”, making it capable of supporting
wide range signals and achieving low out-of-band noise while realizing low power consumption.
Moreover, the AK4497 has six types of 32-bit digital filters, realizing simple and flexible sound tuning in
wide range of applications. The AK4497 accepts up to 768kHz PCM data and 22.4MHz DSD data, ideal
for a high-resolution audio source playback that are becoming widespread in network audios,
USB-DACs and Car Audio Systems.
Application: AV Receivers, CD/SACD player, Network Audios, USB DACs, USB Headphones, Sound
Plates/Bars, Measurement Equipment, Control Systems, Public Audios (PA), IC-Recorders,
Bluetooth Headphones, HD Audio/Voice Conference Systems
2. Features
THD+N: -116dB
DR, S/N: 131dB (2.6 Vrms Output)
128dB (2 Vrms Output)
256 Times Over Sampling
Sampling Rate: 8kHz 768kHz
32-bit 8x Digital Filter
- Short Delay Sharp Roll-off, GD=6.0/fs,
Ripple: 0.005dB, Attenuation: 100dB
- Short Delay Slow Roll-off, GD=5.0/fs
- Sharp Roll-off
- Slow Roll-off
- Low-dispersion Short Delay Filter
- Super Slow Roll-off
2.8MHz, 5.6MHz, 11.2MHz, 22.4MHz DSD Input Support
- Filter1 (fc=39kHz, 2.8MHz mode), Filter2 (fc=76kHz, 2.8MHz mode)
Digital De-emphasis for 32, 44.1, 48kHz sampling
Soft Mute
Digital Attenuator (255 levels and 0.5dB step + mute)
Mono Mode
External Digital Filter Interface
Audio I/F Format: 24/32 bit MSB justified, 16/20/24/32 bit LSB justified, I2S, DSD, TDM
Master Clock
8kHz ~ 32kHz: 256fs or 384fs or 512fs or 768fs or 1152fs
8kHz ~ 54kHz: 256fs or 384fs or 512fs or 768fs
8kHz ~ 108kHz: 256fs or 384fs
108kHz ~ 216kHz: 128fs or 192fs
~ 384kHz: 32fs or 48fs or 64fs or 96fs
~ 768kHz: 16fs or 32fs or 48fs or 64fs
Power Supply:
TVDD=AVDD= 3.0 3.6V (by Internal LDO), VDDL/R= 4.75 ~ 5.25V
TVDD=AVDD= 1.7 3.6V (by external supply), DVDD=1.7 1.98V,
VDDL/R= 4.75 5.25V
Digital Input Level: CMOS
Package: 64-pin TQFP
AK4497
Quality Oriented 32-Bit 2ch DAC
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3. Table of Contents
1. General Description ........................................................................................................................ 1
2. Features .......................................................................................................................................... 1
3. Table of Contents ............................................................................................................................ 2
4. Block Diagram ................................................................................................................................. 4
5. Pin Configurations and Functions ................................................................................................... 5
■ Pin Configurations .............................................................................................................................. 5
■ Pin Functions ..................................................................................................................................... 6
■ Handling of Unused Pin ..................................................................................................................... 8
6. Absolute Maximum Ratings .......................................................................................................... 10
7. Recommended Operating Conditions .......................................................................................... 10
8. Electrical Characteristics .............................................................................................................. 11
■ Analog Characteristics ..................................................................................................................... 11
■ DSD Mode ........................................................................................................................................ 13
■ Sharp Roll-Off Filter Characteristics ................................................................................................ 14
■ Slow Roll-Off Filter Characteristics .................................................................................................. 16
■ Short Delay Sharp Roll-Off Filter Characteristics ............................................................................ 18
■ Short Delay Slow Roll-Off Filter Characteristics .............................................................................. 20
■ Low-dispersion Short Delay Filter Characteristics ........................................................................... 22
■ DSD Filter Characteristics ................................................................................................................ 24
■ DC Characteristics ........................................................................................................................... 24
■ Switching Characteristics ................................................................................................................. 25
■ Timing Diagram ................................................................................................................................ 30
9. Functional Descriptions................................................................................................................. 35
■ D/A Conversion Mode (PCM Mode, DSD Mode, EXDP Mode) ...................................................... 37
■ D/A Conversion Mode Switching Timing ......................................................................................... 37
■ System Clock ................................................................................................................................... 39
■ Audio Interface Format .................................................................................................................... 49
■ Digital Filter ...................................................................................................................................... 61
■ De-emphasis Filter (PCM Mode) ..................................................................................................... 62
■ Output Volume (PCM Mode, DSD Mode, EXDF Mode) .................................................................. 62
■ Gain Adjustment Function (PCM Mode, DSD Mode, EXDF Mode) ................................................ 63
■ Zero Detection (PCM Mode, DSD Mode, EXDF Mode) .................................................................. 64
■ L/R Channel Output Signal Select, Phase Inversion Function (PCM Mode, DSD Mode, EXDF Mode)
.............................................................................................................................................................. 65
■ Sound Quality (PCM Mode, DSD Mode, EXDF Mode) ................................................................... 65
■ DSD Signal Full Scale (FS) Detection ............................................................................................. 66
■ Soft Mute Operation (PCM Mode, DSD Mode, EXDF Mode) ......................................................... 68
■ LDO .................................................................................................................................................. 69
■ Shutdown Switch .............................................................................................................................. 69
■ Over Current Protection for Analog Output Pins ............................................................................. 69
■ Power Up/Down Function ................................................................................................................ 70
■ Synchronize Function (PCM mode, EXDF mode) ........................................................................... 78
■ Register Control Interface ................................................................................................................ 80
■ Register Map .................................................................................................................................... 84
■ Register Definitions .......................................................................................................................... 86
10. Recommended External Circuits .................................................................................................. 95
11. Package ........................................................................................................................................ 99
■Outline Dimensions ........................................................................................................................... 99
■ Material & Lead Finish ................................................................................................................... 100
■ Marking ........................................................................................................................................... 100
12. Ordering Guide ........................................................................................................................... 101
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■ Ordering Guide ............................................................................................................................... 101
13. Revision History .......................................................................................................................... 101
IMPORTANT NOTICE ........................................................................................................................... 102
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4. Block Diagram
MCLK
SDATA/DINL/DSDL
SMUTE/CSN
BICK/BCK/DCLK
SD/ CCLK/SCL
SLOW/CDTI/SDA
VSSR
VDDR
PDN
AVDD
SCF
SCF
Clock
Divider
DVSS
DVDD
SSLOW/WCK
ACKS/
CAD1
PSN
DIF0/
DZFL
DIF2/
CAD0
VSSL
VDDL
VCML
AOUTRN
VCMR
VREFHL
VREFLL
VREFLR
VREFHR
AVSS
AOUTLP
AOUTLN
AOUTRP
PCM
Data
Interface
DSD
Data
Interface
External
DF
Interface
Control
Register
Vref
LRCK/DINR/DSDR
DIF1/
DZFR
DATT
Soft Mute
Modulator
Volume bypass
DSDD bit “1”
Normal path
DSDD bit “0”
Oscillator
TVDD
TDM1
DCHAIN
LDO
LDOE
TDM0/DCLK
DEM0/DSDL
GAIN/DSDR
TDMO
INVR
TESTE
HLOAD
/I2C
EXTR
IREF
DSD
Filter
De-emphasis
&
Interpolator
MCLK Detection
Figure 1. Block Diagram
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5. Pin Configurations and Functions
■ Pin Configurations
Figure 2. Pin Configurations
The exposed pad on the bottom surface of the package must be connected to AVSS.
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■ Pin Functions
No.
Pin Name
I/O
Function
1
LDOE
I
Internal LDO Enable Pin. “L”: Disable, “H”: Enable
2
PDN
I
Power-Down Mode Pin
When at “L”, the AK4497 is in power-down mode and is held in reset. The
AK4497 must always be reset upon power-up.
3
BICK
I
Audio Serial Data Clock Pin in PCM Mode
BCK
I
Audio Serial Data Clock Pin
DCLK
I
DSD Clock Pin in DSD Mode (DSDPATH bit = “1”)
4
SDATA
I
Audio Serial Data Input Pin in PCM Mode
DINL
I
Lch Audio Serial Data Input Pin
DSDL
I
DSD Lch Data Input Pin in DSD Mode(DSDPATH bit = “1”)
5
LRCK
I
L/R Clock Pin in PCM Mode
DINR
I
Rch Audio Serial Data Input Pin
DSDR
I
DSD Rch Data Input Pin in DSD Mode(DSDPATH bit = “1”)
6
SSLOW
I
Digital Filter Select Pin in Pin Control Mode
WCK
I
Word Clock input pin
7
TDMO
O
Audio Serial Data Output in Daisy Chain mode (Internal pull-down pin)
8
SMUTE
I
When this pin is changed to “H”, soft mute cycle is initiated.
When returning “L”, the output mute releases.
CSN
I
Chip Select Pin in Register Control Mode
9
SD
I
Digital Filter Select Pin in Pin Control Mode
CCLK
I
Control Data Clock Pin in Register Control Mode
SCL
I
I2C=”H”: Control Data Clock Input Pin
10
SLOW
I
Digital Filter Select Pin in Pin Control Mode
CDTI
I
Control Data Input Pin in Register Control Mode
SDA
I/O
I2C=”H”: Control Data Input Pin
11
DIF0
I
Digital Input Format 0 Pin in Pin Control Mode
DZFL
O
Lch Zero Input Detect Pin in Register Control Mode (Internal pull-down pin)
12
DIF1
I
Digital Input Format 1 Pin in Pin Control Mode
DZFR
O
Rch Zero Input Detect Pin in Register Control Mode (Internal pull-down pin)
13
DIF2
I
Digital Input Format 2 Pin in Pin Control Mode
CAD0
I
Chip Address 0 Pin in Register Control Mode
14
PSN
I
Pin Control Mode or Register Control Mode select Pin (Internal pull-up pin)
“L”: Register Control Mode, “H”: Pin Control Mode
15
HLOAD
I
Heavy Load Mode Enable Pin in Pin Control Mode.
I2C
Resister Control Interface Pin in Register Control Mode.
16
DEM0
I
De-emphasis Enable 0 Pin in Pin Control Mode
DSDL
I
DSD Lch Data Input Pin in DSD Mode (DSDPATH bit =”0”)
17
GAIN
I
Output Gain Control Pin in Pin control mode (+2.5dB)
DSDR
I
DSD Rch Input Pin in DSD Mode (DSDPATH bit =”0”)
18
ACKS
I
Auto Setting Mode Select Pin in Pin control mode
“L”: Manual Setting Mode, “H”: Auto Setting Mode
CAD1
I
Chip Address 1 Pin in Register Control Mode
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No.
Pin Name
I/O
Function
19
TDM0
I
TDM Mode Select Pin in Pin Control Mode.
DCLK
I
DSD clock Pin in DSD Mode (DSDPATH bit = “0”)
20
TDM1
I
TDM Mode select Pin in Pin Control Mode.
21
DCHAIN
I
Daisy Chain Mode Select Pin in Pin Control Mode.
22
INVR
I
Rch Output Data Invert Enable Pin in Pin Control Mode.
23
TESTE
I
Test Mode Enable Pin. (Internal pull-down pin)
24-26
VREFHR
I
Rch High Level Voltage Reference Input Pin
27-29
VREFLR
I
Rch Low Level Voltage Reference Input Pin
30
VCMR
I
Right Channel Common Voltage Pin,
Normally connected to VREFLR with a 10uF electrolytic cap.
This pin is prohibited to connect other devices.
31,32
AOUTRN
O
Rch Negative Analog Output Pin
33,34
AOUTRP
O
Rch Positive Analog Output Pin
35-37
VDDR
-
Rch Analog Power Supply Pin
38-40
VSSR
-
Analog Ground Pin
41-43
VSSL
-
Analog Ground Pin
44-46
VDDL
-
Lch Analog Power Supply Pin
47,48
AOUTLP
O
Lch Positive Analog Output Pin
49,50
AOUTLN
O
Lch Negative Analog Output Pin
51
VCML
-
Left channel Common Voltage Pin
Normally connected to VREFLL with a 10uF electrolytic cap.
This pin is prohibited to connect other devices.
52-54
VREFLL
I
Lch Low Level Voltage Reference Input Pin
55-57
VREFHL
I
Lch High Level Voltage Reference Input Pin
58
EXTR
I
External Resistor Connect Pin
Rext=33kΩ(±0.1%) to AVSS
59
AVDD
-
(LDOE pin = “H”)
Analog Power Supply Pin, 3.0 3.6V
-
(LDOE pin = “L”)
Analog Power Supply Pin, 1.7 3.6V
60
AVSS
-
Analog Ground Pin
61
MCLK
I
Master Clock Input Pin
62
DVDD
O
(LDOE pin = “H”)
LDO Output Pin,
This pin should be connected to DVSS with 1.0µF.
This pin is prohibited to connect other devices.
-
(LDOE pin = “L”)
Digital Power Supply Pin, 1.7 1.98V
63
DVSS
-
Digital Ground Pin
64
TVDD
-
(LDOE pin = “H”)
Digital Power Supply Pin, 3.0 3.6V
-
(LDOE pin = “L”)
Digital Power Supply Pin, 1.7 3.6V
Note 1. All input pins except internal pull-up/down pins must not be left floating.
Note 2. The AK4497 must be reset by PDN pin after changing Pin/Register control mode by the PSN pin.
Note 3. PCM mode, DSD mode and EXDF mode are controlled by register settings.
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■ Handling of Unused Pin
Unused I/O pins must be connected appropriately.
(1) Pin Control Mode (PCM mode only)
Classification
Pin Name
Status
Analog
AOUTLP, AOUTLN
Open
AOUTRP, AOUTRN
Open
Digital
TESTE
Connect to DVSS or Open
(2) Resister Control Mode
1. PCM Mode
Classification
Pin Name
Status
Analog
AOUTLP, AOUTLN
Open
AOUTRP, AOUTRN
Open
Digital
TESTE
Connect to DVSS or Open
TDMO, DZFL, DZFR
Open
2. DSD Mode
DSDPATH bit = “0”
Classification
Pin Name
Status
Analog
AOUTLP, AOUTLN
Open
AOUTRP, AOUTRN
Open
Digital
BICK, SDATA, LRCK, WCK, TDM1,
DCHAIN, INVR, TESTE
Connect to DVSS
TESTE
Connect to DVDD or Open
TDMO, DZFL, DZFR
Open
DSDPATH bit = “1”
Classification
Pin Name
Status
Analog
AOUTLP, AOUTLN
Open
AOUTRP, AOUTRN
Open
Digital
DEM0, GAIN, TDM0, WCK, TDM1,
DCHAIN, INVR
Connect to DVSS
TESTE
Connect to DVSS or Open
TDMO, DZFL, DZFR
Open
3. EXDF Mode
Classification
Pin Name
Status
Analog
AOUTLP, AOUTLN
Open
AOUTRP, AOUTRN
Open
Digital
DEM0, GAIN, TDM0, TDM1,
DCHAIN, INVR
Connect to DVSS
TESTE
Connect to DVSS or Open
TDMO, DZFL, DZFR
Open
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4. I2C-Bus Mode
Classification
Pin Name
Status
Digital
CSN
Connect to DVSS
Pull-up and Pull-down pins List
Classification
Pin Name
Status
pull-up pin (typ=100kΩ)
PSN
Connect to TVDD or Open
pull-down pin (typ=100kΩ)
TDMO, DZFL, DZFR, TESTE
Connect to DVSS or Open
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6. Absolute Maximum Ratings
(AVSS=DVSS=VSSL=VSSR=VREFLL=VREFLR=0V; Note 4)
Parameter
Symbol
Min.
Max.
Unit
Power
Supplies:
Digital I/O
Digital Core
Clock Interface
Analog
|AVSS DVSS| (Note 5)
TVDDam
DVDDam
AVDDam
VDDL/Ram
GND
0.3
0.3
0.3
0.3
-
4.0
2.5
4.0
6.0
0.3
V
V
V
V
V
Input Current, Any Pin Except Supplies
IIN
-
10
mA
Digital Input Voltage
VIND
0.3
TVDD+0.3
V
Ambient Temperature (Power supplied)
Ta
40
85
C
Storage Temperature
Tstg
65
150
C
Note 4. All voltages with respect to ground.
Note 5. AVSS, DVSS, VSSL and VSSR must be connected to the same analog ground plane. Connect
the exposed pad on the bottom surface of the package to AVSS.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
7. Recommended Operating Conditions
(AVSS=DVSS=VSSL=VSSR=VREFLL=VREFLR=0V; Note 4)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Power Supplies
■ LDOE pin= “L”
Digital I/O
Clock Interface
Digital Core
Analog
■ LDOE pin= “H”
Digital I/O
Clock Interface
Analog
TVDD
AVDD
DVDD
VDDL/R
TVDD
AVDD
VDDL/R
DVDD
DVDD
1.7
4.75
3.0
3.0
4.75
1.8
1.8
1.8
5.0
3.3
3.3
5.0
3.6
3.6
1.98
5.25
3.6
3.6
5.25
V
V
V
V
V
V
V
Voltage Reference
(Note 7)
“H” voltage reference
“L” voltage reference
VREFHL/R
VREFLL/R
VDDL/R-0.5
-
-
VSSL/R
VDDL/R
-
V
V
Note 4. All voltages with respect to ground.
Note 6. The analog output voltage scales with the voltage of (VREFHL/R VREFLL/R).
Note 7. TVDD and AVDD must be connected to the same ground plane and powered up at the same time.
When not using the LDO (LDOE pin = “L”), all power supplies (DVDD (1.8V), TVDD and AVDD
(3.3V) and VDDL/R (5V)) should be powered up at the same time or sequentially in the order of
3.3V (TVDD, AVDD), 1.8V (DVDD) and 5V (VDDL/R).
Note 8. The internal LDO outputs DVDD (1.8V) when the LDOE pin = “H”. 3.3V (TVDD and AVDD) power
supplies must be powered up before or at the same time with 5V (VDDL/R) power supplies when
the LDOE pin = “H”.
* AKM assumes no responsibility for the usage beyond the conditions in this data sheet.
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8. Electrical Characteristics
■ Analog Characteristics
(Ta=25C; LDOE pin = “L”, AVDD=TVDD=3.3V, DVDD=1.8V, AVSS=DVSS=VSSL/R=0V;
VREFHL/R=VDDL/R=5.0V, VREFLL/R= 0V; Input data = 24bit; BICK=64fs; Signal Frequency = 1kHz;
Sampling Frequency = 44.1kHz; Measurement bandwidth = 20Hz ~ 20kHz; External Circuit: Figure 77;
SC[2:0] bit=“000”; 2Vrms output mode (GC[2:0] bit=“000” or GAIN pin=“L”); Heavy load drive
mode=off(HLOAD bit=”0” or HLOAD pin=”L”); unless otherwise specified.)
Parameter
Min.
Typ.
Max.
Unit
Resolution
-
-
32
Bits
Dynamic Characteristics (Note 9)
THD+N
fs=44.1kHz
BW=20kHz
0dBFS
GC[2:0]= “000” or
GAIN= “L”
-
116
108
dB
GC[2:0]= “100” or
GAIN= “H”
-
113
-
60dBFS
-
65
-
dB
fs=96kHz
BW=40kHz
0dBFS
-
113
-
dB
60dBFS
-
62
-
dB
fs=192kHz
BW=40kHz
0dBFS
-
110
-
dB
60dBFS
-
-62
-
dB
BW=80kHz
60dBFS
-
-59
-
dB
Dynamic Range (60dBFS with A-weighted) (Note 10)
125
128
-
dB
S/N (A-weighted)
(Note 11)
GC[2:0]= “000” or GAIN= “L”
125
128
-
dB
GC[2:0]= “100” or GAIN= “H”
Stereo mode
-
131
-
dB
Mono mode
(Note 17)
-
133
-
Interchannel Isolation (1kHz)
110
120
-
dB
DC Accuracy
Interchannel Gain Mismatch
-
0.15
0.3
dB
Gain Drift (Note 12)
-
20
-
ppm/C
Output
Voltage
GC[2:0] bits=“000” or GAIN pin=“L” (Note 13)
2.65
2.8
2.95
Vpp
GC[2:0] bits=“100” or GAIN pin=“H” (Note 14)
3.55
3.75
3.95
Vpp
Load
Resistance
(Note 15)
HLOAD bit=“0” or HLOAD pin=“L”
8
10
-
k
HLOAD bit=“1” or HLOAD pin=“H”
120
-
-
Load Capacitance (Note 15)
-
-
25
pF
Note 9. Measured by Audio Precision APx555. Averaging mode.
Note 10. 101dB at 16bit data and 118dB at 20bit data.
Note 11. S/N does not depend on the input data size.
Note 12. The voltage on (VREFH VREFL) is held +5V externally.
Note 13. The analog output voltage with 0dBFS input signal when GC[2:0] bits = “000” or the GAIN pin =
“L” is calculated by the following formula.
AOUTL/R (typ.@0dB) = (AOUT+) (AOUT) = 2.8Vpp (VREFHL/R VREFLL/R)/5.
Note 14. The analog output voltage with 0dBFS input signal when GC[2:0] bits = “100” or the GAIN pin =
“H” is calculated by the following formula.
AOUTL/R (typ.@0dB) = (AOUT+) (AOUT) = 3.75Vpp (VREFHL/R VREFLL/R)/5.
Note 15. Regarding Load Resistance, AC load is 8k (min) with a DC cut capacitor when HLOAD bit = “0”
or the HLOAD pin = “L”. DC load is 120 (min) without a DC cut capacitor if the HLOAD pin = “H”.
The load resistance value is with respect to ground. Analog characteristics are sensitive to
capacitive load that is connected to the output pin. Therefore the capacitive load must be
minimized.
Note 16. It is recommended to use a resistor with 0.1% absolute error for the output stage of the adding
circuit.
Note 17. This mode is shown in Figure 78.
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(Ta=25C; AVDD=TVDD=3.3V, DVDD=1.8V(@LDOE pin= “L”), AVSS=DVSS=VSSL/R=0V;
VREFHL/R=VDDL/R=5.0V, VREFLL/R= 0V; Input data = 24bit; BICK=64fs; Signal Frequency = 1kHz;
Sampling Frequency = 44.1kHz; SC[2:0] bits= “000”); 2Vrms output mode (GC[2:0] bits= “000” or GAIN
pin = “L”); Heavy load drive mode=off (HLOAD bit= “0” or HLOAD pin= “L”); unless otherwise specified.)
Power Supplies
Parameter
Min.
Typ.
Max.
Unit
Power Supply Current
Normal operation (PDN pin = “H”)
VDDL/R(total)
64
96
mA
VREFHL/R
1
1.5
mA
AVDD
-
1
1.5
mA
TVDD
LDOE pin = “H”
fs= 44.1kHz
8
12
mA
fs= 96kHz
-
13
20
mA
fs = 192kHz
-
20
30
mA
LDOE pin = “L”
1
1.5
mA
DVDD
LDOE pin = “L”
fs= 44.1kHz
8
12
mA
fs= 96kHz
13
20
mA
fs = 192kHz
20
30
mA
Total Idd per channel (HLOAD pin = “H”)
・fs=44.1kHz
45
72
mA/ch
Power down (PDN pin = “L”) (Note 18)
TVDD+AVDD+VDDL/R+DVDD
-
10
100
A
Note 18. In power down mode, the PSN pin = TVDD and all other digital input pins including clock pins
(MCLK, BICK and LRCK) are held to DVSS.
Note 19. The DVDD pin becomes an output pin when the LDOE pin = “H”.
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■ DSD Mode
(Ta=25C; AVDD=TVDD=3.3V, DVDD=1.8V (@LDOE pin = “L”), AVSS=DVSS=VSSL/R=0V;
VREFHL/R=VDDL/R=5.0V, VREFLL/R= 0V; Signal Frequency = 1kHz; Measurement bandwidth = 20Hz
~ 20kHz; External Circuit; Example circuit 3 (Figure 77); SC[2:0] bit=“000”; 2Vrms output mode (GC[2:0]
bits=“000” or GAIN pin=“L”); Heavy load drive mode=off(HLOAD bit=”0” or HLOAD pin= “L”); unless
otherwise specified.)
Parameter
Min.
Typ.
Max.
Unit
Dynamic Characteristics
THD+N
(Note 20)
DSD dataStream: 2.8224MHz
0dBFS
-
116
-
dB
DSD dataStream: 5.6448MHz
0dBFS
-
116
-
dB
DSD dataStream: 11.2896MHz
0dBFS
-
116
-
dB
S/N
(A-weighted,
Normal path)
(Note 20)
DSD dataStream: 2.8224MHz
Digital“0”
(Note 23)
-
128
-
dB
DSD dataStream: 5.6448MHz
Digital“0”
(Note 23)
-
128
-
dB
DSD dataStream: 11.2896MHz
Digital“0”
(Note 23)
-
128
-
dB
DC Accuracy
Output Voltage (Normal path) (Note 13)
2.65
2.8
2.95
Vpp
Output Voltage (Volume Bypass) (Note 24)
2.38
2.5
2.63
Vpp
Note 20. Analog characteristics are not guaranteed when the DSD dataStream is 22.5782MHz.
Note 21. The peak level of DSD signal should be in the range of 25% ~ 75% Duty according to the
SACD format book (Scarlet Book).
Note 22. The output level is assumed as 0dB when a 1kHz 25% ~ 75% duty sine wave is input. Click
noise may occur if the input signal exceeds 0dB.
Note 23. Digital “0” is a digital zero code pattern (“01101001”) according to the SACD format book
(Scarlet Book).
Note 24. When DSDD bit = “1”, the analog output voltage with 25 ~ 75% input duty is given by following
formula.
AOUTL/R (typ.@0dB) = (AOUTLP/RP) (AOUTLN/RN) = 2.5Vpp (VREFHL/R
VREFLL/R)/5.0.
[AK4497]
016003187-E-00 2016/05
- 14 -
■ Sharp Roll-Off Filter Characteristics
Sharp Roll-Off Filter Characteristics (fs=44.1kHz)
(Ta=-40~85C; VDDL/R=4.75 5.25V, AVDD= TVDD=1.7 3.6V, DVDD=1.7~1.98V; Normal Speed
Mode; DEM=OFF; SD bit=“0” or SD pin = “L”, SLOW bit=“0” or SLOW pin = “L”, SSLOQ bit = “0” or
SSLOW pin = “L”)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Digital Filter
Frequency Response
(Note 25)
0.01dB
6.0dB
PB
-
0
-
22.05
20.0
-
kHz
kHz
Passband (Note 26)
PB
0
20.0
kHz
Stopband (Note 26)
SB
24.1
kHz
Passband Ripple (Note 27)
PR
0.005
dB
Stopband Attenuation (Note 25)
SA
100
dB
Group Delay (Note 28)
GD
-
29.2
-
1/fs
Digital Filter + SCF (Note 25)
Frequency Response: 0 20.0kHz
0.2
-
+0.1
dB
Sharp Roll-Off Filter Characteristics (fs=96kHz)
(Ta=-40~85C; VDDL/R=4.75 5.25V, AVDD= TVDD=1.7 3.6V, DVDD=1.7~1.98V; Double Speed
Mode; DEM=OFF; SD bit=“0” or SD pin = “L”, SLOW bit=“0” or SLOW pin = “L”, SSLOW bit = “0” or
SSLOW pin = “L”)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Digital Filter
Frequency Response
(Note 25)
0.01dB
6.0dB
PB
0
-
48.0
43.5
-
kHz
kHz
Passband (Note 26)
PB
0
43.5
kHz
Stopband (Note 26)
SB
52.5
kHz
Passband Ripple (Note 27)
PR
0.005
dB
Stopband Attenuation (Note 25)
SA
100
dB
Group Delay (Note 28)
GD
-
29.2
-
1/fs
Digital Filter + SCF (Note 25)
Frequency Response: 0 40.0kHz
0.6
-
+0.1
dB
Sharp Roll-Off Filter Characteristics (fs=192kHz)
(Ta=-40~85C; VDDL/R=4.75 5.25V, AVDD= TVDD=1.7 3.6V, DVDD=1.7~1.98V; Quad Speed Mode;
DEM=OFF; SD bit=“0” or SD pin=“L”, SLOW bit=“0” or SLOW pin=“L”, SSLOW bit=“0” or SSLOW pin=“L”)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Digital Filter
Frequency Response
(Note 25)
0.01dB
6.0dB
-
-
0
-
96.0
87.0
-
kHz
kHz
Passband (Note 26)
PB
0
87.0
kHz
Stopband (Note 26)
SB
105
kHz
Passband Ripple (Note 27)
PR
0.005
dB
Stopband Attenuation (Note 25)
SA
100
dB
Group Delay (Note 28)
GD
-
29.2
-
1/fs
Digital Filter + SCF (Note 25)
Frequency Response: 0 80.0kHz
2.0
-
+0.1
dB
Note 25. Frequency response refers to the output level (0dB) of a 1kHz, 0dB sine wave input.
Note 26. The passband and stopband frequencies scale with fs. For example, PB=0.4535×fs (@0.01dB),
SB=0.546×fs.
Note 27. The first stage of the Interpolator. This is a passband gain amplitude of the 4 times oversampling
filter.
Note 28. The calculating delay time which occurred by digital filtering. This time is from setting the
16/20/24/32 bit data of both channels to the output of analog signal.
[AK4497]
016003187-E-00 2016/05
- 15 -
Figure 3. Sharp Roll-off Filter Frequency Response
Figure 4. Sharp Roll-off Filter Passband Ripple
[AK4497]
016003187-E-00 2016/05
- 16 -
■ Slow Roll-Off Filter Characteristics
Slow Roll-Off Filter Characteristics (fs = 44.1kHz)
(Ta=-40~85C; VDDL/R=4.75 5.25V, AVDD= TVDD=1.7 3.6V, DVDD=1.7~1.98V; Normal Speed
Mode; DEM=OFF; SD bit=“0” or SD pin=“L”, SLOW bit=“1” or SLOW pin=“H”, SSLOW bit=“0” or SSLOW
pin=“L”)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Digital Filter
Frequency Response
(Note 25)
0.01dB
6.0dB
PB
-
0
-
-
21.0
8.0
-
kHz
kHz
Passband (Note 29)
PB
0
-
8.0
kHz
Stopband (Note 29)
SB
39.2
-
-
kHz
Passband Ripple (Note 27)
PR
-
-
0.007
dB
Stopband Attenuation (Note 25)
SA
92
-
-
dB
Group Delay (Note 28)
GD
-
6.5
-
1/fs
Digital Filter + SCF (Note 25)
Frequency Response: 0 20.0kHz
5.0
-
+0.1
dB
Slow Roll-Off Filter Characteristics (fs = 96kHz)
(Ta=-40~85C; VDDL/R=4.75 5.25V, AVDD= TVDD=1.7 3.6V, DVDD=1.7~1.98V; Double Speed
Mode; DEM=OFF; SD bit=“0” or SD pin=“L”, SLOW bit=“1” or SLOW pin=“H”, SSLOW bit=“0” or SSLOW
pin=“L”)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Digital Filter
Frequency Response
(Note 25)
0.01dB
6.0dB
PB
0
-
-
45.6
17.6
-
kHz
kHz
Passband (Note 29)
PB
0
-
17.6
kHz
Stopband (Note 29)
SB
85.4
-
-
kHz
Passband Ripple (Note 27)
PR
-
-
0.007
dB
Stopband Attenuation (Note 25)
SA
92
-
-
dB
Group Delay (Note 28)
GD
-
6.5
-
1/fs
Digital Filter + SCF (Note 25)
Frequency Response: 0 40.0kHz
3.8
-
+0.1
dB
Slow Roll-Off Filter Characteristics (fs = 192kHz)
(Ta=-40~85C; VDDL/R=4.75 5.25V, AVDD= TVDD=1.7 3.6V, DVDD=1.7~1.98V; Quad Speed Mode;
DEM=OFF; SD bit=“0” or SD pin=“L”, SLOW bit=“1” or SLOW pin=“H”, SSLOW bit=“0” or SSLOW
pin=“L”)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Digital Filter
Frequency Response
(Note 25)
0.01dB
6.0dB
-
-
0
-
-
91.2
35.2
-
kHz
kHz
Passband (Note 29)
PB
0
-
35.2
kHz
Stopband (Note 29)
SB
170.7
-
-
kHz
Passband Ripple (Note 27)
PR
-
-
0.007
dB
Stopband Attenuation (Note 25)
SA
100
-
-
dB
Group Delay (Note 28)
GD
-
6.5
-
1/fs
Digital Filter + SCF (Note 25)
Frequency Response: 0 80.0kHz
5.0
-
+0.1
dB
Note 29. The passband and stopband frequencies scale with fs. For example, PB = 0.1836 × fs
(@0.01dB), SB = 0.8889 × fs.
[AK4497]
016003187-E-00 2016/05
- 17 -
Figure 5. Slow Roll-off Filter Frequency Response
Figure 6. Slow Roll-off Filter Passband Ripple
[AK4497]
016003187-E-00 2016/05
- 18 -
■ Short Delay Sharp Roll-Off Filter Characteristics
Short Delay Sharp Roll-Off Filter Characteristics (fs = 44.1kHz)
(Ta=-40~85C; VDDL/R=4.75 5.25V, AVDD= TVDD=1.7 3.6V, DVDD=1.7~1.98V; Normal Speed
Mode; DEM=OFF; SD bit=“1” or SD pin=“H”, SLOW bit=“0” or SLOW bit=“L”, SSLOW bit=“0” or SSLOW
pin=“L”)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Digital Filter
Frequency Response
(Note 25)
0.01dB
6.0dB
-
-
0
-
-
22.05
20.0
-
kHz
kHz
Passband (Note 30)
PB
0
-
20.0
kHz
Stopband (Note 30)
SB
24.1
-
-
kHz
Passband Ripple (Note 27)
PR
-
-
0.005
dB
Stopband Attenuation (Note 25)
SA
100
-
-
dB
Group Delay (Note 28)
GD
-
6.0
-
1/fs
Digital Filter + SCF (Note 25)
Frequency Response: 0 20.0kHz
2.0
-
+0.1
dB
Short Delay Sharp Roll-Off Filter Characteristics (fs = 96kHz)
(Ta=-40~85C; VDDL/R=4.75 5.25V, AVDD= TVDD=1.7 3.6V, DVDD=1.7~1.98V; Double Speed
Mode; DEM=OFF; SD bit=“1” or SD pin=“H”, SLOW bit=“0” or SLOW bit=“L”, SSLOW bit=“0” or SSLOW
pin=“L”)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Digital Filter
Frequency Response
(Note 25)
0.01dB
6.0dB
-
-
0
-
-
48.0
43.5
-
kHz
kHz
Passband (Note 30)
PB
0
-
43.5
kHz
Stopband (Note 30)
SB
52.5
-
-
kHz
Passband Ripple (Note 27)
PR
-
-
0.005
dB
Stopband Attenuation (Note 25)
SA
100
-
-
dB
Group Delay (Note 28)
GD
-
6.0
-
1/fs
Digital Filter + SCF (Note 25)
Frequency Response: 0 40.0kHz
6.0
-
+0.1
dB
Short Delay Sharp Roll-Off Filter Characteristics (fs = 192kHz)
(Ta=-40~85C; VDDL/R=4.75 5.25V, AVDD= TVDD=1.7 3.6V, DVDD=1.7~1.98V; Quad Speed Mode;
DEM=OFF; SD bit=“1” or SD pin=“H”, SLOW bit=“0” or SLOW bit=“L”, SSLOW bit=“0” or SSLOW pin=“L”)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Digital Filter
Frequency Response
(Note 25)
0.01dB
6.0dB
-
-
0
-
-
96.0
87.0
-
kHz
kHz
Passband (Note 30)
PB
0
-
87.0
kHz
Stopband (Note 30)
SB
104.9
-
-
kHz
Passband Ripple (Note 27)
PR
-
-
0.005
dB
Stopband Attenuation (Note 25)
SA
100
-
-
dB
Group Delay (Note 28)
GD
-
6.0
-
1/fs
Digital Filter + SCF (Note 25)
Frequency Response: 0 80.0kHz
2.0
-
+0.1
dB
Note 30. The passband and stopband frequencies scale with fs. For example, PB=0.4535×fs (@0.01dB),
SB=0.546×fs.
[AK4497]
016003187-E-00 2016/05
- 19 -
Figure 7. Short delay Sharp Roll-off Filter Frequency Response
Figure 8. Short delay Sharp Roll-off Filter Passband Ripple
[AK4497]
016003187-E-00 2016/05
- 20 -
■ Short Delay Slow Roll-Off Filter Characteristics
Short Delay Slow Roll-Off Filter Characteristics (fs = 44.1kHz)
(Ta=-40~85C; VDDL/R=4.75 5.25V, AVDD= TVDD=1.7 3.6V, DVDD=1.7~1.98V; Normal Speed
Mode; DEM=OFF; SD bit=“1” or SD pin=“H”, SLOW bit=“1” or SLOW pin=“H”, SSLOW bit=“0” or SSLOW
pin=“L”)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Digital Filter
Frequency Response
(Note 25)
0.01dB
6.0dB
-
-
0
-
-
21.0
8.0
-
kHz
kHz
Passband (Note 30)
PB
0
-
8.0
kHz
Stopband (Note 30)
SB
39.2
-
-
kHz
Passband Ripple (Note 27)
PR
-
-
0.007
dB
Stopband Attenuation (Note 25)
SA
92
-
dB
Group Delay (Note 28)
GD
-
5.0
-
1/fs
Digital Filter + SCF (Note 25)
Frequency Response: 0 20.0kHz
5.0
-
+0.1
dB
Short Delay Slow Roll-Off Filter Characteristics (fs = 96kHz)
(Ta=-40~85C; VDDL/R=4.75 5.25V, AVDD= TVDD=1.7 3.6V, DVDD=1.7~1.98V; Double Speed
Mode; DEM=OFF; SD bit=“1” or SD pin=“H”, SLOW bit=“1” or SLOW pin=“H”, SSLOW bit=“0” or SSLOW
pin=“L”)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Digital Filter
Frequency Response
(Note 25)
0.01dB
6.0dB
-
-
0
-
-
45.6
17.6
-
kHz
kHz
Passband (Note 30)
PB
0
-
17.6
kHz
Stopband (Note 30)
SB
85.4
-
-
kHz
Passband Ripple (Note 27)
PR
-
-
0.005
dB
Stopband Attenuation (Note 25)
SA
100
-
-
dB
Group Delay (Note 28)
GD
-
5.0
-
1/fs
Digital Filter + SCF (Note 25)
Frequency Response: 0 40.0kHz
3.8
-
+0.1
dB
Short Delay Slow Roll-Off Filter Characteristics (fs = 192kHz)
(Ta=-40~85C; VDDL/R=4.75 5.25V, AVDD= TVDD=1.7 3.6V, DVDD=1.7~1.98V; Quad Speed Mode;
DEM=OFF; SD bit=“1” or SD pin=“H”, SLOW bit=“1” or SLOW pin=“H”, SSLOW bit=“0” or SSLOW
pin=“L”)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Digital Filter
Frequency Response
(Note 25)
0.01dB
6.0dB
-
-
0
-
-
91.2
35.2
-
kHz
kHz
Passband (Note 30)
PB
0
-
35.2
kHz
Stopband (Note 30)
SB
170.7
-
-
kHz
Passband Ripple (Note 27)
PR
-
-
0.005
dB
Stopband Attenuation (Note 25)
SA
100
-
-
dB
Group Delay (Note 28)
GD
-
5.0
-
1/fs
Digital Filter + SCF (Note 25)
Frequency Response: 0 80.0kHz
5.0
-
+0.1
dB
Note 31. The passband and stopband frequencies scale with fs. For example, PB = 0.1836 × fs
(@0.01dB), SB = 0.8866 × fs.
[AK4497]
016003187-E-00 2016/05
- 21 -
Figure 9. Short Delay Slow Roll-off Filter Frequency Response
Figure 10. Short Delay Slow Roll-off Filter Passband Ripple
[AK4497]
016003187-E-00 2016/05
- 22 -
■ Low-dispersion Short Delay Filter Characteristics
Low-dispersion Short Delay Filter Characteristics (fs = 44.1kHz)
(Ta=-40~85C; VDDL/R=4.755.25V, AVDD=TVDD=1.73.6V, DVDD=1.7~1.98V; Normal Speed Mode
DEM=OFF; SD bit=“1” or SD pin =“H”, SLOW bit=“0” or SLOW pin=“L”, SSLOW bit=“1” or SSLOW
pin=“H”)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Digital Filter
Frequency Response
(Note 25)
0.05dB
6.0dB
PB
-
0
-
-
22.5
18.4
-
kHz
kHz
Passband (Note 32)
PB
0
-
18.4
kHz
Stopband (Note 32)
SB
25.7
-
-
kHz
Passband Ripple (Note 27)
PR
-
-
0.05
dB
Stopband Attenuation (Note 25)
SA
80
-
-
dB
Group Delay (Note 28)
GD
-
10.0
-
1/fs
Group Delay Distortion
ΔGD
-
±0.035
-
1/fs
Digital Filter + SCF (Note 25)
Frequency Response: 0 20.0kHz
0.8
-
+0.1
dB
Low-dispersion Short Delay Filter Characteristics (fs = 96kHz)
(Ta=-40~85C; VDDL/R=4.755.25V, AVDD=TVDD=1.73.6V, DVDD=1.7~1.98V; Double Speed Mode;
DEM=OFF; SD bit=“1” or SD pin =“H”, SLOW bit=“0” or SLOW pin=“L”, SSLOW bit=“1” or SSLOW
pin=“H”)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Digital Filter
Frequency Response
(Note 25)
0.05dB
6.0dB
PB
0
-
-
48.0
40.1
-
kHz
kHz
Passband (Note 32)
PB
0
-
40.1
kHz
Stopband (Note 32)
SB
55.9
-
-
kHz
Passband Ripple (Note 27)
PR
-
-
0.05
dB
Stopband Attenuation (Note 25)
SA
80
-
-
dB
Group Delay (Note 28)
GD
-
10.0
-
1/fs
Group Delay Distortion
ΔGD
±0.035
-
1/fs
Digital Filter + SCF (Note 25)
Frequency Response: 0 40.0kHz
0.6
-
+0.1
dB
Low-dispersion Short Delay Filter Characteristics (fs = 192kHz)
(Ta=-40~85C; VDDL/R=4.755.25V, AVDD=TVDD=1.73.6V, DVDD=1.7~1.98V; Quad Speed Mode;
DEM=OFF; SD bit=“1” or SD pin =“H”, SLOW bit=“0” or SLOW pin=“L”, SSLOW bit=“1” or SSLOW
pin=“H”)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Digital Filter
Frequency Response
(Note 25)
0.05dB
6.0dB
-
-
0
-
-
98.0
80.2
-
kHz
kHz
Passband (Note 32)
PB
0
-
80.2
kHz
Stopband (Note 32)
SB
111.8
-
-
kHz
Passband Ripple (Note 27)
PR
-
-
0.05
dB
Stopband Attenuation (Note 25)
SA
80
-
-
dB
Group Delay (Note 28)
GD
-
10.0
-
1/fs
Group Delay Distortion
ΔGD
-
±0.035
-
1/fs
Digital Filter + SCF (Note 25)
Frequency Response: 0 80.0kHz
2.0
-
+0.1
dB
Note 32. The passband and stopband frequencies scale with fs. For example, PB = 0.418 × fs
(@0.05dB), SB = 0.582 × fs.
[AK4497]
016003187-E-00 2016/05
- 23 -
Figure 11. Low Dispersion Short Delay Filter Frequency Response
Figure 12. Low Dispersion Short Delay Filter Passband Ripple
[AK4497]
016003187-E-00 2016/05
- 24 -
■ DSD Filter Characteristics
(Ta=-40~85C; VDDL/R=4.755.25V, AVDD=TVDD=1.73.6V, DVDD=1.7~1.98V; fs=44.1kHz; DP
bit=“1”, DSDF bit = “0”, DSDSEL[1:0] bits = “00”)
Parameter
Min.
Typ.
Max.
Unit
Digital Filter Response (Note 34)
Frequency Response
(Note 35)
20kHz
-0.77
dB
50kHz
-5.25
dB
100kHz
-18.80
dB
(Ta=-40~85C; VDDL/R=4.755.25V, AVDD=TVDD=1.73.6V, DVDD=1.7~1.98V; fs=44.1kHz; DP
bit=“1”, DSDF bit=“1”, DSDSEL[1:0] bits= “00”)
Parameter
Min.
Typ.
Max.
Unit
Digital Filter Response (Note 34)
Frequency Response
(Note 35)
20kHz
-0.19
dB
100kHz
-5.29
dB
150kHz
-15.57
dB
Note 33. The peak level of DSD signal should be in the range of 25% ~ 75% duty according to the SACD
format book (Scarlet Book).
Note 34. The frequency response refers to the output level of 0dB when a 1kHz 25%~75% duty sine wave
is input.
Note 35. The frequency (20k, 100k and 200kHz) will be doubled when the sampling speed is 128fs
(DSDSEL[1:0] bits = “01”) and it will be quadrupled when the sampling speed is 256fs
(DSDSEL[1:0] bits = “10”).
■ DC Characteristics
(Ta=-40~85C; VDDL/R=4.755.25V, AVDD=TVDD=1.73.6V, DVDD=1.7~1.98V)
Parameter
Symbol
Min.
Typ.
Max.
Unit
AVDD=TVDD= 1.7 3.0V
High-Level Input Voltage
Low-Level Input Voltage
VIH
VIL
80%TVDD
-
-
-
-
20%TVDD
V
V
AVDD=TVDD= 3.0V 3.6V
High-Level Input Voltage
Low-Level Input Voltage
VIH
VIL
70%TVDD
-
-
-
-
30%TVDD
V
V
High-Level Output Voltage
(TDMO, DZFL, DZFR pins: Iout=-100µA)
Low-Level Output Voltage
(except SDA pin: Iout= 100µA)
(SDA pin, 2.0V TVDD 3.6V: Iout= 3mA)
(SDA pin, 1.7V TVDD 2.0V: Iout= 3mA)
VOH
VOL
VOL
VOL
TVDD0.5
-
-
-
-
-
-
-
0.5
0.4
20%TVDD
V
V
V
V
Input Leakage Current (Note 36)
Iin
-
-
10
A
Note 36. The TESTE, TDMO, DIF0 and DIF1 pins have internal pull-down and the PSN pin has internal
pull-up devices. Therefore the TESTE, TDMO, DIF0, DIF1 and PSN pins are not included in this
specification.
[AK4497]
016003187-E-00 2016/05
- 25 -
■ Switching Characteristics
(Ta=-40~85C; VDDL/R=4.755.25V, AVDD=TVDD=1.73.6V, DVDD=1.7~1.98V, CL=20pF)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Master Clock Timing
Frequency
Duty Cycle
Minimum Pulse Width
fCLK
dCLK
tCLKH
tCLKL
2.048
40
9.155
9.155
-
-
-
-
49.152
60
-
-
MHz
%
nsec
nsec
LRCK Clock Timing (Note 37)
Normal Mode (TDM[1:0] bits = “00”)
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
Oct speed mode
Hex speed mode
Duty Cycle
fsn
fsd
fsq
fso
fsh
Duty
8
54
108
-
-
45
-
-
-
384
768
-
54
108
216
-
-
55
kHz
kHz
kHz
kHz
kHz
%
TDM128 mode (TDM[1:0] bits = “01”)
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
High time
Low time
fsn
fsd
fsq
tLRH
tLRL
8
54
108
1/128fs
1/128fs
-
-
-
-
-
54
108
216
-
-
kHz
kHz
kHz
nsec
nsec
TDM256 mode (TDM[1:0] bits = “10”)
Normal Speed Mode High time
Double Speed Mode
High time
Low time
fsn
fsd
tLRH
tLRL
8
54
1/256fs
1/256fs
-
-
-
-
54
108
-
-
kHz
kHz
nsec
nsec
TDM512 mode (TDM[1:0] bits = “11”)
Normal Speed Mode
High time
Low time
fsn
tLRH
tLRL
8
1/512fs
1/512fs
-
-
-
54
-
-
kHz
nsec
nsec
Note 37. The MCLK frequency must be changed while the AK4497 is in reset state by setting the PDN pin
= “L” or RSTN bit = “0”.
[AK4497]
016003187-E-00 2016/05
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(Ta=-40~85C; VDDL/R=4.755.25V, AVDD=TVDD=1.73.6V, DVDD=1.7~1.98V, CL=20pF, PSN pin=
“L”, AFSD bit= "1")
Parameter
Symbol
Min.
Typ.
Max.
Unit
Master Clock Timing (FS Auto Detect Mode)
Frequency
Duty Cycle
Minimum Pulse Width
fCLK
dCLK
tCLKH
tCLKL
7.68
40
9.155
9.155
-
-
-
-
49.152
60
-
-
MHz
%
nsec
nsec
LRCK Clock Timing (FS Auto Detect Mode) (Note 38)
Normal Mode (TDM[1:0] bits = “00”)
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
Oct speed mode
Hex speed mode
Duty Cycle
fsn
fsd
fsq
fso
fsh
Duty
30
88.2
176.4
-
-
45
-
-
-
384
768
-
54
108
216
-
-
55
kHz
kHz
kHz
kHz
kHz
%
TDM128 mode (TDM[1:0] bits = “01”)
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
High time
Low time
fsn
fsd
fsq
tLRH
tLRL
30
88.2
176.4
1/128fs
1/128fs
-
-
-
-
-
54
108
216
-
-
kHz
kHz
kHz
nsec
nsec
TDM256 mode (TDM[1:0] bits = “10”)
Normal Speed Mode High time
Double Speed Mode
High time
Low time
fsn
fsd
tLRH
tLRL
30
-
1/256fs
1/256fs
-
-
-
-
54
108
-
-
kHz
kHz
nsec
nsec
TDM512 mode (TDM[1:0] bits = “11”)
Normal Speed Mode
High time
Low time
fsn
tLRH
tLRL
30
1/512fs
1/512fs
-
-
-
54
-
-
kHz
nsec
nsec
Note 38. Normal operation is not guaranteed if a frequency not shown above is input to the LRCK when
the AK4497 is in Sampling Frequency Auto Detect Mode.
[AK4497]
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Parameter
Symbol
Min.
Typ.
Max.
Unit
PCM Audio Interface Timing
Normal Mode (TDM[1:0] bits = “00”)
BICK Period
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
Oct speed mode
Hex speed mode
BICK Pulse Width Low
BICK Pulse Width High
BICK “” to LRCK Edge (Note 39)
LRCK Edge to BICK “” (Note 39)
SDATA Hold Time
SDATA Setup Time
tBCK
tBCK
tBCK
tBCK
tBCK
tBCKL
tBCKH
tBLR
tLRB
tSDH
tSDS
1/256fsn
1/128fsd
1/64fsq
1/64fso
1/64fsh
9
9
5
5
5
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
TDM128 mode (TDM[1:0] bits = “01”)
BICK Period
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
BICK Pulse Width Low
BICK Pulse Width High
BICK “” to LRCK Edge (Note 39)
LRCK Edge to BICK “” (Note 39)
SDATA Hold Time
SDATA Setup Time
tBCK
tBCK
tBCK
tBCKL
tBCKH
tBLR
tLRB
tSDH
tSDS
1/128fsn
1/128fsd
1/128fsq
14
14
14
14
5
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
TDM256 mode (TDM[1:0] bits = “10”)
BICK Period
Normal Speed Mode
Double Speed Mode (Note 40)
BICK Pulse Width Low
BICK Pulse Width High
BICK “” to LRCK Edge (Note 39)
LRCK Edge to BICK “” (Note 39)
TDMO Setup time BICK “”
TDMO Hold time BICK “” (Note 42)
SDATA Hold Time
SDATA Setup Time
tBCK
tBCK
tBCKL
tBCKH
tBLR
tLRB
tBSS
tBSH
tSDH
tSDS
1/256fsn
1/256fsd
14
14
14
14
5
5
5
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
TDM512 mode (TDM[1:0] bits = “11”)
BICK Period
Normal Speed Mode (Note 41)
BICK Pulse Width Low
BICK Pulse Width High
BICK “” to LRCK Edge (Note 39)
LRCK Edge to BICK “” (Note 39)
TDMO Setup time BICK “”
TDMO Hold time BICK “” (Note 42)
SDATA Hold Time
SDATA Setup Time
tBCK
tBCKL
tBCKH
tBLR
tLRB
tBSS
tBSH
tSDH
tSDS
1/512fsn
14
14
14
14
5
5
5
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
Note 39. BICK rising edge must not occur at the same time as LRCK edge.
Note 40. Daisy Chain Mode, fsd (max) = 96 kHz if “TVDD < 3.0V”.
Note 41. Daisy Chain Mode, fsn (max) = 48 kHz if “TVDD < 3.0V”.
Note 42. LDOE pin = “L”, tBSH (min) = 4 nsec if “TVDD > 2.6V”.
[AK4497]
016003187-E-00 2016/05
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Parameter
Symbol
Min.
Typ.
Max.
Unit
PCM Audio Interface Timing
External Digital Filter Mode
BCK Period
BCK Pulse Width Low
BCK Pulse Width High
BCK “” to WCK Edge
WCK Period
WCK Edge to BCK “”
WCK Pulse Width Low
WCK Pulse Width High
DINL/R Hold Time
DINL/R Setup Time
tB
tBL
tBH
tBW
tWCK
tWB
tWCKL
tWCKH
tDH
tDS
27
10
10
5
1.3
5
54
54
5
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
nsec
nsec
nsec
nsec
usec
nsec
nsec
nsec
nsec
nsec
DSD Audio Interface Timing
Sampling Frequency
fs
30
48
kHz
(64fs mode, DSDSEL [1:0] bits = “00”)
DCLK Period
DCLK Pulse Width Low
DCLK Pulse Width High
DCLK Edge to DSDL/R (Note 43)
tDCK
tDCKL
tDCKH
tDDD
-
144
144
20
1/64fs
-
-
-
-
-
-
20
nsec
nsec
nsec
nsec
(128fs mode, DSDSEL [1:0] bits = “01”)
DCLK Period
DCLK Pulse Width Low
DCLK Pulse Width High
DCLK Edge to DSDL/R (Note 43)
tDCK
tDCKL
tDCKH
tDDD
-
72
72
10
1/128fs
-
-
-
-
-
-
10
nsec
nsec
nsec
nsec
(256fs mode, DSDSEL [1:0] bits = “10”)
DCLK Period
DCLK Pulse Width Low
DCLK Pulse Width High
DCLK Edge to DSDL/R (Note 43)
tDCK
tDCKL
tDCKH
tDDD
-
36
36
5
1/256fs
-
-
-
-
-
-
5
nsec
nsec
nsec
nsec
(512fs mode, DSDSEL [1:0] bit = “11”)
DCLK Period
DCLK Pulse Width Low
DCLK Pulse Width High
DSDL/R Setup Time
DSDL/R Hold Time
tDCK
tDCKL
tDCKH
tDDS
tDDH
-
18
18
5
5
1/512fs
-
-
-
-
-
-
-
-
-
nsec
nsec
nsec
nsec
nsec
Note 43. DSD data transmitting device must meet this time. “tDDD” is defined from DCLK “↓” until
DSDL/R edge when DCKB bit = “0” (default), “tDDD” is defined from DCLK “↑” until DSDL/R
edge when DCKB bit = “1”. If the audio data format is in phase modulation mode, “tDDD” is
defined from DCLK edge “↓” or “↑” until DSDL/R edge regardless of DCKB bit setting.
Note 44. The AK4497 does not support Phase Modulation Mode in DSD512fs Mode.
[AK4497]
016003187-E-00 2016/05
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Parameter
Symbol
Min.
Typ.
Max.
Unit
Control Interface Timing (3-wire IF mode):
CCLK Period
CCLK Pulse Width Low
CCLK Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN “H” Time
CSN “” to CCLK “”
CCLK “” to CSN “”
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
tCSH
200
80
80
40
40
150
50
50
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
Control Interface Timing (I2C Bus mode):
SCL Clock Frequency
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low Time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling (Note 45)
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
Pulse Width of Spike Noise Suppressed by Input Filter
Capacitive load on bus
fSCL
tBUF
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
tF
tSU:STO
tSP
Cb
-
1.3
0.6
1.3
0.6
0.6
0
0.1
-
-
0.6
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
400
-
-
-
-
-
-
-
0.3
0.3
-
50
400
kHz
usec
usec
usec
usec
usec
usec
usec
usec
usec
usec
nsec
pF
Power-down & Reset Timing (Note 46)
PDN Accept Pulse Width
PDN Reject Pulse Width
tAPD
tRPD
150
-
-
-
-
30
nsec
nsec
Note 45. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
Note 46. The AK4497 should be reset by bringing the PDN pin “L” upon power-up.
Note 47. I2C -bus is a trademark of NXP B.V.
[AK4497]
016003187-E-00 2016/05
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■ Timing Diagram
1/fCLK
tCLKL
VIH
tCLKH
MCLK
VIL
dCLK=tCLKH x fCLK, tCLKL x fCLK
1/fs
VIH
LRCK
VIL
tLRL
tLRH
tBCK
tBCKL
VIH
tBCKH
BICK
VIL
tWCK
tWCKL
VIH
tWCKH
WCK
VIL
tB
tBL
VIH
tBH
BCK
VIL
Figure 13. Clock Timing
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tLRB
LRCK
VIH
BICK
VIL
TDMO
50%TVDD
tBSS
VIH
VIL
tBLR
tSDS
SDATA
VIH
VIL
tSDH
tBSH
Figure 14. Audio Interface Timing (PCM Mode)
tWB
WCK
VIH
BCK
VIL
tDS
VIH
DINL
DINR
VIL
tDH
VIH
VIL
tBW
Figure 15. Audio Interface Timing (External Digital Filter I/F Mode)
[AK4497]
016003187-E-00 2016/05
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VIH
DCLK
VIL
tDDD
VIH
DSDL
DSDR
VIL
tDCKH
tDCKL
tDCK
tDDD
VIH
DSDL
DSDR
VIL
DSD Audio Interface Timing (DSD64fs, 128fs, 256fs Mode)
VIH
DCLK
VIL
VIH
DSDL
DSDR
VIL
tDCKH
tDCKL
tDCK
tDDH
tDDS
DSD Audio Interface Timing (DSD512fs Mode)
Figure 16. Audio Interface Timing (DSD Normal Mode, DCKB bit = “0”)
VIH
DCLK
VIL
tDDD
VIH
DSDL
DSDR
VIL
tDCKH
tDCKL
tDCK
tDDD
tDDD
VIH
DSDL
DSDR
VIL
tDDD
Figure 17. Audio Interface Timing (DSD Phase Modulation Mode, DCKB bit = “0”)
[AK4497]
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tCSS
CSN
VIH
CCLK
VIL
VIH
CDTI
VIL
VIH
VIL
C1
C0
R/W
A4
tCCKL
tCCKH
tCDS
tCDH
tCCK
Figure 18. WRITE Command Input Timing
CSN
VIH
CCLK
VIL
VIH
CDTI
VIL
VIH
VIL
D3
D2
D1
D0
tCSW
tCSH
Figure 19. WRITE Data Input Timing
[AK4497]
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tHIGH
SCL
SDA
VIH
tLOW
tBUF
tHD:STA
tR
tF
tHD:DAT
tSU:DAT
tSU:STA
Stop
Start
Start
Stop
tSU:STO
VIL
VIH
VIL
tSP
Figure 20. I2C Bus Mode Timing
tAPD
tRPD
PDN VIL
Figure 21. Power Down & Reset Timing
[AK4497]
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9. Functional Descriptions
Each function of the AK4497 is controlled by Pins (pin control mode) and Registers (register control
mode) (Table 1). Select the control mode by setting the PSN pin. The AK4497 must be powered down
when changing the PSN pin setting. There is a possibility of malfunction if the device is not powered down
when changing the control mode since the previous setting is not initialized. Register settings are invalid
in pin control mode, and pin settings are invalid in register control mode.
Table 2 shows available functions of each control mode and Table 3 shows available functions in
PCM/DSD/EXDF mode.
Table 1. Pin/Register Control Mode Select
PSN pin
Control Mode
L
Register Control Mode
H
Pin Control Mode
Table 2. Function List @Pin/Register Control Mode
Function
Pin Control Mode
Register Control
Mode
DSD/EXDF Mode Select
-
Y
System Clock Setting Select
Y
Y
Audio Format Select
Y
Y
TDM Mode
Y
Y
Digital Filter Select
Y
Y
De-emphasis Filter Select
Y
Y
Digital Attenuator
-
Y
Zero Detection
-
Y
Mono Mode
-
Y
Output signal select
(Monaural, Channel select)
-
Y
Output signal polarity select
(Invert)
Y
Y
Sound Color Select
-
Y
DSD Full Scale Detect
-
Y
Soft Mute
Y
Y
Register Reset
-
Y
Synchronization
-
Y
Resistor Control
-
Y
Gain Control
Y
Y
Heavy Load Mode
Y
Y
(Y: Available, -: Not available)
[AK4497]
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Table 3. Function List of PCM/EXDF/DSD mode @Register Control Mode
Function
Default
Add
Bit
PCM
EXDF
DSD
PCM/DSD/EXDF Mode Select
PCM mode
00H
02H
EXDF
DP
Y
Y
Y
System clock setting @DSD mode
512fs
02H
DCKS
-
-
Y
System clock setting @EXDF mode
16fs(fs=44.1kHz)
00H
ECS
-
Y
-
Digital Filter select @DSD mode
39kHz filter
09H
DSDF
-
-
Y
Digital Filter select @PCM mode
Short delay
sharp roll off
filter
01-02-05H
SD
SLOW
SSLOW
Y
-
-
De-emphasis Response
OFF
01H
DEM[1:0]
Y
-
-
Path select @ DSD mode
Normal Path
06H
DSDD
-
-
Y
Audio Data Interface Format
@ PCM Mode
32bit MSB
00H
DIF[2:0]
Y
-
-
Audio Data Interface Format
@ EXDF Mode
32bit LSB
00H
DIF[2:0]
-
Y
-
TDM Interface Format
Normal Mode
0AH
TDM[1:0]
Y
-
-
Daisy Chain
Normal Mode
0BH
DCHAIN
Y
-
-
Attenuation Level
0dB
03-04H
ATT[7:0]
Y
Y
Y
Data Zero Detect Enable
Disable
01H
DZFE
Y
Y
Y
Inverting Enable of DZF
“H” active
02H
DZFB
Y
Y
Y
Mono/Stereo mode select
Stereo
02H
MONO
Y
Y
Y
Data Invert mode select
OFF
05H
INVL/R
Y
Y
Y
The data selection of L channel and
R channel
R channel
02H
SELLR
Y
Y
Y
Sound Color Select
Off
08H
SC[2:0]
Y
Y
Y
DSD Mute Function @ Full scale
Detected
Disable
06H
DDM
-
-
Y
Soft Mute Enable
Normal
Operation
01H
SMUTE
Y
Y
Y
RSTN
Reset
00H
RSTN
Y
Y
Y
Synchronization
Enable
07H
SYNCE
Y
Y
-
(Y: Available, N/A: Not available)
[AK4497]
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■ D/A Conversion Mode (PCM Mode, DSD Mode, EXDP Mode)
The AK4497 can perform D/A conversion for either PCM data or DSD data. The DP bit controls
PCM/DSD mode. When DSD mode, DSD data can be input from the #16, #17 and #19 pins if DSDPATH
bit = “0” and DSD data can be input from the #3, #4, and #5 pins if DSDPATH bit = “1”. The AK4497 must
be reset by setting RSTN bit = “0” when PSM/DSD mode is changed by DP bit or when DSD signal input
pins are changed by DSDPATH bit. It takes about 2 ~ 3/fs to change the mode. Wait 4/fs or more to
change RSTN bit after changing these settings.
When the AK4497 is in pin control mode, PCM mode is only available. External digital filter I/F can be
selected by setting DP bit = “0” and EXDF bit = “1”. When using an external digital filter (EXDF I/F mode),
data is input to each MCLK, BCK, WCK, DINL and DINR pin. EXDF bit controls the modes. When
switching internal and external digital filters by EXDF bit, the AK4497 must be reset by RSTN bit. A Digital
filter switching takes 2~3k/fs. The AK4497 is in DSD mode when DP bit = “1” and EXDF bit “1”.
Table 4. PCM/DSD/EXDF Mode Control
DP bit
EXDF bit
DSDPATH
bit
D/A Conv.
Mode
Pin Assignment
#3 pin
#4 pin
#5 pin
#16 pin
#17 pin
#19 pin
0
(default)
0
(default)
x
PCM
BICK
SDATA
LRCK
Not Use
Not Use
Not Use
1
x
0
(default)
DSD
Not Use
Not Use
Not Use
DSDL
DSDR
DCLK
1
x
1
DSD
DCLK
DSDL
DSDR
Not Use
Not Use
Not Use
0
1
x
EXDF
BCK
DINL
DINR
Not Use
Not Use
Not Use
(x: Do not care)
■ D/A Conversion Mode Switching Timing
Figure 22 and Figure 23 show switching timing of PCM/EXDF and DSD modes. To prevent noise caused
by excessive input, DSD signal should be input 4/fs after setting RSTN bit = “0” until the device is
completely reset internally when the conversion mode is changed to DSD mode from PCM/ESDF mode.
DSD signal should be stopped 4/fs after setting RSTN bit = “0”until the device is completely reset
internally when the conversion mode is changed to PCM/EXDE from DSD mode.
RSTN bit
D/A Data
D/A Mode
4/fs
0
PCM or EXDF Data
DSD Data
PCM or EXDF Mode
DSD Mode
Figure 22. D/A Mode Switching Timing (from PCM/EXDF to DSD)
[AK4497]
016003187-E-00 2016/05
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RSTN bit
D/A Data
D/A Mode
4/fs
DSD Data
PCM Data or EXDF Data
DSD Mode
PCM or EXDF Mode
4/fs
0
Figure 23. D/A Mode Switching Timing (from DSD/PCM or EXDF)
Figure 24 shows switching timing of PCM and EXDF modes. Set EXDF bit 4/fs after setting RSTN bit =
“0” until the device is completely reset internally when changing the conversion mode.
RSTN bit
D/A Data
D/A Mode
4/fs
PCM or EXDF Data
PCM or EXDF Data
PCM or EXDF Mode
PCM or EXDF Mode
0
Figure 24. D/A Mode Switching Timing (PCM ⇔ EXDF)
[AK4497]
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■ System Clock
[1] PCM Mode
The external clocks, which are required to operate the AK4497, are MCLK, BICK and LRCK. MCLK, BICK
and LRCK should be synchronized but the phase is not critical. The MCLK is used to operate the digital
interpolation filter, the delta-sigma modulator and SCF.
There are Manual Setting Mode, Auto Setting Mode and Fs Auto Detection mode for MCLK frequency
setting. In manual setting mode (ACKS pin=“L” or ACKS bit=“0”), MCLK frequency is set automatically but
the sampling speed (LRCK frequency) is set by DFS[2:0] bits (Table 6). Sampling frequency is fixed to
normal speed mode in pin control mode (PSN pin = “H”), and it is set by DFS[2:0] bits in register control
mode (PSN pin = “L”). In register control mode, the AK4497 is in manual setting mode when power-down
is released (PDN pin = “L” → “H”).
In auto setting mode (ACKS pin = “H” or ACKS bit=“1”), sampling speed and MCLK frequency are
detected automatically (Table 7, Table 11) and then the initial master clock is set to the appropriate
frequency (Table 8, Table 15, Table 16).
In FS auto detect mode (AFSD bit= “1”), sampling speed is automatically detected (Table 7, Table 11)
and the initial master clock is set to the appropriate frequency. In this mode, ACKS bit and DFS[2:0] bits
settings are invalid. Fs auto detect mode is not supported by pin control mode.
The AK4497 is automatically placed in power-down state when MCLK is stopped for more than 1us
during a normal operation (PDN pin =“H”), and the analog output becomes Hi-z state. When MCLK is
input again, the AK4497 exits power-down state and starts operation. The AK4497 is in power-down
mode until MCLK BICK and LRCK are supplied and the analog output is floating state.
Table 5. System Clock Setting Mode @Register Control Mode
AFSD bit
ACKS bit
Mode
0
0
Manual setting Mode
(default)
1
Auto setting Mode
1
x
FS Auto Detect Mode
(x: Do not care)
[AK4497]
016003187-E-00 2016/05
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(1) Pin Control Mode (PSN pin = “H”)
(1)-1. Manual Setting Mode (ACKS pin = “L”)
The MCLK frequency corresponding to each sampling speed should be provided externally (Table 6).
DFS1-0 bits are fixed to “00”. In this mode, quad speed and double speed modes are not available.
Table 6. System Clock Example (Manual Setting Mode @Pin Control Mode)
LRCK
MCLK (MHz)
BICK
fs
128fs
192fs
256fs
384fs
512fs
768fs
1152fs
64fs
32.0kHz
N/A
N/A
8.1920
12.2880
16.3840
24.5760
36.8640
2.0480MHz
44.1kHz
N/A
N/A
11.2896
16.9344
22.5792
33.8688
N/A
2.8224MHz
48.0kHz
N/A
N/A
12.2880
18.4320
24.5760
36.8640
N/A
3.0720MHz
(N/A: Not available)
(1)-2. Auto Setting Mode (ACKS pin = “H”)
In auto setting mode, MCLK frequency and sampling frequency are detected automatically (Table 7).
MCLK of corresponded frequency to each sampling speed mode should be input externally (Table 8).
Table 7. Sampling Speed (Auto Setting Mode @Pin Control Mode)
MCLK
Sampling Speed
1152fs
Normal (fs32kHz)
512fs/256fs
768fs/384fs
Normal
256fs
384fs
Double
128fs
192fs
Quad
64fs
96fs
Oct
32fs
48fs
Hex
Table 8. System Clock Example (Auto Setting Mode @Pin Control Mode)
LRCK
MCLK(MHz)
Sampling
Speed
Fs
32fs
48fs
64fs
96fs
128fs
192fs
32.0kHz
N/A
N/A
N/A
N/A
N/A
N/A
Normal
44.1kHz
N/A
N/A
N/A
N/A
N/A
N/A
48.0kHz
N/A
N/A
N/A
N/A
N/A
N/A
88.2kHz
N/A
N/A
N/A
N/A
N/A
N/A
Double
96.0kHz
N/A
N/A
N/A
N/A
N/A
N/A
176.4kHz
N/A
N/A
N/A
N/A
22.5792
33.8688
Quad
192.0kHz
N/A
N/A
N/A
N/A
24.5760
36.8640
384kHz
N/A
N/A
24.576
36.864
N/A
N/A
Oct
768kHz
24.576
36.864
N/A
N/A
N/A
N/A
Hex
(N/A: Not available)
[AK4497]
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Table 9. System Clock Example 2 (Auto Setting Mode @Pin Control Mode)
LRCK
MCLK(MHz)
Sampling
Speed
Fs
256fs
384fs
512fs
768fs
1024fs
1152fs
32.0kHz
8.1920
12.2880
16.3840
24.5760
32.7680
36.8640
Normal
44.1kHz
11.2896
16.9344
22.5792
33.8688
N/A
N/A
48.0kHz
12.2880
18.4320
24.5760
36.8640
N/A
N/A
88.2kHz
22.5792
33.8688
N/A
N/A
N/A
N/A
Double
96.0kHz
24.5760
36.8640
N/A
N/A
N/A
N/A
176.4kHz
N/A
N/A
N/A
N/A
N/A
N/A
Quad
192.0kHz
N/A
N/A
N/A
N/A
N/A
N/A
384kHz
N/A
N/A
N/A
N/A
N/A
N/A
Oct
768kHz
N/A
N/A
N/A
N/A
N/A
N/A
Hex
(N/A: Not available)
When MCLK= 256fs/384fs, auto setting mode supports sampling rate of 8kHz~96kHz (Table 10).
However, the DR and S/N performances will degrade approximately 3dB as compared to when MCLK =
256fs/384fs for DR and MCLK= 512fs/768fs for S/N, respectively if the sampling rate is under 54kHz.
Table 10. DR and S/N Relationship with MCLK Frequency (fs = 44.1kHz)
ACKS pin
MCLK
DR,S/N
(A-weighted)
L
256fs/384fs/512fs/768fs
128dB
H
256fs/384fs
125dB
H
512fs/768fs
128dB
[AK4497]
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(2) Register Control Mode (PSN pin = “L”)
(2)-1. Manual Setting Mode (AFSD bit=“0”, ACKS bit=“0”)
MCLK frequency is detected automatically and the sampling speed is set by DFS[2:0] bits (Table 11). The
MCLK frequency corresponding to each sampling speed that should be provided externally (Table 12,
Table 14). The AK4497 is set to Manual Setting Mode at power-up (PDN pin = “L” →“H”). When DFS2-0
bits are changed, the AK4497 should be reset by RSTN bit.
Table 11. Sampling Speed (Manual Setting Mode @Register Control Mode)
DFS2
bit
DFS1
bit
DFS0
bit
Sampling Rate (fs)
0
0
0
Normal Speed Mode
8kHz 54kHz
(default)
0
0
1
Double Speed Mode
54kHz 108kHz
0
1
0
Quad Speed Mode
120kHz 216kHz
0
1
1
Quad Speed Mode
120kHz 216kHz
1
0
0
Oct Speed Mode
384kHz
1
0
1
Hex Speed Mode
768kHz
1
1
0
Oct Speed Mode
384kHz
1
1
1
Hex Speed Mode
768kHz
Table 12. System Clock Example 1 (Manual Setting Mode @Register Control Mode)
LRCK
MCLK(MHz)
Sampling
Speed
Fs
16fs
32fs
48fs
64fs
96fs
128fs
32.0kHz
N/A
N/A
N/A
N/A
N/A
N/A
Normal
44.1kHz
N/A
N/A
N/A
N/A
N/A
N/A
48.0kHz
N/A
N/A
N/A
N/A
N/A
N/A
88.2kHz
N/A
N/A
N/A
N/A
N/A
N/A
Double
96.0kHz
N/A
N/A
N/A
N/A
N/A
N/A
176.4kHz
N/A
N/A
N/A
N/A
N/A
22.5792
Quad
192.0kHz
N/A
N/A
N/A
N/A
N/A
24.5760
384kHz
N/A
12.288
18.432
24.576
36.864
N/A
Oct
768kHz
12.288
24.576
36.864
49.152
N/A
N/A
Hex
(N/A: Not available)
Table 13. System Clock Example 2 (Manual Setting Mode @Register Control Mode)
LRCK
MCLK(MHz)
Sampling
Speed
fs
192fs
256fs
384fs
512fs
768fs
1024fs
1152fs
32.0kHz
N/A
8.1920
12.2880
16.3840
24.5760
32.7680
36.8640
Normal
44.1kHz
N/A
11.2896
16.9344
22.5792
33.8688
N/A
N/A
48.0kHz
N/A
12.2880
18.4320
24.5760
36.8640
N/A
N/A
88.2kHz
N/A
22.5792
33.8688
45.1584
N/A
N/A
N/A
Double
96.0kHz
N/A
24.5760
36.8640
49.152
N/A
N/A
N/A
176.4kHz
33.8688
45.1584
N/A
N/A
N/A
N/A
N/A
Quad
192.0kHz
36.8640
49.152
N/A
N/A
N/A
N/A
N/A
384kHz
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Oct
768kHz
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Hex
(N/A: Not available)
[AK4497]
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(2)-2. Auto Setting Mode (AFSD bit= “0”, ACKS bit = “1”)
MCLK frequency and the sampling speed are detected automatically (Table 14) and DFS[2:0] bits are
ignored. The MCLK frequency corresponding to each sampling speed should be provided externally
(Table 15, Table 16).
Table 14. Sampling Speed (Auto Setting Mode)
MCLK
Sampling Speed
1152fs
Normal (fs32kHz)
512fs/256fs
768fs/384fs
Normal
256fs
384fs
Double
128fs
192fs
Quad
64fs
96fs
Oct
32fs
48fs
Hex
Table 15. System Clock Example (Auto Setting Mode)
LRCK
MCLK(MHz)
Sampling Speed
fs
32fs
48fs
64fs
96fs
128fs
32.0kHz
N/A
N/A
N/A
N/A
N/A
Normal
44.1kHz
N/A
N/A
N/A
N/A
N/A
48.0kHz
N/A
N/A
N/A
N/A
N/A
88.2kHz
N/A
N/A
N/A
N/A
N/A
Double
96.0kHz
N/A
N/A
N/A
N/A
N/A
176.4kHz
N/A
N/A
N/A
N/A
22.5792
Quad
192.0kHz
N/A
N/A
N/A
N/A
24.5760
384kHz
N/A
N/A
24.576
36.864
N/A
Oct
768kHz
24.576
36.864
N/A
N/A
N/A
Hex
(N/A: Not available)
Table 16. System Clock Example (Auto Setting Mode)
LRCK
MCLK(MHz)
Sampling Speed
fs
192fs
256fs
384fs
512fs
768fs
1152fs
32.0kHz
N/A
8.1920
12.2880
16.3840
24.5760
36.8640
Normal
44.1kHz
N/A
11.2896
16.9344
22.5792
33.8688
N/A
48.0kHz
N/A
12.2880
18.4320
24.5760
36.8640
N/A
88.2kHz
N/A
22.5792
33.8688
N/A
N/A
N/A
Double
96.0kHz
N/A
24.5760
36.8640
N/A
N/A
N/A
176.4kHz
33.8688
N/A
N/A
N/A
N/A
N/A
Quad
192.0kHz
36.8640
N/A
N/A
N/A
N/A
N/A
384kHz
N/A
N/A
N/A
N/A
N/A
N/A
Oct
768kHz
N/A
N/A
N/A
N/A
N/A
N/A
Hex
(N/A: Not available)
When MCLK= 256fs/384fs, auto setting mode supports sampling rate from 8kHz to 96kHz (Table 14).
However, the DR and S/N performances will degrade approximately 3dB as compared to when MCLK =
256fs/384fs for DR and MCLK= 512fs/768fs for S/N, respectively if the sampling rate is under 54kHz.
Table 17. DR and S/N Relationship with MCLK Frequency (fs = 44.1kHz)
ACKS bit
MCLK
DR, S/N
(A-weighted)
0
256fs/384fs/512fs/768fs
128dB
1
256fs/384fs
125dB
1
512fs/768fs
128dB
[AK4497]
016003187-E-00 2016/05
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(2)-3. Sampling Frequency (FS) Auto Detect Mode (AFSD bit= “1”)
MCLK frequency and the sampling rate is detected automatically (Table 14). In this mode, DFS[2:0] bits
and ACKS bit settings are invalid. The MCLK frequency corresponding to each sampling speed should
be provided externally (Table 18, Table 19). Internal operation sequence in FS auto detect mode is
shown in Figure 25.
Table 18. System Clock Example 1 @PCM Mode
LRCK
MCLK(MHz)
Sampling
Speed
Fs
16fs
32fs
48fs
64fs
96fs
128fs
32.0kHz
N/A
N/A
N/A
N/A
N/A
N/A
Normal
44.1kHz
N/A
N/A
N/A
N/A
N/A
N/A
48.0kHz
N/A
N/A
N/A
N/A
N/A
N/A
88.2kHz
N/A
N/A
N/A
N/A
N/A
N/A
Double
96.0kHz
N/A
N/A
N/A
N/A
N/A
N/A
176.4kHz
N/A
N/A
N/A
N/A
N/A
22.5792
Quad
192.0kHz
N/A
N/A
N/A
N/A
N/A
24.5760
384kHz
N/A
12.288
18.432
24.576
36.864
N/A
Oct
768kHz
12.288
24.576
36.864
49.152
N/A
N/A
Hex
(N/A: Not available)
Table 19. System Clock Example 2 @PCM Mode
LRCK
MCLK(MHz)
Sampling
Speed
fs
192fs
256fs
384fs
512fs
768fs
1024fs
1152fs
32.0kHz
N/A
8.1920
12.2880
16.3840
24.5760
32.768
36.8640
Normal
44.1kHz
N/A
11.2896
16.9344
22.5792
33.8688
N/A
N/A
48.0kHz
N/A
12.2880
18.4320
24.5760
36.8640
N/A
N/A
88.2kHz
N/A
22.5792
33.8688
45.1584
N/A
N/A
N/A
Double
96.0kHz
N/A
24.5760
36.8640
49.152
N/A
N/A
N/A
176.4kHz
33.8688
45.1584
N/A
N/A
N/A
N/A
N/A
Quad
192.0kHz
36.8640
49.152
N/A
N/A
N/A
N/A
N/A
384kHz
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Oct
768kHz
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Hex
(N/A: Not available)
[AK4497]
016003187-E-00 2016/05
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(2)-4. FS Auto Detect Mode Enable
Figure 25 and Figure 26 show system timing when switching to FS Auto Detect Mode.
<Switching to FS Auto Detect Mode>
AFSD bit
8~9/fs
ClockSetting
Mode
Manual or Auto SettingMode
FS AutoDetect Mode
(2)
Internal
ClockSetting
ClockSetting Fix
(3)
RSTN bit
(1)
Internal OSC
Power Up
InternalState
(DigitalCore)
Normal Operation
Normal Operation
2~3/fs
3~4/fs
0
2~3/fs
Figure 25. Switching to FS AutoDetect Mode
Notes:
(1) Digital block of the AK4497 should be reset when changing the clock setting mode. Refer to
Figure 57 and Figure 58 for power up sequence.
(2) The internal oscillator starts operation by setting AFSD bit= “1”. It takes 10us (max.) until the
internal oscillator is stabilized.
(3) FS auto detect mode starts in 8/fs ~ 9/fs after setting AFSD bit= “1”. Internal operation rate will be
stabilized in 2/fs ~ 3/fs. Digital block should be reset state until the internal operation rate is
stabilized.
[AK4497]
016003187-E-00 2016/05
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<Switching to Other Clock Setting Mode from FS Auto Detect Mode>
RSTN bit
AFSD bit
ClockSetting
Mode
FSAutoDetectMode
Manual or Autosetting Mode
Internal OSC
Power Up
3~4/fs
2~3/fs
InternalState
(DigitalCore)
Normal Operation
Normal Operation
0
(1)
4/fs
Figure 26. Switching from FS AutoDetect Mode
Note:
(1) FS auto detect mode ends by setting AFSD bit = “0” and the internal oscillator will stop operation.
[AK4497]
016003187-E-00 2016/05
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[2] DSD Mode
The AK4497 has a DSD playback function. The external clocks that are required in DSD mode are MCLK
and DCLK. MCLK should be synchronized with DCLK but the phase is not critical. The frequency of
MCLK is set by DCKS bit (Table 20).
The AK4497 is automatically placed in power-down state when MCLK is stopped during a normal
operation (PDN pin =“H”), and the analog output becomes Hi-z state. When the reset is released (PDN
pin = “L” → “H”), the AK4497 is in power-down state until MCLK and DCLK are input.
Table 20. System Clock (DSD Mode, fs=32kHz, 44.1kHz, 48kHz)
DCKS bit
MCLK Frequency
DCLK Frequency
0
512fs
64fs/128fs/256fs
(default)
1
768fs
64fs/128fs/256fs
The AK4497 supports DSD data stream of 2.8224MHz (64fs), 5.6448MHz (128fs), 11.2896MHz (256fs)
and 22.5792MHz (512fs). The data sampling speed is selected by DSDSEL[1:0] bits (Table 21).
Table 21. DSD Data Stream Select
DSDSEL1
DSDSEL0
DSD Data Stream
fs=32kHz
fs=44.1kHz
fs=48kHz
0
0
2.048MHz
2.8224MHz
3.072MHz
(default)
0
1
4.096MHz
5.6448MHz
6.144MHz
1
0
8.192MHz
11.2896MHz
12.288MHz
1
1
16.284MHz
22.5792MHz
24.576MHz
The AK4497 has a Volume bypass function for play backing DSD signal. Two modes are selectable by
DSDD bit (Table 22). When setting DSDD bit = “1”, the output volume control and zero detect functions
are not available.
Table 22. DSD Playback Path Select
DSDD
Mode
0
Normal Path
(default)
1
Volume Bypass
[AK4497]
016003187-E-00 2016/05
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[3] External Digital Filter Mode (EXDF mode)
The external clocks that are required in EXDF mode are MCLK, BCK and WCK. The BCK and MCLK
clocks must be the same frequency and must not burst. BCK and MCLK frequencies for each sampling
speed are shown in Table 23. ECS bit selects WCK frequency from 384kHz and 768kHz. DW indicates
the number of BCK in one WCK cycle.
All circuits except the internal LDO are automatically placed in power-down state when MCLK edge is not
detected for more than 1us during a normal operation (PDN pin =“H”), and the analog output becomes
Hi-Z state. The power-down state is released and the AK4497 starts operation by inputting MCLK again.
In this case, register settings are not initialized.
When the reset is released (PDN pin = “L” → “H”), the AK4497 is in power-down state until MCLK, BCK
and WCK are input.
Table 23. System Clock Example (EXDF mode)
Sampling
Speed[kHz]
MCLK&BCK [MHz]
WCK
ECS
128fs
192fs
256fs
384fs
512fs
768fs
44.1(30~48)
N/A
N/A
N/A
N/A
22.5792
33.8688
16fs
0
(default)
32
48
DW
44.1(30~48)
N/A
N/A
11.2896
16.9344
22.5792
33.8688
8fs
1
32
48
64
96
DW
96(54~96)
N/A
N/A
24.576
36.864
N/A
N/A
8fs
0
32
48
DW
96(54~96)
12.288
18.432
24.576
36.864
N/A
N/A
4fs
1
32
48
64
96
DW
192(108~192)
24.576
36.864
N/A
N/A
N/A
N/A
4fs
0
32
48
DW
192(108~192)
24.576
36.864
N/A
N/A
N/A
N/A
2fs
1
64
96
DW
[AK4497]
016003187-E-00 2016/05
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■ Audio Interface Format
[1] PCM mode
(1) Input Data Format
Data is shifted in via the SDATA pin using BICK and LRCK inputs. Eight data formats are supported and
selected by the DIF2-0 pins (Pin control mode) or DIF[2:0] bits (Register control mode) as shown in Table
24. In all formats the serial data is MSB first, 2's compliment format and is latched on the rising edge of
BICK. Mode 2 can be used for 20-bit and 16-bit MSB justified formats by zeroing the unused LSBs.
Normal Mode (TDM[1:0] bits = “00” or TDM1-0 pins = “LL”)
2ch Data is shifted in via the SDATA pin using BICK and LRCK inputs. Eight data formats are supported
and selected by the DIF2-0 pins (Pin control mode) or DIF[2:0] bits (Register control mode) as shown in
Table 24. In all formats the serial data is MSB first, 2's compliment format and is latched on the rising edge
of BICK. Mode 6 can be used for 24-bit, 20-bit and 16-bit MSB justified formats by zeroing the unused
LSBs.
TDM128 Mode (TDM[1:0] bits = “01” or TDM1-0 pins = “LH”)
4ch Data is shifted in via the SDATA pin using BICK and LRCK inputs. Data slot can be selected by
SDS[2:0] bits (Table 25). BICK is fixed to 128fs. Six data formats are supported and selected by the
DIF2-0 pins (Pin control mode) or DIF[2:0] bits (Register control mode) as shown in Table 24. In all
formats the serial data is MSB first, 2's compliment format and is latched on the rising edge of BICK.
TDM256 Mode (TDM[1:0] bits =“10” or TDM1-0 pins =“HL”)
8ch Data is shifted in via the SDATA pin using BICK and LRCK inputs. Data slot can be selected by
SDS[2:0] bits (Table 25). BICK is fixed to 256fs. Six data formats are supported and selected by the
DIF2-0 pins (Pin control mode) or DIF[2:0] bits (Register control mode) as shown in Table 24. In all
formats the serial data is MSB first, 2's compliment format and is latched on the rising edge of BICK.
TDM512 Mode (TDM[1:0] bits = “11” or TDM1-0 pins = “HH”)
16ch Data is shifted in via the SDATA pin using BICK and LRCK inputs. Data slot can be selected by
SDS[2:0] bits (Table 25). BICK is fixed to 512fs. Six data formats are supported and selected by the
DIF2-0 pins (Pin control mode) or DIF[2:0] bits (Register control mode) as shown in Table 24. In all
formats the serial data is MSB first, 2's compliment format and is latched on the rising edge of BICK.
[AK4497]
016003187-E-00 2016/05
- 50 -
Table 24. Audio Interface Format
Mode
TDM1
bit
TDM0
bit
DIF2
bit
DIF1
bit
DIF0
bit
SDATA Format
LRCK
BICK
Figure
Normal
(Note 48)
0
0
0
0
0
0
16-bit LSB justified
H/L
32fs
Figure 27
1
0
0
1
20-bit LSB justified
H/L
40fs
Figure 28
2
0
1
0
24-bit MSB justified
H/L
48fs
Figure 29
3
0
1
1
16-bit I2S Compatible
L/H
32fs
Figure 30
24-bit I2S Compatible
L/H
48fs
4
1
0
0
24-bit LSB justified
H/L
48fs
Figure 28
5
1
0
1
32-bit LSB justified
H/L
64fs
Figure 31
6
1
1
0
32-bit MSB justified
H/L
64fs
Figure 32
(default)
7
1
1
1
32-bit I2S Compatible
L/H
64fs
Figure 33
TDM128
8
0
1
0
1
0
24-bit MSB justified
H/L
128fs
Figure 34
9
0
1
1
24-bit I2S Compatible
L/H
128fs
Figure 35
10
1
0
0
24-bit LSB justified
H/L
128fs
Figure 36
11
1
0
1
32-bit LSB justified
H/L
128fs
Figure 34
12
1
1
0
32-bit MSB justified
H/L
128fs
Figure 34
13
1
1
1
32-bit I2S Compatible
L/H
128fs
Figure 35
TDM256
14
1
0
0
1
0
24-bit MSB justified
H/L
256fs
Figure 37
15
0
1
1
24-bit I2S Compatible
L/H
256fs
Figure 38
16
1
0
0
24-bit LSB justified
H/L
256fs
Figure 39
17
1
0
1
32-bit LSB justified
H/L
256fs
Figure 37
18
1
1
0
32-bit MSB justified
H/L
256fs
Figure 37
19
1
1
1
32-bit I2S Compatible
L/H
256fs
Figure 38
TDM512
20
1
1
0
1
0
24-bit MSB justified
H/L
512fs
Figure 40
21
0
1
1
24-bit I2S Compatible
L/H
512fs
Figure 41
22
1
0
0
24-bit LSB justified
H/L
512fs
Figure 42
23
1
0
1
32-bit LSB justified
H/L
512fs
Figure 40
24
1
1
0
32-bit MSB justified
H/L
512fs
Figure 40
25
1
1
1
32-bit I2S Compatible
L/H
512fs
Figure 41
Note 48. BICK more than setting bit must be input to each channel. In the LRCK column, “H/L” indicates that
L channel data can be input when LRCK is “H” and R channel data can be input when LRCK is “L”.
“L/H” indicates L channel data can be input when LRCK is “L” and R channel data can be input
when LRCK is “H”.
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SDATA
BICK
LRCK
SDATA
15
14
6
5
4
BICK
0
1
10
11
12
13
14
15
0
1
10
11
12
13
14
15
0
1
3
2
1
0
15
14
(32fs)
(64fs)
0
14
1
15
16
17
31
0
1
14
15
16
17
31
0
1
15
14
0
15
14
0
Mode 0
Don’t care
Don’t care
15:MSB, 0:LSB
Mode 0
15
14
6
5
4
3
2
1
0
Lch Data
Rch Data
Figure 27. Mode 0 Timing
SDATA
LRCK
BICK
(64fs)
0
9
1
10
11
12
31
0
1
9
10
11
12
31
0
1
19
0
19
0
Mode 1
Don’t care
Don’t care
19:MSB, 0:LSB
SDATA
Mode 4
23:MSB, 0:LSB
20
19
0
20
19
0
Don’t care
Don’t care
22
21
22
21
Lch Data
Rch Data
8
23
23
8
Figure 28. Mode 1, 4 Timing
LRCK
BICK
(64fs)
SDATA
0
22
1
2
24
31
0
1
31
0
1
23:MSB, 0:LSB
22
1
0
Don’t care
23
Lch Data
Rch Data
23
30
22
2
24
23
30
22
1
0
Don’t care
23
22
23
Figure 29. Mode 2 Timing
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LRCK
BICK
(64fs)
SDATA
0
3
1
2
24
31
0
1
31
0
1
23:MSB, 0:LSB
22
1
0
Don’t care
23
Lch Data
Rch Data
23
25
3
2
24
23
25
22
1
0
Don’t care
23
23
Figure 30. Mode 3 Timing
LRCK
BICK(128fs)
SDATA
0
1
2
20
21
22
32
33
63
0
1
2
20
21
22
32
33
63
0
1
0
31
1
BICK(64fs)
SDATA
0
1
2
12
13
14
23
24
31
0
1
2
12
13
14
23
24
31
0
31
1
30
9
31
30
20
19
18
9
31
20
19
18
31: MSB, 0:LSB
8
0
1
8
0
1
Lch Data
Rch Data
0
31
1
Figure 31. Mode 5 Timing
LRCK
BICK(128fs)
SDATA
0
1
2
20
21
22
32
33
63
0
1
2
20
21
22
32
33
63
0
31
1
30
0
31
30
12
11
10
0
31
12
11
10
BICK(64fs)
SDATA
0
1
2
12
13
14
23
24
31
0
1
2
12
13
14
23
24
31
0
31
1
30
9
31
30
20
19
18
9
31
20
19
18
31: MSB, 0:LSB
8
0
1
8
0
1
Lch Data
Rch Data
Figure 32. Mode 6 Timing
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LRCK
BICK(128fs)
SDATA
0
1
2
20
21
22
33
34
63
0
1
2
20
21
22
33
34
63
0
1
31
0
31
13
12
11
0
13
12
11
BICK(64fs)
SDATA
0
1
2
12
13
14
24
25
31
0
1
2
12
13
14
24
25
31
0
0
1
31
9
0
31
21
20
19
9
0
21
20
19
31: MSB, 0:LSB
8
1
2
8
1
2
Lch Data
Rch Data
Figure 33. Mode 7 Timing
LRCK
BICK(128fs)
128 BICK
L1
32 BICK
R1
32 BICK
32 BICK
32 BICK
SDATA
22
0
22
0
23
23
22
23
Mode8
SDATA
30
0
30
0
31
31
30
31
Mode11,12
Figure 34. Mode 8/11/12 Timing
LRCK
BICK(128fs)
128 BICK
L1
32 BICK
R1
32 BICK
32 BICK
32 BICK
SDATA
22
0
22
0
23
23
23
SDATA
Mode9
Mode13
30
0
30
0
31
31
30
31
Figure 35. Mode 9/13 Timing
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LRCK
BICK(128fs)
128 BICK
L1
32 BICK
R1
32 BICK
32 BICK
32 BICK
SDATA
22
0
22
0
23
23
23
Figure 36. Mode 10 Timing
23
LRCK
BICK (256fs)
22
0
L1
32 BICK
256 BICK
22
0
R1
32 BICK
22
23
23
32 BICK
32 BICK
SDATA
31
30
0
30
31
31
30
0
SDATA
Mode14
Mode17,18
32 BICK
32 BICK
32 BICK
32 BICK
Figure 37. Mode 14/17/18 Timing
LRCK
BICK (256fs)
23
0
L1
32 BICK
256 BICK
23
0
R1
32 BICK
23
32 BICK
32 BICK
SDATA
Mode15
31
0
31
30
31
0
30
SDATA
Mode19
32 BICK
32 BICK
32 BICK
32 BICK
Figure 38. Mode 15/19 Timing
LRCK
BICK(256fs)
SDATA
256 BICK
22
0
L1
32 BICK
22
0
R1
32 BICK
32 BICK
32 BICK
23
23
23
32 BICK
32 BICK
32 BICK
32 BICK
Figure 39. Mode 16 Timing
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BICK(512fs)
SDATA
Mode8
LRCK
512BICK
22
2
0
23
22
0
23
SDATA
Mode11,12
L1
32 BICK
R1
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
22
0
31
23
22
0
31
31
Figure 40. Mode 20/23/24 Timing
BICK(512fs)
SDATA
Mode21
LRCK
512BICK
22
2
0
23
22
0
23
SDATA
Mode25
L1
32 BICK
R1
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
22
0
31
23
22
0
31
31
Figure 41. Mode 21/25 Timing
BICK(512fs)
SDATA
Mode22
LRCK
512BICK
22
2
0
23
22
0
23
L1
32 BICK
R1
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
23
Figure 42. Mode 22 Timing
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(2) Data Slot Selection Function
Data slot of 1cycle LRCK for each audio data format is defined as Figure 43~ Figure 46. DAC output data
can be selected by SDS[2:0] bits as shown in Table 25.
LRCK
SDATA
R1
L1
Figure 43. Data Slot in Normal Mode
SDATA
R1
L1
LRCK
128 BICK
R2
L2
Figure 44. Data Slot in TDM128 Mode
SDATA
R1
L1
LRCK
256 BICK
R2
L2
R3
L3
R4
L4
Figure 45. Data Slot in TDM256 Mode
SDATA
R1
L1
LRCK
512 BICK
R2
L2
R3
L3
R4
L4
R5
R6
L6
R7
L7
R8
L8
L5
Figure 46. Data Slot in TDM512 Mode
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Table 25. Data Select
SDS2
bit
SDS1
bit
SDS0
bit
DAC
Lch
Rch
Normal
x
x
x
L1
R1
(default)
TDM128
x
x
0
L1
R1
x
x
1
L2
R2
TDM256
x
0
0
L1
R1
x
0
1
L2
R2
x
1
0
L3
R3
x
1
1
L4
R4
TDM512
0
0
0
L1
R1
0
0
1
L2
R2
0
1
0
L3
R3
0
1
1
L4
R4
1
0
0
L5
R5
1
0
1
L6
R6
1
1
0
L7
R7
1
1
1
L8
R8
(x: Do not care)
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(3) Daisy Chain
The AK4497 supports cascading of multiple devices by daisy chain connection in TDM512/256 mode
(TDM[1:0] bits = “10”, “11”). DCHAIN bit or DCHAIN pin controls Daisy Chain mode (Table 26). SDS[2:0]
bits setting will be invalid in Daisy Chain mode.
Table 26. Daisy Chain Control
DCHAIN bit
DCHAIN pin
Mode
TDMO pin
0
Normal
L
(default)
1
Daisy Chain
Data output
(3)-1. TDM512 Mode
Figure 47 shows daisy chain connection in TDM512 mode (TDM[1:0] bits = “11”). 16ch data is input to the
SDATA pin of the second AK4497 and the TDMO pin of the second AK4497 is connected to the SDATA
pin of the first AK4497.
Figure 48 shows data input/output example of daisy chain in TDM512 mode. The second AK4497
receives L8 and R8 data as DAC inputs and outputs the data by shifting 2ch from the TDMO pin. The first
AK4497 receives L7 and R7 data as DAC input. Settings of DIF[2:0] bits of the first and second AK4497’s
must be the same.
First
AK4497
Second
AK4497
DSP
SDATA
TDMO
SDATA
TDMO
Figure 47. Daisy Chain (TDM512 Mode)
SDATA
R1
L1
LRCK
512 BICK
R2
L2
R3
L3
R4
L4
R5
R6
L6
R7
L7
R8
L8
L5
TDMO
R2
R3
L3
R4
L4
R5
L5
L2
Second AK4497
First AK4497
R1
L1
R6
L6
R7
L7
L8
R8
Figure 48. Daisy Chain (TDM512 Mode)
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(3)-2. TDM256 Mode
Figure 47 shows daisy chain connection in TDM256 mode (TDM[1:0] bits = “10”). 8ch data is input to the
SDATA pin of the second AK4497 and the TDMO pin of the second AK4497 is connected to the SDATA
pin of the first AK4497.
Figure 49 shows data input/output example of daisy chain in TDM256 mode. The second AK4497
receives L4 and R4 data as DAC inputs and outputs the data from the TDMO pin by shifting 2ch. The first
AK4497 receives L3 and R3 data as DAC input. Settings of DIF[2:0] bits of the first and second AK4497’s
must be the same.
SDATA
R1
L1
LRCK
256 BICK
R2
L2
R3
L3
R4
L4
TDMO
R1
L1
R2
L2
Second AK4497
First AK4497
R3
L3
R4
L4
Figure 49. Daisy Chain (TDM256 Mode)
[2] DSD Mode
In DSD mode, L channel data and R channel data must be input to the DSDL pin and the DSDR pin,
respectively by synchronizing to DCLK. Input pins can be selected by DSDPATH bit. When DSDPATH bit
= “0”, the TDM0 pin, the DEM pin and the GAIN pin become DCLK, DSDL and DSDR input pins,
respectively. When DSDPATH bit = “1”, the BICK pin, the SDATA pin and the LRCK pin become DCLK,
DSDL and DSDR input pins, respectively.
In case of DSD mode, the settings of DIF2-0 pins and DIF[2:0] bits are ignored. The frequency of DCLK is
selected between 64fs, 128fs and 256fs by DSDSEL[1:0] bits. Phase modulation function is not available
in 512fs mode (DSDSEL[1:0] bits = “11”).
DCLK (64fs,128fs,256fs,512fs)
DCKB bit=”1”
DCLK (64fs,128fs,256fs,512fs)
DCKB bit=”0”
DSDL,DSDR
Normal
DSDL,DSDR
Phase Modulation
D1
D0
D1
D2
D0
D2
D3
D1
D2
D3
Figure 50. DSD Mode Timing
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[3] External Digital Filter Mode (EXDF mode)
The audio data is input by BCK and WCK from the DINL and DINR pins. Three formats are available
(Table 27) by DIF2-0 bits setting. The data is latched on the rising edge of BCK. The BCK and MCLK
clocks must not burst.
Table 27. Audio Interface Format (EXDF mode)
Mode
DIF2
DIF1
DIF0
Input Format
0
0
0
0
16-bit LSB justified
1
0
0
1
N/A
2
0
1
0
16-bit LSB justified
3
0
1
1
N/A
4
1
0
0
24-bit LSB justified
5
1
0
1
32-bit LSB justified
6
1
1
0
24-bit LSB justified
(default)
7
1
1
1
32-bit LSB justified
(N/A: Not available)
BCK
WCK
DINL or
DINR
23
22
BCK
0
1
8
9
10
11
16
17
26
27
28
29
30
31
0
1
21
20
17
16
0
5
1
6
7
8
47
48
49
65
92
93
94
95
0
1
31
30
3
1
0
15
14
6
5
4
3
2
1
0
Don’t care
Don’t care
DINL or
DINR
2
31
24
Don’t care
Don’t care
BCK
0
13
1
14
15
16
23
24
25
44
45
46
47
0
1
3
1
0
Don’t care
DINL or
DINR
2
31
Don’t care
Don’t care
1/16fs or 1/8fs or 1/4fs or 1/2fs
Figure 51. EXDF Mode Timing
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■ Digital Filter
Six types of digital filter in PCM mode and two types of digital filter in DSD mode are available in the
AK4497 for sound color selection of music playback.
In PCM mode, digital filter can be selected by the SD, SLOW and SSLOW pins if the AK4497 is in pin
control mode, and digital filter can be selected by SD, SLOW and SSLOW bits in register control mode
(Table 28).
Table 28. Digital Filter Setting
SSLOW
SD
SLOW
Mode
0
0
0
Sharp Roll-off Filter
0
0
1
Slow Roll-off Filter
0
1
0
Short Delay sharp Roll-off Filter
(default)
0
1
1
Short Delay Slow Roll-off Filter
1
0
0
Super Slow Roll-off Filter
1
0
1
Super Slow Roll-off Filter
1
1
0
Low Dispersion Shot Delay Filter
1
1
1
Reserved
Note: Do not use Reserved mode (SSLOQ bit= “1”, SD bit= “1”, SLOW bit= “1”) in PCM mode.
In DSD mode, the cutoff frequency of digital filter can be switched by DSDF bit. Table 29 shows the cutoff
frequency of fs = 44.1kHz. The cutoff frequency tracks the sampling frequency (fs). Do not set GS[2:0]
bits to “100” when DSDD bit = “0” and DSDF bit = “1”. Otherwise a pop noise may occur.
Table 29. DSD Filter Select
DSDF bit
Cut Off Frequency @fs=44.1kHz
DSD64fs
DSD128fs
DSD256fs
DSD512fs
0
39kHz
78kHz
156kHz
312kHz
(default)
1
76kHz
152kHz
304kHz
608kHz
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■ De-emphasis Filter (PCM Mode)
A digital de-emphasis filter is available for 32kHz, 44.1kHz or 48kHz sampling rates (tc = 50/15µs) and is
enabled or disabled by DEM1-0 pins or DEM1-0 bits. When DSD mode or EXDF mode, DEM1-0 bits are
ignored. The setting value is held even if PCM, DSD and EXDF mode is switched.
Table 30. De-emphasis Control
DEM1
DEM0
Mode
0
0
44.1kHz
0
1
OFF
(default)
1
0
48kHz
1
1
32kHz
■ Output Volume (PCM Mode, DSD Mode, EXDF Mode)
The AK4497 includes channel independent digital output volumes (ATTL/R) with 256 levels at 0.5dB step
including MUTE. When changing output levels, it is executed in soft transition thus no switching noise
occurs during these transitions. It can attenuate the input data from 0dB to -127dB and mute when
assuming the output signal level is 0dB when ATTL/R[7:0] bits = FFH.
Table 31. Attenuation Level of Digital Attenuator
ATTL/R[7:0]bits
(register 03-04H)
Attenuation Level
FFH
+0dB
(default)
FEH
-0.5dB
FDH
-1.0dB
:
:
:
:
02H
-126.5dB
01H
-127.0dB
00H
MUTE (-∞)
The transition time of digital output volume is set by ATS[1:0] bits (Table 31). When changing output
levels between Mode0-3, it is executed in soft transition thus no switching noise occurs during these
transitions. Register setting values will be kept even switching the PCM and DSD modes.
Table 32. Transition Time between Set Values of ATT[7:0] bits
Mode
ATS1
ATS0
ATT speed
EXDF bit=”0”,
DP bit=”0”
EXDF bit=”1”
DP bit=”0”
DP bit=”1”
0
0
0
4080/fs
4080*WCK Cycle
4080/(2*fs)
(default)
1
0
1
2040/fs
2040*WCK Cycle
2040/(2*fs)
2
1
0
510/fs
510*WCK Cycle
510/(2*fs)
3
1
1
255/fs
255*WCK Cycle
255/(2*fs)
It takes 4080/fs (92.5ms@fs=44.1kHz) from FFH (0dB) to 00H (MUTE) in Mode 0. The attenuation level is
initialized to FFH (0dB) by setting the PDN pin = “L”.
If the volume is changed during reset period, the output volume will become a setting value after releasing
the reset. It will change to a setting value immediately if the volume is changed within 5/fs after releasing
reset.
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■ Gain Adjustment Function (PCM Mode, DSD Mode, EXDF Mode)
The AK4497 has the gain adjustment function. The analog output amplitude can be adjusted by GC[2:0]
bits or the GAIN pin.
Table 33. Output Level between Set Values of GC[2:0] Bits
GC[2]
bit
GC[1]
bit
GC[0]
bit
AOUTLP/LN/RP/RN Output Level
PCM
DSD:
Normal Path
DSD:
Volume
Bypass
0
0
0
2.8Vpp
2.8Vpp
2.5Vpp
(default)
0
0
1
2.8Vpp
2.5Vpp
2.5Vpp
0
1
0
2.5Vpp
2.5Vpp
2.5Vpp
0
1
1
2.5Vpp
2.5Vpp
2.5Vpp
1
0
0
3.75Vpp
3.75Vpp
2.5Vpp
1
0
1
3.75Vpp
2.5Vpp
2.5Vpp
1
1
0
2.5Vpp
2.5Vpp
2.5Vpp
1
1
1
2.5Vpp
2.5Vpp
2.5Vpp
Table 34. Output Level between Set Values of GAIN Pin (Valid Only in PCM Mode)
GAIN pin
AOUTLP/LN/RP/RN
Output Level
L
2.8 Vpp
H
3.75 Vpp
Note 49. DSDF bit must be set to “0” if GC[2:0] bits are set to “100” when using DSD Normal Path. Click
noise may occur if DSDF bit is set to “1”.
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■ Zero Detection (PCM Mode, DSD Mode, EXDF Mode)
The AK4497 has a channel-independent zeros detect function. When the input data at each channel is
continuously zeros for 8192 LRCK cycles, the DZF pin of each channel outputs zero detection flag
independently. The DZFL/R pin outputs zero detection flag if the input data is continuously zeros for
16384 LRCK cycles in DSD 512fs mode (DP bit = “1” and DSDSEL[1:0] bits = “11”). Polarity of the
detection flag of the DZFL/R pin can be selected by DZFB bit. The DZFL/R pin goes “H” for zero detection
when DZFB bit = “0”, the DZFL/R pin goes “L” when DZFB bit = “1”.
When DZFB bit = “0”, the DZFL/R pin immediately returns to “L” if the input data of each channel is not
zero after going to “H”. If the RSTN bit is “0”, the DZF pins of both L and R channels go to “H”. The DZFL/R
pin returns to “L” in 4 ~ 5/fs after the input data of each channel becomes “1” when RSTN bit is set to “1”.
If DZFM bit is set to “1” while DZFB bit = “0”, the DZF pins of both L and R channels go to “H” only when
the input data for both channels are continuously zeros for 8192 LRCK cycles (16384 LRCK cycles in
DSD 512fs mode). The zero detect function can be disabled by setting the DZFE bit. In this case, DZF
pins of both channels are always “L”. The zero detect function is also disabled when Volume Bypass is
selected in DSD mode (Table 22).
Table 35. Zero Detect Select.
DZFE
DZFB
RSTN
Data
DZF pin
0
0
-
-
L
1
-
-
H
1
0
0
-
H
1
not zero
L
zero detect
H
1
0
-
L
1
not zero
H
zero detect
L
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■ L/R Channel Output Signal Select, Phase Inversion Function (PCM Mode, DSD Mode, EXDF
Mode)
In register control mode, input and output combination of the AK4497 can be changed by MONO bit and
SELLR bit. In addition, the output signal phase can be inverted by INVL bit and INVR bit. These functions
are available on all audio formats. In pin control mode, the phase of R channel output can be inverted by
setting the INVR pin.
Table 36. Output Select (Register Control)
MONO bit
SELLR bit
INVL bit
INVR bit
Lch Out
Rch Out
0
0
0
0
Lch In
Rch In
0
1
Lch In
Rch In Invert
1
0
Lch In Invert
Rch In
1
1
Lch In Invert
Rch In Invert
0
1
0
0
Rch In
Lch In
0
1
Rch In
Lch In Invert
1
0
Rch In Invert
Lch In
1
1
Rch In Invert
Lch In Invert
1
0
0
0
Lch In
Lch In
0
1
Lch In
Lch In Invert
1
0
Lch In Invert
Lch In
1
1
Lch In Invert
Lch In Invert
1
1
0
0
Rch In
Rch In
0
1
Rch In
Rch In Invert
1
0
Rch In Invert
Rch In
1
1
Rch In Invert
Rch In Invert
Table 37. Output Select (Pin Control)
INVR pin
Lch Out
Rch Out
0
Lch In
Rch In
1
Lch In
Rch In Invert
■ Sound Quality (PCM Mode, DSD Mode, EXDF Mode)
Sound quality of the AK4497 can be selected by SC[2:0] bits. The analog characteristics specification of
the AK4497 is applicable to Setting 1 and Setting 4. The characteristics are not guaranteed in Setting 2, 3
and 5.
Table 38. Sound Quality Select Mode
SC1 bit
SC0 bit
Internal Operation
0
0
Analog internal current, maximum (Setting1)
(default)
0
1
Analog internal current, minimum (Setting2)
1
0
Analog internal current, medium (Setting3)
1
1
Analog internal current, minimum (Setting2)
Table 39. Sound Quality Select Mode
SC2 bit
Sound
0
Default (Setting 4)
(default)
1
High Sound Quality Mode (Setting 5)
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■ DSD Signal Full Scale (FS) Detection
The AK4497 has independent full scale detection function for each channel for DSD mode.
The AK4497 detects full scale signal when the DSDL/R input data is continuously “0” (-FS) or “1” (+FS) for
2048 cycles and the detection flag for corresponding channel (DML or DMR bit) becomes “1”. DML and
DMR bits can be read out at the register address 06H.
When the AK4497 detects full scale signal while DDM bit = “1”, the analog output is muted according to
Table 41. ATS[2:0] bits control a mute transition time. ATS[2:0] bits and DSDD bit settings are also valid
when the AK4497 returns to normal status from full scale detection status.
The recovery timing from full scale detection status and the operation mode of full scale detection are
controlled by DDM bit, DMC bit and DMRE bit. RSTN bit must be set to “0” when changing DDM bit
setting.
Table 40. DSD Mode and Device Status after Full-Scale Detection (DDM bit= “1”)
DSDD
Mode
Analog Output
Full Scale Detection Status
0
Normal Path
VCML/R (Mute)
Soft Mute
(default)
1
Volume Bypass
VCM/L/R (Mute)
Rapid Mute
Table 41. Recovery Method to Normal Operation Mode from Full Scale Detection Status
DDM
DMC
DMRE
Status After Detection
0
*
*
When full scale is detected, Mute function is disabled.
(default)
1
0
*
When full scale is detected, Mute function is enabled.
The AK4497 returns to normal operation automatically
by a normal signal input.
1
1
0
When full scale is detected, Mute function is enabled.
The AK4497 keeps mute mode, even if a normal signal is
input.
1
1
1
(Note 50)
When full scale is detected, Mute function is enabled.
The AK4497 returns to normal operation when a normal
signal is input and DMRE bit is set to “1”.
Note 50. DMRE bit returns to “0” automatically after the AK4497 returns to normal operation.
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DSD Error
(DML or DMRbit)
DSD Data
DSD Data
DSD Data (FS or -FS )
DSD Data
2048fs
AOUT
(DSDD bit= “1”)
AOUT
(DSDD bit= “0”)
ATT Transition Period
ATT Transition Period
Figure 52. Analog Output Waveform in DSD FS Detection (DMC bit= “0”)
DSD Error
(DML or DMRbit)
DSD Data
DSD Data
DSD Data (FS or -FS )
DSD Data
2048fs
AOUT
(DSDD bit= “1”)
AOUT
(DSDD bit= “0”)
DMRE bit
ATT Transition Period
ATT Transition Period
Figure 53. Analog Output Waveform in DSD FS Detection (DMC bit= “1”)
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■ Soft Mute Operation (PCM Mode, DSD Mode, EXDF Mode)
The soft mute operation is performed at digital domain. When the SMUTE pin goes to “H” or the SMUTE
bit set to “1”, the output signal is attenuated by during ATT_DATA ATT transition time from the
current ATT level. When the SMUTE pin is returned to “L” or the SMUTE bit is returned to “0”, the mute is
cancelled and the output attenuation gradually changes to the ATT level during ATT_DATA ATT
transition time. If the soft mute is cancelled before attenuating after starting the operation, the
attenuation is discontinued and returned to ATT level by the same cycle. The soft mute is effective for
changing the signal source without stopping the signal transmission.
SMUTE pin or
SMUTE bit
Attenuation
DZFL/R pin
ATT_Level
-
AOUTL/R
8192/fs
GD
GD
(1)
(2)
(3)
(4)
(1)
(2)
Figure 54. Soft Mute Function
Notes:
(1) ATT_DATA ATT transition time. For example, this time is 4080LRCK cycles (1020/fs) at
ATT_DATA=255 in PCM Normal Speed Mode.
(2) The analog output corresponding to the digital input has group delay (GD).
(3) If the soft mute is cancelled before attenuating after starting the operation, the attenuation is
discontinued and returned to ATT level by the same cycle.
(4) When the input data for each channel is continuously zeros for 8192 LRCK cycles (16384 LRCK
cycles in DSD 512fs mode), the DZF pin for each channel goes to “H”. The DZF pin immediately
returns to “L” if input data are not zero.
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■ LDO
When TVDD = 3.0 ~3.6V, the power for digital core circuit (DVDD) is supplied by the internal LDO by
setting the LDOE pin to “H”. Table 42 shows the DVDD pin statuses with the PDN and LDOE pins setting.
The internal LDO is powered up by setting the PDN pin from “L” to “H” (power-down release) and it starts
supping 1.8V DVDD. It takes 0.1ms (max.) to power-up the internal LDO.
Table 42. LDO Select Mode
PDN pin
LDOE pin
TVDD
DVDD
X
L
1.7~3.6V
LDO OFF: Supply 1.7 ~ 1.98V to the DVDD pin externally
L
H
3.0~3.6V
500ohm Pull Down
H
H
3.0~3.6V
LDO ON: LDO outputs 1.8V.
(Do not connect DVDD with other devices.)
(X: Do not care)
The AK4497 has error detect function as shown in Table 43 for LDO operation (LDOE pin = “H”). The
internal LDO will be powered down and stop supplying the power to the digital core when an error is
detected. In this case, the analog signal output becomes unstable. The AK4497 must be reset by setting
the PDN pin = “L” → “H” to recover from the error detection status.
Table 43. Error Detection
No
Error
Error Detection Condition
1
Internal Reference Voltage Error
Internal reference voltage does not rise.
2
LDO Over Voltage Detection
LDO voltage exceeds 2.2V.
3
LDO Over Current Detection
LDO current is 40mA or less, or 110mA or more.
■ Shutdown Switch
A shutdown switch is placed between the DVSS pin and VSS for the digital core to prevent SIDD leak of
DVDD digital power supply. The on-resistance is maximum 1Ω and the DVDD leak current will be 2uA at
the maximum.
When using LDO (LDOE pin = “H”), the shutdown switch is ON after counting by internal oscillator
following a power-down release (PDN pin “L” → “H”). It takes 2ms (max.) for the shutdown switch
power-up.
When not using LDO (LDOE pin = “L”), the shutdown switch is ON immediately after a power-down
release (PDN pin “L” → “H”). It takes 1us (max.) for the shutdown switch power-up.
■ Over Current Protection for Analog Output Pins
The AK4497 has channel independent over current detection function for analog output pins
(AOUTLP/LN and AOUTRP/RN pins). This function limits the current not to exceed approximately 120mA
when an excessive current over about 120mA (min) is detected. This function is invalid when the PDN pin
= “L” or PW bit = “0” or when the MCLK is stopped.
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■ Power Up/Down Function
The AK4497 is powered down by setting the PDN pin to “L”. In power-down state, all circuits stop
operation and initialized, and the analog output becomes floating (Hi-z) state. The PDN pin must held “L”
for more than 150ns for a certain reset. There is a possibility of malfunctions with the “L” pulse less than
150ns. Power-down is released by setting the PDN pin to “H” from “L”. In this time IREF and LDO (if
LDOE pin = “H”) are powered up and the analog output becomes floating (Hi-z) state.
(a) Pin Control Mode (PSN pin = “H”)
All circuits will be powered up by inputting MCLK, LRCK and BICK clocks after the PDN pin = “H”. The
analog circuit starts operation just after supplying all necessary clocks (MCLK, LRCK and BICK) and the
digital circuit starts operation about 4/fs after the clock supply. Figure 55 shows system timing example of
power down/up when using the internal LDO (LDOE pin “H”). When power up the AK4497 with the LDOE
pin = “H”, 3.3V power supplies (AVDD and TVDD) should be powered up before or at the same time of 5V
power supplies (VDDL/R).
PDN pin
Power
(VDDL/R)
Reset
Normal Operation (DAC input available)
Clock In
MCLK,LRCK,BICK
DAC In
(Digital)
DAC Out
(Analog)
External
Mute
Mute ON
(6)
“0”data
GD
(3)
(5)
GD
(5)
Mute ON
“0”data
Internal State
(4)
(4)
(1)
Internal PDN
(2)
DVDD pin
Power
(TVDD,AVDD)
Analog Reference
(VREFHL,VREFHR)
Don’t care
(7)
(8)
Figure 55. Power-down/up Sequence Example (Pin Control Mode, LDOE pin= “H”)
Notes:
(1) The PDN pin must be held “L” for more than 150ns after supplying AVDD, TVDD and VDDL/R.
(2) Internal LDO is powered up after the PDN pin = “H” when the LDOE pin= “H”. The internal circuit
will starts operation after the shutdown switch is ON (max. 2ms) following the internal oscillator
count up.
(3) The analog output corresponding to the digital input has group delay (GD).
(4) Analog outputs are floating (Hi-Z) in power down mode.
(5) Click noise occurs at the edge of PDN signal. This noise is output even if “0” data is input.
(6) Mute the analog output externally if click noise (5) adversely affect system performance.
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(7) Clock inputs (MCLK, BICK and LRCK) can be stopped in power down state.
(8) Do not input a clock when power supplies are powered down.
The timing example when not using the internal LDO (LODE pin = “L”) is shown in Figure 56. When the
LDOE pin= “L”, 1.8V (DVDD), 3.3V (AVDD, TVDD) and 5V (VDDL, VDDR) power supplies should be
powered up at the same time, otherwise power up 3.3V power supplies (AVDD, TVDD) first, the 1.8V
power supply (DVDD) next and 5V power supplies (VDDL/R) last.
Power
(DVDD)
Reset
Normal Operation (DAC input available)
Clock In
MCLK,LRCK,BICK
DAC In
(Digital)
DAC Out
(Analog)
External
Mute
Mute ON
(6)
“0”data
GD
(3)
(5)
GD
(5)
Mute ON
“0”data
Internal State
(4)
(4)
Internal PDN
(2)
Power
(TVDD,AVDD)
Power
(VDDL/R)
Don’t care
(7)
(8)
Analog Reference
(VREFHL/R)
PDN pin
(1)
Figure 56. Power-down/up Sequence Example (Pin Control Mode, LDOE pin= “L”)
Notes:
(1) The PDN pin must be held “L” for more than 150ns after AVDD, TVDD, DVDD and VDDL/R
reached 90%.
(2) Internal shutdown switch is powered up after the PDN pin = “H” when the LDOE pin= “L”. The
internal circuit will start operation after the shutdown switch is ON (max. 1us).
(3) The analog output corresponding to the digital input has group delay (GD).
(4) Analog outputs are floating (Hi-Z) in power down mode.
(5) Click noise occurs at the edge of PDN signal. This noise is output even if “0” data is input.
(6) Mute the analog output externally if click noise (5) adversely affect system performance.
(7) Clock inputs (MCLK, BICK and LRCK) can be stopped in power down state.
(8) Do not input a clock when power supplies are powered down.
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(b) Register Control Mode (PSN pin= “L”)
A register access becomes available after the PDN pin = “H”. The analog circuit starts operation by
supplying necessary clocks (MCLK, LRCK and BICK for PCM mode, MCLK and DCLK for DSD mode,
MCLK, BCK and WCK for EXDF mode) and the clock divider is powered up about after 4/fs. The
analog output pins output analog common voltages (VCML, VCMR) in this time. Then the AK4497
transitions to normal operation by setting RSTN bit = “1”. When power up the AK4497 with the LDOE
pin = “H”, 3.3V power supplies (AVDD and TVDD) should be powered up before or at the same time of
5V power supplies (VDDL/R).
PDN pin
Analog Reference
(VREFHL/R)
Clock In
MCLK,LRCK,BICK
DAC In
(Digital)
DAC Out
(Analog)
External
Mute
Mute ON
(6)
“0”data
GD
(5)
GD
Mute ON
“0”data
Internal State
(Digital Core)
(4)
(4)
(1)
Internal PDN
(2)
DVDD pin
Power
(TVDD,AVDD)
DZFL/R
(7)
RSTN bit
Normal Operation
Normal Operation
(5)
Internal State
(Resister
(Clock devider)
Power Off
(3)
(8)
(9)
(9)
(11)
(11)
(10)
Power
(VDDL/R)
Power Off
Power Off
Power Off
Don’t Care
Figure 57. Power-down/up Sequence Example (Resister Control Mode, LDOE pin= “H”)
Notes:
(1) The PDN pin must be held “L” for more than 150ns after AVDD, DVDD, TVDD and VDDL/R
reached 90%.
(2) Internal LDO is powered up after the PDN pin = “H” when the LDOE pin= “H”. The internal circuit
will starts operation after the shutdown switch is ON (max. 2ms) following the internal oscillator
count up.
(3) The analog output corresponding to the digital input has group delay (GD).
(4) Analog outputs are floating (Hi-Z) in power down mode.
(5) Click noise occurs at the edge of PDN signal. This noise is output even if “0” data is input.
(6) Mute the analog output externally if click noise (5) adversely affect system performance.
(7) The DZFL/R pins are “L” in power-down mode (PDN pin = “L”).
(8) The clock divider is powered up in about 4/fs after the internal PDN is released.
(9) It takes 3~4/fs until a reset instruction is valid when writing RSTN bit to “0” and it takes 2~3/fs when
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releasing the reset.
(10) Clock inputs (MCLK, BICK and LRCK) can be stopped in power down state.
(11) Do not input a clock when power supplies are powered down.
The system timing example of power up/down when not using LDO (LODE pin = “L”) is shown in Figure
58. When the LDOE pin= “L”, 1.8V (DVDD), 3.3V (AVDD, TVDD) and 5V (VDDL, VDDR) power supplies
should be powered up at the same time, otherwise power up the 3.3V power supplies (AVDD, TVDD) first,
1.8V power supply (DVDD) next and 5V power supplies (VDDL/R) last.
PDN pin
Analog Reference
(VREFHL/R)
Clock In
MCLK,LRCK,BICK
DAC In
(Digital)
DAC Out
(Analog)
External
Mute
Mute ON
(6)
“0”data
GD
(5)
GD
Mute ON
“0”data
Internal State
(Digital Core)
(4)
(4)
(1)
Internal PDN
(2)
Power
(TVDD,AVDD)
DZFL/R
(7)
RSTN bit
Normal Operation
Normal Operation
(5)
Internal State
(Resister
(Clock devider)
Power Off
(3)
(8)
(9)
(9)
(11)
(11)
(10)
Power
(VDDL/R)
Power Off
Power Off
Power Off
Don’t Care
Power
(DVDD)
Figure 58. Power-down/up Sequence Example (Resister Control Mode, LDOE pin= “L”)
Notes:
(1) The PDN pin must be held “L” for more than 150ns after supplying AVDD, TVDD and VDDL/R.
(2) Internal shutdown switch is powered up after the PDN pin = “H” when the LDOE pin= “L”. The
internal circuit will start operation after the shutdown switch is ON (max. 1us).
(3) The analog output corresponding to the digital input has group delay (GD).
(4) Analog outputs are floating (Hi-Z) in power down mode.
(5) Click noise occurs at the edge of PDN signal. This noise is output even if “0” data is input.
(6) Mute the analog output externally if click noise (5) adversely affect system performance.
(7) The DZFL/R pins are “L” in power-down mode (PDN pin = “L”).
(8) The clock divider is powered up in about 4/fs after the internal PDN is released.
(9) It takes 3~4/fs until the internal RSTN is changed when changing RSTN bit to “0” and it takes
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2~3/fs when changing RSTN bit to “1”.
(10) Clock inputs (MCLK, BICK and LRCK) can be stopped in power down state.
(11) Do not input a clock when power supplies are powered down.
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■ Power-OFF/Reset Function
Power-off and Reset function of the AK4497 are controlled by PW bit, RSTN bit and MCLK (Table 44).
Table 44. Power Off, Reset Function
Mode
PDN
Pin
MCLK
Supply
PW
bit
RSTN
bit
DIGITAL
Block
ANALOG
Block
LDO
Register
Analog Output
Power Down
L
－
－
－
OFF
OFF
OFF
Hi-Z
MCLK Stop
H
No
－
－
OFF
OFF
ON
Hi-Z
Power OFF
H
Yes
0
－
OFF
OFF
ON
Hi-Z
Reset
H
Yes
1
0
OFF
ON
ON
VCML/R
Normal Operation
H
Yes
1
1
ON
ON
ON
Signal Output
[1] Power ON/OFF by MCLK Clock
The AK4497 detects a clock stop and all circuits including MCLK stop detection circuit, control register
and IREF (except LDO when the LDOE pin = “H”) stop operation if MCLK is not input for 1us (min.) during
operation (PDN pin = “H”). In this case, the analog output goes floating state (Hi-Z). The AK4497 returns
to normal operation if PW bit and RSTN bit are “1” after starting to supply MCLK again. The zero detect
function is disabled when MCLK is stopped.
Notes:
(1) The AK4497 detects MCLK stop and becomes power off state when MCLK edge is not detected for
1us (min.) during operation.
(2) The analog output goes to floating state (Hi-Z).
(3) Click noise can be reduced by inputting “0” data when stopping and resuming MCLK supply.
(4) Resume MCLK input to release the power-off state by MCLK. In this case, power-up sequence by
the PDN pin or power-on sequence by PW bit are not necessary.
(5) The analog output corresponding to the digital input has group delay (GD).
Figure 59. Power ON/OFF by MCLK Clock
Normal Operation
Internal
State
Power
-
off
Normal Operation
D/A Out
(Analog)
D/A In
(Digital)
Clock In
MCLK,
(
1
)
MCLK Stop
PDN
pin
(1)
(2)
Hi
-
Z
(
4
)
(3
)
(5)
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[2] Power ON/OFF by PW bit
All circuits including control register and IREF (except LDO when the LDOE pin = “H”) stop operation by
setting PW bit to “0”. In this case, control register access is available. The analog output goes to floating
state (Hi-Z). Figure 60 shows power ON/OFF sequence by PW bit.
Internal
State
PW bit
Power-off
Normal Operation
GD
GD
“0” data
DAC Out
(Analog)
DAC In
(Digital)
(1)
(3)
(3)
(1)
(2) Hi-Z
Normal Operation
RSTN bit
(4)
DZFL/DZFR
External
MUTE
(6)
Mute ON
(5)
(5)
Notes:
(1) The analog output corresponding to the digital input has group delay (GD).
(2) The analog output is floating (Hi-Z) state when PW bit = “0”.
(3) Click noise occurs at the edge of PW bit. This noise is output even if “0” data is input.
(4) The zero detect function is enable when the AK4497 is power off (PW bit= “0”). This figure shows
the seuqnece when DZFE bit= “1”, DZFB bit = “0” and DZFM bit= “0”.
(5) It takes 4~5/fs until a power down instruction is valid when writing PW bit and it takes 1~2/fs when
releasing the power down.
(6) Mute the analog output externally if click noise (3) or Hi-z output (2) adversely affect system
performance.
Figure 60. Power ON/OFF Timing Example
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[3] Reset by RSTN bit
Digital circuits except control registers and clock divider are reset by setting RSTN bit to “0”. In this case,
control register settings are held, the analog output becomes VCML/R voltage and the DZFL/R pins
output “H”. Figure 61 shows power ON/OFF sequence by RSTN bit.
Internal
State
RSTN bit
Digital Block Power-off
Normal Operation
GD
GD
“0” data
DAC Out
(Analog)
DAC In
(Digital)
(1)
(3)
DZFL/R
(3)
(1)
(2)
Normal Operation
2/fs(4)
Internal
RSTN signal
2~3/fs (5)
3~4/fs (5)
(6)
Notes:
(1) The analog output corresponding to the digital input has group delay (GD).
(2) The analog output is VCOM voltage when RSTN bit = “0”.
(3) Click noise occurs at the edge of PW bit. This noise is output even if “0” data is input.
(4) This figure shows the seuqnece when DZFE bit= “1”, DZFB bit = “0” and DZFM bit= “0”. The
DZFL/R pin goes “H” on a falling edge of RSTN bit and goes “L” 2/fs after a rising edge of internal
RSTN bit.
(5) It takes 3~4/fs until the internal RSTN is changed when changing RSTN bit to “0” and it takes
2~3/fs when changing RSTN bit to “1”.
(6) Mute the analog output externally if click noise (3) adversely affect system performance.
Figure 61. Reset Timing Example
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■ Synchronize Function (PCM mode, EXDF mode)
The AK4497 has a function that resets the internal counter to keep the timing of falling edge of the internal
clock CLK1 and the external clock edge in a certain range. With this synchronize function, group delays
between each device can be kept within 4/256fs when using multiple AK4497’s.
Clock synchronize function becomes valid when input data of both L and R channels are “0” for 8192
times continuously in PCM mode or EXDF mode, when both L and R channels become “0” and kept for
8192 times continuously by attenuation or when RSTN bit = “0”. In PCM mode, the internal counter is
synchronized with a rising edged of LRCK (falling edge of LRCK in I2C mode), and it is synchronized with
a rising edge of WCK in EXDF mode. In this case, the analog output has the same voltage as VCML/R.
This function is disabled by setting SYNCE bit = “0” in register control mode. Figure 62 shows a
synchronizing sequence when the input data is “0” for 8192 times continuously. Figure 63 shows a
synchronizing sequence by RSTN bit.
SMUTE
Attenuation
Both DZFL/R pin
ATT_Level
-
AOUT
8192/fs
GD
(1)
(2)
(1)
D/A In
(Digital)
GD
GD
8192/fs
(2)
SYNC
Operation (2)
SYNC
Operation (2)
Internal Counter
Reset
Internal
Data
2~3/fs (3)
(4)
(5)
Notes:
(1) Regarding ATT Transition time, refer to “■ Output Volume (PCM Mode, DSD Mode, EXDF Mode)”.
(2) When both L and R channels data are “0” for 8192 times continuously, the DZFL and DZFR pins
become “H” and the synchronize function is valid.
(3) Internal data is fixed to “0” forcibly for 2 to 3/fs when internal counter is reset.
(4) A click noise may occur when the internal counter is reset. This noise is output even if a “0” data is
input. Mute the analog output externally if this click noise affects the system performance.
(5) When the internal clock and external clock are in synchronization, the internal counter is not reset
even if the synchronize function is valid.
Figure 62. Synchronizing Sequenc by Continuous “0” Data Input for 8192 Times
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If RSTN bit is set to “0”, the output signal of the DZFL/R pin becomes “H”. Then, the DAC is reset after 3~
4/fs and the analog output becomes the same voltage as VCML/R. The synchronize function becomes
valid when both of the DZFL and the DZFR pins output “H”.
Internal
State
RSTN bit
Digital Block Power-down
Normal Operation
GD
GD
D/A Out
(Analog)
D/A In
(Digital)
(3)
(5)
Both DZFL/R pin
(5)
(3)
Normal Operation
2/fs(4)
Internal
RSTN bit
2~3/fs (4)
3~4/fs (4)
Internal Counter
Reset
Internal
Data
2~3/fs (2)
force”0”
SYNC Operation (1)
(2)
Note:
(1) The DZFL and the DZFR pins become “H” by a falling edge of RSTN bit, and becomes “L” 2/fs after a
rising edge of internal signal of RSTN bit. The synchronize function is valid During the DZFL/R pin =
“H”.
(2) Internal data is fixed to “0” forcibly for 2 to 3/fs when the internal counter is reset.
(3) Since the analog output corresponding to digital input has group delay (GD), it is recommended to
have a no-input period longer than the group delay before writing “0” to RSTN bit.
(4) It takes 3 to 4/fs when falling to change the internal RSTN signal of the LSI after writing to RSTN bit. It
also takes 2 to 3/fs when rising to change the internal RSTN signal of the LSI. The synchronize
function becomes valid immediately when “0” is written to RSTN bit. Therefore, there is a case that the
internal counter is reset before internal RSTN signal of the LSI is changed.
(5) A click noise occurs on the rising or falling edge of the internal RSTN signal and when the internal
counter is reset. This noise is output even if a “0” data is input. Mute the analog output externally if this
click noise affects the system performance.
Figure 63. Synchronizing Sequence by RSTN Bit
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■ Register Control Interface
[1] 3-wire Serial Control Mode (I2C pin = “L”)
Pins (pin control mode) or registers (register control mode) can control the functions of the AK4497. In pin
control mode, the register setting is ignored, and in register control mode the pin settings are ignored.
When the state of the PSN pin is changed, the AK4497 should be powered down by the PDN pin.
Otherwise, malfunctions may occur since previous settings are not initialized. The register control
interface is enabled by the PSN pin = “L”. Internal registers may be written to through 3-wire µP interface
pins: CSN, CCLK and CDTI. The data on this interface consists of Chip address (2-bits, C1/0),
Read/Write (1-bit; fixed to “1”, write only), Register address (MSB first, 5-bits) and Control data (MSB first,
8-bits). The data is output on a falling edge of CCLK and the data is received on a rising edge of CCLK.
The writing of data is valid when CSN “”. The clock speed of CCLK is 5MHz (max).
Setting the PDN pin to “L” resets the registers to their default values. In register control mode, the digital
block except control registers and clock divider is reset by setting RSTN bit to “0”. In this case, the register
values are not initialized.
CDTI
CCLK
C1
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
D4
D5
D6
D7
A1
A2
A3
A4
R/W
C0
A0
D0
D1
D2
D3
CSN
C1-C0: Chip Address (C1 bit =CAD1 pin, C0 bit =CAD0 pin)
R/W: READ/WRITE (Fixed to “1”, Write only)
A4-A0: Register Address
D7-D0: Control Data
Figure 64. Control I/F Timing
* The AK4497 does not support read commands in 3-wire serial control mode.
* When the AK4497 is in power down mode (PDN pin = “L”), writing into control registers is prohibited.
* The control data cannot be written when the CCLK rising edge is 15 times or less, or 17 times or more
during CSN is “L”.
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[2] I2C-bus Control Mode (I2C pin = “H”)
The AK4497 supports the fast-mode I2C-bus (max: 400kHz, Ver. 1.0).
(1) WRITE Operations
Figure 65 shows the data transfer sequence for the I2C-bus mode. All commands are preceded by a
START condition. A HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START
condition (Figure 71). After the START condition, a slave address is sent. This address is 7 bits long
followed by the eighth bit that is a data direction bit (R/W). The most significant five bits of the slave
address are fixed as “00100”. The next bits are CAD1 and CAD0 (device address bits). This bit identifies
the specific device on the bus. The hard-wired input pin (CAD1pins, CAD0 pin) sets these device address
bits (Figure 66). If the slave address matches that of the AK4497, the AK4497 generates an acknowledge
and the operation is executed. The master must generate the acknowledge-related clock pulse and
release the SDA line (HIGH) during the acknowledge clock pulse (Figure 72). A R/W bit value of “1”
indicates that the read operation is to be executed, and “0” indicates that the write operation is to be
executed.
The second byte consists of the control register address of the AK4497 and the format is MSB first.
(Figure 67). The data after the second byte contains control data. The format is MSB first, 8bits (Figure
68). The AK4497 generates an acknowledge after each byte is received. Data transfer is always
terminated by a STOP condition generated by the master. A LOW to HIGH transition on the SDA line
while SCL is HIGH defines a STOP condition (Figure 71).
The AK4497 can perform more than one byte write operation per sequence. After receipt of the third byte
the AK4497 generates an acknowledge and awaits the next data. The master can transmit more than one
byte instead of terminating the write cycle after the first data byte is transferred. After receiving each data
packet the internal address counter is incremented by one, and the next data is automatically taken into
the next address. If the address exceeds “15H” prior to generating a stop condition, the address counter
will “roll over” to “00H” and the previous data will be overwritten.
The data on the SDA line must remain stable during the HIGH period of the clock. HIGH or LOW state of
the data line can only be changed when the clock signal on the SCL line is LOW (Figure 73) except for the
START and STOP conditions.
SDA
S
T
A
R
T
A
C
K
A
C
K
S
Slave
Address
A
C
K
Sub
Address(n)
Data(n)
P
S
T
O
P
Data(n+x)
A
C
K
Data(n+1)
A
C
K
R/W= “0”
A
C
K
Figure 65. Data Transfer Sequence at I2C Bus Mode
0
0
1
0
0
CAD1
CAD0
R/W
(CAD0 is set by the pin)
Figure 66. The First Byte
0
0
0
A4
A3
A2
A1
A0
Figure 67. The Second Byte
D7
D6
D5
D4
D3
D2
D1
D0
Figure 68. The Third Byte and After The Third Byte
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(2) READ Operation
Set the R/W bit = “1” for the READ operation of the AK4497. After transmission of data, the master can
read the next address’s data by generating an acknowledge instead of terminating the write cycle after
the receipt of the first data word. After receiving each data packet the internal address counter is
incremented by one, and the next data is automatically taken into the next address. If the address
exceeds “15H” prior to generating stop condition, the address counter will “roll over” to “00H” and the data
of “00H” will be read out.
The AK4497 supports two basic read operations: Current Address Read and Random Address Read.
(2)-1. Current Address Read
The AK4497 has an internal address counter that maintains the address of the last accessed word
incremented by one. Therefore, if the last access (either a read or write) were to address “n”, the next
CURRENT READ operation would access data from the address “n+1”. After receipt of the slave address
with R/W bit “1”, the AK4497 generates an acknowledge, transmits 1-byte of data to the address set by
the internal address counter and increments the internal address counter by 1. If the master does not
generate an acknowledge but generates a stop condition instead, the AK4497 ceases the transmission.
SDA
S
T
A
R
T
A
C
K
A
C
K
S
Slave
Address
A
C
K
Data(n+1)
P
S
T
O
P
Data(n+x)
A
C
K
Data(n+2)
A
C
K
R/W= “1”
A
C
K
Data(n)
Figure 69. Current Address Read
(2)-2. Random Address Read
The random read operation allows the master to access any memory location at random. Prior to issuing
the slave address with the R/W bit “1”, the master must first perform a “dummy” write operation. The
master issues a start request, a slave address (R/W bit = “0”) and then the register address to read. After
the register address is acknowledged, the master immediately reissues the start request and the slave
address with the R/W bit “1”. The AK4497 then generates an acknowledge, 1 byte of data and increments
the internal address counter by 1. If the master does not generate an acknowledge but generates a stop
condition instead, the AK4497 ceases the transmission.
SDA
S
T
A
R
T
A
C
K
A
C
K
S
Slave
Address
A
C
K
Data(n)
P
S
T
O
P
Data(n+x)
A
C
K
Data(n+1)
A
C
K
R/W= “0”
A
C
K
Sub
Address(n)
S
T
A
R
T
A
C
K
S
Slave
Address
R/W= “1”
Figure 70. Random Address Read
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SCL
SDA
stop condition
start condition
S
P
Figure 71. Start Condition and Stop Condition
SCL FROM
MASTER
acknowledge
DATA
OUTPUT BY
TRANSMITTER
DATA
OUTPUT BY
RECEIVER
1
9
8
START
CONDITION
not acknowledge
clock pulse for
acknowledgement
S
2
Figure 72. Acknowledge (I2C Bus)
SCL
SDA
data line
stable;
data valid
change
of data
allowed
Figure 73. Bit Transfer (I2C Bus)
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■ Register Map
Addr
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
00H
Control 1
ACKS
EXDF
ECS
AFSD
DIF2
DIF1
DIF0
RSTN
01H
Control 2
DZFE
DZFM
SD
DFS1
DFS0
DEM1
DEM0
SMUTE
02H
Control 3
DP
0
DCKS
DCKB
MONO
DZFB
SELLR
SLOW
03H
Lch ATT
ATT7
ATT6
ATT5
ATT4
ATT3
ATT2
ATT1
ATT0
04H
Rch ATT
ATT7
ATT6
ATT5
ATT4
ATT3
ATT2
ATT1
ATT0
05H
Control4
INVL
INVR
0
0
0
0
DFS2
SSLOW
06H
DSD1
DDM
DML
DMR
DMC
DMRE
0
DSDD
DSDSEL0
07H
Control5
0
0
0
0
GC2
GC1
GC0
SYNCE
08H
Sound Control
0
0
0
0
HLOAD
SC2
SC1
SC0
09H
DSD2
0
0
0
0
0
DSDPATH
DSDF
DSDSEL1
0AH
Control 7
TDM1
TDM0
SDS1
SDS2
0
PW
0
0
0BH
Control 8
ATS1
ATS0
0
SDS0
0
0
DCHAIN
TEST
0CH
Reserved
0
0
0
0
0
0
0
0
0DH
Reserved
0
0
0
0
0
0
0
0
0EH
Reserved
0
0
0
0
0
0
0
0
0FH
Reserved
0
0
0
0
0
0
0
0
10H
Reserved
0
0
0
0
0
0
0
0
11H
Reserved
0
0
0
0
0
0
0
0
12H
Reserved
0
0
0
0
0
0
0
0
13H
Reserved
0
0
0
0
0
0
0
0
14H
Reserved
0
0
0
0
0
0
0
0
15H
DFS read
0
0
0
0
0
ADFS2
ADFS1
ADFS0
Notes:
• In 3-wire serial control mode, the AK4497 does not support read commands.
• The AK4497 supports read command in I2C-bus control mode.
• If the address exceeds “15H”, the address counter will “roll over” to “00H” and the next write/read
address will be “00H” by automatic increment function in I2C-Bus mode.
• Bits indicated as 0 in each address and TEST bit in “0BH” must contain a “0” value. Malfunctions may
occur if a “1” data is written to these bits.
• When the PDN pin goes to “L”, the registers are initialized to their default values.
• When RSTN bit is set to “0”, the digital block except control registers and clock divider is reset, and the
registers are not initialized to their default values.
• When the state of the PSN pin is changed, the AK4497 should be reset by the PDN pin.
(Note) The AK4497 is register compatible with the AK4490 and the AK4495.
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(Reference) AK4490 Register Map
Addr
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
00H
Control 1
ACKS
EXDF
ECS
0
DIF2
DIF1
DIF0
RSTN
01H
Control 2
DZFE
DZFM
SD
DFS1
DFS0
DEM1
DEM0
SMUTE
02H
Control 3
DP
0
DCKS
DCKB
MONO
DZFB
SELLR
SLOW
03H
Lch ATT
ATT7
ATT6
ATT5
ATT4
ATT3
ATT2
ATT1
ATT0
04H
Rch ATT
ATT7
ATT6
ATT5
ATT4
ATT3
ATT2
ATT1
ATT0
05H
Control4
INVL
INVR
0
0
0
0
DFS2
DFTHR
06H
DSD1
DDM
DML
DMR
DMC
DMRE
0
DSDD
DSDSEL0
07H
Control5
0
0
0
0
0
0
0
SYNCE
08H
Sound Control
0
0
0
0
0
0
SC1
SC0
09H
DSD2
0
0
0
0
0
0
DSDF
DSDSEL1
(Reference) AK4495 Register Map
Addr
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
00H
Control 1
ACKS
EXDF
ECS
0
DIF2
DIF1
DIF0
RSTN
01H
Control 2
DZFE
DZFM
SD
DFS1
DFS0
DEM1
DEM0
SMUTE
02H
Control 3
DP
0
DCKS
DCKB
MONO
DZFB
SELLR
SLOW
03H
Lch ATT
ATT7
ATT6
ATT5
ATT4
ATT3
ATT2
ATT1
ATT0
04H
Rch ATT
ATT7
ATT6
ATT5
ATT4
ATT3
ATT2
ATT1
ATT0
05H
Control4
INVL
INVR
0
0
0
0
DFS2
DFTHR
06H
Control5
DDM
DML
DMR
DMC
DMRE
DSDD1
DSDD0
DSDSEL
07H
Control6
0
0
0
0
0
0
0
SYNCE
08H
Sound Control
0
0
0
0
0
SC2
SC1
SC0
09H
Reserved
0
0
0
0
0
0
0
0
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■ Register Definitions
Addr
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
00H
Control 1
ACKS
EXDF
ECS
AFSD
DIF2
DIF1
DIF0
RSTN
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
1
1
0
0
RSTN: Internal Timing Reset
0: Reset. All registers are not initialized. (default)
1: Normal Operation
DIF[2:0]: Audio Data Interface Modes (Table 24)
Initial value is “110” (Mode 6: 32-bit MSB justified)
AFSD: Sampling Frequency Auto Detect Mode Enable (PCM & EXDF mode only). (Table 5)
0: Disable: Manual or Auto Setting Mode (default)
1: Enable: Auto Detect Mode
When AFSD bit = “1”, DFS[2:0] bits are ignored.
ECS: EXDF mode clock setting (Table 23)
0: WCK=768kHz mode (default)
1: WCK=384kHz mode
EXDF: External Digital Filter I/F Mode (Register Control mode only)
0: Disable: Internal Digital Filter mode (default)
1: Enable: External Digital Filter mode
ACKS: Master Clock Frequency Auto Setting Mode Enable (PCM & EXDF mode only). (Table 14, Table 5)
0: Disable: Manual Setting Mode (default)
1: Enable: Auto Setting Mode
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Addr
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
01H
Control 2
DZFE
DZFM
SD
DFS1
DFS0
DEM1
DEM0
SMUTE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
1
0
0
0
1
0
SMUTE: Soft Mute Enable
0: Normal Operation (default)
1: DAC outputs soft-muted.
DEM[1:0]: De-emphasis Filter Control (Table 30)
Initial value is “01” (OFF).
DFS[1:0]: Sampling Speed Control. (Table 7, Table 11)
Initial value is “000” (Normal Speed). Click noise occurs when DFS1-0 bits are changed.
SD: Minimum delay Filter Enable. (Table 28)
0: Traditional filter
1: Short delay filter (default)
DZFM: Data Zero Detect Mode
0: Channel Separated Mode (default)
1: Channel ANDed Mode
If the DZFM bit is set to “1”, the DZF pins of both L and R channels go to “H” only when the
input data at both channels are continuously zeros for 8192 LRCK cycles.
DZFE: Data Zero Detect Enable
0: Disable (default)
1: Enable
Zero detect function can be disabled by DZFE bit “0”. In this case, the DZF pins of both
channels are always “L”.
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Addr
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
02H
Control 3
DP
0
DCKS
DCKB
MONO
DZFB
SELLR
SLOW
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
SLOW: Slow Roll-off Filter Enable. (Table 28)
0: Slow roll-off filter disable (default)
1: Slow roll-off filter
SELLR: The data selection of L channel and R channel, when MONO mode
0: All channel output L channel data, when MONO mode. (default)
L channel output L channel data, Rchannel data output Rchannel data(default)
1: All channel output R channel data, when MONO mode.
L channel output R channel data, Rchannel data output Lchannel data
DZFB: Inverting Enable of DZF. (Table 35)
0: DZF pin goes “H” at Zero Detection (default)
1: DZF pin goes “L” at Zero Detection
MONO: MONO mode Stereo mode select
0: Stereo mode (default)
1: MONO mode
DCKB: Polarity of DCLK (DSD Only)
0: DSD data is output from DCLK falling edge. (default)
1: DSD data is output from DCLK rising edge.
DCKS: Master Clock Frequency Select at DSD mode (DSD only)
0: 512fs (default)
1: 768fs
DP: DSD/PCM Mode Select
0: PCM Mode (default)
1: DSD Mode
When DP bit is changed, the AK4497 should be reset by RSTN bit.
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Addr
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
03H
Lch ATT
ATT7
ATT6
ATT5
ATT4
ATT3
ATT2
ATT1
ATT0
04H
Rch ATT
ATT7
ATT6
ATT5
ATT4
ATT3
ATT2
ATT1
ATT0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
1
1
1
1
1
1
1
1
ATT[7:0]: Attenuation Level
255 levels 0.5dB step + mute
Data Attenuation
FFH 0dB (default)
FEH -0.5dB
FDH -1.0dB
: :
: :
02H -126.5dB
01H -127.0dB
00H MUTE (-)
Addr
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
05H
Control 4
INVL
INVR
0
0
0
0
DFS2
SSLOW
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
SSLOW: Super Slow Roll Off (Digital Filter bypass mode) Enable. (Table 28)
0: Disable (default)
1: Enable
DFS2: Sampling Speed Control. (Table 11)
INVR: AOUTR Output Phase Inverting
0: Disable (default)
1: Enable
INVL: AOUTL Output Phase Inverting
0: Disable (default)
1: Enable
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Addr
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
06H
DSD1
DDM
DML
DMR
DMC
DMRE
0
DSDD
DSDSEL0
R/W
R/W
R
R
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
DSDSEL[1:0]: DSD Sampling Speed Control
Table 21. DSD Data Stream Select
DSDSEL1
DSDSEL0
DSD Data Stream
fs=32kHz
fs=44.1kHz
fs=48kHz
0
0
2.048MHz
2.8224MHz
3.072MHz
(default)
0
1
4.096MHz
5.6448MHz
6.144MHz
1
0
8.192MHz
11.2896MHz
12.288MHz
1
1
16.284MHz
22.5792MHz
24.576MHz
DSDD: DSD Play back path control
Table 22. DSD Playback Path Select
DSDD
Mode
0
Normal Path
(default)
1
Volume Bypass
DMRE: DSD Mute Release
0: Hold (default)
1: Mute Release
This register is only valid when DDM bit = “1” and DMC bit = “1”. When the AK4497 mutes
DSD data by DDM and DMC bits settings, the mute is released by setting DMRE bit to “1”.
Table 41. Recovery Method to Normal Operation Mode from Full Scale Detection Status
DDM
DMC
DMRE
Status After Detection
0
*
*
When full scale is detected, Mute function is disabled.
(default)
1
0
*
When full scale is detected, Mute function is enabled.
The AK4497 returns to normal operation automatically
by a normal signal input.
1
1
0
When full scale is detected, Mute function is enabled.
The AK4497 keeps mute mode, even if a normal signal is
input.
1
1
1
(Note 50)
When full scale is detected, Mute function is enabled.
The AK4497 returns to normal operation when a normal
signal is input and DMRE bit is set to “1”.
Note 50. DMRE bit returns to “0” automatically after the AK4497 returns to normal operation.
DMC: DSD Mute Control
0: Auto Return (default)
1: Mute Hold (manual return)
This register is only valid when DDM bit = “1”. It selects the mute releasing mode of when the
DSD data level becomes under full-scale after the AK4497 mutes DSD data by DDM bit
setting.
DMR/DML This register outputs detection flag when a full scale signal is detected at DSDR/L channel.
(only in I2C mode)
DDM: DSD Data Mute
0: Disable (default)
1: Enable
The AK4497 has an internal mute function that mutes the output when DSD audio data
becomes all “1” or all “0” for 2048 Samples (DCLK cycle). DDM bit controls this function.
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Addr
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
07H
Control 5
0
0
0
0
GC2
GC1
GC0
SYNCE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
1
SYNCE: SYNC Mode Enable
0: SYNC Mode Disable
1: SYNC Mode Enable (default)
GC[2:0]: PCM, DSD mode Gain Control
Table 33. Output Level between Set Values of GC[2:0] Bit
GC[2]
bit
GC[1]
bit
GC[0]
bit
AOUTLP/LN/RP/RN Ouput Level
PCM
DSD:
Normal Path
DSD:
Volume Bypass
0
0
0
2.8 Vpp
2.8 Vpp
2.5 Vpp
(default)
0
0
1
2.8 Vpp
2.5 Vpp
2.5 Vpp
0
1
0
2.5 Vpp
2.5 Vpp
2.5 Vpp
0
1
1
2.5 Vpp
2.5 Vpp
2.5 Vpp
1
0
0
3.75 Vpp
3.75 Vpp
2.5 Vpp
1
0
1
3.75 Vpp
2.5 Vpp
2.5 Vpp
1
1
0
2.5 Vpp
2.5 Vpp
2.5 Vpp
1
1
1
2.5 Vpp
2.5 Vpp
2.5 Vpp
Addr
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
08H
Sound Control
0
0
0
0
HLOAD
SC2
SC1
SC0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
SC[2:0]: Sound Control.
Table 38. Sound Quality Select Mode
SC1 bit
SC0 bit
Internal Operation
0
0
Analog internal current, maximum (Setting1)
(default)
0
1
Analog internal current, minimum (Setting2)
1
0
Analog internal current, medium (Setting3)
1
1
Analog internal current, minimum (Setting2)
Table 39. Sound Quality Select Mode
SC2 bit
Sound
0
Default (Setting 4)
(default)
1
High Sound Quality Mode (Setting 5)
HLOAD: Heavy Load Mode Enable
0: Heavy Load Mode Disable (default)
1: Heavy Load Mode Enable
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Addr
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
09H
DSD2
0
0
0
0
0
DSDPATH
DSDF
DSDSEL1
R/W
R
R
R
R
R
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
DSDSEL1: DSD Sampling Speed Control.
Table 21. DSD Data Stream Select
DSDSEL1
DSDSEL0
DSD data stream
fs=32kHz
fs=44.1kHz
fs=48kHz
0
0
2.048MHz
2.8224MHz
3.072MHz
(default)
0
1
4.096MHz
5.6448MHz
6.144MHz
1
0
8.192MHz
11.2896MHz
12.288MHz
1
1
16.284MHz
22.5792MHz
24.576MHz
DSDF: Cut-off frequency of DSD Filter Control
Table 29. DSD Filter Select
DSDF bit
Cut Off Frequency @fs=44.1kHz
DSD64fs
DSD128fs
DSD256fs
DSD512fs
0
39kHz
78kHz
156kHz
312kHz
(default)
1
76kHz
152kHz
304kHz
608kHz
DSDPATH: DSD Data Input Pin Select
0: #16, 17, 19 (default)
1: #3, 4, 5 Table 4. PCM/DSD/EXDF Mode Control
DP bit
EXDF bit
DSDPATH
bit
D/A Conv.
Mode
Pin Assignment
#3 pin
#4 pin
#5 pin
#16 pin
#17 pin
#19 pin
0
(default)
0
(default)
x
PCM
BICK
SDATA
LRCK
Not Use
Not Use
Not Use
1
x
0
(default)
DSD
Not Use
Not Use
Not Use
DSDL
DSDR
DCLK
1
x
1
DSD
DCLK
DSDL
DSDR
Not Use
Not Use
Not Use
0
1
*
EXDF
BCK
DINL
DINR
Not Use
Not Use
Not Use
(x: Do not care)
Addr
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
0AH
Control 7
TDM1
TDM0
SDS1
SDS2
0
PW
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
1
0
0
PW: Power ON/OFF Control
0: Power Off
1: Power On (default)
SDS[2:0]: Output Data Slot Selection of Each Channel
0: Normal Operation
1: Changing Data Slot (Table 25)
Default value is “000”
TDM[1:0]: TDM Mode Select
00: Normal (default)
01: TDM128
10: TDM256
11: TDM512
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Addr
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
0BH
Control 8
ATS1
ATS0
0
SDS0
0
0
DCHAIN
TEST
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
TEST: “0” data must be written to Test bit. Otherwise malfunctions may occur.
DCHAIN: Daisy Chain Mode Enable
0: Daisy Chain Mode Disable (default)
1: Daisy Chain Mode Enable
SDS[2:0]: Output Data Slot Selection of Each Channel
0: Normal Operation
1: Changing Data Slot (Table 25)
ATS[1:0]: Transition Time between Set Values of ATT[7:0] bits (Table 32)
Default value is “00”.
Addr
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
0CH
Reserved
0
0
0
0
0
0
0
0
0DH
Reserved
0
0
0
0
0
0
0
0
0EH
Reserved
0
0
0
0
0
0
0
0
0FH
Reserved
0
0
0
0
0
0
0
0
10H
Reserved
0
0
0
0
0
0
0
0
11H
Reserved
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
0CH: Reserved
0DH: Reserved
0EH: Reserved
0FH: Reserved
10H: Reserved
11H: Reserved
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Addr
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
12H
Reserved
0
0
0
0
0
0
0
0
13H
Reserved
0
0
0
0
0
0
0
0
14H
Reserved
0
0
0
0
0
0
0
0
R/W
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
12H: Reserved
13H: Reserved
14H: Reserved
Addr
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
15H
ADFS read
0
0
0
0
0
ADFS2
ADFS1
ADFS0
R/W
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
ADFS[2:0]: Mode Detection Result in FS Auto Detect Mode
ADFS2
bit
ADFS1
bit
ADFS0
bit
Mode
0
0
0
Normal Speed Mode
0
0
1
Double Speed Mode
0
1
0
Quad Speed Mode
0
1
1
Quad Speed Mode
1
0
0
Oct Speed Mode
1
0
1
Hex Speed Mode
1
1
0
Oct Speed Mode
1
1
1
Hex Speed Mode
[AK4497]
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10. Recommended External Circuits
Analog 5.0V
Digital 3.3V
+
0.1u
10u
0.1u
10u
DSP
+
0.1u
10u
PDN
DVDD
1
BICK/BCK
2
SDATA/DINL
3
LRCK/DINR
4
SSLOW/WCK
5
SMUTE/CSN
6
SD/CCLK/SCL
7
SLOW/CDTI/SDA
8
DIF0/DZFL
9
DIF1/DZFR
10
DIF2/CAD0
11
GAIN
/DSDR
AOUTLP
19
20
ACKS
/CAD1
TDM0/
DCLK
TDM1
DCHAIN
VREFHR
VREFHR
VREFLR
VREFLR
VCMR
AOUTRN
VDDL
VDDL
VSSL
VSSL
VSSR
N
VSSR
VDDR
VDDR
AOUTRP
DVSS
MCLK
AVSS
AVDD
VREFHL
VREFHL
VREFLL
VREFLL
VCML
0.1u
2200u
LDOE
24
INVR
AOUTRP
AOUTLP
EXTR
AOUTLN
12
PSN
VDDR
VSSR
N
VSSL
VDDL
VREFLL
VREFHL
AK4497
TVDD
TDMO
13
14
15
16
HLOAD/I2C
DEM0/DSDL
TESTE
21
22
23
17
18
VREFHR
VREFLR
AOUTRN
24
25
26
27
28
29
30
31
32
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
+
+
+
Micro-
Controller
33k
Ceramic Capacitor
+
Electrolytic Capacitor
Resistor
AOUTLN
Rch Out
Rch
LPF
Rch
Mute
Lch Out
Lch
LPF
Lch
Mute
1u
33
0.1u
2200u
+
+
+
0.1u
10u
0.1u
10u
+
+
Digital 1.8V
AVDD 3.3V
10u
10u
Notes: - Chip Address = “00”. BICK = 64fs, LRCK = fs
- Power lines of AVDD, TVDD, VDDL and VDDR should be distributed separately from the point
with low impedance of regulator etc.
- AVSS, DVSS, VSSL and VSSR must be connected to the same analog ground plane. (Analog
ground should has low impedance as a solid pattern. THD+N characteristics will degrade if there
are impedances between each VSS.)
- It is recommended to connect a damping resistor if THD+N characteristics degrade by high
frequency noise of MCLK.
- All input pins except pull-down/pull-up pins should not be allowed to float.
Figure 74. Typical Connection Diagram
(AVDD=TVDD=3.3V, VDDL/R=5.0V, LDOE= “L”, Pin Control Mode)
[AK4497]
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1. Grounding and Power Supply Decoupling
To minimize coupling by digital noise, decoupling capacitors should be connected to AVDD, TVDD, DVDD,
VDDL and VDDR. AVDD and VDDL/R are supplied from analog supply in system, and TVDD and DVDD
are supplied from digital supply in system. Power lines of VDDL/R should be distributed separately from
the point with low impedance of regulator etc. When not using LDO (LDOE pin = “L”), power supplies
should be powered up in the order of 3.3V power supplies (AVDD, TVDD) first, the 1.8V power supply
(DVDD) next and 5V power supplies (VDDL/R) last. When using LDO (LDOE pin = “H”), the internal LDO
outputs 1.8V. AVSS, DVSS, VSSL and VSSR must be connected to the same analog ground plane.
Decoupling capacitors for high frequency should be placed as near as possible to the supply pin.
2. Voltage Reference
The differential voltage between VREFHL/R and VREFLL/R sets the full scale of the analog output range.
The VREFHL/R pin is normally connected to the 5.0V reference voltage, and the VREFLL/R pin is normally
connected to the 0V reference voltage. VREFHL/R and VREFLL/R should be connected with a 0.1µF
ceramic capacitor and a 2200uF electrolytic capacitor as near as possible to the pin to eliminate the effects
of high frequency noise.
The VREFH and VREFL pins should be treated to not have noises from other supply pins. If the analog
characteristics cannot satisfy the specification by this noise, connect the VREFH to analog 5.0V via a 10 Ω
resistor and connect the VREFL pin to the analog ground via a 10 Ω resistor. (A low-pass filter of fc=500Hz
will be composed by a 2200uF capacitor and a 10Ω resistor. This low-pass filter removes signal frequency
noise from other power supply pins.)
VCML/R is a common voltage of this chip. No load current may be drawn from the VCML/R pin. All signals,
especially clocks, should be kept away from the VREFHL/R and VREFLL/R pins in order to avoid
unwanted noise coupling into the AK4497.
3. Analog Outputs
The analog outputs are full differential outputs. The differential outputs are summed externally, VAOUT =
(AOUT+) (AOUT) between AOUT+ and AOUT. If the summing gain is 1, the output range of the setting
the GAIN pin = “L” or GC[2] bit = “0” is 2.8Vpp (typ, VREFHL/R VREFLL/R = 5V) centered around VCML
and VCMR voltages. In this case, the output range after summing will be 5.6V (typ.). The output range of
the setting the GAIN pin = “H” or GC[2] bit = “1” is 3.75Vpp (typ.) centered around VCML and VCMR
voltages. In this case, the output range after summing will be 7.5Vpp (typ.). The bias voltage of the external
summing circuit is supplied externally.
The input data format is 2's complement. The output voltage (VAOUT) is a positive full scale for 7FFFFFFFH
(@32bit) and a negative full scale for 80000000H (@32bit). The ideal VAOUT is 0V for 00000000H (@32bit).
The internal switched-capacitor filters attenuate the noise generated by the delta-sigma modulator beyond
the audio passband. Figure 75 and Figure 76 show examples of external LPF circuit summing the
differential outputs by a single op-amp. Figure 77 shows an example of differential output circuit and
external LPF circuit with two op-amps. Figure 78 shows an example of external LPF circuit with two
op-amps when MONO bit = “1”. A resistor that has 0.1% or less absolute error must be used for external
LPFs.
300
300
30
100
10
100
+Vop
6.8n
-Vop
AOUT-
AOUT+
Analog
Out
20n
AK4497
43n
130n
OPA1611
6
2
3
4
7
Figure 75. External LPF Circuit Example 1 (fc = 98kHz(typ), Q=0.667(typ))
[AK4497]
016003187-E-00 2016/05
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Table 45. Frequency Response of External LPF Circuit Example 1
Gain(1kHz,typ)
0 dB
Frequency
Response
(ref:1kHz,typ)
20kHz
-0.07 dB
40kHz
-0.32 dB
80kHz
-2.13 dB
215
590
33
33.2
5.1
90.9
+Vop
3.09n
-Vop
AOUT-
AOUT+
Analog
Out
AK4497
OPA1611
39.2n
255n
20n
6
2
3
4
7
Figure 76. External LPF Circuit Example 2 (fc = 104kHz(typ), Q=0.693(typ))
Table 46. Frequency Response of External LPF Circuit Example 2
Gain(1kHz,typ)
+8.78 dB
Frequency
Response
(ref:1kHz,typ)
20kHz
-0.02 dB
40kHz
-0.15 dB
80kHz
-1.46 dB
22
100u
22
10k
56n
200
400
27n
1
4
3
2
8
10u
0.1u
0.1u
10u
OPA1612
22
100u
22
10k
56n
200
400
27n
7
4
5
6
8
10u
0.1u
0.1u
10u
OPA1612
LME49710
+
+
+
+
-
*
+
-
+
+
+
Lch
-15
+15
AOUT-
AOUT+
AK4497
Figure 77. External LPF Circuit Example 3 (fc = 186kHz(typ), Q=0.67(typ))
Table 47. Frequency Response of External LPF Circuit Example 3
Gain(1kHz,typ)
+9.54 dB
Frequency
Response
(ref:1kHz,typ)
20kHz
-0.01 dB
40kHz
-0.06 dB
80kHz
-0.32 dB
[AK4497]
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44
100u
22
10k
56n
200
400
27n
1
4
3
2
8
10u
0.1u
0.1u
10u
OPA1612
44
100u
22
10k
56n
200
400
27n
7
4
5
6
8
10u
0.1u
0.1u
10u
OPA1612
LME49710
+
+
+
+
-
*
+
-
+
+
+
-15
+15
AOUTLP
AOUTLN
AK4497
AOUTRP
AOUTRN
100u
10k
44
100u
10k
+
+
44
Figure 78. External LPF Circuit Example for mono mode (fc = 186kHz(typ), Q=0.67(typ))
[AK4497]
016003187-E-00 2016/05
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11. Package
■Outline Dimensions
(HTQFP10×10-64)
0.05 ~ 0.15 1.00 ± 0.05
1.2 MAX
S
0.10 S
0.22 ± 0.05
1
(5.95)
(5.95)
12.0 ± 0.20
12.0 ± 0.20
0.50
16
17 32
33
48
4964
10.0 ± 0.20
10.0 ± 0.20
0.60 ± 0.15
0.09 ~ 0.2
A
C
M
0.10 SA C
[AK4497]
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■ Material & Lead Finish
Package molding compound: Epoxy, Halogen (bromine and chlorine) free
Lead frame material: EFTEC64
Pin surface treatment: Solder (Pb free) plate
■ Marking
1) Pin #1 indication
2) AKM Logo
3) Date Code: XXXXXXX (7 digits)
4) Marking Code: AK4497EQ
5) Audio 4 pro Logo
AK4497EQ
XXXXXXX
AKM
1
64
[AK4497]
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12. Ordering Guide
■ Ordering Guide
AK4497EQ 40 +85C (Assuming the exposed pad is connected to the printing board)
64-pin TQFP (0.5mm pitch)
AKD4497 Evaluation Board for AK4497
13. Revision History
Date (Y/M/D)
Revision
Reason
Page
Contents
16/05/16
00
First Edition
[AK4497]
016003187-E-00 2016/05
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IMPORTANT NOTICE
0. Asahi Kasei Microdevices Corporation (“AKM”) reserves the right to make changes to the
information contained in this document without notice. When you consider any use or application
of AKM product stipulated in this document (“Product”), please make inquiries the sales office of
AKM or authorized distributors as to current status of the Products.
1. All information included in this document are provided only to illustrate the operation and
application examples of AKM Products. AKM neither makes warranties or representations with
respect to the accuracy or completeness of the information contained in this document nor grants
any license to any intellectual property rights or any other rights of AKM or any third party with
respect to the information in this document. You are fully responsible for use of such information
contained in this document in your product design or applications. AKM ASSUMES NO
LIABILITY FOR ANY LOSSES INCURRED BY YOU OR THIRD PARTIES ARISING FROM THE
USE OF SUCH INFORMATION IN YOUR PRODUCT DESIGN OR APPLICATIONS.
2. The Product is neither intended nor warranted for use in equipment or systems that require
extraordinarily high levels of quality and/or reliability and/or a malfunction or failure of which may
cause loss of human life, bodily injury, serious property damage or serious public impact,
including but not limited to, equipment used in nuclear facilities, equipment used in the aerospace
industry, medical equipment, equipment used for automobiles, trains, ships and other
transportation, traffic signaling equipment, equipment used to control combustions or explosions,
safety devices, elevators and escalators, devices related to electric power, and equipment used
in finance-related fields. Do not use Product for the above use unless specifically agreed by AKM
in writing.
3. Though AKM works continually to improve the Product’s quality and reliability, you are
responsible for complying with safety standards and for providing adequate designs and
safeguards for your hardware, software and systems which minimize risk and avoid situations in
which a malfunction or failure of the Product could cause loss of human life, bodily injury or
damage to property, including data loss or corruption.
4. Do not use or otherwise make available the Product or related technology or any information
contained in this document for any military purposes, including without limitation, for the design,
development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or
missile technology products (mass destruction weapons). When exporting the Products or related
technology or any information contained in this document, you should comply with the applicable
export control laws and regulations and follow the procedures required by such laws and
regulations. The Products and related technology may not be used for or incorporated into any
products or systems whose manufacture, use, or sale is prohibited under any applicable domestic
or foreign laws or regulations.
5. Please contact AKM sales representative for details as to environmental matters such as the
RoHS compatibility of the Product. Please use the Product in compliance with all applicable laws
and regulations that regulate the inclusion or use of controlled substances, including without
limitation, the EU RoHS Directive. AKM assumes no liability for damages or losses occurring as a
result of noncompliance with applicable laws and regulations.
6. Resale of the Product with provisions different from the statement and/or technical features set
forth in this document shall immediately void any warranty granted by AKM for the Product and
shall not create or extend in any manner whatsoever, any liability of AKM.
7. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior
written consent of AKM.
