®
Altera Corporation 595
MAX 7000A
Programmable Logic
Device Family
June 1999, ver. 2.01 Data Sheet
A-DS-M7000A-02.01
Includes
MAX 7000AE
Features...
■
High-performance CMOS EEPROM-based programmable logic
devices (PLDs) built on second-generation Multiple Array MatriX
(MAX
®
) architecture (see Table 1)
■
3.3-V in-system programmability (ISP) through the built-in
IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with
advanced pin-locking capability
Preliminary
Information
■
Built-in boundary-scan test (BST) circuitry compliant with
IEEE Std. 1149.1-1990
■
Enhanced ISP features
– Enhanced ISP algorithm for faster programming (excluding
EPM7128A and EPM7256A devices)
– ISP_Done bit to ensure complete programming (excluding
EPM7128A and EPM7256A devices)
– Pull-up resistor on I/O pins during in-system programming
■
Pin-compatible with the popular 5.0-V MAX 7000S devices
■
High-density PLDs ranging from 600 to 10,000 usable gates
■
4.5-ns pin-to-pin logic delays with counter frequencies of up to
192.3 MHz
f
For information on in-system programmable 5.0-V MAX 7000 or 2.5-V
MAX 7000B devices, see the
MAX 7000 Programmable Logic Device Family
Data Sheet
or the
MAX 7000B Programmable Logic Device Family Advance
Information Brief
.
Table 1. MAX 7000A Device Features
Feature EPM7032AE EPM7064AE EPM7128AE
EPM7128A
EPM7256AE
EPM7256A
EPM7512AE
Usable gates 600 1,250 2,500 5,000 10,000
Macrocells 32 64 128 256 512
Logic array blocks 2 4 8 16 32
Maximum user I/O
pins 36 68 100 164 212
t
PD
(ns) 4.5 4.5 5.0 6.0 7.5
t
SU
(ns) 3.0 3.0 3.2 3.7 4.9
t
FSU
(ns) 2.5 2.5 2.5 2.5 3.0
t
CO1
(ns) 2.8 2.8 3.0 3.3 4.5
f
CNT
(MHz) 192.3 192.3 181.8 156.3 119.0
596 Altera Corporation
MAX 7000A Programmable Logic Device Family Data Sheet Preliminary Information
...and More
Features
■
MultiVolt
TM
I/O interface enabling device core to run at 3.3 V, while
I/O pins are compatible with 5.0-V, 3.3-V, and 2.5-V logic levels
■
Pin counts ranging from 44 to 256 in a variety of thin quad flat pack
(TQFP), plastic quad flat pack (PQFP), ball-grid array (BGA), space-
saving FineLine BGA
TM
, and plastic J-lead chip carrier (PLCC)
packages
■
Supports hot-socketing in MAX 7000AE devices
■
Programmable interconnect array (PIA) continuous routing structure
for fast, predictable performance
■
Peripheral component interconnect (PCI) compatible
■
Bus friendly architecture including programmable slew-rate control
■
Open-drain output option
■
Programmable macrocell registers with individual clear, preset,
clock, and clock enable controls
■
Programmable power-up states for macrocell registers in
MAX 7000AE devices
■
Programmable power-saving mode for 50
%
or greater power
reduction in each macrocell
■
Configurable expander product-term distribution, allowing up to
32 product terms per macrocell
■
Programmable security bit for protection of proprietary designs
■
6 to 10 pin- or logic-driven output enable signals
■
Two global clock signals with optional inversion
■
Enhanced interconnect resources for improved routability
■
Fast input setup times provided by a dedicated path from I/O pin to
macrocell registers
■
Programmable output slew-rate control
■
Programmable ground pins
■
Software design support and automatic place-and-route provided by
Altera’s MAX+PLUS
®
II development system for Windows-based
PCs and Sun SPARCstation, HP 9000 Series 700/800, and IBM RISC
System/6000 workstations, and the Quartus
TM
development system
for Windows-based PCs and Sun SPARCstation and HP 9000
Series 700 workstations
■
Additional design entry and simulation support provided by EDIF
2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM),
Verilog HDL, VHDL, and other interfaces to popular EDA tools from
manufacturers such as Cadence, Exemplar Logic, Mentor Graphics,
OrCAD, Synopsys, Synplicity, and VeriBest
■
Programming support with Altera’s Master Programming Unit
(MPU), BitBlaster
TM
serial download cable, and ByteBlasterMV
TM
parallel port download cable, as well as programming hardware
from third-party manufacturers and any Jam
TM
File (
.jam
),
Jam Byte-Code File (
.jbc
), or Serial Vector Format File- (
.svf
) capable
in-circuit tester
Altera Corporation 597
MAX 7000A Programmable Logic Device Family Data Sheet
Preliminary Information
General
Description
MAX 7000A (including MAX 7000AE) devices are high-density, high-
performance devices based on Altera’s second-generation MAX
architecture. Fabricated with advanced CMOS technology, the EEPROM-
based MAX 7000A devices operate with a 3.3-V supply voltage and
provide 600 to 10,000 usable gates, ISP, pin-to-pin delays as fast as 4.5 ns,
and counter speeds of up to 192.3 MHz. MAX 7000A devices in the -5, -6,
-7, and -10 speed grades are compatible with the timing requirements of
the PCI Special Interest Group (PCI SIG)
PCI Local Bus Specification,
Revision 2.2
. See Table 2.
Notes:
(1) Contact Altera Applications for up-to-date information on available device speed
grades.
(2) Timing parameters for these speed grades are preliminary.
Table 2. MAX 7000A Speed Grades
Notes (1), (2)
Device Speed Grade
-4 -5 -6 -7 -10 -12
EPM7032AE
v v v
EPM7064AE
v v v
EPM7128A
EPM7128AE
vvvvv
EPM7256A
EPM7256AE
vvvvv
EPM7512AE
vvv
598 Altera Corporation
MAX 7000A Programmable Logic Device Family Data Sheet Preliminary Information
The MAX 7000A architecture supports 100
%
TTL emulation and high-
density integration of SSI, MSI, and LSI logic functions. It easily integrates
multiple devices ranging from PALs, GALs, and 22V10s to MACH, and
pLSI devices. MAX 7000A devices are available in a wide range of
packages, including PLCC, BGA, FineLine BGA, PQFP, and TQFP
packages. See Table 3.
Notes:
(1) Contact Altera for up-to-date information on available device package options.
(2) When the IEEE Std. 1149.1 (JTAG) interface is used for in-system programming or boundary-scan testing, four I/O
pins become JTAG pins.
(3) All FineLine BGA packages are footprint-compatible via the SameFrame feature. Therefore, designers can design a
board to support a variety of devices, providing a flexible migration path across densities and pin counts. Device
migration is fully supported by Altera development tools. See “SameFrame Pin-Outs” on page 608 for more details.
MAX 7000A devices use CMOS EEPROM cells to implement logic
functions. The user-configurable MAX 7000A architecture accommodates
a variety of independent combinatorial and sequential logic functions.
The devices can be reprogrammed for quick and efficient iterations
during design development and debug cycles, and can be programmed
and erased up to 100 times.
MAX 7000A devices contain from 32 to 512 macrocells that are combined
into groups of 16 macrocells, called logic array blocks (LABs). Each
macrocell has a programmable-
AND
/fixed-
OR
array and a configurable
register with independently programmable clock, clock enable, clear, and
preset functions. To build complex logic functions, each macrocell can be
supplemented with both shareable expander product terms and high-
speed parallel expander product terms to provide up to 32 product terms
per macrocell.
Table 3. MAX 7000A Maximum User I/O Pins
Notes (1), (2)
Device 44-Pin
PLCC
44-Pin
TQFP
84-Pin
PLCC
100-Pin
TQFP
100-Pin
FineLine
BGA
(3)
144-Pin
TQFP
208-Pin
PQFP
256-Pin
BGA
256-Pin
FineLine
BGA
(3)
EPM7032AE 36 36
EPM7064AE 36 36 68 68 68
EPM7128A 68 84 84 100 100
EPM7128AE 68 84 84 100 100
EPM7256A 84 120 164 164
EPM7256AE 84 84 120 164 164
EPM7512AE 120 176 212 212
Altera Corporation 599
MAX 7000A Programmable Logic Device Family Data Sheet
Preliminary Information
MAX 7000A devices provide programmable speed/power optimization.
Speed-critical portions of a design can run at high speed/full power,
while the remaining portions run at reduced speed/low power. This
speed/power optimization feature enables the designer to configure one
or more macrocells to operate at 50
%
or lower power while adding only a
nominal timing delay. MAX 7000A devices also provide an option that
reduces the slew rate of the output buffers, minimizing noise transients
when non-speed-critical signals are switching. The output drivers of all
MAX 7000A devices can be set for 2.5 V or 3.3 V and all input pins are
2.5-V, 3.3-V, and 5.0-V tolerant, allowing MAX 7000A devices to be used
in mixed-voltage systems.
MAX 7000A devices are supported by the Quartus and MAX+PLUS II
development systems, which are integrated packages that offer
schematic, text—including VHDL, Verilog HDL, and the Altera
Hardware Description Language (AHDL)—and waveform design entry,
compilation and logic synthesis, simulation and timing analysis, and
device programming. The Quartus and MAX+PLUS II software provides
EDIF 2 0 0 and 3 0 0, LPM, VHDL, Verilog HDL, and other interfaces for
additional design entry and simulation support from other industry-
standard PC- and UNIX-workstation-based EDA tools. The
MAX+PLUS II software runs on Windows-based PCs, as well as Sun
SPARCstation, HP 9000 Series 700/800, and IBM RISC System/6000
workstations. The Quartus software runs on Windows-based PCs, as well
as Sun SPARCstation and HP 9000 Series 700 workstations.
f
For more information on development tools, see the
MAX+PLUS II
Programmable Logic Development System & Software Data Sheet
and the
Quartus Programmable Logic Development System Data Sheet
.
Functional
Description
The MAX 7000A architecture includes the following elements:
■
Logic array blocks (LABs)
■
Macrocells
■
Expander product terms (shareable and parallel)
■
Programmable interconnect array
■
I/O control blocks
The MAX 7000A architecture includes four dedicated inputs that can be
used as general-purpose inputs or as high-speed, global control signals
(clock, clear, and two output enable signals) for each macrocell and I/O
pin. Figure 1 shows the architecture of MAX 7000A devices.
600 Altera Corporation
MAX 7000A Programmable Logic Device Family Data Sheet Preliminary Information
Figure 1. MAX 7000A Device Block Diagram
Note:
(1) EPM7032AE, EPM7064AE, EPM7128A, EPM7128AE, EPM7256A, and EPM7256AE devices have six output enables.
EPM7512AE devices have 10 output enables.
Logic Array Blocks
The MAX 7000A device architecture is based on the linking of
high-performance LABs. LABs consist of 16-macrocell arrays, as shown in
Figure 1. Multiple LABs are linked together via the PIA, a global bus that
is fed by all dedicated input pins, I/O pins, and macrocells.
Each LAB is fed by the following signals:
■
36 signals from the PIA that are used for general logic inputs
■
Global controls that are used for secondary register functions
■
Direct input paths from I/O pins to the registers that are used for fast
setup times
6
6
INPUT/GCLRn
6 or 10 Output Enables
(1)
6 or 10 Output Enables
(1)
16
36 36
16
I/O
Control
Block
LAB C LAB D
I/O
Control
Block
6
16
36 36
16
I/O
Control
Block
LAB A
Macrocells
1 to 16
LAB B
I/O
Control
Block
6
PIA
INPUT/GCLK1
INPUT/OE2/GCLK2
INPUT/OE1
3 to 16 I/O
3 to 16 I/O
3 to 16 I/O
3 to 16 I/O
3 to 16
3 to 16
3 to 16
3 to 16
3 to 16
3 to 16
3 to 16
3 to 16
3 to 163 to 16
3 to 163 to 16
Macrocells
17 to 32
Macrocells
33 to 48 Macrocells
49 to 64
Altera Corporation 601
MAX 7000A Programmable Logic Device Family Data Sheet
Preliminary Information
Macrocells
The MAX 7000A macrocell can be individually configured for either
sequential or combinatorial logic operation. The macrocell consists of
three functional blocks: the logic array, the product-term select matrix,
and the programmable register. Figure 2 shows the MAX 7000A
macrocell.
Figure 2. MAX 7000A Macrocell
Combinatorial logic is implemented in the logic array, which provides
five product terms per macrocell. The product-term select matrix allocates
these product terms for use as either primary logic inputs (to the
OR
and
XOR
gates) to implement combinatorial functions, or as secondary inputs
to the macrocell’s register preset, clock, and clock enable control
functions.
Two kinds of expander product terms (“expanders”) are available to
supplement macrocell logic resources:
■
Shareable expanders, which are inverted product terms that are fed
back into the logic array
■
Parallel expanders, which are product terms borrowed from adjacent
macrocells
Product-
Term
Select
Matrix
36 Signals
from PIA 16 Expander
Product Terms
LAB Local Array
Par allel Logic
Expanders
(from other
macrocells)
Shared Logic
Expanders
Clear
Select
Global
Clear Global
Clocks
Clock/
Enable
Select
2
PRN
CLRN
D Q
ENA
,,
,,
,,
Register
Bypass To I/O
Control
Block
,,,
,,,
,,
,,
,,
,,
,,
,,
F rom
I/O pin
To PIA
Programmable
Register
Fast Input
Select
VCC
602 Altera Corporation
MAX 7000A Programmable Logic Device Family Data Sheet Preliminary Information
The MAX+PLUS II development system automatically optimizes
product-term allocation according to the logic requirements of the design.
For registered functions, each macrocell flipflop can be individually
programmed to implement D, T, JK, or SR operation with programmable
clock control. The flipflop can be bypassed for combinatorial operation.
During design entry, the designer specifies the desired flipflop type; the
MAX+PLUS II software then selects the most efficient flipflop operation
for each registered function to optimize resource utilization.
Each programmable register can be clocked in three different modes:
■
Global clock signal. This mode achieves the fastest clock-to-output
performance.
■
Global clock signal enabled by an active-high clock enable. A clock
enable is generated by a product term. This mode provides an enable
on each flipflop while still achieving the fast clock-to-output
performance of the global clock.
■
Array clock implemented with a product term. In this mode, the
flipflop can be clocked by signals from buried macrocells or I/O pins.
Two global clock signals are available in MAX 7000A devices. As shown
in Figure 1, these global clock signals can be the true or the complement
of either of the global clock pins,
GCLK1
or
GCLK2
.
Each register also supports asynchronous preset and clear functions. As
shown in Figure 2, the product-term select matrix allocates product terms
to control these operations. Although the product-term-driven preset and
clear from the register are active high, active-low control can be obtained
by inverting the signal within the logic array. In addition, each register
clear function can be individually driven by the active-low dedicated
global clear pin (
GCLRn
). Upon power-up, each register in a MAX 7000AE
device may be set to either a high or low state. This power-up state is
specified at design entry.
All MAX 7000A I/O pins have a fast input path to a macrocell register.
This dedicated path allows a signal to bypass the PIA and combinatorial
logic and be clocked to an input D flipflop with an extremely fast (as low
as 2.5 ns) input setup time.
Altera Corporation 603
MAX 7000A Programmable Logic Device Family Data Sheet
Preliminary Information
Expander Product Terms
Although most logic functions can be implemented with the five product
terms available in each macrocell, more complex logic functions require
additional product terms. Another macrocell can be used to supply the
required logic resources. However, the MAX 7000A architecture also
offers both shareable and parallel expander product terms (“expanders”)
that provide additional product terms directly to any macrocell in the
same LAB. These expanders help ensure that logic is synthesized with the
fewest possible logic resources to obtain the fastest possible speed.
Shareable Expanders
Each LAB has 16 shareable expanders that can be viewed as a pool of
uncommitted single product terms (one from each macrocell) with
inverted outputs that feed back into the logic array. Each shareable
expander can be used and shared by any or all macrocells in the LAB to
build complex logic functions. A small delay (tSEXP) is incurred when
shareable expanders are used. Figure 3 shows how shareable expanders
can feed multiple macrocells.
Figure 3. MAX 7000A Shareable Expanders
Shareable expanders can be shared by any or all macrocells in an LAB.
Macrocell
Product-Term
Logic
Product-Term Select Matrix
Macrocell
Product-Term
Logic
36 Signals
from PIA 16 Shared
Expanders
604 Altera Corporation
MAX 7000A Programmable Logic Device Family Data Sheet Preliminary Information
Parallel Expanders
Parallel expanders are unused product terms that can be allocated to a
neighboring macrocell to implement fast, complex logic functions.
Parallel expanders allow up to 20 product terms to directly feed the
macrocell OR logic, with five product terms provided by the macrocell and
15 parallel expanders provided by neighboring macrocells in the LAB.
The MAX+PLUS II Compiler can allocate up to three sets of up to
five parallel expanders automatically to the macrocells that require
additional product terms. Each set of five parallel expanders incurs a
small, incremental timing delay (tPEXP). For example, if a macrocell
requires 14 product terms, the Compiler uses the five dedicated product
terms within the macrocell and allocates two sets of parallel expanders;
the first set includes five product terms and the second set includes
four product terms, increasing the total delay by 2 × tPEXP.
Two groups of eight macrocells within each LAB (e.g., macrocells 1
through 8 and 9 through 16) form two chains to lend or borrow parallel
expanders. A macrocell borrows parallel expanders from lower-
numbered macrocells. For example, macrocell 8 can borrow parallel
expanders from macrocell 7, from macrocells 7 and 6, or from macrocells
7, 6, and 5. Within each group of eight, the lowest-numbered macrocell
can only lend parallel expanders and the highest-numbered macrocell can
only borrow them. Figure 4 shows how parallel expanders can be
borrowed from a neighboring macrocell.
Altera Corporation 605
MAX 7000A Programmable Logic Device Family Data Sheet
Preliminary Information
Figure 4. MAX 7000A Parallel Expanders
Unused product terms in a macrocell can be allocated to a neighboring macrocell.
Programmable Interconnect Array
Logic is routed between LABs on the PIA. This global bus is a
programmable path that connects any signal source to any destination on
the device. All MAX 7000A dedicated inputs, I/O pins, and macrocell
outputs feed the PIA, which makes the signals available throughout the
entire device. Only the signals required by each LAB are actually routed
from the PIA into the LAB. Figure 5 shows how the PIA signals are routed
into the LAB. An EEPROM cell controls one input to a 2-input AND gate,
which selects a PIA signal to drive into the LAB.
Preset
Clock
Clear
Product-
Term
Select
Matrix
Preset
Clock
Clear
Product-
Term
Select
Matrix
Macrocell
Product-
Term Logic
From
Previous
Macrocell
To Next
Macrocell
Macrocell
Product-
Term Logic
36 Signals
from PIA 16 Shared
Expanders
606 Altera Corporation
MAX 7000A Programmable Logic Device Family Data Sheet Preliminary Information
Figure 5. MAX 7000A PIA Routing
While the routing delays of channel-based routing schemes in masked or
field-programmable gate arrays (FPGAs) are cumulative, variable, and
path-dependent, the MAX 7000A PIA has a predictable delay. The PIA
makes a design’s timing performance easy to predict.
I/O Control Blocks
The I/O control block allows each I/O pin to be individually configured
for input, output, or bidirectional operation. All I/O pins have a tri-state
buffer that is individually controlled by one of the global output enable
signals or directly connected to ground or VCC. Figure 6 shows the I/O
control block for MAX 7000A devices. The I/O control block has 6 or
10 global output enable signals that are driven by the true or complement
of two output enable signals, a subset of the I/O pins, or a subset of the
I/O macrocells.
To LAB
PIA Signals
Altera Corporation 607
MAX 7000A Programmable Logic Device Family Data Sheet
Preliminary Information
Figure 6. I/O Control Block of MAX 7000A Devices
When the tri-state buffer control is connected to ground, the output is
tri-stated (high impedance) and the I/O pin can be used as a dedicated
input. When the tri-state buffer control is connected to VCC, the output is
enabled.
The MAX 7000A architecture provides dual I/O feedback, in which
macrocell and pin feedbacks are independent. When an I/O pin is
configured as an input, the associated macrocell can be used for buried
logic.
From
Macrocell
Fast Input to
Macrocell
Register
Slew-Rate Control
To PIA
To Other I/O Pins
6 or 10 Global
Output Enable Signals (1)
PIA
VCC
Open-Drain Output
OE Select Multiplexer
GND
Note:
(1) EPM7032AE, EPM7064AE, EPM7128A, EPM7128AE, EPM7256A, and EPM7256AE devices have six output enable
signals. EPM7512AE devices have 10 output enable signals.
608 Altera Corporation
MAX 7000A Programmable Logic Device Family Data Sheet Preliminary Information
SameFrame
Pin-Outs
MAX 7000A devices support the SameFrame pin-out feature for
FineLine BGA packages. The SameFrame pin-out feature is the
arrangement of balls on FineLine BGA packages such that the lower-ball-
count packages form a subset of the higher-ball-count packages.
SameFrame pin-outs provide the flexibility to migrate not only from
device to device within the same package, but also from one package to
another. A given printed circuit board (PCB) layout can support multiple
device density/package combinations. For example, a single board layout
can support a range of devices from an EPM7128A device in a 256-pin
FineLine BGA package to an EPM7512AE device in a 256-pin
FineLine BGA package.
The Quartus and MAX+PLUS II software provides support to design
PCBs with SameFrame pin-out devices. Devices can be defined for present
and future use. The Quartus and MAX+PLUS II software generates
pin-outs describing how to lay out a board to take advantage of this
migration (see Figure 7).
Figure 7. SameFrame Pin-Out Example
Designed for 256-PinFineLine BGA Package
Printed Circuit Board
100-Pin FineLine BGA Package
(Reduced I/O Count or
Logic Requirements)
256-Pin FineLine BGA Package
(Increased I/O Count or
Logic Requirements)
100-Pin
FineLine
BGA
256-Pin
FineLine
BGA
Altera Corporation 609
MAX 7000A Programmable Logic Device Family Data Sheet
Preliminary Information
In-System
Programma-
bility (ISP)
MAX 7000A devices can be programmed in-system via an industry-
standard 4-pin IEEE Std. 1149.1-1990 (JTAG) interface. ISP offers quick,
efficient iterations during design development and debugging cycles. The
MAX 7000A architecture internally generates the high programming
voltages required to program EEPROM cells, allowing in-system
programming with only a single 3.3-V power supply. During in-system
programming, the I/O pins are tri-stated and weakly pulled-up to
eliminate board conflicts. The pull-up value is nominally 50 kΩ.
MAX 7000AE devices have an enhanced ISP algorithm for faster
programming. These devices also offer an ISP_Done bit that provides safe
operation when in-system programming is interrupted. This ISP_Done
bit, which is the last bit programmed, prevents all I/O pins from driving
until the bit is programmed. This feature is available in EPM7032AE,
EPM7064AE, EPM7128AE, EPM7256AE, and EPM7512AE devices only.
ISP simplifies the manufacturing flow by allowing devices to be mounted
on a printed circuit board (PCB) with standard pick-and-place equipment
before they are programmed. MAX 7000A devices can be programmed by
downloading the information via in-circuit testers, embedded processors,
the Altera BitBlaster serial download cable, and the ByteBlasterMV
parallel port download cable. Programming the devices after they are
placed on the board eliminates lead damage on high-pin-count packages
(e.g., QFP packages) due to device handling. MAX 7000A devices can be
reprogrammed after a system has already shipped to the field. For
example, product upgrades can be performed in the field via software or
modem.
In-system programming can be accomplished with either an adaptive or
constant algorithm. An adaptive algorithm reads information from the
unit and adapts subsequent programming steps to achieve the fastest
possible programming time for that unit. Because some in-circuit testers
cannot support an adaptive algorithm, Altera offers devices tested with a
constant algorithm. Devices tested to the constant algorithm contain an
“F” suffix in the ordering code and are marked with an “F” on the bottom
right-hand corner of the device.
The Jam programming and test language can be used to program
MAX 7000A devices with in-circuit testers, PCs, or embedded processors.
fFor more information on using the Jam language, see Application Note 88
(Using the Jam Language for ISP & ICR via an Embedded Processor).
610 Altera Corporation
MAX 7000A Programmable Logic Device Family Data Sheet Preliminary Information
Programming
with External
Hardware
MAX 7000A devices can be programmed on Windows-based PCs with an
Altera Logic Programmer card, the MPU, and the appropriate device
adapter. The MPU performs continuity checking to ensure adequate
electrical contact between the adapter and the device. For more
information, see the Altera Programming Hardware Data Sheet.
The MAX+PLUS II software can use text- or waveform-format test vectors
created with the MAX+PLUS II Text Editor or Waveform Editor to test the
programmed device. For added design verification, designers can
perform functional testing to compare the functional device behavior with
the results of simulation.
Data I/O, BP Microsystems, and other programming hardware
manufacturers provide programming support for Altera devices. For
more information, see Programming Hardware Manufacturers.
IEEE Std.
1149.1 (JTAG)
Boundary-Scan
Support
MAX 7000A devices include the JTAG BST circuitry defined by IEEE Std.
1149.1-1990. Table 4 describes the JTAG instructions supported by
MAX 7000A devices. The pin-out tables starting on page 634 of this data
sheet show the location of the JTAG control pins for each device. If the
JTAG interface is not required, the JTAG pins are available as user I/O
pins.
Table 4. MAX 7000A JTAG Instructions
JTAG Instruction Description
SAMPLE/PRELOAD Allows a snapshot of signals at the device pins to be captured and examined during
normal device operation, and permits an initial data pattern output at the device pins.
EXTEST Allows the external circuitry and board-level interconnections to be tested by forcing a
test pattern at the output pins and capturing test results at the input pins.
BYPASS Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST
data to pass synchronously through a selected device to adjacent devices during normal
device operation.
IDCODE Selects the IDCODE register and places it between the TDI and TDO pins, allowing the
IDCODE to be serially shifted out of TDO.
USERCODE Selects the 32-bit USERCODE register and places it between the TDI and TDO pins,
allowing the USERCODE value to be shifted out of TDO. USERCODE instructions are
available for MAX 7000AE devices only.
UESCODE These instructions select the user electronic signature (UESCODE) and allow the
UESCODE to be shifted out of TDO. UESCODE instructions are available for EPM7128A
and EPM7256A devices only.
ISP Instructions These instructions are used when programming MAX 7000A devices via the JTAG ports
with the BitBlaster, ByteBlaster, or ByteBlasterMV download cable, or using a Jam File
(.jam), Jam Byte-Code File (.jbc), or Serial Vector Format File (.svf) via an embedded
processor or test equipment.
Altera Corporation 611
MAX 7000A Programmable Logic Device Family Data Sheet
Preliminary Information
The instruction register length of MAX 7000A devices is 10 bits. The UES
register length in MAX 7000A devices is 16 bits. The MAX 7000AE
USERCODE register length is 32 bits. Tables 5 and 6 show the boundary-
scan register length and device IDCODE information for MAX 7000A
devices.
Notes to tables:
(1) The most significant bit (MSB) is on the left.
(2) The least significant bit (LSB) for all JTAG IDCODEs is 1.
fSee Application Note 39 (IEEE 1149.1 (JTAG) Boundary-Scan Testing in Altera
Devices) for more information on JTAG BST.
Table 5. MAX 7000A Boundary-Scan Register Length
Device Boundary-Scan Register Length
EPM7032AE 96
EPM7064AE 192
EPM7128A 288
EPM7128AE 288
EPM7256A 480
EPM7256AE 480
EPM7512AE 624
Table 6. 32-Bit MAX 7000A Device IDCODE Note (1)
Device IDCODE (32 bits)
Version
(4 Bits)
Part Number (16 Bits) Manufacturer’s
Identity (11 Bits)
1 (1 Bit)
(2)
EPM7032AE 0001 0111 0000 0011 0010 00001101110 1
EPM7064AE 0001 0111 0000 0110 0100 00001101110 1
EPM7128A 0000 0111 0001 0010 1000 00001101110 1
EPM7128AE 0001 0111 0001 0010 1000 00001101110 1
EPM7256A 0000 0111 0010 0101 0110 00001101110 1
EPM7256AE 0001 0111 0010 0101 0110 00001101110 1
EPM7512AE 0001 0111 0101 0001 0010 00001101110 1
612 Altera Corporation
MAX 7000A Programmable Logic Device Family Data Sheet Preliminary Information
Figure 8 shows the timing information for the JTAG signals.
Figure 8. MAX 7000A JTAG Waveforms
Table 7 shows the JTAG timing parameters and values for MAX 7000A
devices.
Table 7. JTAG Timing Parameters & Values for MAX 7000A Devices
Symbol Parameter Min Max Unit
tJCP TCK clock period 100 ns
tJCH TCK clock high time 50 ns
tJCL TCK clock low time 50 ns
tJPSU JTAG port setup time 20 ns
tJPH JTAG port hold time 45 ns
tJPCO JTAG port clock to output 25 ns
tJPZX JTAG port high impedance to valid output 25 ns
tJPXZ JTAG port valid output to high impedance 25 ns
tJSSU Capture register setup time 20 ns
tJSH Capture register hold time 45 ns
tJSCO Update register clock to output 25 ns
tJSZX Update register high impedance to valid output 25 ns
tJSXZ Update register valid output to high impedance 25 ns
TDO
TCK
tJPZX tJPCO
tJPH
tJPXZ
tJCP tJPSU
tJCL
tJCH
TDI
TMS
Signal
to Be
Captured
Signal
to Be
Driven
tJSZX
tJSSU tJSH
tJSCO tJSXZ
Altera Corporation 613
MAX 7000A Programmable Logic Device Family Data Sheet
Preliminary Information
Programmable
Speed/Power
Control
MAX 7000A devices offer a power-saving mode that supports low-power
operation across user-defined signal paths or the entire device. This
feature allows total power dissipation to be reduced by 50% or more,
because most logic applications require only a small fraction of all gates to
operate at maximum frequency.
The designer can program each individual macrocell in a MAX 7000A
device for either high-speed or low-power operation. As a result, speed-
critical paths in the design can run at high speed, while the remaining
paths can operate at reduced power. Macrocells that run at low power
incur a nominal timing delay adder (tLPA) for the tLAD, tLAC, tIC, tACL, tEN,
and tSEXP parameters.
Output
Configuration
MAX 7000A device outputs can be programmed to meet a variety of
system-level requirements.
MultiVolt I/O Interface
The MAX 7000A device architecture supports the MultiVolt I/O interface
feature, which allows MAX 7000A devices to connect to systems with
differing supply voltages. MAX 7000A devices in all packages can be set
for 2.5-V, 3.3-V, or 5.0-V I/O pin operation. These devices have one set of
VCC pins for internal operation and input buffers (VCCINT), and another
set for I/O output drivers (VCCIO).
The VCCIO pins can be connected to either a 3.3-V or 2.5-V power supply,
depending on the output requirements. When the VCCIO pins are
connected to a 2.5-V power supply, the output levels are compatible with
2.5-V systems. When the VCCIO pins are connected to a 3.3-V power
supply, the output high is at 3.3 V and is therefore compatible with 3.3-V
or 5.0-V systems. Devices operating with VCCIO levels lower than 3.0 V
incur a nominally greater timing delay of tOD2 instead of tOD1. Inputs can
always be driven by 2.5-V, 3.3-V, or 5.0-V signals.
Table 8 describes the MAX 7000A MultiVolt I/O support.
Table 8. MAX 7000A MultiVolt I/O Support
VCCIO Voltage Input Signal (V) Output Signal (V)
2.5 3.3 5.0 2.5 3.3 5.0
2.5 vvvv
3.3 vvv vv
614 Altera Corporation
MAX 7000A Programmable Logic Device Family Data Sheet Preliminary Information
Open-Drain Output Option
MAX 7000A devices provide an optional open-drain (equivalent to
open-collector) output for each I/O pin. This open-drain output enables
the device to provide system-level control signals (e.g., interrupt and
write enable signals) that can be asserted by any of several devices. It can
also provide an additional wired-OR plane.
Open-drain output pins on MAX 7000A devices (with a pull-up resistor to
the 5.0-V supply) can drive 5.0-V CMOS input pins that require a VIH of
3.5 V. When the open-drain pin is active, it will drive low. When the pin
is inactive, the trace will be pulled up to 5.0 V by the resistor. The open-
drain pin will only drive low or tri-state; it will never drive high. The rise
time is dependent on the value of the pull-up resistor and load
impedance. The IOL current specification should be considered when
selecting a pull-up resistor.
Programmable Ground Pins
Each unused I/O pin on MAX 7000A devices may be used as an
additional ground pin. In EPM7128A and EPM7256A devices, utilizing
unused I/O pins as additional ground pins requires using the associated
macrocell. In MAX 7000AE devices, this programmable ground feature
does not require the use of the associated macrocell; therefore, the buried
macrocell is still available for user logic.
Slew-Rate Control
The output buffer for each MAX 7000A I/O pin has an adjustable output
slew rate that can be configured for low-noise or high-speed performance.
A faster slew rate provides high-speed transitions for high-performance
systems. However, these fast transitions may introduce noise transients
into the system. A slow slew rate reduces system noise, but adds a
nominal delay of 4 to 5 ns. When the configuration cell is turned off, the
slew rate is set for low-noise performance. Each I/O pin has an individual
EEPROM bit that controls the slew rate, allowing designers to specify the
slew rate on a pin-by-pin basis. The slew rate control affects both the
rising and falling edges of the output signal.
Altera Corporation 615
MAX 7000A Programmable Logic Device Family Data Sheet
Preliminary Information
Power
Sequencing &
Hot-Socketing
Because MAX 7000A family devices can be used in a mixed-voltage
environment, they have been designed specifically to tolerate any possible
power-up sequence. The VCCIO and VCCINT power planes can be powered
in any order.
Signals can be driven into MAX 7000A devices before and during power
up without damaging the device. Additionally, MAX 7000A devices do
not drive out during power up. Once operating conditions are reached,
MAX 7000A devices operate as specified by the user.
Design Security All MAX 7000A devices contain a programmable security bit that controls
access to the data programmed into the device. When this bit is
programmed, a design implemented in the device cannot be copied or
retrieved. This feature provides a high level of design security, because
programmed data within EEPROM cells is invisible. The security bit that
controls this function, as well as all other programmed data, is reset only
when the device is reprogrammed.
Generic Testing MAX 7000A devices are fully functionally tested. Complete testing of
each programmable EEPROM bit and all internal logic elements ensures
100% programming yield. AC test measurements are taken under
conditions equivalent to those shown in Figure 9. Test patterns can be
used and then erased during early stages of the production flow.
Figure 9. MAX 7000A AC Test Conditions
VCC
To Test
System
C1 (includes JIG
capacitance)
Device input
rise and fall
times < 2 ns
Device
Output
703 Ω
[521 Ω]
8,060 Ω
[481 Ω]
Power supply transients can affect AC
measurements. Simultaneous transitions
of multiple outputs should be avoided for
accurate measurement. Threshold tests
must not be performed under AC
conditions. Large-amplitude, fast-ground-
current transients normally occur as the
device outputs discharge the load
capacitances. When these transients flow
through the parasitic inductance between
the device ground pin and the test system
ground, significant reductions in
observable noise immunity can result.
Numbers in brackets are for 2.5-V
outputs. Numbers without brackets are for
3.3-V devices or outputs.
616 Altera Corporation
MAX 7000A Programmable Logic Device Family Data Sheet Preliminary Information
Operating
Conditions
Tables 9 through 12 provide information on absolute maximum ratings,
recommended operating conditions, operating conditions, and
capacitance for MAX 7000A devices.
Table 9. MAX 7000A Device Absolute Maximum Ratings Note (1)
Symbol Parameter Conditions Min Max Unit
VCC Supply voltage With respect to ground
(2)
–0.5 4.6 V
VIDC input voltage –2.0 5.75 V
IOUT DC output current, per pin –25 25 mA
TSTG Storage temperature No bias –65 150 ° C
TAAmbient temperature Under bias –65 135 ° C
TJJunction temperature FineLine BGA, PQFP, and TQFP
packages, under bias 135 ° C
Table 10. MAX 7000A Device Recommended Operating Conditions
Symbol Parameter Conditions Min Max Unit
VCCINT Supply voltage for internal logic
and input buffers
(3)
3.0 3.6 V
VCCIO Supply voltage for output
drivers, 3.3-V operation
(3)
3.0 3.6 V
Supply voltage for output
drivers, 2.5-V operation
(3)
2.3 2.7 V
VCCISP Supply voltage during in-
system programming 3.0 3.6 V
VIInput voltage
(2)
,
(4)
–0.5 5.75 V
VOOutput voltage 0 VCCIO V
TAAmbient temperature For commercial use 0 70 ° C
For industrial use –40 85 ° C
TJJunction temperature For commercial use 0 90 ° C
For industrial use –40 105 ° C
tRInput rise time 40 ns
tFInput fall time 40 ns
Altera Corporation 617
MAX 7000A Programmable Logic Device Family Data Sheet
Preliminary Information
Table 11. MAX 7000A Device DC Operating Conditions Note (5)
Symbol Parameter Conditions Min Max Unit
VIH High-level input voltage 1.7 5.75 V
VIL Low-level input voltage
(2)
–0.5 0.8 V
VOH 3.3-V high-level TTL output
voltage IOH = –8 mA DC, VCCIO = 3.00 V
(6)
2.4 V
3.3-V high-level CMOS output
voltage IOH = –0.1 mA DC, VCCIO = 3.00 V
(6)
VCCIO – 0.2 V
2.5-V high-level output voltage IOH = –100 µA DC, VCCIO = 2.30 V
(6)
2.1 V
IOH = –1 mA DC, VCCIO = 2.30 V
(6)
2.0 V
IOH = –2 mA DC, VCCIO = 2.30 V
(6)
1.7 V
VOL 3.3-V low-level TTL output
voltage IOL = 8 mA DC, VCCIO = 3.00 V
(7)
0.45 V
3.3-V low-level CMOS output
voltage IOL = 0.1 mA DC, VCCIO = 3.00 V
(7)
0.2 V
2.5-V low-level output voltage IOL = 100 µA DC, VCCIO = 2.30 V
(7)
0.2 V
IOL = 1 mA DC, VCCIO = 2.30 V
(7)
0.4 V
IOL = 2 mA DC, VCCIO = 2.30 V
(7)
0.7 V
IIInput leakage current VI = VCCINT or ground –10 10 µA
IOZ Tri-state output off-state
current VO = VCCINT or ground –10 10 µA
RISP Value of I/O pin pull-up resistor
during programming in-system
or during power-up
VCCIO = 3.0 to 3.6 V
(8)
20 50 kΩ
VCCIO = 2.3 to 2.7 V
(8)
30 80 kΩ
VCCIO = 2.3 to 3.6 V
(9)
20 74 kΩ
Table 12. MAX 7000A Device Capacitance Note (10)
Symbol Parameter Conditions Min Max Unit
CIN Input pin capacitance VIN = 0 V, f = 1.0 MHz 8 pF
CI/O I/O pin capacitance VOUT = 0 V, f = 1.0 MHz 8 pF
618 Altera Corporation
MAX 7000A Programmable Logic Device Family Data Sheet Preliminary Information
Notes to tables:
(1) See the Operating Requirements for Altera Devices Data Sheet.
(2) Minimum DC input voltage is –0.5 V. During transitions, the inputs may undershoot to –2.0 V for input currents
less than 100 mA and periods shorter than 20 ns.
(3) VCC must rise monotonically.
(4) In MAX 7000AE devices, all pins, including dedicated inputs, I/O pins, and JTAG pins, may be driven before
VCCINT and VCCIO are powered.
(5) These values are specified in Table 10 on page 616.
(6) The parameter is measured with 50% of the outputs each sourcing the specified current. The IOH parameter refers
to high-level TTL or CMOS output current.
(7) The parameter is measured with 50% of the outputs each sinking the specified current. The IOL parameter refers to
low-level TTL or CMOS output current.
(8) For EPM7128A and EPM7256A devices, this pull-up exists while a device is programmed in-system.
(9) For MAX 7000AE devices, this pull-up exists while devices are programmed in-system and in unprogrammed
devices during power-up.
(10) Capacitance is measured at 25° C and is sample-tested only. The OE1 pin (high-voltage pin during programming)
has a maximum capacitance of 20 pF.
Figure 10 shows the typical output drive characteristics of MAX 7000A
devices.
Figure 10. Output Drive Characteristics of MAX 7000A Devices
Timing Model MAX 7000A device timing can be analyzed with the Quartus and
MAX+PLUS II software, with a variety of popular industry-standard
EDA simulators and timing analyzers, or with the timing model shown in
Figure 11. MAX 7000A devices have predictable internal delays that
enable the designer to determine the worst-case timing of any design. The
MAX+PLUS II software provides timing simulation, point-to-point delay
prediction, and detailed timing analysis for device-wide performance
evaluation.
VO Output Voltage (V)
1 2 3 4
10
20
30
40
IOL
IOH
VCCINT = 3.3 V
VCCIO = 3.3 V
Room Temperature
50
60
Typical I
Output
Current (mA)
O
VO Output Voltage (V)
1 2 3 4
10
20
30
40VCCINT = 3.3 V
VCCIO = 2.5 V
IOL
IOH
Room Temperature
50
60
2.5 V3.3 V
Typical I
Output
Current (mA)
O
Altera Corporation 619
MAX 7000A Programmable Logic Device Family Data Sheet
Preliminary Information
Figure 11. MAX 7000A Timing Model
The timing characteristics of any signal path can be derived from the
timing model and parameters of a particular device. External timing
parameters, which represent pin-to-pin timing delays, can be calculated
as the sum of internal parameters. Figure 12 shows the timing relationship
between internal and external delay parameters.
fSee Application Note 94 (Understanding MAX 7000 Timing) for more
information.
Logic Array
Delay
t
LAD
Output
Delay
t
OD3
t
OD2
t
OD1
t
XZ
Z
t
X1
t
ZX2
t
ZX3
Input
Delay
t
IN
Register
Delay
t
SU
t
H
t
PRE
t
CLR
t
RD
t
COMB
t
FSU
t
FH
PIA
Delay
t
PIA
Shared
Expander Delay
t
SEXP
Register
Control Delay
t
LAC
t
IC
t
EN
I/O
Delay
t
IO
Global Control
Delay
t
GLOB
Internal Output
Enable Delay
t
IOE
Parallel
Expander Delay
t
PEXP
Fast
Input Delay
t
FIN
620 Altera Corporation
MAX 7000A Programmable Logic Device Family Data Sheet Preliminary Information
Figure 12. MAX 7000A Switching Waveforms
Combinatorial Mode
Input Pin
I/O Pin
PIA Delay
Shared Expander
Delay
Logic Array
Input
Parallel Expander
Delay
Logic Array
Output
Output Pin
t
IN
t
LAC
, t
LAD
t
PIA
t
OD
t
PEXP
t
IO
t
SEXP
t
COMB
Global Clock Mode
Global
Clock Pin
Global Clock
at Register
Data or Enable
(Logic Array Output)
t
F
t
CH
t
CL
t
R
t
IN
t
GLOB
t
SU
t
H
Array Clock Mode
Input or I/O Pin
Clock into PIA
Clock into
Logic Array
Clock at
Register
Data from
Logic Array
Register to PIA
to Logic Array
Register Output
to Pin
t
F
t
R
t
ACH
t
ACL
t
SU
t
IN
t
IO
t
RD
t
PIA
t
CLR
, t
PRE
t
H
t
PIA
t
IC
t
PIA
t
OD
t
OD
t
R
& t
F
< 2 ns. Inputs are
driven at 3 V for a logic
high and 0 V for a logic
low. All timing
characteristics are
measured at 1.5 V.
Altera Corporation 621
MAX 7000A Programmable Logic Device Family Data Sheet
Preliminary Information
Tables 13 through 20 show EPM7128A, EPM7256A, and MAX 7000AE
AC operating conditions.
Table 13. EPM7128A External Timing Parameters Note (1)
Symbol Parameter Conditions Speed Grade Unit
-6 -7 -10 -12
Min Max Min Max Min Max Min Max
tPD1 Input to non-registered
output C1 = 35 pF
(2)
6.0 7.5 10.0 12.0 ns
tPD2 I/O input to non-
registered output C1 = 35 pF
(2)
6.0 7.5 10.0 12.0 ns
tSU Global clock setup time
(2)
4.2 5.3 7.0 8.5 ns
tHGlobal clock hold time
(2)
0.0 0.0 0.0 0.0 ns
tFSU Global clock setup time
of fast input 2.5 3.0 3.0 3.0 ns
tFH Global clock hold time of
fast input 0.0 0.0 0.0 0.0 ns
tCO1 Global clock to output
delay C1 = 35 pF 1.0 3.7 1.0 4.6 1.0 6.1 1.0 7.3 ns
tCH Global clock high time 3.0 3.0 4.0 5.0 ns
tCL Global clock low time 3.0 3.0 4.0 5.0 ns
tASU Array clock setup time
(2)
1.9 2.4 3.1 3.8 ns
tAH Array clock hold time
(2)
1.5 2.2 3.3 4.3 ns
tACO1 Array clock to output
delay C1 = 35 pF
(2)
1.0 6.0 1.0 7.5 1.0 10.0 1.0 12.0 ns
tACH Array clock high time 3.0 3.0 4.0 5.0 ns
tACL Array clock low time 3.0 3.0 4.0 5.0 ns
tCNT Minimum global clock
period
(2)
6.9 8.6 11.5 13.8 ns
fCNT Maximum internal global
clock frequency
(2)
,
(3)
144.9 116.3 87.0 72.5 MHz
tACNT Minimum array clock
period
(2)
6.9 8.6 11.5 13.8 ns
fACNT Maximum internal array
clock frequency
(2)
,
(3)
144.9 116.3 87 72.5 MHz
fMAX Maximum clock
frequency
(4)
166.7 166.7 125.0 100.0 MHz
622 Altera Corporation
MAX 7000A Programmable Logic Device Family Data Sheet Preliminary Information
Table 14. EPM7128A Internal Timing Parameters (Part 1 of 2)
Symbol Parameter Conditions Speed Grade Unit
-6 -7 -10 -12
Min Max Min Max Min Max Min Max
t
IN
Input pad and buffer delay 0.6 0.7 0.9 1.1 ns
t
IO
I/O input pad and buffer
delay 0.6 0.7 0.9 1.1 ns
t
FIN
Fast input delay 2.7 3.1 3.6 3.9 ns
t
SEXP
Shared expander delay 2.5 3.2 4.3 5.1 ns
t
PEXP
Parallel expander delay 0.7 0.8 1.1 1.3 ns
t
LAD
Logic array delay 2.4 3.0 4.1 4.9 ns
t
LAC
Logic control array delay 2.4 3.0 4.1 4.9 ns
t
IOE
Internal output enable
delay 0.0 0.0 0.0 0.0 ns
t
OD1
Output buffer and pad
delay, slow slew rate = off
VCCIO = 3.3 V
C1 = 35 pF 0.4 0.6 0.7 0.9 ns
t
OD2
Output buffer and pad
delay, slow slew rate = off
VCCIO = 2.5 V
C1 = 35 pF
(5)
0.9 1.1 1.2 1.4 ns
t
OD3
Output buffer and pad
delay, slow slew rate = on
VCCIO = 2.5 V or 3.3 V
C1 = 35 pF 5.4 5.6 5.7 5.9 ns
t
ZX1
Output buffer enable
delay, slow slew rate = off
VCCIO = 3.3 V
C1 = 35 pF 4.0 4.0 5.0 5.0 ns
t
ZX2
Output buffer enable
delay, slow slew rate = off
VCCIO = 2.5 V
C1 = 35 pF
(5)
4.5 4.5 5.5 5.5 ns
t
ZX3
Output buffer enable
delay, slow slew rate = on
VCCIO = 3.3 V
C1 = 35 pF 9.0 9.0 10.0 10.0 ns
t
XZ
Output buffer disable
delay C1 = 5 pF 4.0 4.0 5.0 5.0 ns
t
SU
Register setup time 1.9 2.4 3.1 3.8 ns
t
H
Register hold time 1.5 2.2 3.3 4.3 ns
t
FSU
Register setup time of fast
input 0.8 1.1 1.1 1.1 ns
t
FH
Register hold time of fast
input 1.7 1.9 1.9 1.9 ns
Altera Corporation 623
MAX 7000A Programmable Logic Device Family Data Sheet
Preliminary Information
t
RD
Register delay 1.7 2.1 2.8 3.3 ns
t
COMB
Combinatorial delay 1.7 2.1 2.8 3.3 ns
t
IC
Array clock delay 2.4 3.0 4.1 4.9 ns
t
EN
Register enable time 2.4 3.0 4.1 4.9 ns
t
GLOB
Global control delay 1.0 1.2 1.7 2.0 ns
t
PRE
Register preset time 3.1 3.9 5.2 6.2 ns
t
CLR
Register clear time 3.1 3.9 5.2 6.2 ns
t
PIA
PIA delay
(2)
0.9 1.1 1.5 1.8 ns
t
LPA
Low-power adder
(6)
11.0 10.0 10.0 10.0 ns
Table 14. EPM7128A Internal Timing Parameters (Part 2 of 2)
Symbol Parameter Conditions Speed Grade Unit
-6 -7 -10 -12
Min Max Min Max Min Max Min Max
624 Altera Corporation
MAX 7000A Programmable Logic Device Family Data Sheet Preliminary Information
Table 15. EPM7256A External Timing Parameters Note (1)
Symbol Parameter Conditions Speed Grade Unit
-6 -7 -10 -12
Min Max Min Max Min Max Min Max
tPD1 Input to non-registered
output C1 = 35 pF
(2)
6.0 7.5 10.0 12.0 ns
tPD2 I/O input to non-
registered output C1 = 35 pF
(2)
6.0 7.5 10.0 12.0 ns
tSU Global clock setup time
(2)
3.7 4.6 6.2 7.4 ns
tHGlobal clock hold time
(2)
0.0 0.0 0.0 0.0 ns
tFSU Global clock setup time
of fast input 2.5 3.0 3.0 3.0 ns
tFH Global clock hold time of
fast input 0.0 0.0 0.0 0.0 ns
tCO1 Global clock to output
delay C1 = 35 pF 1.0 3.3 1.0 4.2 1.0 5.5 1.0 6.6 ns
tCH Global clock high time 3.0 3.0 4.0 4.0 ns
tCL Global clock low time 3.0 3.0 4.0 4.0 ns
tASU Array clock setup time
(2)
0.8 1.0 1.4 1.6 ns
tAH Array clock hold time
(2)
1.9 2.7 4.0 5.1 ns
tACO1 Array clock to output
delay C1 = 35 pF
(2)
1.0 6.2 1.0 7.8 1.0 10.3 1.0 12.4 ns
tACH Array clock high time 3.0 3.0 4.0 4.0 ns
tACL Array clock low time 3.0 3.0 4.0 4.0 ns
tCNT Minimum global clock
period
(2)
6.4 8.0 10.7 12.8 ns
fCNT Maximum internal global
clock frequency
(2)
,
(3)
156.3 125.0 93.5 78.1 MHz
tACNT Minimum array clock
period
(2)
6.4 8.0 10.7 12.8 ns
fACNT Maximum internal array
clock frequency
(2)
,
(3)
156.3 125.0 93.5 78.1 MHz
fMAX Maximum clock
frequency
(2)
,
(4)
166.7 166.7 125.0 125.0 MHz
Altera Corporation 625
MAX 7000A Programmable Logic Device Family Data Sheet
Preliminary Information
Table 16. EPM7256A Internal Timing Parameters (Part 1 of 2)
Symbol Parameter Conditions Speed Grade Unit
-6 -7 -10 -12
Min Max Min Max Min Max Min Max
t
IN
Input pad and buffer delay 0.3 0.4 0.5 0.6 ns
t
IO
I/O input pad and buffer
delay 0.3 0.4 0.5 0.6 ns
t
FIN
Fast input delay 2.4 3.0 3.4 3.8 ns
t
SEXP
Shared expander delay 2.8 3.5 4.7 5.6 ns
t
PEXP
Parallel expander delay 0.5 0.6 0.8 1.0 ns
t
LAD
Logic array delay 2.5 3.1 4.2 5.0 ns
t
LAC
Logic control array delay 2.5 3.1 4.2 5.0 ns
t
IOE
Internal output enable
delay 0.2 0.3 0.4 0.5 ns
t
OD1
Output buffer and pad
delay, slow slew rate = off
VCCIO = 3.3 V
C1 = 35 pF
0.3 0.4 0.5 0.6 ns
t
OD2
Output buffer and pad
delay, slow slew rate = off
VCCIO = 2.5 V
C1 = 35 pF
(5)
0.8 0.9 1.0 1.1 ns
t
OD3
Output buffer and pad
delay
slow slew rate = on
VCCIO = 2.5 V or 3.3 V
C1 = 35 pF 5.3 5.4 5.5 5.6 ns
t
ZX1
Output buffer enable
delay
slow slew rate = off
VCCIO = 3.3 V
C1 = 35 pF 4.0 4.0 5.0 5.0 ns
t
ZX2
Output buffer enable
delay
slow slew rate = off
VCCIO = 2.5 V
C1 = 35 pF
(5)
4.5 4.5 5.5 5.5 ns
t
ZX3
Output buffer enable
delay
slow slew rate = on
VCCIO = 2.5 V or 3.3 V
C1 = 35 pF 9.0 9.0 10.0 10.0 ns
t
XZ
Output buffer disable
delay C1 = 5 pF 4.0 4.0 5.0 5.0 ns
t
SU
Register setup time 1.0 1.3 1.7 2.0 ns
t
H
Register hold time 1.7 2.4 3.7 4.7 ns
626 Altera Corporation
MAX 7000A Programmable Logic Device Family Data Sheet Preliminary Information
t
FSU
Register setup time of fast
input 1.2 1.4 1.4 1.4 ns
t
FH
Register hold time of fast
input 1.3 1.6 1.6 1.6 ns
t
RD
Register delay 1.6 2.0 2.7 3.2 ns
t
COMB
Combinatorial delay 1.6 2.0 2.7 3.2 ns
t
IC
Array clock delay 2.7 3.4 4.5 5.4 ns
t
EN
Register enable time 2.5 3.1 4.2 5.0 ns
t
GLOB
Global control delay 1.1 1.4 1.8 2.2 ns
t
PRE
Register preset time 2.3 2.9 3.8 4.6 ns
t
CLR
Register clear time 2.3 2.9 3.8 4.6 ns
t
PIA
PIA delay
(2)
1.3 1.6 2.1 2.6 ns
t
LPA
Low-power adder
(6)
11.0 10.0 10.0 10.0 ns
Table 16. EPM7256A Internal Timing Parameters (Part 2 of 2)
Symbol Parameter Conditions Speed Grade Unit
-6 -7 -10 -12
Min Max Min Max Min Max Min Max
Altera Corporation 627
MAX 7000A Programmable Logic Device Family Data Sheet
Preliminary Information
Table 17. MAX 7000AE External Timing Parameters Notes (1), (7)
Symbol Parameter Conditions Speed Grade Unit
-4 -5 -6
Min Max Min Max Min Max
tPD1 Input to non-registered output C1 = 35 pF
(2)
4.5 5.0 6.0 ns
tPD2 I/O input to non-registered
output C1 = 35 pF
(2)
4.5 5.0 6.0 ns
tSU Global clock setup time
(2)
3.0 3.2 3.7 ns
tHGlobal clock hold time
(2)
0.0 0.0 0.0 ns
tFSU Global clock setup time of fast
input 2.5 2.5 2.5 ns
tFH Global clock hold time of fast
input 0.0 0.0 0.0 ns
tCO1 Global clock to output delay C1 = 35 pF 1.0 2.8 1.0 3.0 1.0 3.3 ns
tCH Global clock high time 2.0 2.0 3.0 ns
tCL Global clock low time 2.0 2.0 3.0 ns
tASU Array clock setup time
(2)
1.4 1.0 0.8 ns
tAH Array clock hold time
(2)
0.8 0.8 1.9 ns
tACO1 Array clock to output delay C1 = 35 pF
(2)
4.4 5.2 1.0 6.2 ns
tACH Array clock high time 2.0 2.0 3.0 ns
tACL Array clock low time 2.0 2.0 3.0 ns
tCNT Minimum global clock period
(2)
5.2 5.5 6.4 ns
fCNT Maximum internal global clock
frequency
(2)
,
(3)
192.3 181.8 156.3 MHz
tACNT Minimum array clock period
(2)
5.2 5.5 6.4 ns
fACNT Maximum internal array clock
frequency
(2)
,
(3)
192.3 181.8 156.3 MHz
fMAX Maximum clock frequency
(4)
250.0 250.0 166.7 MHz
Table 18. MAX 7000AE Internal Timing Parameters (Part 1 of 2) Notes (1), (7)
Symbol Parameter Conditions Speed Grade Unit
-4 -5 -6
Min Max Min Max Min Max
t
IN
Input pad and buffer delay 0.3 0.3 0.3 ns
t
IO
I/O input pad and buffer delay 0.3 0.3 0.3 ns
t
FIN
Fast input delay 2.6 2.6 2.4 ns
t
SEXP
Shared expander delay 1.9 2.4 2.8 ns
628 Altera Corporation
MAX 7000A Programmable Logic Device Family Data Sheet Preliminary Information
t
PEXP
Parallel expander delay 0.5 0.6 0.5 ns
t
LAD
Logic array delay 1.9 2.5 2.5 ns
t
LAC
Logic control array delay 1.8 2.3 2.5 ns
t
IOE
Internal output enable delay 0.0 0.0 0.2 ns
t
OD1
Output buffer and pad delay
slow slew rate = off
VCCIO = 3.3 V
C1 = 35 pF
0.3 0.4 0.3 ns
t
OD2
Output buffer and pad delay
slow slew rate = off
VCCIO = 2.5 V
C1 = 35 pF
(5)
0.8 0.9 0.8 ns
t
OD3
Output buffer and pad delay
slow slew rate = on
VCCIO = 2.5 V or 3.3 V
C1 = 35 pF 5.3 5.4 5.3 ns
t
ZX1
Output buffer enable delay
slow slew rate = off
VCCIO = 3.3 V
C1 = 35 pF 4.0 4.0 4.0 ns
t
ZX2
Output buffer enable delay
slow slew rate = off
VCCIO = 2.5 V
C1 = 35 pF
(5)
4.5 4.5 4.5 ns
t
ZX3
Output buffer enable delay
slow slew rate = on
VCCIO = 2.5 V or 3.3 V
C1 = 35 pF 9.0 9.0 9.0 ns
t
XZ
Output buffer disable delay C1 = 5 pF 4.0 4.0 4.0 ns
t
SU
Register setup time 1.4 0.8 1.0 ns
t
H
Register hold time 0.8 1.0 1.7 ns
t
FSU
Register setup time of fast input 0.9 0.8 1.2 ns
t
FH
Register hold time of fast input 1.6 1.7 1.3 ns
t
RD
Register delay 1.2 1.4 1.6 ns
t
COMB
Combinatorial delay 1.3 1.0 1.6 ns
t
IC
Array clock delay 1.9 2.3 2.7 ns
t
EN
Register enable time 1.8 2.3 2.5 ns
t
GLOB
Global control delay 1.0 0.9 1.1 ns
t
PRE
Register preset time 2.3 2.6 2.3 ns
t
CLR
Register clear time 2.3 2.6 2.3 ns
t
PIA
PIA delay
(2)
0.7 0.8 1.3 ns
t
LPA
Low-power adder
(6)
12.0 12.0 11.0 ns
Table 18. MAX 7000AE Internal Timing Parameters (Part 2 of 2) Notes (1), (7)
Symbol Parameter Conditions Speed Grade Unit
-4 -5 -6
Min Max Min Max Min Max
Altera Corporation 629
MAX 7000A Programmable Logic Device Family Data Sheet
Preliminary Information
Table 19. MAX 7000AE External Timing Parameters Notes (1), (7)
Symbol Parameter Conditions Speed Grade Unit
-7 -10 -12
Min Max Min Max Min Max
tPD1 Input to non-registered output C1 = 35 pF
(2)
7.5 10.0 12.0 ns
tPD2 I/O input to non-registered
output C1 = 35 pF
(2)
7.5 10.0 12.0 ns
tSU Global clock setup time
(2)
4.9 6.6 7.8 ns
tHGlobal clock hold time
(2)
0.0 0.0 0.0 ns
tFSU Global clock setup time of fast
input 3.0 3.0 3.0 ns
tFH Global clock hold time of fast
input 0.0 0.0 0.0 ns
tCO1 Global clock to output delay C1 = 35 pF 1.0 4.5 1.0 5.9 1.0 7.1 ns
tCH Global clock high time 3.0 4.0 5.0 ns
tCL Global clock low time 3.0 4.0 5.0 ns
tASU Array clock setup time
(2)
1.6 2.1 2.4 ns
tAH Array clock hold time
(2)
2.1 3.4 4.4 ns
tACO1 Array clock to output delay C1 = 35 pF
(2)
7.8 10.4 12.5 ns
tACH Array clock high time 3.0 4.0 5.0 ns
tACL Array clock low time 3.0 4.0 5.0 ns
tCNT Minimum global clock period
(2)
8.4 11.2 13.3 ns
fCNT Maximum internal global clock
frequency
(2)
,
(3)
119.0 89.3 75.2 MHz
tACNT Minimum array clock period
(2)
8.4 11.2 13.3 ns
fACNT Maximum internal array clock
frequency
(2)
,
(3)
119.0 89.3 75.2 MHz
fMAX Maximum clock frequency
(4)
166.7 125.0 100.0 MHz
Table 20. MAX 7000AE Internal Timing Parameters (Part 1 of 2) Notes (1), (7)
Symbol Parameter Conditions Speed Grade Unit
-7 -10 -12
Min Max Min Max Min Max
t
IN
Input pad and buffer delay 0.4 0.6 0.7 ns
t
IO
I/O input pad and buffer delay 0.4 0.6 0.7 ns
t
FIN
Fast input delay 3.3 3.7 4.1 ns
t
SEXP
Shared expander delay 3.6 4.9 5.9 ns
630 Altera Corporation
MAX 7000A Programmable Logic Device Family Data Sheet Preliminary Information
t
PEXP
Parallel expander delay 0.8 1.1 1.3 ns
t
LAD
Logic array delay 3.7 5.0 6.0 ns
t
LAC
Logic control array delay 3.4 4.6 5.6 ns
t
IOE
Internal output enable delay 0.0 0.0 0.0 ns
t
OD1
Output buffer and pad delay
slow slew rate = off
VCCIO = 3.3 V
C1 = 35 pF
0.6 0.7 0.9 ns
t
OD2
Output buffer and pad delay
slow slew rate = off
VCCIO = 2.5 V
C1 = 35 pF
(5)
1.1 1.2 1.4 ns
t
OD3
Output buffer and pad delay
slow slew rate = on
VCCIO = 2.5 V or 3.3 V
C1 = 35 pF 5.6 5.7 5.9 ns
t
ZX1
Output buffer enable delay
slow slew rate = off
VCCIO = 3.3 V
C1 = 35 pF 4.0 5.0 5.0 ns
t
ZX2
Output buffer enable delay
slow slew rate = off
VCCIO = 2.5 V
C1 = 35 pF
(5)
4.5 5.5 5.5 ns
t
ZX3
Output buffer enable delay
slow slew rate = on
VCCIO = 2.5 V or 3.3 V
C1 = 35 pF 9.0 10.0 10.0 ns
t
XZ
Output buffer disable delay C1 = 5 pF 4.0 5.0 5.0 ns
t
SU
Register setup time 1.3 1.7 2.0 ns
t
H
Register hold time 2.4 3.8 4.8 ns
t
FSU
Register setup time of fast input 1.1 1.1 1.1 ns
t
FH
Register hold time of fast input 1.9 1.9 1.9 ns
t
RD
Register delay 2.1 2.8 3.3 ns
t
COMB
Combinatorial delay 1.5 2.0 2.4 ns
t
IC
Array clock delay 3.4 4.6 5.6 ns
t
EN
Register enable time 3.4 4.6 5.6 ns
t
GLOB
Global control delay 1.4 1.8 2.2 ns
t
PRE
Register preset time 3.9 5.2 6.2 ns
t
CLR
Register clear time 3.9 5.2 6.2 ns
t
PIA
PIA delay
(2)
1.3 1.7 2.0 ns
t
LPA
Low-power adder
(6)
10.0 10.0 10.0 ns
Table 20. MAX 7000AE Internal Timing Parameters (Part 2 of 2) Notes (1), (7)
Symbol Parameter Conditions Speed Grade Unit
-7 -10 -12
Min Max Min Max Min Max
Altera Corporation 631
MAX 7000A Programmable Logic Device Family Data Sheet
Preliminary Information
Notes to tables:
(1) These values are specified in Table 10 on page 616.
(2) These values are specified for a PIA fan-out of one LAB (16 macrocells). For each additional LAB fan-out in these
devices, add an additional 0.1 ns to the PIA timing value.
(3) Measured with a 16-bit loadable, enabled, up/down counter programmed into each LAB.
(4) The fMAX values represent the highest frequency for pipelined data.
(5) Operating conditions: VCCIO = 2.5 ± 0.2 V for commercial and industrial use.
(6) The tLPA parameter must be added to the tLAD, tLAC, tIC, tACL, tEN, and tSEXP parameters for macrocells running in
low-power mode.
(7) MAX 7000AE timing values are preliminary.
Power
Consumption
Supply power (P) versus frequency (fMAX, in MHz) for MAX 7000A
devices is calculated with the following equation:
P = PINT + PIO = ICCINT × VCC + PIO
The PIO value, which depends on the device output load characteristics
and switching frequency, can be calculated using the guidelines given in
Application Note 74 (Evaluating Power for Altera Devices).
The ICCINT value depends on the switching frequency and the application
logic. The ICCINT value is calculated with the following equation:
ICCINT =
(A × MCTON) + [B × (MCDEV – MCTON)] + (C × MCUSED × fMAX × togLC)
The parameters in this equation are:
MCTON = Number of macrocells with the Turbo BitTM option turned
on, as reported in the MAX+PLUS II Report File (.rpt)
MCDEV = Number of macrocells in the device
MCUSED = Total number of macrocells in the design, as reported in
the Report File
fMAX = Highest clock frequency to the device
togLC = Average percentage of logic cells toggling at each clock
(typically 12.5%)
A, B, C = Constants, shown in Table 21
632 Altera Corporation
MAX 7000A Programmable Logic Device Family Data Sheet Preliminary Information
Note:
(1) Values for these devices are preliminary.
This calculation provides an ICC estimate based on typical conditions
using a pattern of a 16-bit, loadable, enabled, up/down counter in each
LAB with no output load. Actual ICC should be verified during operation
because this measurement is sensitive to the actual pattern in the device
and the environmental operating conditions.
Table 21. MAX 7000A I
CC
Equation Constants
Device A B C
EPM7032AE
(1)
0.46 0.28 0.032
EPM7064AE
(1)
0.46 0.28 0.032
EPM7128A
(1)
0.46 0.28 0.032
EPM7128AE
(1)
0.46 0.28 0.032
EPM7256A
(1)
0.46 0.28 0.032
EPM7256AE
(1)
0.46 0.28 0.032
EPM7512AE
(1)
0.46 0.28 0.032
Altera Corporation 633
MAX 7000A Programmable Logic Device Family Data Sheet
Preliminary Information
Figure 13 shows the typical supply current versus frequency for
MAX 7000A devices.
Figure 13. I
CC
vs. Frequency for MAX 7000A Devices (Part 1 of 2)
VCC = 3.3 V
Room Temperature
0
Frequency (MHz)
High Speed
Low Power
50 100 150 200
181.8 MHz
56.17 MHz
250
EPM7128A & EPM7128AE
EPM7032AE
VCC = 3.3 V
Room Temperature
Frequency (MHz)
30
40
60
70
80
90 VCC = 3.3 V
Room Temperature
0
Frequency (MHz)
High Speed
Non-Turbo
50 100 150 200
192.3 MHz
58.1 MHz
250
050 100 150 200 250
EPM7064AE
10
50
20
15
20
30
35
40
45
High Speed
Non-Turbo
192.3 MHz
58.1 MHz
5
25
10
Typical I
Active (mA)
CC Typical I
Active (mA)
CC
Typical I
Active (mA)
CC
60
80
120
140
160
180
20
100
40
634 Altera Corporation
MAX 7000A Programmable Logic Device Family Data Sheet Preliminary Information
Figure 13. I
CC
vs. Frequency for MAX 7000A Devices (Part 2 of 2)
Device
Pin-Outs
Tables 22 through 32 show the pin names and numbers for the pins in
MAX 7000A and MAX7000AE device packages.
EPM7256A & EPM7256AE
VCC = 3.3 V
Room Temperature
Frequency (MHz)
Low Power
156.3 MHz
57.14 MHz
50
100
150
200
250
300
350
High Speed
050 100 150 200
Typical I
Active (mA)
CC
EPM7512AE
VCC = 3.3 V
Room Temperature
Frequency (MHz)
Low Power
119 MHz
53.76 MHz
100
200
300
400
500
600
020 40 80 100
Typical I
Active (mA)
CC
High Speed
60 120 140
Table 22. EPM7032AE Dedicated Pin-Outs
Dedicated Pin 44-Pin PLCC 44-Pin TQFP
INPUT/GCLK1 43 37
INPUT/GCLRn 1 39
INPUT/OE1 44 38
INPUT/OE2/GCLK2 2 40
TDI
(1)
7 1
TMS
(1)
13 7
TCK
(1)
32 26
TDO
(1)
38 32
GNDINT 22, 42 16, 36
GNDIO 10, 30 4, 24
VCCINT (3.3 V) 3, 23 17, 41
VCCIO (2.5 V or 3.3 V) 15, 35 9, 29
No Connect (N.C.) – –
Total User I/O Pins
(2)
36 36
Altera Corporation 635
MAX 7000A Programmable Logic Device Family Data Sheet
Preliminary Information
Table 23. EPM7032AE I/O Pin-Outs
LAB MC 44-Pin
PLCC
44-Pin
TQFP
LAB MC 44-Pin
PLCC
44-Pin
TQFP
A 1 4 42 B 17 41 35
2 5 43 18 40 34
3 6 44 19 39 33
4 7
(1)
1
(1)
20 38
(1)
32
(1)
5 8 2 21 37 31
6 9 3 22 36 30
7 11 5 23 34 28
8 12 6 24 33 27
9 13
(1)
7
(1)
25 32
(1)
26
(1)
10 14 8 26 31 25
11 16 10 27 29 23
12 17 11 28 28 22
13 18 12 29 27 21
14 19 13 30 26 20
15 20 14 31 25 19
16 21 15 32 24 18
636 Altera Corporation
MAX 7000A Programmable Logic Device Family Data Sheet Preliminary Information
Table 24. EPM7064AE Dedicated Pin-Outs
Dedicated Pin 44-Pin
PLCC
44-Pin
TQFP
100-Pin
TQFP
100-Pin
FineLine BGA
INPUT/GCLK1 43 37 87 A6
INPUT/GCLRn 1 39 89 B5
INPUT/OE1 44 38 88 B6
INPUT/OE2/GCLK2 2 40 90 A5
TDI
(1)
7 1 4 A1
TMS
(1)
13 7 15 F3
TCK
(1)
32 26 62 F8
TDO
(1)
38 32 73 A10
GNDINT 22, 42 16, 36 38, 86 C3, D6, D7, E5, F6,
G4, G5, H8
GNDIO 10, 30 4, 24 11, 26, 43, 59, 74,
95 –
VCCINT (3.3 V Only) 3, 23 17, 41 39, 91 D5, G6
VCCIO (2.5 V or 3.3 V) 15, 35 9, 29 3, 18, 34, 51, 66, 82 C8, D4, E6, F5, G7,
H3
No Connect (N.C.) – – 1, 2, 5, 7, 22, 24,
27, 28, 49, 50, 53,
55, 70, 72, 77, 78
B1, B10, C1, C9,
C10, D8, E3, E4,
H1, H9, H10, J1,
J2, J10, K1, K9
Total User I/O Pins
(2)
36 36 68 68
Altera Corporation 637
MAX 7000A Programmable Logic Device Family Data Sheet
Preliminary Information
Table 25. EPM7064AE I/O Pin-Outs (44-Pin PLCC & 44-Pin TQFP Packages)
LAB MC 44-Pin
PLCC
44-Pin
TQFP
LAB MC 44-Pin
PLCC
44-Pin
TQFP
A 1 12 6 C 33 24 18
2 – – 34 – –
3 11 5 35 25 19
4 9 3 36 26 20
5 8 2 37 27 21
6 – – 38 – –
7 – – 39 – –
8 7
(1)
1
(1)
40 28 22
9 – – 41 29 23
10 – – 42 – –
11 6 44 43 – –
12 – – 44 – –
13 – – 45 – –
14 5 43 46 31 25
15 – – 47 – –
16 4 42 48 32
(1)
26
(1)
B 17 21 15 D 49 33 27
18 – – 50 – –
19 20 14 51 34 28
20 19 13 52 36 30
21 18 12 53 37 31
22 – – 54 – –
23 – – 55 – –
24 17 11 56 38
(1)
32
(1)
25 16 10 57 39 33
26 – – 48 – –
27 – – 59 – –
28 – – 60 – –
29 – – 61 – –
30 14 8 62 40 34
31 – – 63 – –
32 13
(1)
7
(1)
64 41 35
638 Altera Corporation
MAX 7000A Programmable Logic Device Family Data Sheet Preliminary Information
Notes to tables:
(1) This pin may function as either a JTAG port or a user I/O pin. If the device is configured to use the JTAG ports for
in-system programming, this pin is not available as a user I/O pin.
(2) The user I/O pin count includes dedicated input pins and all I/O pins.
Table 26. EPM7064AE I/O Pin-Outs (100-Pin TQFP & 100-Pin FineLine BGA Packages)
LAB MC 100-Pin
TQFP
100-Pin
FineLine
BGA
LAB MC 100-Pin
TQFP
100-Pin
FineLine
BGA
A 1 14 F4 C 33 40 K6
2 13 E2 34 41 J6
3 12 E1 35 42 H6
4 10 D2 36 44 K7
5 9 D1 37 45 J7
6 8 D3 38 46 H7
7 6 C2 39 47 J8
8 4
(1)
A1
(1)
40 48 K8
9 100 B2 41 52 K10
10 99 A2 42 54 J9
11 98 A3 43 56 G9
12 97 B3 44 57 G10
13 96 A4 45 58 G8
14 94 B4 46 60 F9
15 93 C4 47 61 F10
16 92 C5 48 62
(1)
F8
(1)
B 17 37 K5 D 49 63 F7
18 36 J5 50 64 E9
19 35 H5 51 65 E10
20 33 K4 52 67 E8
21 32 J4 53 68 E7
22 31 H4 54 69 D9
23 30 J3 55 71 D10
24 29 K3 56 73
(1)
A10
(1)
25 25 K2 57 75 B9
26 23 H2 48 76 A9
27 21 G2 59 79 A8
28 20 G1 60 80 B8
29 19 G3 61 81 A7
30 17 F2 62 83 B7
31 16 F1 63 84 C7
32 15
(1)
F3
(1)
64 85 C6
Altera Corporation 639
MAX 7000A Programmable Logic Device Family Data Sheet
Preliminary Information
Table 27. EPM7128A & EPM7128AE Dedicated Pin-Outs
Dedicated Pin 84-Pin
PLCC
100-Pin
TQFP
100-Pin
FineLine
BGA
144-Pin
TQFP
256-Pin
FineLine BGA
INPUT/GCLK1 83 87 A6 125 D9
INPUT/GCLRn 1 89 B5 127 E8
INPUT/OE1 84 88 B6 126 E9
INPUT/OE2/GCLK2 2 90 A5 128 D8
TDI
(1)
14 4 A1 4 D4
TMS
(1)
23 15 F3 20 J6
TCK
(1)
62 62 F8 89 J11
TDO
(1)
71 73 A10 104 D13
GNDINT 42, 82 38, 86 D6, G5 52, 57,
124, 129 A8, C9, G9, K8, P9
GNDIO 7, 19, 32,
47, 59, 72 11, 26,
43, 59,
74, 95
C3, D7,
E5, F6,
G4, H8
3, 13, 17,
33, 59, 64,
85, 105,
135
A3, B10, C2, D14, F6, G10, H8, J9, K7,
L11, M3, P6, P10, R2, R3, T1, T15
VCCINT
(3.3 V only) 3, 43 39, 91 D5, G6 51, 58,
123, 130 B9, C8, G8, K9, P8
VCCIO
(2.5 V or 3.3 V) 13, 26,
38, 53,
66, 78
3, 18, 34,
51, 66, 82 C8, D4,
E6, F5,
G7, H3
24, 50, 73,
76, 95,
115, 144
B3, B5, C14, E15, F11, G3, G7, G15, H9,
J8, K10, L3, L6, M15, P14, T2, T3
No Connect (N.C.) – – – 1, 2, 12,
19, 34, 35,
36, 43, 46,
47, 48, 49,
66, 75, 90,
103, 108,
120, 121,
122
A1, A2, A4, A5, A6, A7, A9, A10, A11, A12,
A13, A14, A15, A16, B1, B2, B4, B6, B7,
B8, B11, B12, B13, B14, B 15, B16, C1,
C3, C4, C6, C11, C13, C15, C16, D1, D2,
D3, D15, D16, E1, E2, E3, E14, E16, F1,
F2, F15, F16, G1, G2, G14, G16, H1, H2,
H15, H16, J1, J2, J15, J16, K1, K2, K3,
K14, K15, K16, L1, L2, L15, L16, M1, M14,
M16, N1, N2, N3, N14, N15, N16, P1, P2,
P3, P4, P12, P13, P15, P16, R1, R4, R5,
R6, R7, R8, R9, R11, R12, R13, R14, R15,
R16, T4, T5, T6, T7, T8, T9, T10, T11, T12,
T13, T14, T16
Total User I/O Pins
(2)
68 84 84 100 100
640 Altera Corporation
MAX 7000A Programmable Logic Device Family Data Sheet Preliminary Information
Table 28. EPM7128A & EPM7128AE I/O Pin-Outs (Part 1 of 2)
LAB MC 84-Pin
PLCC
100-
Pin
TQFP
100-Pin
FineLine
BGA
144-Pin
TQFP
256-Pin
FineLine
BGA
LAB MC 84-Pin
PLCC
100-
Pin
TQFP
100-Pin
FineLine
BGA
144-
Pin
TQFP
256-Pin
FineLine
BGA
A 1 – 2 C1 143 F4 C 33 – 25 K1 32 N4
2 – – – – – 34 – – – – –
3 12 1 B1 142 E4 35 31 24 J1 31 M4
4 – – – 141 C5 36 – – – 30 M2
5 11 100 B2 140 E5 37 30 23 H1 29 L4
6 10 99 A2 139 D5 38 29 22 H2 28 L5
7 – – – – – 39 – – – – –
8 9 98 A3 138 D6 40 28 21 G2 27 K5
9 – 97 B3 137 E6 41 – 20 G1 26 K4
10 – – – – – 42 – – – – –
11 8 96 A4 136 D7 43 27 19 G3 25 K6
12 – – – 134 C7 44 – – – 23 J3
13 6 94 B4 133 E7 45 25 17 F2 22 J5
14 5 93 C4 132 F7 46 24 16 F1 21 J4
15 – – – – – 47 – – – – –
16 4 92 C5 131 F8 48 23
(1)
15
(1)
F3
(1)
20
(1)
J6
(1)
B 17 22 14 F4 18 J7 D 49 41 37 K5 56 N8
18 – – – – – 50 – – – – –
19 21 13 E2 16 H5 51 40 36 J5 55 M8
20 – – – 15 H3 52 – – – 54 P7
21 20 12 E1 14 H4 53 39 35 H5 53 L8
22 – 10 E3 11 H6 54 – 33 K4 45 N7
23 – – – – – 55 – – – – –
24 18 9 E4 10 H7 56 37 32 J4 44 M7
25 17 8 D2 9 G5 57 36 31 H4 42 L7
26 – – – – – 58 – – – – –
27 16 7 D1 8 G4 59 35 30 J3 41 M6
28 – – – 7 F3 60 – – – 40 P5
29 15 6 D3 6 G6 61 34 29 K3 39 N6
30 – 5 C2 5 F5 62 – 28 J2 38 M5
31 – – – – – 63 – – – – –
32 14
(1)
4
(1)
A1
(1)
4
(1)
D4
(1)
64 33 27 K2 37 N5
Altera Corporation 641
MAX 7000A Programmable Logic Device Family Data Sheet
Preliminary Information
Notes to tables:
(1) This pin can function as either a JTAG port or a user I/O pin. If the device is configured to use the JTAG ports for
BST or in-system programming, this pin is not available as a user I/O pin.
(2) The user I/O pin count includes dedicated input pins and all I/O pins.
E 65 44 40 K6 60 N9 G 97 63 63 F7 91 J10
66 – – – – – 98 – – – – –
67 45 41 J6 61 M9 99 64 64 E9 92 H12
68 – – – 62 R10 100 – – – 93 H14
69 46 42 H6 63 L9 101 65 65 E10 94 H13
70 – 44 K7 65 N10 102 – 67 E8 96 H11
71 – – – – – 103 – – – – –
72 48 45 J7 67 M10 104 67 68 E7 97 H10
73 49 46 H7 68 L10 105 68 69 D9 98 G12
74 – – – – – 106 – – – – –
75 50 47 J8 69 M11 107 69 70 D10 99 G13
76 – – – 70 P11 108 – – – 100 F14
77 51 48 K8 71 N11 109 70 71 D8 101 G11
78 – 49 K9 72 N12 110 – 72 C9 102 F12
79 – – – – – 111 – – – – –
80 52 50 K10 74 N13 112 71
(1)
73
(1)
A10
(1)
104
(1)
D13
(1)
F 81 – 52 J10 77 M13 H 113 – 75 C10 106 F13
82 – – – – – 114 – – – – –
83 54 53 H10 78 L13 115 73 76 B10 107 E13
84 – – – 79 L14 116 – – – 109 C12
85 55 54 H9 80 L12 117 74 77 B9 110 E12
86 56 55 J9 81 M12 118 75 78 A9 111 D12
87 – – – – – 119 – – – – –
88 57 56 G9 82 K12 120 76 79 A8 112 D11
89 – 57 G10 83 K13 121 – 80 B8 113 E11
90 – – – – – 122 – – – – –
91 58 58 G8 84 K11 123 77 81 A7 114 D10
92 – – – 86 J14 124 – – – 116 C10
93 60 60 F9 87 J12 125 79 83 B7 117 E10
94 61 61 F10 88 J13 126 80 84 C7 118 F10
95 – – – – – 127 – – – – –
96 62
(1)
62
(1)
F8
(1)
89
(1)
J11
(1)
128 81 85 C6 119 F9
Table 28. EPM7128A & EPM7128AE I/O Pin-Outs (Part 2 of 2)
LAB MC 84-Pin
PLCC
100-
Pin
TQFP
100-Pin
FineLine
BGA
144-Pin
TQFP
256-Pin
FineLine
BGA
LAB MC 84-Pin
PLCC
100-
Pin
TQFP
100-Pin
FineLine
BGA
144-
Pin
TQFP
256-Pin
FineLine
BGA
642 Altera Corporation
MAX 7000A Programmable Logic Device Family Data Sheet Preliminary Information
Table 29. EPM7256A & EPM7256AE Dedicated Pin-Outs
Dedicated Pin 100-Pin TQFP 144-Pin TQFP 208-Pin PQFP 256-Pin
FineLine BGA
INPUT/GCLK1 87 125 184 D9
INPUT/GCLRn 89 127 182 E8
INPUT/OE1 88 126 183 E9
INPUT/OE2/GCLK2 90 128 181 D8
TDI
(1)
4 4 176 D4
TMS
(1)
15 20 127 J6
TCK
(1)
62 89 30 J11
TDO
(1)
73 104 189 D13
GNDINT 38, 86 52, 57, 124, 129 75, 82, 180, 185 A8, C9, G9, K8, P9
GNDIO
(2)
11, 26, 43, 59,
74, 95 3, 13, 17, 33,
59, 64, 85, 105,
135
14, 32, 50, 72,
94, 116, 134,
152, 174, 200
A3, B10, C2, D14, F6, G10, H8,
J9, K7, L11, M3, P6, P10, R2,
R3, T1, T15
VCCINT (3.3 V Only) 39, 91 51, 58, 123, 130 74, 83, 179, 186 B9, C8, G8, K9, P8
VCCIO (2.5 V or 3.3 V)
(2)
3, 18, 34, 51,
66, 82 24, 50, 73, 76,
95, 115, 144 5, 23, 41, 63, 85,
107, 125, 143,
165, 191
B3, B5, C14, E15, F11, G3, G7,
G15, H9, J8, K10, L3, L6, M15,
P14, T2, T3
No Connect (N.C.) – – 1, 2, 51, 52, 53,
54, 103, 104,
105, 106, 155,
156, 157, 158,
207, 208
A1, A2, A6, A12, A13, A14, A15,
A16, B1, B2, B15, B16, C1, C15,
C16, D1, D3, D15, D16, G1,
G16, H15, H16, J1, K1, L1, L2,
M1, M16, N1, N2, N14, N15,
N16, P1, P2, P15, P16, R1, R14,
R15, R16, T7, T8, T10, T11, T14,
T16
Total User I/O Pins
(3)
84 120 164 164
Altera Corporation 643
MAX 7000A Programmable Logic Device Family Data Sheet
Preliminary Information
Table 30. EPM7256A & EPM7256AE I/O Pin-Outs (Part 1 of 4)
LAB MC 100-Pin
TQFP
144-Pin
TQFP
208-Pin
PQFP
256-Pin
FineLine
BGA
LAB MC 100-Pin
TQFP
144-Pin
TQFP
208-Pin
PQFP
256-Pin
FineLine
BGA
A 1 – – 153 C3 C 33 – 36 108 N4
2 – – – – 34 – – – –
3 – 2 154 C4 35 – 35 109 P3
4 – – – – 36 – – – –
5 – 1 159 E5 37 – 34 110 N3
6 – 143 160 D5 38 – – 111 M4
7 – – – – 39 – – – –
8 2 – 161 C5 40 25 32 112 M2
9 1 – 162 B4 41 24 31 113 L4
10 – – – – 42 – – – –
11 100 142 163 A4 43 23 30 114 L5
12 – – – – 44 – – – –
13 – 141 164 A5 45 22 29 115 K6
14 99 140 166 D6 46 – – 117 K5
15 – – – – 47 – – – –
16 98 139 167 C6 48 21 28 118 K4
B 17 – – 141 F5 D 49 31 44 92 N6
18 – – – – 50 – – – –
19 – 10 142 F2 51 30 43 93 T5
20 – – – – 52 – – – –
21 – 9 144 E1 53 29 42 95 M6
22 – – 145 F4 54 28 41 96 R5
23 – – – – 55 – – – –
24 8 8 146 F3 56 – 40 97 M5
25 7 7 147 E2 57 – – 98 P5
26 – – – – 58 – – – –
27 6 6 148 D2 59 – 39 99 N5
28 – – – – 60 – – – –
29 5 5 149 E3 61 – 38 100 T4
30 – – 150 E4 62 – – 101 R4
31 – – – – 63 – – – –
32 4
(1)
4
(1)
151 D4
(1)
64 27 37 102 P4
644 Altera Corporation
MAX 7000A Programmable Logic Device Family Data Sheet Preliminary Information
E 65 – – 168 B6 G 97 – – 119 K3
66 – – – – 98 – – – –
67 – – 169 E6 99 – 27 120 K2
68 – – – – 100 – – – –
69 – 138 170 F7 101 – 26 121 J7
70 – – 171 E7 102 – – 122 H7
71 – – – – 103 – – – –
72 97 137 172 D7 104 20 25 123 J5
73 96 136 173 C7 105 19 23 124 J2
74 – – – – 106 – – – –
75 94 134 175 B7 107 17 22 126 J3
76 – – – – 108 – – – –
77 93 133 176
(1)
A7 109 16 21 127
(1)
J4
78 – 132 177 F8 110 – – 128 H6
79 – – – – 111 – – – –
80 92 131 178 B8 112 15
(1)
20
(1)
129 J6
(1)
F 81 – – 130 H5 H 113 37 – 79 M8
82 – – – – 114 – – – –
83 – 19 131 H1 115 36 54 80 N8
84 – – – – 116 – – – –
85 – 18 132 H2 117 – 53 81 L8
86 – – 133 H3 118 35 – 84 R7
87 – – – – 119 – – – –
88 14 16 135 H4 120 – 49 86 P7
89 13 15 136 G6 121 – 48 87 N7
90 – – – – 122 – – – –
91 12 14 137 G5 123 – 47 88 M7
92 – – – – 124 – – – –
93 10 12 138 G2 125 33 46 89 L7
94 – – 139 G4 126 – – 90 T6
95 – – – – 127 – – – –
96 9 11 140 F1 128 32 45 91 R6
Table 30. EPM7256A & EPM7256AE I/O Pin-Outs (Part 2 of 4)
LAB MC 100-Pin
TQFP
144-Pin
TQFP
208-Pin
PQFP
256-Pin
FineLine
BGA
LAB MC 100-Pin
TQFP
144-Pin
TQFP
208-Pin
PQFP
256-Pin
FineLine
BGA
Altera Corporation 645
MAX 7000A Programmable Logic Device Family Data Sheet
Preliminary Information
I 129 80 114 197 C11 K 161 – – 38 K11
130 – – – – 162 – – – –
131 81 116 196 B11 163 57 82 37 K12
132 – – – – 164 – – – –
133 – 117 195 A11 165 – 83 36 K14
134 – – 194 F10 166 – – 35 K13
135 – – – – 167 – – – –
136 – 118 193 E10 168 58 84 34 K15
137 – 119 192 A10 169 – 86 33 K16
138 – – – – 170 – – – –
139 83 120 190 C10 171 60 87 31 J13
140 – – – – 172 – – – –
141 84 121 189
(1)
D10 173 61 88 30
(1)
J14
142 – – 188 F9 174 – – 29 J12
143 – – – – 175 – – – –
144 85 122 187 A9 176 62
(1)
89
(1)
28 J11
(1)
J 145 63 – 27 J15 L 177 – – 78 R8
146 – – – – 178 – – – –
147 64 90 26 J16 179 – 55 77 T9
148 – – – – 180 – – – –
149 65 91 25 J10 181 – 56 76 R9
150 – – 24 H14 182 – – 73 N9
151 – – – – 183 – – – –
152 – 92 22 H13 184 40 60 71 M9
153 – 93 21 H12 185 41 61 70 L9
154 – – – – 186 – – – –
155 67 94 20 H11 187 42 62 69 R10
156 – – – – 188 – – – –
157 – 96 19 H10 189 44 63 68 N10
158 – – 18 G11 190 – – 67 M10
159 – – – – 191 – – – –
160 68 97 17 G14 192 45 65 66 L10
Table 30. EPM7256A & EPM7256AE I/O Pin-Outs (Part 3 of 4)
LAB MC 100-Pin
TQFP
144-Pin
TQFP
208-Pin
PQFP
256-Pin
FineLine
BGA
LAB MC 100-Pin
TQFP
144-Pin
TQFP
208-Pin
PQFP
256-Pin
FineLine
BGA
646 Altera Corporation
MAX 7000A Programmable Logic Device Family Data Sheet Preliminary Information
M 193 – 106 4 B14 O 225 – – 49 R13
194 – – – – 226 – – – –
195 75 107 3 C13 227 – 74 48 P13
196 – – – – 228 – – – –
197 – 108 206 B13 229 – 75 47 N13
198 – – 205 F12 230 – – 46 M14
199 – – – – 231 – – – –
200 – 109 204 E12 232 52 77 45 M13
201 76 110 203 D12 233 53 78 44 L13
202 – – – – 234 – – – –
203 77 111 202 C12 235 54 79 43 L14
204 – – – – 236 – – – –
205 – – 201 B12 237 55 80 42 L12
206 78 112 199 E11 238 – – 40 L15
207 – – – – 239 – – – –
208 79 113 198 D11 240 56 81 39 L16
N 209 – – 16 G13 P 241 46 66 65 R11
210 – – – – 242 – – – –
211 69 98 15 G12 243 47 67 64 P11
212 – – – – 244 – – – –
213 – 99 13 F16 245 48 68 62 N11
214 – – 12 F15 246 49 69 61 M11
215 – – – – 247 – – – –
216 70 100 11 F13 248 – – 60 T12
217 – 101 10 F14 249 – 70 59 R12
218 – – – – 250 – – – –
219 71 102 9 E16 251 – – 58 M12
220 – – – – 252 – – – –
221 72 103 8 E14 253 – 71 57 P12
222 – – 7 E13 254 – – 56 N12
223 – – – – 255 – – – –
224 73
(1)
104
(1)
6 D13
(1)
256 50 72 55 T13
Table 30. EPM7256A & EPM7256AE I/O Pin-Outs (Part 4 of 4)
LAB MC 100-Pin
TQFP
144-Pin
TQFP
208-Pin
PQFP
256-Pin
FineLine
BGA
LAB MC 100-Pin
TQFP
144-Pin
TQFP
208-Pin
PQFP
256-Pin
FineLine
BGA
Altera Corporation 647
MAX 7000A Programmable Logic Device Family Data Sheet
Preliminary Information
Notes to tables:
(1) This pin can function as either a JTAG pin or a user I/O pin. If the device is programmed to use the JTAG ports for
BST or in-system programming, this pin is not available as a user I/O pin.
(2) EPM7512AE devices in the 208-pin PQFP package support vertical migration from EPM7256E, EPM7256S, and
EPM7256A devices. EPM7512AE devices contain additional I/O pins which are no connects on the EPM7256E,
EPM7256S, and EPM7256A devices. To support these additional I/O pins, EPM7512AE devices have two additional
VCCIO (pins 105 and 207) and GNDIO (pins 51 and 158) pins that are no-connect pins on the EPM7256E, EPM7256S,
and EPM7256A devices. To achieve vertical migration between the EPM7256A and EPM7512AE devices, the no-
connect pins 105 and 207 may be tied to VCCIO and pins 51 and 158 may be tied to GNDIO on the EPM7256A devices.
On the EPM7256E and EPM7256S devices, these no-connect pins must not be tied to VCCIO or GNDIO.
(3) The user I/O pin count includes dedicated input pins and all I/O pins.
Table 31. EPM7512AE Dedicated Pin-Outs
Dedicated Pin 144-Pin
TQFP
208-Pin
PQFP
(1)
256-Pin
BGA
256-Pin
FineLine BGA
INPUT/GCLK1 125 184 L1 D9
INPUT/GCLRn 127 182 K2 E8
INPUT/OE1 126 183 K1 E9
INPUT/OE2/GCLK2 128 181 K3 D8
TDI
(2)
4 176 A2 D4
TMS
(2)
20 127 B12 J6
TCK
(2)
89 30 V12 J11
TDO
(2)
104 189 Y2 D13
GNDINT 52, 57, 124, 129 75, 82, 180, 185 J20, K4, K18, L2,
L17 A8, C9, G9, K8, P9
GNDIO 3, 13, 17, 33, 59, 64,
85, 105, 135 14, 32, 50, 51, 72,
94, 116, 134, 152,
158, 174, 200
A1, B2, B19, B20,
C3, C18, D4, D17,
U4, U17, V3, V18,
V19, W2, W19, Y1,
Y20
A3, B10, C2, D14,
F6, G10, H8, J9, K7,
L11, M3, P6, P10,
R2, R3, T1, T15
VCCINT 51, 58, 123, 130 74, 83, 179, 186 J1, J19, L4, M19,
M20 B9, C8, G8, K9, P8
VCCIO 24, 50, 73, 76,
95, 115, 144 5, 23, 41, 63, 85,
105, 107, 125, 143,
165, 191, 207
C4, C17, D3, D5,
D16, D18, E4, E17,
T4, T17, U3, U5,
U16, U18, V2, V4,
V17
B3, B5, C14, E15,
F11, G3, G7, G15,
H9, J8, K10,L3, L6,
M15, P14, T2, T3
No Connect (N.C.) – – – –
Total User I/O Pins
(3)
120 176 212 212
648 Altera Corporation
MAX 7000A Programmable Logic Device Family Data Sheet Preliminary Information
Table 32. EPM7512AE I/O Pin-Outs (Part 1 of 8)
LAB MC 144-Pin
TQFP
208-Pin
PQFP
(1)
256-Pin
BGA
256-Pin
FineLine
BGA
LAB MC 144-Pin
TQFP
208-Pin
PQFP
(1)
256-Pin
BGA
256-Pin
FineLine
BGA
A 1 134 173 H3 D7 C 33 142 163 F4 E4
2 – – – – 34 – – – –
3 – – – – 35 – – – –
4 – – – – 36 – – – –
5 – – H2 C7 37 141 164 E3 C5
6 – – – – 38 – – – –
7 – – – – 39 – – – –
8 – – – – 40 – – – –
9 – 175 H1 B7 41 140 166 E2 A5
10 – – – – 42 – – – –
11 133 176
(2)
J4 A7 43 – 167 F3 D5
12 – – – – 44 – – – –
13 – – – – 45 – – – –
14 132 177 J3 F8 46 139 168 E1 E5
15 – – – – 47 – – – –
16 131 178 J2 B8 48 – – F2 E6
B 17 – 169 G4 D6 D 49 2 – B3 B2
18 – – – – 50 – – – –
19 – – – – 51 – – – –
20 – – – – 52 – – – –
21 138 170 F1 C6 53 1 – C2 A2
22 – – – – 54 – – – –
23 – – – – 55 – – – –
24 – – – – 56 – – – –
25 137 171 G3 B6 57 – 159 B1 B4
26 – – – – 58 – – – –
27 136 172 G2 A6 59 – 160 C1 A4
28 – – – – 60 – – – –
29 – – – – 61 – – – –
30 – – G1 F7 62 – 161 D2 C4
31 – – – – 63 – – – –
32 – – H4 E7 64 143 162 D1 C3
Altera Corporation 649
MAX 7000A Programmable Logic Device Family Data Sheet
Preliminary Information
E 65 – – B5 E3 G 97 – – C9 H6
66 – – – – 98 – – – –
67 7 153 C5 C1 99 15 141 D9 G5
68 – – – – 100 – – – –
69 – – D6 B1 101 14 142 A8 G4
70 – – – – 102 – – – –
71 – – – – 103 – – – –
72 – – – – 104 – – – –
73 – 154 A4 A1 105 – 144 B8 G2
74 – – – – 106 – – – –
75 6 155 B4 D2 107 – 145 C8 G1
76 – – – – 108 – – – –
77 – – – – 109 – – – –
78 5 156 A3 D3 110 12 146 D8 G6
79 – – – – 111 – – – –
80 4
(2)
157 A2
(2)
D4
(2)
112 – – A7 F5
F 81 – 147 B7 F2 H 113 19 135 A11 J1
82 – – – – 114 – – – –
83 – 148 C7 F3 115 – 136 A10 H7
84 – – – – 116 – – – –
85 11 149 A6 F1 117 18 137 B10 H5
86 – – – – 118 – – – –
87 – – – – 119 – – – –
88 – – – – 120 – – – –
89 – – D7 F4 121 – – D10 H2
90 – – – – 122 – – – –
91 10 150 B6 E1 123 – 138 C10 H3
92 – – – – 124 – – – –
93 – – – – 125 – – – –
94 9 151 A5 D1 126 – 139 A9 H1
95 – – – – 127 – – – –
96 8 – C6 E2 128 16 140 B9 H4
Table 32. EPM7512AE I/O Pin-Outs (Part 2 of 8)
LAB MC 144-Pin
TQFP
208-Pin
PQFP
(1)
256-Pin
BGA
256-Pin
FineLine
BGA
LAB MC 144-Pin
TQFP
208-Pin
PQFP
(1)
256-Pin
BGA
256-Pin
FineLine
BGA
650 Altera Corporation
MAX 7000A Programmable Logic Device Family Data Sheet Preliminary Information
I 129 – – D12 K1 K 161 29 115 B16 N4
130 – – – – 162 – – – –
131 – 129 C12 J7 163 – 117 C15 M2
132 – – – – 164 – – – –
133 20
(2)
130 B12
(2)
J6
(2)
165 – 118 A17 M1
134 – – – – 166 – – – –
135 – – – – 167 – – – –
136 – – – – 168 – – – –
137 – 131 A12 J5 169 28 119 B15 M4
138 – – – – 170 – – – –
139 – – D11 J4 171 – – D14 M5
140 – – – – 172 – – – –
141 – – – 173 – – – –
142 – 132 C11 J3 174 – 120 A16 L5
143 – – – – 175 – – – –
144 – 133 B11 J2 176 27 121 A15 L4
J 145 – 122 C14 L2 L 177 34 109 A20 R1
146 – – – – 178 – – – –
147 – – B14 L1 179 – – – –
148 – – – – 180 – – – –
149 26 123 A14 K6 181 32 110 A19 P2
150 – – – – 182 – – – –
151 – – – – 183 – – – –
152 – – – – 184 – – – –
153 25 124 D13 K5 185 – 111 B17 N3
154 – – – – 186 – – – –
155 23 126 C13 K4 187 – 112 A18 N2
156 – – – – 188 – – – –
157 – – – – 189 – – – –
158 22 127
(2)
B13 K3 190 31 113 D15 P1
159 – – – – 191 – – – –
160 21 128 A13 K2 192 30 114 C16 N1
Table 32. EPM7512AE I/O Pin-Outs (Part 3 of 8)
LAB MC 144-Pin
TQFP
208-Pin
PQFP
(1)
256-Pin
BGA
256-Pin
FineLine
BGA
LAB MC 144-Pin
TQFP
208-Pin
PQFP
(1)
256-Pin
BGA
256-Pin
FineLine
BGA
Altera Corporation 651
MAX 7000A Programmable Logic Device Family Data Sheet
Preliminary Information
M 193 – 101 E18 P5 O 225 47 88 H19 R7
194 – – – – 226 – – – –
195 – – – – 227 46 89 H18 P7
196 – – – – 228 – – – –
197 – 102 D20 N5 229 45 90 H17 T7
198 – – – – 230 – – – –
199 – – – – 231 – – – –
200 – – – – 232 – – – –
201 37 103 D19 T4 233 – 91 G20 L8
202 – – – – 234 – – – –
203 – 104 C20 R4 235 44 92 G19 N7
204 – – – – 236 – – – –
205 – – – – 237 – – – –
206 36 106 C19 P4 238 – – G18 M7
207 – – – – 239 – – – –
208 35 108 B18 P3 240 43 93 F20 L7
N 209 42 95 G17 R6 P 241 54 79 K20 M9
210 – – – – 242 – – – –
211 – – – – 243 – – – –
212 – – – – 244 – – – –
213 41 96 F19 T6 245 – 80 K19 L9
214 – – – – 246 – – – –
215 – – – – 247 – – – –
216 – – – – 248 – – – –
217 40 97 E20 N6 249 53 81 K17 R8
218 – – – – 250 – – – –
219 39 98 F18 M6 251 – 84 J18 T8
220 – – – – 252 – – – –
221 – – – – 253 – – – –
222 – 99 E19 R5 254 49 86 J17 N8
223 – – – – 255 – – – –
224 38 100 F17 T5 256 48 87 H20 M8
Table 32. EPM7512AE I/O Pin-Outs (Part 4 of 8)
LAB MC 144-Pin
TQFP
208-Pin
PQFP
(1)
256-Pin
BGA
256-Pin
FineLine
BGA
LAB MC 144-Pin
TQFP
208-Pin
PQFP
(1)
256-Pin
BGA
256-Pin
FineLine
BGA
652 Altera Corporation
MAX 7000A Programmable Logic Device Family Data Sheet Preliminary Information
Q 257 55 78 L20 N9 S 289 66 62 P17 K11
258 – – – – 290 – – – –
259 – – – – 291 – – – –
260 – – – – 292 – – – –
261 – 77 L19 T9 293 67 61 R19 M12
262 – – – – 294 – – – –
263 – – – – 295 – – – –
264 – – – – 296 – – – –
265 56 76 L18 R9 297 68 60 T20 N12
266 – – – – 298 – – – –
267 – 73 M18 L10 299 69 59 R18 T12
268 – – – – 300 – – – –
269 – – – – 301 – – – –
270 60 71 M17 M10 302 – 58 T19 R12
271 – – – – 303 – – – –
272 61 70 N20 N10 304 70 57 T18 T13
R 273 62 69 N19 R10 T 305 – 56 R17 P12
274 – – – – 306 – – – –
275 63 68 N18 T10 307 – – – –
276 – – – – 308 – – – –
277 – 67 N17 M11 309 – 55 U20 T14
278 – – – – 310 – – – –
279 – – – – 311 – – – –
280 – – – – 312 – – – –
281 – 66 P20 N11 313 71 54 U19 P13
282 – – – – 314 – – – –
283 65 65 P19 P11 315 72 53 V20 R13
284 – – – – 316 – – – –
285 – – – – 317 – – – –
286 – – P18 R11 318 – 52 W20 R14
287 – – – – 319 – – – –
288 – 64 R20 T11 320 74 49 W18 R15
Table 32. EPM7512AE I/O Pin-Outs (Part 5 of 8)
LAB MC 144-Pin
TQFP
208-Pin
PQFP
(1)
256-Pin
BGA
256-Pin
FineLine
BGA
LAB MC 144-Pin
TQFP
208-Pin
PQFP
(1)
256-Pin
BGA
256-Pin
FineLine
BGA
Altera Corporation 653
MAX 7000A Programmable Logic Device Family Data Sheet
Preliminary Information
U 321 75 48 Y19 P15 W 353 82 35 W14 L16
322 – – – – 354 – – – –
323 – – – – 355 – – Y14 L13
324 – – – – 356 – – – –
325 – 47 Y18 N15 357 83 34 U13 L12
326 – – – – 358 – – – –
327 – – – – 359 – – – –
328 – – – – 360 – – – –
329 – 46 W17 T16 361 84 33 V13 K12
330 – – – – 362 – – – –
331 – 45 Y17 R16 363 86 31 W13 K14
332 – – – – 364 – – – –
333 – – – – 365 – – – –
334 77 44 U15 P16 366 87 30
(2)
Y13 K15
335 – – – – 367 – – – –
336 78 43 V16 N14 368 88 29 U12 K16
V 337 79 42 W16 N16 X 369 89
(2)
– V12
(2)
J11
(2)
338 – – – – 370 – – – –
339 80 40 V15 M14 371 – 28 W12 J12
340 – – – – 372 – – – –
341 – 39 Y16 N13 373 – 27 Y12 J13
342 – – – – 374 – – – –
343 – – – – 375 – – – –
344 – – – – 376 – – – –
345 81 38 W15 M16 377 – 26 V11 J14
346 – – – – 378 – – – –
347 – – U14 M13 379 – – U11 J15
348 – – – – 380 – – – –
349 – – – – 381 – – – –
350 – 37 Y15 L14 382 – 25 W11 K13
351 – – – – 383 – – – –
352 – 36 V14 L15 384 90 24 Y11 J16
Table 32. EPM7512AE I/O Pin-Outs (Part 6 of 8)
LAB MC 144-Pin
TQFP
208-Pin
PQFP
(1)
256-Pin
BGA
256-Pin
FineLine
BGA
LAB MC 144-Pin
TQFP
208-Pin
PQFP
(1)
256-Pin
BGA
256-Pin
FineLine
BGA
654 Altera Corporation
MAX 7000A Programmable Logic Device Family Data Sheet Preliminary Information
Y 385 91 22 Y10 H10 AA 417 – 10 V7 F14
386 – – – – 418 – – – –
387 – 21 W10 H11 419 – 9 Y6 F15
388 – – – 420 – – – –
389 92 20 V10 H12 421 98 8 U7 F16
390 – – – – 422 – – – –
391 – – – – 423 – – – –
392 – – – – 424 – – – –
393 – – U10 H15 425 – – W6 E12
394 – – – – 426 – – – –
395 – 19 Y9 H16 427 99 7 Y5 E13
396 – – – – 428 – – – –
397 – – – – 429 – – – –
398 – 18 W9 H14 430 100 6 V6 E14
399 – – – – 431 – – – –
400 93 17 V9 H13 432 101 – W5 E16
Z 401 – – U9 G12 BB 433 – – V5 D16
402 – – – – 434 – – – –
403 – 16 Y8 G13 435 102 4 U6 C16
404 – – – – 436 – – – –
405 94 15 W8 G14 437 – – Y4 B16
406 – – – – 438 – – – –
407 – – – – 439 – – – –
408 – – – – 440 – – – –
409 96 13 V8 G16 441 – 3 W4 A16
410 – – – – 442 – – – –
411 – 12 U8 G11 443 103 2 Y3 D15
412 – – – – 444 – – – –
413 – – – – 445 – – – –
414 97 11 Y7 F12 446 104
(2)
1 Y2
(2)
D13
(2)
415 – – – – 447 – – – –
416 – – W7 F13 448 106 208 W3 C15
Table 32. EPM7512AE I/O Pin-Outs (Part 7 of 8)
LAB MC 144-Pin
TQFP
208-Pin
PQFP
(1)
256-Pin
BGA
256-Pin
FineLine
BGA
LAB MC 144-Pin
TQFP
208-Pin
PQFP
(1)
256-Pin
BGA
256-Pin
FineLine
BGA
Altera Corporation 655
MAX 7000A Programmable Logic Device Family Data Sheet
Preliminary Information
CC 449 – – W1 B15 EE 481 – 196 P3 D11
450 – – – – 482 – – – –
451 – – – – 483 – – – –
452 – – – – 484 – – – –
453 107 – V1 A15 485 113 195 P2 C11
454 – – – – 486 – – – –
455 – – – – 487 – – – –
456 – – – – 488 – – – –
457 108 206 U2 B14 489 114 194 P1 A11
458 – – – – 490 – – – –
459 – 205 U1 A14 491 116 193 N4 B11
460 – – – – 492 – – – –
461 – – – – 493 – – – –
462 – 204 T3 B13 494 117 – N3 F10
463 – – – – 495 – – – –
464 109 203 R4 A13 496 – – N2 E10
DD 465 – 202 T2 C13 FF 497 118 192 N1 D10
466 – – – – 498 – – – –
467 – – – – 499 – – – –
468 – – – – 500 – – – –
469 110 201 R3 D12 501 – – M4 C10
470 – – – – 502 – – – –
471 – – – – 503 – – – –
472 – – – – 504 – – – –
473 111 199 T1 C12 505 119 190 M3 A10
474 – – – – 506 – – – –
475 – 198 R2 B12 507 120 189
(2)
M2 J10
476 – – – – 508 – – – –
477 – – – – 509 – – – –
478 112 197 P4 A12 510 121 188 M1 F9
479 – – – – 511 – – – –
480 – – R1 E11 512 122 187 L3 A9
Table 32. EPM7512AE I/O Pin-Outs (Part 8 of 8)
LAB MC 144-Pin
TQFP
208-Pin
PQFP
(1)
256-Pin
BGA
256-Pin
FineLine
BGA
LAB MC 144-Pin
TQFP
208-Pin
PQFP
(1)
256-Pin
BGA
256-Pin
FineLine
BGA
656 Altera Corporation
MAX 7000A Programmable Logic Device Family Data Sheet Preliminary Information
Notes to tables:
(1) The EPM7512AE device in the 208-pin PQFP package supports vertical migration from the EPM7256E, EPM7256S,
and EPM7256A devices. The EPM7512AE device contains additional I/O pins which are no connects on the
EPM7256E, EPM7256S, and EPM7256A devices. To support these additional I/O pins, the EPM7512AE device has
two additional VCCIO (pins 105 and 207) and GNDIO (pins 51 and 158) pins that are no-connect pins on the
EPM7256E, EPM7256S, and EPM7256A devices. To achieve vertical migration between the EPM7256A and
EPM7512AE devices, the no-connect pins 105 and 207 may be tied to VCCIO and pins 51 and 158 may be tied to
GNDIO on the EPM7256A devices. On the EPM7256E and EPM7256S devices, these no-connect pins must not be
tied to VCCIO or GNDIO. EPM7512AE devices have identical pin-outs.
(2) This pin may function as either a JTAG port or a user I/O pin. If the device is configured to use the JTAG ports for
in-system programming, this pin is not available as a user I/O pin.
(3) The user I/O pin count includes dedicated input pins and all I/O pins.
Figures 14 through 21 show the package pin-out diagrams for
MAX 7000A devices.
Figure 14. 44-Pin PLCC/TQFP Package Pin-Out Diagram
Package outlines not drawn to scale.
44-Pin PLCC
I/O
I/O
I/O
VCC
INPUT/OE2/(GCLK2)
INPUT/GCLRn
INPUT/OE1n
INPUT/GCLK1
GND
I/O
I/O
I/O
I/O/(TDO)
I/O
I/O
VCC
I/O
I/O
I/O/(TCK)
I/O
GND
I/O
I/O
I/O
I/O
I/O
GND
VCC
I/O
I/O
I/O
I/O
I/O
6 5 4 3 2 1 44 43 42 41 40
18 19 20 21 22 23 24 25 26 27 28
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
EPM7032AE
EPM7064AE
I/O/(TDI)
I/O
I/O
GND
I/O
I/O
I/O/(TMS)
I/O
VCC
I/O
I/O
44-Pin TQFP
Pin 12 Pin 23
Pin 34
Pin 1
I/O
I/O
I/O
VCC
INPUT/OE2/(GCLK2)
INPUT/GCLRn
INPUT/OE1n
INPUT/GCLK1
GND
I/O
I/O
I/O
I/O/(TDO)
I/O
I/O
VCC
I/O
I/O
I/O/(TCK)
I/O
GND
I/O
I/O
I/O
I/O
I/O
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O/(TDI)
I/O
I/O
GND
I/O
I/O
I/O/(TMS)
I/O
VCC
I/O
I/O
EPM7032AE
EPM7064AE
Altera Corporation 657
MAX 7000A Programmable Logic Device Family Data Sheet
Preliminary Information
Figure 15. 84-Pin PLCC Package Pin-Out Diagram
Package outline not drawn to scale.
Figure 16. 100-Pin TQFP Package Pin-Out Diagram
Package outline not drawn to scale.
I/O
VCCIO
I/O/TDI
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O/TMS
I/O
VCCIO
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
VCCINT
INPUT/OE2/GCLK2
INPUT/GLCRn
INPUT/OE1
INPUT/GCLK1
GND
I/O
I/O
I/O
VCCIO
I/O
I/O
I/O
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
11
10
9
8
7
6
5
4
3
2
1
84
83
82
81
80
79
78
77
76
75
I/O
I/O
GND
I/O/TDO
I/O
I/O
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O/TCK
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCIO
I/O
I/O
I/O
GND
VCCINT
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
VCCIO
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
EPM7128A
EPM7128AE
I/O
Pin 1
Pin 26
Pin 76
Pin 51
EPM7064AE
EPM7128A
EPM7128AE
EPM7256A
EPM7256AE
658 Altera Corporation
MAX 7000A Programmable Logic Device Family Data Sheet Preliminary Information
Figure 17. 100-Pin FineLine BGA Package Pin-Out Diagram
Figure 18. 144-Pin TQFP Package Pin-Out Diagram
Package outline not drawn to scale
.
Indicates
location of
Ball A1
A1 Ball
Pad Corner
A
B
C
D
E
F
G
H
J
K
10 9 8 7 6 5 4 3 2 1
EPM7064AE
EPM7128A
EPM7128AE
EPM7256AE
Package outline not drawn to scale.
Indicates location
of Pin 1
Pin 1 Pin 109
Pin 73
Pin 37
EPM7128A
EPM7128AE
EPM7256A
EPM7256AE
EPM7512AE
Altera Corporation 659
MAX 7000A Programmable Logic Device Family Data Sheet
Preliminary Information
Figure 19. 208-Pin PQFP Package Pin-Out Diagram
Package outline not drawn to scale
.
Pin 1 Pin 157
Pin 105Pin 53
EPM7256A
EPM7256AE
EPM7512AE
660 Altera Corporation
MAX 7000A Programmable Logic Device Family Data Sheet Preliminary Information
Figure 20. 256-Pin BGA Package Pin-Out Diagram
Package outline not drawn to scale.
Indicates
Location of
Ball A1
A1 Ball
Pad Corner
G
F
E
D
C
B
A
H
J
K
L
M
N
P
R
T
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
EPM7512AE
U
V
W
X
Y
17181920
Altera Corporation 661
MAX 7000A Programmable Logic Device Family Data Sheet
Preliminary Information
Figure 21. 256-Pin FineLine BGA Package Pin-Out Diagram
Package outline not drawn to scale
.
Revision
History
The information contained in the MAX 7000A Programmable Logic Device
Family Data Sheet version 2.01 supersedes information published in
previous versions. The following changes were made to MAX 7000A
Programmable Logic Device Family Data Sheet version 2.01:
■Note (2) on page 618 was updated.
■Minor stylistic changes were made throughout the data sheet.
Indicates
Location of
Ball A1
A1 Ball
Pad Corner
G
F
E
D
C
B
A
H
J
K
L
M
N
P
R
T
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
EPM7128A
EPM7128AE
EPM7256A
EPM7256AE
EPM7512AE
Copyright © 1995, 1996, 1997, 1998, 1999 Altera Corporation, 101 Innovation Drive,
San Jose, CA 95134, USA, all rights reserved.
By accessing this information, you agree to be bound by the terms of Altera’s
Legal Notice.
