High Power 53mm Silicon Controlled Rectifier 1000 A Avy. The C702 Reverse Blocking Thyristor now has extended voltage blocking capability through unique multi-diffusion processing of 53 mm nominal silicon without sacrificing essential ratings and characteristics. The C702 is designed specifically for phase control applications like DC motor control, power supplies, cycloconverters and load commutated inverters. FEATURES Optimized pilot gate for high di/dt rating @ Excellent withstand to high dv/dt voltage fronts @ Enhanced surge and It ratings for fuse coordination @ Glazed-fluted ceramic with metal metal welded seal 1.0 in., 25.4 mm creepage % in., 15.9 mm clearance MAXIMUM ALLOWABLE RATINGS Up To 3200 Volts C702 THYRISTOR (SCR) PRESSPAK REPETITIVE PEAK OFF-STATE REPETHNTIVE PEAK OFF-STATE TRANSIENT PEAK REVERSE TYPE AND REVERSE VOLTAGE AND REVERSE VOLTAGE VOLTAGE, Vrsm' VornM/VRRM VoRM/VRAM Tj= -40C to OC T y= -40C to +125C Ty = GOC to +125C C702CB 3200 Volts 3300 Volts 3300 Volts C702CA 3100 3200 3200 C702CP 3000 3100 3100 C702LT 2900 3000 3000 C702LN 2300 2900 2500 C702LS 2700 2800 2800 C702LM 2600 2700 2700 C702LE 2500 2600 2600 C702LD 2400 2500 2500 C702LC 2300 2400 2400 C702LB 2200 2300 2300 Average Forward Current, On-State @ Tease = 70C, IT( AV)... ccc e cece eee ec eee ee eee e eee ence eae neean ee nee nen tee neaee 1000A Peak One-Cycle Surge On-State Current, ITSM Cy 16KA LOOMS 20... cece cece eee teen eee een b acer eenen eee et neeenenenes iSKA Maximum Repetitive Rate-of-Rise of Anode Current @ [S00V bias .......0:-cccseceeeeeeneeene ree eeeeeteneeeereneees 100A; us (Switching Rates < 60 Hz; snubber discharge < 65A; see required gate drive) I"t (for fusing) (at 8.3 milliseconds) Peak Gate Power Dissipation, PGM ....-.....-.eeccsesseenes bas ede pentane e cee e ee beat eee eect enone eegenenate 200 W @ 40us pulse Average Gate Power Dissipation, PG(AV) --.-----.-.ceceeecececerer seer enenn een ee eee ee ete se eu eau nents esas taebtasteaeanaeee 20W Peak Reverse Gate Voltage, VGRM..-c.ccscccescccnteeeeeceene nese eee pa snes ener est en ene n nage eee EES H Eee eee SES ESD EG ESSE ES 20V Peak Gate Current ....-...... 2000 ccce cece cence reer e ee nee eee Ene EET AE ESS DEES E Scan EEO ESS poet eee e eden e tebe eererens 158A Storage Temperature, TSTG .....-.----000055 vee ee eee see bb nebo eee nen ened eaeeeee tener sneeateneetenseaersusenees APC to +150C Operating Temperature, T]..........2.2.. 00200200202 cece cece eee ce eee eee eens needa ene nas ae ene eeeaeennee 40C to +125C Mounting Force Required .......... 2.0.0. cccccc cece cence nee ee nee EERE e ORE EERO EERO OE EEE EE EERE ETRE RCE RHEE EES 5000 - 6000 Ib. 22.4 = 26.7 KN NOTES: 1. Half sine pulse, l0rmms MAXIMUM pulse width, non repetitive 2. Assume presspak mounted to heat dissipator of Jess than 0.3 C; W 3. All ratings and tests in accordance with NEMA-ELA JEDEC Standard RS-397 1 of 4 175 Great Valley Pkwy., Malvern, PA 19355, USA C702 Rev. A 9/17/2001CHARACTERISTICS Characteristic Symbol Min. Typ. Max. Units Test Conditions or Qualifications Peak reverse and off- istate leakage current @ Vorm Vram 10 ma -|Tj = 25C, opened gate @ Voam Vram 200 125C, opened gate @ 0.8 Vpam 0.8 Vaam 75 125C, opened gate Critical rate of rise at off- state voltage (higher dvidt 500 1000 Vis |. may cause destructive Tj = 125C opened gate switching) Vp = 0.8 Vorm 25 See gate Delay Time ty 1. 5 us Vp = 1500V source , Vp = 500V below IT = 1000A, 125C Peak On-State Voliage Vim 1.5 Vv Half sine pulse 8.3 msec Vp = 10V DC Gate Trigger Current ler 200 ma To = 25C, Vp = 10V (not for operational use} 5 Te = 125C, Vp = 0.5Vonm DC Gate Trigger Current 45 Te = 25C, Vp =10V (not for operational use) Ver Vv . 0.5 To = 125C, Vp = 0.5Vbam Te = 125C, IT = 1000A, 10A/us Min, Circuit Commutated Reverse Voltage = 100V , L Turn-off Time 4 125 250 as Reapplied off-state voltage 20 Vims to 2000 volts Tj) = 25C, di/dt = -0.5ma/us Holding Current | 3 S, (200420, 105C E = 7.5 Vis oreing wurren H 35 50 100 125C R=109 Freq = 60 Hz 250 450 800 560 Tj = 725C, Gate Drive Latching Current I 175 315 500 ma | 705C, 30V 10a 155 285 125C, duration 15us * DC trigger current and voltage are indicated as a characieristic. Turn-on in this manner will not support rated di/dt. Oo 200 AMPERES. 3 Ss 3 3 s Ty = 125S n < . 8 10 z = : . my 1 2 5 4 5 5 7 +o 2 3 2 3 13 ON-STATE VOLTAGE = VOLTS TIME BASE WIDTH - m sec MAXIMUM FORWARD CONDUCTION NON-REPETITIVE Its AND [7T CAPABILITY CHARACTERISTIC ON-STATE FOR FUSE COORDINATION 2of 4 175 Great Valley Pkwy., Malvern, PA 19355, USA C702 Rev. A 9/17/2001 {KA} 15MSWITCHING VOLTAGE Vp (VOLTS) C 8 8 2 110 Q 180 CONDUCTION ANGLE 100 MAXIMUM ALLOWABLE CASE TEMPERATURE 8 0 200 400 600 800 = 1,000 1.200 1.400 AVERAGE ON-STATE CURRENT - AMPERES MAXIMUM ALLOWABLE CASE TEMPERATURES FOR SINUSOIDAL CURRENT WAVEFORM DOUBLE-SIDE COOLED 1.600 1.800 CONDUCTION ANGLE = 60 90120 180* Hz D. or 180* 2 ~~ _ CONDUCTION ANGLE AVERAGE ON-STATE POWER DISSIPATION WATTS oo iy 1 2 4 6 8 1 2 4 6 8 TO AVERAGE ON-STATE CURRENT AMPERES AVERAGE FORWARD POWER DISSIPATION FOR SINUSOIDAL CURRENT WAVEFORM ~ N\ oN \ 2000 > GATE SUPPLY 30V/10f is SE5A 1500 CIRCLHT M difdt N 4 GATE SUPPLY a ma 20v/700 1000 p ts AS is S50A Ug ON 600 30 50 100 200 MAXIMUM ALLOWABLE [NRUSH CURRENT di/dt, Ais NOTE: ALLOW 25% HIGHER di/dt FOR SINGLE SHOT (NON-REPETITIVE) MAXIMUM ALLOWABLE INRUSH CURRENT, CIRCUIT DI/DT AND SNUBBER DISCHARGE IS FOR TWO LEVELS OF GATE DRIVE 8 8 110 1 Pe DUTY CYCLE (%) = 100 8 70 21623 13 | 3 MAXIMUM ALLOWABLE CASE TEMPERATURE - C & & a 200 400 600 B00 1,000 1.200 7.400 1,600 (71,800 AVERAGE ON-STATE CURRENT - AMPERES MAXIMUM ALLOWABLE CASE TEMPERATURES FOR RECTANGULAR CURRENT WAVEFORM DOUBLE-SIDE COOLED PERCENT OUTY CYCLE = 162/3 214, 59 ZZ. ~L DUTY CYCLE (%} = 100 (t/T) AVERAGE ON-STATE POWEA DISSIPATION WATTS WW 2 4 6 B81 2 4 4 AVERAGE ON-STATE CURRENT AMPERES AVERAGE FORWARD POWER DISSIPATION FOR RECTANGULAR CURRENT WAVEFORM 400 yoo. Tas 128C a I> 1000 200 vane g ' c IREC wh 3 n we E 6 g 40 wr = 20 wy 2 4 za di/et (amps/ies) PEAK RECOVERY CURRENT VERSUS COMMUTATING CIRCUIT DI/DT 3 of 4 175 Great Valley Pkwy., Malvern, PA 19355, USA C702 Rev A 9/11/2001& T Thyristor Gate Impedance MAXIMUM This is enhanced by fast rising gate voltage, increasing anode bias and DYNAMIC temperature. INST. VOLTAGE (VOLTS) > It is shown at a minimum for de voltage, zero bias and low temperature. -~ It is shown at a maximum for operating bias and recommended gate . drive. Gate Suppty Load fines (A) and (B) are applicable in accordance with di/dt ratings. = o The short circuit current rise time should be approximately 0.5us and the duration longer than the delay time expected for the thyristor. TO CATHO f aera GATE SUPPLY was OR GATE GK Minimum Acceptable Gate Current The intersection of load line and gate characteristic (encircled) indicates the minimum value of actual current flowing into the gate that is required during the delay time interval needed for the published di, dt and snubber discharge ratings. MINIMUM STATIG 1 2 3 INSTANTANEOUS CURRENT (4} GATE SUPPLY Igg OR THYRISTOR GATE Ick RB 02 01 3 8 TRANSIENT THERMAL IMPEDANCE *C/WATT 001 oO 02 04.06 08.1 TIME SECONDS NOTES: 1. Add .006C,W to account for both case to dissipator interfaces when properly mounted: .g.. Rays = 020C W. See Mounting Instructions. 2. DC Thermal Impedance is based on average full cycle junction temperature. Instantaneous junction temperature may be. calculated using the following modifications: @ end of conducting portion of cycle 120 sq. wave add .0025C W along entire curve 180 sq. wave add .0018C W along entire curve 180 sine wave add .0010C: W along entire curve end of evcle any wave, subtract .O01C: W along entire curve. 3. Ask for general mounting instructions. 2 4 6 6T as OUTLINE DRAWING inches Millimeters Symbol Notes CATHODE Min. Max. Min. Max. A 6.200 6.240 ,08 6.10 1 oB 0.149 =_ 3.56 ANODE ELEMENTARY DIAG c 16.000 | 20.000 | 406.40 | 508.00 @D 1.700 } 1.900 43.18 48.26 E -_ 2.960 - 75.48 PLATED Sunrex 20 F 1.000 1.070 25.40 27.18 eee ae , vee TERMINAL @) WHITE WIRE G - _ 2 ~ 2 termina, @ RED wiRE SEE NOTE | ~t ; SEE NOTE 2 oe H 005 067 0.13 1.70 rene Xo ob "J oJ 0.136 0.146 3.45 37 PLATED i i K 070 100 1.78 2.54 SURF i. _ c ad sree . ; L 2500 | 63.50 M 030 _- 0.76 - 4. Anode-Cathede Pole Faces @ ( Nickel Plated Copper. NOUES . Mating Surface Requirement TIR <.0005 inch Finish 32. 6. Mounting Force. 5000-6000 Lb., 22.4-26.7 KN- 1. Comour and orientation of term lugs is undefined. 2 Glazed ceramicinsulator with |O0inch (25.40 mm) surface creepage. min. 9. Electrical Insulation. Glazed Ceramic, Creepage in. (25.4mm), Strike % in. (]5.9mm) B. Gate Leads G) G [8 in. #22 Terminated with #8 Ring Terminal, Cathode Wire-Red, Gate Wire-White. 4of4 175 Great Valley Pkwy., Malvern, PA 19355, USA C702 Rev. A 9/17/2001