LT3055 Series
1
Rev. B
For more information www.analog.com
TYPICAL APPLICATION
FEATURES DESCRIPTION
500mA, Linear Regulator
with Precision Current Limit
and Diagnostics
The LT
®
3055 series are micropower, low noise, low dropout
voltage (LDO) linear regulators. The devices supply 500mA
of output current with a dropout voltage of 350mV. A 10nF
bypass capacitor reduces output noise to 25μVRMS in a
10Hz to 100kHz bandwidth and soft starts the reference.
The LT3055’s ±45V input voltage rating combined with its
precision current limit and diagnostic functions make the
IC an ideal choice for robust, high reliability applications.
A single resistor programs the LT3055’s current limit, ac-
curate to ±10% over a wide input voltage and temperature
range. Another resistor programs the LT3055’s minimum
output current monitor, useful for detecting open-circuit
conditions. The current monitor function sources a current
equal to 1/500th of output current. Logic fault pins assert
low if the LT3055 is in current limit (FAULT2), operating
below its minimum output current (FAULT1) or is in thermal
limit (both FAULT1 and FAULT2). PWRGD indicates output
regulation. The TEMP pin indicates average die temperature.
The LT3055 optimizes stability and transient response
with low ESR ceramic capacitors, requiring a minimum of
3.3μF. Internal protection circuitry includes current limit-
ing, thermal limiting, reverse battery protection, reverse
current protection and reverse output protection.
The LT3055 is available in fixed output voltages of 3.3V
and 5V, and as an adjustable device with an output voltage
range from 0.6V to 40V.
5V Supply with 497mA Precision Current Limit, 10mA IMIN
Precision Current Limit, RIMAX = 604Ω
APPLICATIONS
n Output Current: 500mA
n Dropout Voltage: 350mV
n Input Voltage Range: 1.6V to 45V
n Programmable Precision Current Limit: ±10%
n Output Current Monitor: 1/500th of IOUT
n Programmable Minimum IOUT Monitor
n Temperature Monitor: 10mV/°C
n FAULT Indicator: Current Limit, Thermal Limit or
Minimum IOUT
n Low Noise: 25μVRMS (10Hz to 100kHz)
n Adjustable Output (VREF = VOUT(MIN) = 0.6V)
n Output Tolerance: ±2% Over Load, Line and Temperature
n Stable with Low ESR, Ceramic Output Capacitors
(3.3μF Minimum)
n Shutdown Current: <1μA
n Reverse Battery and Thermal Limit Protection
n 16-Lead 4mm × 3mm DFN and MSOP Packages
n Protected Antenna Supplies
n Automotive Telematics
n Industrial Applications (Trucks, Forklifts, etc.)
n High Reliability Applications
n Noise-Sensitive RF or DSP Supplies
All registered trademarks and trademarks are the property of their respective owners.
+OUT
SENSE
LT3055-5
GND
ADJ
IN
IMAX
IMIN
PWRGD
SHDN
200k200k200k
1k
(ADC
FULL-SCALE = 1V)
604Ω
(THRESHOLD = 497mA)
10nF 10µF10µF
22nF
120k
(THRESHOLD = 10mA)
0.1µF
V
IN
6V
5V
IMON
0.1µF
10nF
3055 TA01a
TO
µP
ADC
TEMP
REF/BYP
TO
µP
ADC
FAULT1
FAULT2
TEMPERATURE (°C)
–75
CURRENT LIMIT FAULT THRESHOLD (mA)
510
530
550
125
3055 TA01b
490
470
500
520
540
480
460
450 –25 25 75
–50 150
050 100 175
VOUT(NOMINAL) = 5V
VIN = 7V
VIN = 5.6V
Document Feedback
LT3055 Series
2
Rev. B
For more information www.analog.com
ABSOLUTE MAXIMUM RATINGS
IN Pin Voltage .........................................................±50V
OUT Pin Voltage ........................................... +40V, –50V
Input-to-Output Differential Voltage ..............+50V, –40V
ADJ Pin Voltage ......................................................±50V
SENSE Pin Voltage ..................................................±50V
SHDN Pin Voltage ...................................................±50V
FA U LT1, FA U LT2 , PWRGD Pin Voltage ............–0.3V, 50V
IMON Pin Voltage ..............................................–0.3V, 7V
IMIN Pin Voltage ...............................................–0.3V, 7V
IMAX Pin Voltage ..............................................–0.3V, 7V
(Note 1)
1
2
3
4
5
6
7
8
IN
IN
SHDN
FAULT1
FAULT2
PWRGD
TEMP
IMON
16
15
14
13
12
11
10
9
OUT
OUT
ADJ/SENSE**
GND/ADJ*
GND
REF/BYP
IMAX
IMIN
TOP VIEW
17
GND
MSE PACKAGE
16-LEAD PLASTIC MSOP
TJMAX = 125°C, θJA = 37°C/W, θJC = 5°C/W TO 10°C/W
TJMAX = 150°C FOR H-GRADE
EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB
16
15
14
13
12
11
10
9
17
GND
1
2
3
4
5
6
7
8
OUT
OUT
ADJ/SENSE**
GND/ADJ*
GND
REF/BYP
IMAX
IMIN
IN
IN
SHDN
FAULT1
FAULT2
PWRGD
TEMP
IMON
TOP VIEW
DE PACKAGE
16-LEAD (4mm × 3mm) PLASTIC DFN
TJMAX = 125°C, θJA = 38°C/W, θJC = 4.3°C/W
EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB
*PIN 13 IS GND FOR LT3055; PIN 13 IS ADJ FOR LT3055-3.3 AND LT3055-5.
**PIN 14 IS ADJ FOR LT3055; PIN 14 IS SENSE FOR LT3055-3.3 AND LT3055-5.
PIN CONFIGURATION
TEMP Pin Voltage ............................................–0.3V, 7V
REF/BYP Pin Voltage ...................................................1V
Output Short-Circuit Duration .......................... Indefinite
Operating Junction Temperature Range (Notes 2, 3)
E-, I-Grades ....................................... –40°C to 125°C
MP-Grade .......................................... –55°C to 150°C
H-Grade ............................................. –40°C to 150°C
Storage Temperature Range .................. –65°C to 150°C
Lead Temperature: (Soldering, 10 sec)
MSOP Package Only ......................................... 300°C
LT3055 Series
3
Rev. B
For more information www.analog.com
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LT3055EMSE#PBF LT3055EMSE#TRPBF 3055 16-Lead Plastic MSOP –40°C to 125°C
LT3055IMSE#PBF LT3055IMSE#TRPBF 3055 16-Lead Plastic MSOP –40°C to 125°C
LT3055MPMSE#PBF LT3055MPMSE#TRPBF 3055 16-Lead Plastic MSOP –55°C to 150°C
LT3055HMSE#PBF LT3055HMSE#TRPBF 3055 16-Lead Plastic MSOP –40°C to 150°C
LT3055EMSE-3.3#PBF LT3055EMSE-3.3#TRPBF 305533 16-Lead Plastic MSOP –40°C to 125°C
LT3055IMSE-3.3#PBF LT3055IMSE-3.3#TRPBF 305533 16-Lead Plastic MSOP –40°C to 125°C
LT3055MPMSE-3.3#PBF LT3055MPMSE-3.3#TRPBF 305533 16-Lead Plastic MSOP –55°C to 150°C
LT3055HMSE-3.3#PBF LT3055HMSE-3.3#TRPBF 305533 16-Lead Plastic MSOP –40°C to 150°C
LT3055EMSE-5#PBF LT3055EMSE-5#TRPBF 30555 16-Lead Plastic MSOP –40°C to 125°C
LT3055IMSE-5#PBF LT3055IMSE-5#TRPBF 30555 16-Lead Plastic MSOP –40°C to 125°C
LT3055MPMSE-5#PBF LT3055MPMSE-5#TRPBF 30555 16-Lead Plastic MSOP –55°C to 150°C
LT3055HMSE-5#PBF LT3055HMSE-5#TRPBF 30555 16-Lead Plastic MSOP –40°C to 150°C
LT3055EDE#PBF LT3055EDE#TRPBF 3055 16-Lead (4mm × 3mm) Plastic DFN –40°C to 125°C
LT3055IDE#PBF LT3055IDE#TRPBF 3055 16-Lead (4mm × 3mm) Plastic DFN –40°C to 125°C
LT3055EDE-3.3#PBF LT3055EDE-3.3#TRPBF 05533 16-Lead (4mm × 3mm) Plastic DFN –40°C to 125°C
LT3055IDE-3.3#PBF LT3055IDE-3.3#TRPBF 05533 16-Lead (4mm × 3mm) Plastic DFN –40°C to 125°C
LT3055EDE-5#PBF LT3055EDE-5#TRPBF 30555 16-Lead (4mm × 3mm) Plastic DFN –40°C to 125°C
LT3055IDE-5#PBF LT3055IDE-5#TRPBF 30555 16-Lead (4mm × 3mm) Plastic DFN –40°C to 125°C
Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix
LT3055 Series
4
Rev. B
For more information www.analog.com
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 2)
PARAMETER CONDITIONS MIN TYP MAX UNITS
Minimum Input Voltage (Notes 3, 11, 17) ILOAD = 500mA l 1.6 2.2 V
Regulated Output Voltage (Note 4) LT3055-3.3: VIN = 3.9V, ILOAD = 1mA
3.9V < VIN < 45V, 1mA < ILOAD < 500mA
l
3.267
3.234
3.3
3.3
3.333
3.336
V
V
LT3055-5: VIN = 3.9V, ILOAD = 1mA
5.6V < VIN < 45V, 1mA < ILOAD < 500mA
l
4.95
4.9
5
5
5.05
5.1
V
V
ADJ Pin Voltage (Notes 3, 4) LT3055: VIN = 2.2V, ILOAD = 1mA
2.2V < VIN < 45V, 10mA < ILOAD < 500mA
l
594
588
600 606
612
mV
mV
Line Regulation (Note 3) LT3055: ∆VIN = 2.2V to 45V, ILOAD = 1mA
LT3055-3.3: ∆VIN = 3.9V to 45V, ILOAD = 1mA
LT3055-5: ∆VIN = 5.6V to 45V, ILOAD = 1mA
l
l
l
0.25
1.4
2
3
19.5
30
mV
mV
mV
Load Regulation (Note 3) LT3055: VIN = 2.2V, ILOAD = 1mA to 500mA
LT3055-3.3: VIN = 4.3V, ILOAD = 1mA to 500mA
LT3055-5: VIN = 6V, ILOAD = 1mA to 500mA
l
l
l
0.5
3.5
5.25
4
22
33
mV
mV
mV
Dropout Voltage, VIN = VOUT(NOMINAL) (Notes 5, 6) ILOAD = 10mA
l
140 175
260
mV
mV
ILOAD = 50mA
l
200 250
370
mV
mV
ILOAD = 100mA
l
225 275
410
mV
mV
ILOAD = 500mA
l
350 400
590
mV
mV
GND Pin Current, VIN = VOUT(NOMINAL) + 0.6V
(Notes 6, 7)
ILOAD = 0mA
ILOAD = 1mA
ILOAD = 10mA
ILOAD = 100mA
ILOAD = 500mA
l
l
l
l
l
65
100
270
1.8
11
130
200
550
4.5
25
μA
μA
μA
mA
mA
Quiescent Current in Shutdown VIN = 45V, VSHDN = 0V 0.2 1 μA
ADJ Pin Bias Current (Notes 3,12) VIN = 12V l 16 60 nA
Output Voltage Noise COUT = 10µF, ILOAD = 500mA, VOUT = 600mV,
BW = 10Hz to 100kHz
90 μVRMS
COUT = 10µF, CBYP = 10nF, ILOAD = 500mA,
VOUT = 600mV, BW = 10Hz to 100kHz
25 μVRMS
Shutdown Threshold VOUT = Off to On
VOUT = On to Off
l
l
0.9
1.3
1.1
1.42 V
V
SHDN Pin Current (Note 13) VSHDN = 0V, VIN = 45V
VSHDN = 45V, VIN = 45V
l
l
0.5
1
3
μA
µA
Ripple Rejection VIN-VOUT = 2V, VRIPPLE = 0.5VP-P, fRIPPLE = 120Hz,
ILOAD = 500mA
LT3055, VOUT = 0.6V
LT3055-3.3
LT3055-5
70
55
51
85
70
66
dB
dB
dB
Input Reverse Leakage Current VIN = –45V, VOUT = 0 l 300 μA
Reverse Output Current (Note 14) VOUT = 1.2V, VIN = 0 0 10 μA
Internal Current Limit (Note 3) VIN = 2.2V, VOUT = 0, VIMAX = 0
VIN = 2.2V, ∆VOUT = –5%
l
520
900 mA
mA
External Programmed Current Limit, VOUT = 5V
(Notes 6, 8)
5.6V < VIN < 10V, VOUT = 5V, RIMAX = 1.5k,
FAULT2 Pin Threshold (IFAULT)
l180 200 220 mA
5.6V < VIN < 7V, VOUT = 5V, RIMAX = 604Ω,
FAULT2 Pin Threshold (IFAULT)
l445 495 545 mA
LT3055 Series
5
Rev. B
For more information www.analog.com
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 2)
PARAMETER CONDITIONS MIN TYP MAX UNITS
FAULT, PWRGD Pins Logic Low Voltage Pull-Up Current = 50μA l 0.14 0.25 V
FAULT, PWRGD Pins Leakage Current VFAULT1, VFAULT2, VPWRGD = 5V 0.01 1 μA
IMIN Threshold Accuracy (Notes 6, 9) 5.6V < VIN < 15V, VOUT = 5V, RIMIN = 1.2M
5.6V < VIN < 15V, VOUT = 5V, RIMIN = 120K
l
l
0.9
9
1
10
1.1
11
mA
mA
PWRGD Trip Point % of Nominal Output Voltage, Output Rising l86 90 94 %
PWRGD Trip Point Hysteresis % of Nominal Output Voltage 1 %
Current Monitor Ratio (Notes 6,10), Ratio = IOUT/IMON ILOAD = 10mA, 250mA, 500mA l450 500 550 mA/mA
TEMP Voltage (Note 16) TJ = 25°C
TJ = 125°C
0.25
1.25
V
V
TEMP Error (Note 16) l–0.08 0.08 V
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime. Absolute maximum input-to-output differential
voltage is not achievable with all combinations of rated IN pin and OUT pin
voltages. With the IN pin at 50V, the OUT pin may not be pulled below 0V.
The total differential voltage from IN to OUT must not exceed +50V, –40V.
If OUT is pulled above GND and IN, the total differential voltage from OUT
to IN must not exceed 40V.
Note 2: The LT3055 is tested and specified under pulse load conditions
such that TJ ~ TA. The LT3055E is 100% production tested at TA = 25°C
and performance is guaranteed from 0°C to 125°C. Performance at –40°C
and 125°C is assured by design, characterization and correlation with
statistical process controls. The LT3055I is guaranteed over the full –40°C
to 125°C operating junction temperature range. The LT3055MP is 100%
tested over the –55°C to 150°C operating junction temperature range. The
LT3055H is 100% tested at 150°C operating junction temperature.
Note 3: The LT3055 adjustable version is tested and specified for these
conditions with ADJ pin connected to the OUT pin.
Note 4: Maximum junction temperature limits operating conditions.
Regulated output voltage specifications do not apply for all possible
combinations of input voltage and output current. If operating at the
maximum input voltage, limit the output current range. If operating at
the maximum output current, limit the input voltage range. Current limit
foldback limits the maximum output current as a function of input-to-
output voltage. See Current Limit vs VIN-VOUT in the Typical Performance
Characteristics section.
Note 5: Dropout voltage is the minimum differential IN-to-OUT voltage
needed to maintain regulation at a specified output current. In dropout,
the output voltage equals (VIN – VDROPOUT). For some output voltages,
minimum input voltage requirements limit dropout voltage.
Note 6: To satisfy minimum input voltage requirements, the LT3055
adjustable version is tested and specified for these conditions with an
external resistor divider (60k bottom, 440k top) which sets VOUT to 5V. The
external resistor divider adds 10μA of DC load on the output. This external
current is not factored into GND pin current.
Note 7: GND pin current is tested with VIN = VOUT(NOMINAL) + 0.6V and a
current source load. GND pin current increases in dropout. For the fixed
output voltage versions, an internal resistor divider adds about 10µA to
GND pin current. See GND pin current curves in the Typical Performance
Characteristics section.
Note 8: Current limit varies inversely with the external resistor value tied
from the IMAX pin to GND. For detailed information on how to set the IMAX
pin resistor value, please see the Operation section. If a programmed
current limit is not needed, tie the IMAX pin to GND and internal protection
circuitry implements short-circuit protection as specified.
Note 9: The IMIN fault condition asserts if the output current falls below the
IMIN threshold defined by an external resistor from the IMIN pin to GND.
For detailed information on how to set the IMIN pin resistor value, please
see the Operation section. If the IMIN fault condition is not needed, the IMIN
pin must be left floating (unconnected).
Note 10: Current monitor ratio is tested with the IMON pin fixed at
VOUT – 0.5V and with the input range limited to VOUT + 0.6V < VIN < VOUT
+ 10V for IOUT = 10mA; VOUT + 0.6V < VIN < VOUT + 4V for IOUT = 250mA,
and VOUT + 0.6V < VIN < VOUT + 2V for IOUT = 500mA. Input voltage range
conditions are set to limit power dissipation in the IC to 1W maximum for
test purposes. The current monitor ratio varies slightly when in current
limit or when the IMON voltage exceeds VOUT – 0.5V. Please see the
Operation section for more information. If the current monitor function is
not needed, tie the IMON pin to GND.
Note 11: To satisfy requirements for minimum input voltage, current limit
is tested at VIN = VOUT(NOMINAL) + 1V or VIN = 2.2V, whichever is greater.
Note 12: ADJ pin bias current flows out of the ADJ pin.
Note 13: SHDN pin current flows into the SHDN pin.
Note 14: Reverse output current is tested with the IN pin grounded and the
OUT pin forced to the specified voltage. This current flows into the OUT
pin and out of the GND pin.
Note 15: 500mA of output current does not apply to the full range of input
voltage due to the internal current limit foldback.
Note 16: The TEMP output voltage represents the average temperature of
the die while dissipating quiescent power. Due to the pass device power
dissipation and temperature gradients across the die, the TEMP output
voltage measurement does not guarantee that absolute maximum junction
temperature is not exceeded.
Note 17: Minimum Input Voltage is the input voltage at which the output
voltage is decreased 1% from nominal. At elevated temperatures, an input
voltage greater than this is necessary for correct operation of the TEMP
pin. See Temp Pin Minimum Input Voltage in the Typical Performance
Characteristics section.
LT3055 Series
6
Rev. B
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
Quiescent Current ADJ Pin Voltage Output Voltage–LT3055-3.3
Output Voltage–LT3055-5 Quiescent Current GND Pin Current–LT3055-3.3
Typical Dropout Voltage Guaranteed Dropout Voltage Dropout Voltage
TJ = 25°C, unless otherwise noted.
OUTPUT CURRENT (mA)
0
DROPOUT VOLTAGE (mV)
300
400
500
600
400
3055 G01
200
100
250
350
450
550
150
50
0100 200 300
50 450
150 250 350 500
TJ = 150°C
TJ = 125°C
TJ = 25°C
OUTPUT CURRENT (mA)
0
0
DROPOUT VOLTAGE (mV)
100
200
300
700
500
100 200 250 450
600
400
50
150
250
650
450
550
350
50 150 300 350 400 500
3055 G02
= TEST POINTS
TJ = 150°C
TJ = 25°C
TEMPERATURE (°C)
–75
DROPOUT VOLTAGE (mV)
300
400
500
600
125
3055 G03
200
100
250
350
450
550
150
50
0–25 25 75
–50 150
050 100 175
IL = 500mA
IL = 100mA
IL = 50mA
IL = 10mA
TEMPERATURE (°C)
–75
QUIESCENT CURRENT (µA)
60
70
100
110
130
125
3055 G04
40
20
50
90
80
120
30
10
0–25 25 75
–50 150
050 100 175
VIN = VSHDN = 12V
VOUT = 5V
IL = 10µA
VIN = 12V
ALL OTHER PINS = 0V
TEMPERATURE (°C)
–75
ADJ PIN VOLTAGE (mV)
600
604
608
612
125
3055 G05
596
592
598
602
606
610
594
590
588 –25 25 75
–50 150
050 100 175
IL = 1mA
TEMPERATURE (°C)
–75
OUTPUT VOLTAGE (V)
3.300
3.322
3.344
3.366
125
3055 G06
3.278
3.256
3.289
3.311
3.333
3.355
3.267
3.245
3.234 –25 25 75
–50 150
050 100 175
IL = 1mA
TEMPERATURE (°C)
–75
OUTPUT VOLTAGE (V)
5.02
5.06
5.10
125
3055 G07
4.98
4.94
5.00
5.04
5.08
4.96
4.92
4.90 –25 25 75
–50 150
050 100 175
IL = 1mA
VIN (V)
0
0
GND PIN CURRENT (mA)
2
4
6
8
12
2468
3055 G09
101 35 7 9 11 12
10
1
3
5
7
11
9
RL = 13.2Ω, IL = 250mA
RL = 33Ω, IL = 100mA
RL = 330Ω, IL = 10mA
RL = 6.6Ω, IL = 500mA
VIN (V)
0
0
20
40
60
140
100
245 109
120
80
10
30
50
130
90
110
70
1 3 6781211
3055 G08
LT3055-5
LT3055-3.3
VSHDN = 0V, RL = 0
TJ = 25°C
IL = 0
LT3055 Series
7
Rev. B
For more information www.analog.com
SHDN Pin Input Current SHDN Pin Input Current ADJ Pin Bias Current
Internal Current Limit Internal Current Limit Reverse Output Current
GND Pin Current–LT3055-5 GND Pin Current vs ILOAD SHDN Pin Threshold
TYPICAL PERFORMANCE CHARACTERISTICS
TJ = 25°C, unless otherwise noted.
VIN (V)
0
0
GND PIN CURRENT (mA)
2
4
6
8
12
2468
3055 G10
101 35 7 9 11 12
10
1
3
5
7
11
9
RL = 20Ω, IL = 250mA
RL = 50Ω, IL = 100mA
RL = 500Ω, IL = 10mA
RL = 10Ω, IL = 500mA
ILOAD (mA)
0
GND PIN CURRENT (mA)
12
16
20
400
3055 G11
8
4
10
14
18
6
2
0100 200 300
50 450
150 250 350 500
VIN = 5.6V
VOUT = 5V
TEMPERATURE (°C)
–75
SHDN PIN THRESHOLD (V)
1.0
1.2
1.4
1.5
1.3
1.1
0.9
25 50 100 175
0.6
0.8
0.2
0.4
0.5
0.7
0.1
0.3
0–50 –25 0 75 125 150
3055 G12
OFF TO ON
ON TO OFF
TEMPERATURE (°C)
0
SHDN PIN INPUT CURRENT (µA)
1.0
2.0
3.0
0.5
1.5
2.5
–25 25 75 125
3055 G13
175–50–75 0 50 100 150
SHDN = 45V
SHDN PIN VOLTAGE (V)
0
0
SHDN PIN INPUT CURRENT (µA)
0.5
1.5
2.0
2.5
10 20 25 45
3055 G14
1.0
5 15 30 35 40
3.0
TEMPERATURE (°C)
–75
ADJ PIN BIAS CURRENT (nA)
30
40
50
125
3055 G15
20
10
25
35
45
15
5
0–25 25 75
–50 150
050 100 175
TEMPERATURE (°C)
–75
CURRENT LIMIT (A)
1.0
1.2
1.4
1.5
1.3
1.1
0.9
25 50 100 175
0.6
0.8
0.2
0.4
0.5
0.7
0.1
0.3
0–50 –25 0 75 125 150
3055 G16
VIN = 6V
VOUT = 0V
INPUT/OUTPUT DIFFERENTIAL (V)
0
0
CURRENT LIMIT (A)
0.1
0.3
0.4
0.5
1.0
0.7
10 20 25 45
3055 G17
0.2
0.8
0.9
0.6
5 15 30 35 40
TJ = –55°C
TJ = –40°C
TJ = 25°C
TJ = 125°C
TJ = 150°C
VOUT (V)
0
0
OUTPUT CURRENT (µA)
0.1
0.3
0.4
0.5
1.0
0.7
10 20 25 40
3055 G18
0.2
0.8
0.9
0.6
5 15 30 35
VIN = 0
LT3055 Series
8
Rev. B
For more information www.analog.com
Input Ripple Rejection Load RegulationMinimum Input Voltage
Reverse Output Current Input Ripple RejectionInput Ripple Rejection
TYPICAL PERFORMANCE CHARACTERISTICS
TJ = 25°C, unless otherwise noted.
TEMPERATURE (°C)
–75
OUTPUT CURRENT (µA)
60
80
100
125
3055 G19
40
20
50
70
90
30
10
0–25 25 75
–50 150
050 100 175
VOUT = VADJ = 1.2V
VIN = 0V
IADJ
IOUT
FREQUENCY (Hz)
10 100
30
RIPPLE REJECTION (dB)
40
50
60
70
1k 10k 100k 1M 10M
3055 G20
20
10
0
80
90 CREF/BYP = 0pF
CREF/BYP = 100pF
CREF/BYP = 10nF
ILOAD = 500mA
COUT = 10µF
VOUT = 3.3V
VIN = 4.3V + 50mVRMS RIPPLE
FREQUENCY (Hz)
10 100
30
RIPPLE REJECTION (dB)
40
50
60
70
1k 10k 100k 1M 10M
3055 G21
20
10
0
80
90 COUT = 10µF
COUT = 3.3µF
ILOAD = 500mA
CREF/BYP = 10nF
VOUT = 3.3V
VIN = 4.3V + 50mVRMS RIPPLE
TEMPERATURE (°C)
–75
0
RIPPLE REJECTION (dB)
10
30
40
50
75 100 125 150
90
3055 G22
20
–50 –25 0 25 50 175
60
70
80
ILOAD = 500mA
CREF/BYP = 10nF
VOUT = 3.3V
VIN = 4.3V + 50mVRMS RIPPLE
f = 120Hz
TEMPERATURE (°C)
–75
MINIMUM INPUT VOLTAGE (V)
0.6
1.8
2.0
2.2
–25 25 50 75 100 125 150 175
3055 G23
0.2
1.4
1.0
0.4
1.6
0
1.2
0.8
–50 0
ILOAD = 500mA
TEMPERATURE (°C)
–75
LOAD REGULATION (mV)
0
2
150125
3055 G24
–2
–6
–4
–25 25 75
–50 175
050 100
4
6
8
10
12
14
16
3
∆IL = 1mA TO 500mA
VIN = VOUT + 1V, 2.1V FOR LT3055
LT3055, VOUT = 0.6V
LT3055-3.3
LT3055-5
FREQUENCY (Hz)
0.1
OUTPUT NOISE SPECTRAL DENSITY (µV/√
Hz)
1
10 1k 10k 100k
3055 G25
0.01 100
10
VOUT = 5V
VOUT = 3.3V
VOUT = 2.5V
VOUT = 1.2V
VOUT = 0.6V
COUT = 10µF
IL = 500mA
FREQUENCY (Hz)
0.1
OUTPUT NOISE SPECTRAL DENSITY (µV/√
Hz)
1
10 1k 10k 100k
3055 G26
0.01 100
10
VOUT = 5V
VOUT = 0.6V
COUT = 10µF
IL = 500mA
CREF/BYP = 100pF
CREF/BYP = 1nF
CREF/BYP = 10nF
FREQUENCY (Hz)
0.1
OUTPUT NOISE SPECTRAL DENSITY (µV/√
Hz)
1
10 1k 10k 100k
3055 G27
0.01 100
10 VOUT = 5V
COUT = 10µF
IL = 500mA
CFF = 0pF
CFF = 100pF
CFF = 1nF
CFF = 10nF
Output Noise Spectral Density
CREF/BYP = 0, CFF = 0
Output Noise Spectral Density
vs CREF/BYP, CFF = 0
Output Noise Spectral Density
vs CFF, CREF/BYP = 10nF
LT3055 Series
9
Rev. B
For more information www.analog.com
RMS Output Noise vs CREF/BYP,
VOUT = 0.6V, CFF = 0
RMS Output Noise vs Load
Current, CREF/BYP = 10nF, CFF = 0
RMS Output Noise
vs Feedforward Capacitor (CFF)
Start-Up Time
vs REF/BYP Capacitor
10Hz to 100kHz Output Noise
CREF/BYP = 10nF, CFF = 0
10Hz to 100kHz Output Noise
CREF/BYP = 10nF, CFF = 10nF
5V Transient Response
CFF = 0, IOUT = 50mA to 500mA
5V Transient Response
CFF = 10nF, IOUT = 50mA to 500mA Transient Response (Load Dump)
TYPICAL PERFORMANCE CHARACTERISTICS
TJ = 25°C, unless otherwise noted.
LOAD CURRENT (mA)
0.01
40
OUTPUT NOISE VOLTAGE (µV
RMS)
50
60
70
80
0.1 1 10 100 1000
3055 G28
30
20
10
0
90
110
CREF/BYP = 0pF
CREF/BYP = 100pF
CREF/BYP = 1nF
CREF/BYP = 10nF
100 f = 10Hz TO 100kHz
COUT = 10µF
LOAD CURRENT (mA)
0.01
100
OUTPUT NOISE VOLTAGE (µV
RMS)
110
120
130
140
0.1 1 10 100 1000
3055 G29
30
40
50
60
70
80
90
20
10
0
150
160
VOUT = 5V
VOUT = 3.3V
VOUT = 2.5V
VOUT = 1.2V
VOUT = 0.6V
f = 10Hz TO 100kHz
COUT = 10µF
FEEDFORWARD CAPACITOR, CFF (nF)
20
OUTPUT NOISE VOLTAGE (µV
RMS)
40
60
80
100
0.01 1 10
3055 G30
00.1
120
10
30
50
70
90
110 f = 10Hz TO 100kHz
CREF/BYP = 10nF
COUT = 10µF
IFB-DIVIDER = 10µA
ILOAD = 500mA
VOUT = 5V
VOUT = 3.3V
VOUT = 2.5V
VOUT = 1.2V
VOUT = 0.6V
REF/BYP CAPACITOR (nF)
0
START-UP TIME (ms)
20
40
60
10
30
50
20 40 60 80
3055 G31
100100 30 50 70 90
VOUT
200mV/DIV
IOUT
500mA/DIV
100µs/DIVVIN = 6V
COUT = 10µF
IFB-DIVIDER = 10µA
VOUT = 5V
3055 G34
VOUT
100mV/DIV
IOUT
500mA/DIV
20µs/DIVVIN = 6V
COUT = 10µF
IFB-DIVIDER = 10µA
VOUT = 5V
3055 G35
VOUT
20mV/DIV
VIN
10V/DIV
1ms/DIVVOUT = 5V
IOUT = 100mA
COUT = 10µF
45V
12V
3055 G36
VOUT
200µV/DIV
1ms/DIVCOUT = 10µF
ILOAD = 500mA
VOUT = 5V
3055 G32
VOUT
200µV/DIV
1ms/DIVCOUT = 10µF
ILOAD = 500mA
VOUT = 5V
3055 G33
LT3055 Series
10
Rev. B
For more information www.analog.com
SHDN Transient Response
CREF/BYP = 0
SHDN Transient Response
CREF/BYP = 10nF
Precision Current Limit,
RIMAX = 1.5k
Precision Current Limit,
RIMAX = 604Ω IOUT/IMON Ratio, IOUT = 500mA IOUT/IMON Ratio, IOUT = 500mA
IOUT/IMON Current Ratio IOUT/IMON Current Ratio
Minimum Output Current
Threshold, RIMIN = 1.2M
TYPICAL PERFORMANCE CHARACTERISTICS
TJ = 25°C, unless otherwise noted.
OUT
5V/DIV
IL=500mA
REF/BYP
500mV/DIV
SHDN
2V/DIV
2ms/DIV 3055 G37
OUT
5V/DIV
IL = 500mA
REF/BYP
500mV/DIV
SHDN
2V/DIV
2ms/DIV 3055 G38
TEMPERATURE (°C)
–75
CURRENT LIMIT FAULT THRESHOLD (mA)
204
212
220
125
3055 G39
196
188
200
208
216
192
184
180 –25 25 75
–50 150
050 100 175
VOUT(NOMINAL) = 5V
VIN = 10V
VIN = 5.6V
VIMON (V)
0
IOUT/IMON CURRENT RATIO (mA/mA)
510
530
550
4
3055 G41
490
470
500
520
540
480
460
450 1235
TJ = 150°C
TJ = 125°C
TJ = 25°C
TJ = –40°C
TJ = –55°C
VOUT = 5V
VIN = 5.6V
VIMON (V)
0
IOUT/IMON CURRENT RATIO (mA/mA)
510
530
550
4
3055 G41
490
470
500
520
540
480
460
450 1235
TJ = 150°C
TJ = 125°C
TJ = 25°C
TJ = –40°C
TJ = –55°C
VOUT = 5V
VIN = 7V
IOUT (mA)
0
IOUT/IMON CURRENT RATIO (
mA/mA)
510
530
550
400
3055 G43
490
470
500
520
540
480
460
450 100 200 300
50 450
150 250 350 500
TJ = 150°C
TJ = 125°C
TJ = 25°C
TJ = –40°C
TJ = –55°C
VOUT = 5V
VIN = 5.6V
VIMON = 3.5V
IOUT (mA)
0
IOUT/IMON CURRENT RATIO (
mA/mA)
510
530
550
400
3055 G44
490
470
500
520
540
480
460
450 100 200 300
50 450
150 250 350 500
TJ = 150°C
TJ = 125°C
TJ = 25°C
TJ = –40°C
TJ = –55°C
VOUT = 5V
VIMON = 3.5V
IOUT = 10mA at VIN = 15V
IOUT = 250mA at VIN = 9V
IOUT = 500mA at VIN = 7V
TEMPERATURE (°C)
–75
MINIMUM OUTPUT CURRENT THRESHOLD (mA)
1.02
1.06
1.10
125
3055 G45
0.98
0.94
1.00
1.04
1.08
0.96
0.92
0.90 –25 25 75
–50 150
050 100 175
IMIN RISING THRESHOLD
IMIN FALLING THRESHOLD
TEMPERATURE (°C)
–75
CURRENT LIMIT FAULT THRESHOLD (mA)
510
530
550
125
3055 G40
490
470
500
520
540
480
460
450 –25 25 75
–50 150
050 100 175
VOUT(NOMINAL) = 5V
VIN = 7V
VIN = 5.6V
LT3055 Series
11
Rev. B
For more information www.analog.com
TEMP Pin Error TEMP Pin Minimum Input Voltage
PWRGD Threshold Voltage
Minimum Output Current
Threshold RIMIN = 120k
TEMP Output Voltage
vs Temperature
TYPICAL PERFORMANCE CHARACTERISTICS
TJ = 25°C, unless otherwise noted.
TEMPERATURE (°C)
–75
MINIMUM OUTPUT CURRENT THRESHOLD (mA)
10.2
10.6
11.0
125
3055 G46
9.8
9.4
10.0
10.4
10.8
9.6
9.2
9.0 –25 25 75
–50 150
050 100 175
IMIN RISING THRESHOLD
IMIN FALLING THRESHOLD
TEMPERATURE (°C)
–75
TEMP PIN VOLTAGE (V)
0.75
1.25
1.75
125
3055 G47
0.25
–0.25
0.50
1.00
1.50
0
–0.50
–0.75 –25 25 75
–50 150
050 100 175
TEMPERATURE (°C)
0
–7
TEMP PIN ERROR (°C)
–5
–3
–1
7
3
25 50 125
5
1
–6
–4
–2
6
2
4
0
75 100 150
3055 G48
TEMPERATURE (°C)
–75
ADJ PIN VOLTAGE (mV)
550
570
590
125
3055 G50
530
510
540
560
580
520
500
490 –25 25 75
–50 150
050 100 175
ADJ PIN RISING THRESHOLD
ADJ PIN FALLING THRESHOLD
V
OUT
= 0.6V
I
L
=500mA
TEMP Pin Minimum Input Voltage
OUT Pin Minimum Input Voltage
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
175
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
MINIMUM INPUT VOLTAGE (V)
3055 G49
LT3055 Series
12
Rev. B
For more information www.analog.com
PIN FUNCTIONS
IN (Pins 1, 2): Input. These pins supply power to the
device. The LT3055 requires a local IN bypass capacitor
if it is located more than six inches from the main input
filter capacitor. In general, battery output impedance rises
with frequency, so adding a bypass capacitor in battery-
powered circuits is advisable. A bypass capacitor in the
range of 1µF to 10µF is sufficient. See Input Capacitance
and Stability in the Applications Information section for
more information.
The LT3055 regulator withstands reverse voltages on the
IN pins with respect to ground and the OUT pins. In the
case of a reverse input, which can happen if a battery is
plugged in backwards, the device acts as if there is a diode
in series with its input. No reverse current flows into the
regulator and no reverse voltage appears at the load. The
device protects both itself and the load.
SHDN (Pin 3): Shutdown. Pulling the SHDN pin low puts
the LT3055 into a low power state and turns the output off.
Drive the SHDN pin with either logic or an open-collector/
drain with a pull-up resistor. The resistor supplies the
pull-up current to the open-collector/drain logic, normally
several microamperes, and the SHDN pin current, typically
less than 2μA. If unused, connect the SHDN pin to IN. The
LT3055 does not function if the SHDN pin is not connected.
FAULT1 (Pin 4), FAULT2 (Pin 5): Fault Indicator Pins.
FAULT1 and FAULT2 are open-collector logic pins. If the
output current drops below the minimum current thresh-
old, FAULT1 asserts low. If the output current exceeds the
current limit threshold, FAULT2 asserts low. If the LT3055
enters thermal shutdown, both FAULT1 and FAULT2 assert
low. The FAULT1 and FAULT2 pins are capable of sinking
50μA. There is no internal pull-up resistor; an external
pull-up resistor must be used.
PWRGD (Pin 6): Power Good Pin. The PWRGD pin is an
open-collector output that actively pulls low if the output
is less than 90% of the nominal output value. The PWRGD
pin is capable of sinking 50μA. There is no internal pull-up
resistor, an external pull-up resistor must be used.
TEMP (Pin 7): Temperature Output. The TEMP pin outputs
a voltage proportional to the average junction temperature.
The pin voltage is 250mV for 25°C and has a slope of
10mV/°C. The TEMP pin output impedance is approximately
1500Ω. The TEMP pin is stable with no bypass capacitor
or with a bypass capacitor with a value between 100pF
and 1nF. A 100pF capacitor is recommended to improve
TEMP pin power supply rejection. If not used, leave TEMP
unconnected.
IMON (Pin 8): Output Current Monitor. This pin is the col-
lector of a PNP current mirror that outputs 1/500th of the
power PNP current. The IMON pin requires a small (22nF
minimum) decoupling capacitor. In applications where the
IMON pin is used in an external feedback network (current
sharing, cable drop compensation, etc.) smaller bypass
capacitance values may be used to ensure stability of the
external feedback network. If not used, tie IMON to GND.
IMIN (Pin 9): Minimum Output Current Programming
Pin. This pin is the collector of a PNP current mirror that
outputs 1/2000th of the power PNP load current. This pin
is also the input to the minimum output current fault com-
parator. Connecting a resistor between IMIN and GND sets
the minimum output current fault threshold. For detailed
information on how to set the IMIN pin resistor value, please
see the Operation section. A small external decoupling
capacitor (10nF minimum) is required to improve IMIN
PSRR. If minimum output current programming is not
required, float the IMIN pin (unconnected).
IMAX (Pin 10): Precision Current Limit Programming Pin.
This pin is the collector of a current mirror PNP that is
1/500th the size of the output power PNP. This pin is also the
input to the current limit amplifier. Current limit threshold
is set by connecting a resistor between the IMAX pin and
GND. For detailed information on how to set the IMAX pin
resistor value, please see the Operation section. The IMAX
pin requires a 22nF decoupling capacitor to ground. If not
used, tie IMAX to GND.
LT3055 Series
13
Rev. B
For more information www.analog.com
PIN FUNCTIONS
REF/BYP (Pin 11): Bypass/Soft-Start. Connecting a capaci-
tor from this pin to GND bypasses the LT3055’s reference
noise and soft starts the reference. A 10nF bypass capaci-
tor typically reduces output voltage noise to 25μVRMS in
a 10Hz to 100kHz bandwidth. Soft-start time is directly
proportional to BYP/SS capacitor value. If the LT3055 is
placed in shutdown, BYP/SS is actively pulled low by an
internal device to reset soft-start. If low noise or soft-start
performance is not required, this pin must be left floating
(unconnected). Do not drive this pin with any active cir-
cuitry. Because the REF/BYP pin is the reference input to
the error amplifier, stray capacitance at this point should
be minimized. Special attention should be given to any
stray capacitances that can couple external signals onto
the REF/BYP pin producing undesirable output transients
or ripple. A minimum REF/BYP capacitance of 100pF is
recommended.
GND (LT3055: Pin 12, Pin 13, Exposed Pad Pin 17):
Ground. The exposed pad of the DFN and MSOP pack-
ages is an electrical connection to GND. To ensure proper
electrical and thermal performance, solder Pin 17 to the
PCB ground and tie it directly to Pins 12, 13. Connect the
bottom of the output voltage setting resistor divider directly
to GND (Pin 12) for optimum load regulation.
GND (LT3055-3.3, LT3055-5: Pin 12, Exposed Pad
Pin 17): Ground. The exposed pad of the DFN and MSOP
packages is an electrical connection to GND. To ensure
proper electrical and thermal performance, solder Pin 17
to the PCB ground and tie it directly to Pin 12. Connect
the bottom of the output voltage setting resistor divider
directly to GND (Pin 12) for optimum load regulation.
IN
SHDN
3055 F01
R
P
OUT
VIN
SENSE
GND
LT3055-5
RP
+
+
+
LOAD
Figure1. Kelvin Sense Connection
ADJ (LT3055: Pin 14): Adjust. This pin is the error amplifier’s
inverting terminal. The typical bias current of 16nA flows
out of the pin (see the ADJ pin Bias Current vs Temperature
curve in the Typical Performance Characteristics section).
The ADJ pin voltage is 600mV referenced to GND.
Connecting a capacitor from ADJ to OUT reduces output
noise and improves transient response for output voltages
greater than 600mV. See the Applications Information sec-
tion for calculating the value of the feedforward capacitor.
ADJ (LT3055-3.3, LT3055-5: Pin 13): Adjust. This pin is
the error amplifier’s inverting terminal. The typical bias
current of 16nA flows out of the pin (see the ADJ pin Bias
Current vs Temperature curve in the Typical Performance
Characteristics section). The ADJ pin voltage is 600mV
referenced to GND.
Connecting a capacitor from ADJ to OUT reduces output
noise and improves transient response for output voltages
greater than 600mV. See the Applications Information sec-
tion for calculating the value of the feedforward capacitor.
SENSE (LT3055-3.3, LT3055-5: Pin 14): Sense. This pin
is the top of the internal resistor divider network. SENSE
should be connected directly to the load, as a Kelvin sense,
for optimum load regulation and transient performance.
Connecting this pin to the output pin, rather than directly
to the load, can result in load regulation errors due to the
current across the parasitic resistance of the PCB trace.
OUT (Pins 15,16): Output. These pins supply power to
the load. Stability requirements demand a minimum 3.3μF
ceramic output capacitor with an ESR < 1Ω to prevent
oscillations. For output voltages less than 1.2V, a mini-
mum 4.7µF ceramic output capacitor is required. Large
load transient applications require larger output capaci-
tors to limit peak voltage transients. See the Applications
Information section for details on output capacitance and
reverse output characteristics. Permissible output voltage
range is 600mV to 40V.
LT3055 Series
14
Rev. B
For more information www.analog.com
BLOCK DIAGRAM
+
–
+
–
+
–
IN
R1
D1 QIMIN
1/2000
QIMON
1/500
QIMAX
1/500 QPOWER
1
IMAX
IMIN
FAULT1
IMON
QFAULT1
IMIN
THERMAL LIMIT
THERMAL LIMIT
CURRENT LIMITS
PWRGD
U1
FAULT2
QFAULT2
QPWRGD
3055 F02
540mV
REFERENCE
U2
GND
REF/BYP
SHDN
ADJ
SENSE
30k
R4
IDEAL
DIODE
D3
Q2
R6
R5
D2
ERROR
AMPLIFIER
THERMAL/
CURRENT LIMITS
CURRENT
LIMIT
AMPLIFIER 100k
R3
IMIN
COMPARATOR
100k
R2
600mV
REFERENCE
OUT
+
–
+
–
Q3
+
–
Figure2.
OPERATION
IMON Pin Operation (Current Monitor)
The IMON pin is the collector of a PNP which mirrors the
LT3055 output PNP at a ratio of 1:500 (see Block Diagram).
There is additional circuitry which compensates for early
voltage variation by regulating the collector of the IMON
mirror PNP at the output voltage. This circuitry is active
for VIMON ≤ (VOUT – 500mV). For the range where the
early voltage compensation circuit is active, calculate the
output current from the simple equation:
IOUT =500 •
VIMON
R
IMON
For VIMON > (VOUT-500mV), the IMON mirror PNP collec-
tor is VIMON + VDSSAT (500mV at 500mA). Early voltage
effects increase the IOUT to IMON ratio as VIMON increases.
LT3055 Series
15
Rev. B
For more information www.analog.com
OPERATION
If the open-circuit detection function is not needed, the
IMIN pin must be left floating (unconnected). A small de-
coupling capacitor (10nF minimum) from IMIN to GND is
required to improve IMIN pin power supply rejection and to
prevent FAULT1 pin glitches. See the Typical Performance
Characteristics section for additional information.
IMAX Pin Operation
The IMAX pin is the collector of a PNP which mirrors the
LT3055 output PNP at a ratio of 1:500 (see Block Diagram).
The IMAX pin is also the input to the precision current limit
amplifier. If the output load increases to the point where it
causes the IMAX pin voltage to reach 0.6V, the current limit
amplifier takes control of the output regulation so that the
IMAX pin regulates at 0.6V, regardless of the output voltage.
The current limit threshold (ILIMIT) is set by connecting a
resistor (RIMAX) from IMAX to GND:
RIMAX =500 • 0.6V
I
LIMIT
In cases where the IN to OUT differential voltage exceeds
10V, fold-back current limit lowers the internal current
limit level, possibly causing it to override the external
programmable current limit. See the Internal Current Limit
vs VIN-VOUT graph in the Typical Performance Character-
istics section.
The IMAX pin requires a 22nF decoupling capacitor. If the
external programmable current limit is not needed, the
IMAX pin must be connected to GND. The IMAX threshold
is affected by power dissipation in the LT3055; it increases
at a rate of approximately 0.5 percent per watt.
FAULT Pins Operation
The FAULT1 and FAULT2 pins are
open-drain high voltage
NMOS digital outputs.
The FAULT1 pin asserts during a low
current fault (open circuit). The FAULT2 pin asserts during
a current limit fault (internal or externally programmed).
Both FAULT1 and FAULT2 assert during thermal shutdown.
There is no internal pull-up on the FAULT pins; an external
pull-up resistor is required. The FAULT pins sink up to
50μA of pull-down current. Off state logic may be as high
as 45V, regardless of the input voltage used.
VOUT (V)
0
475
I
OUT
:I
IMON
RATIO (mA/mA)
485
495
505
123 4
3055 F03a
515
525
VIN = 6V
VIMON = 2.5V
IOUT = 500mA (IN CURRENT LIMIT)
480
490
500
510
520
5
EARLY VOLTAGE
EFFECTS
VIMON (V)
0
475
I
OUT
:I
IMON
RATIO (mA/mA)
485
495
505
123 4
3055 F03b
5
515
525
VIN = 6V
VOUT = 5V
IOUT = 500mA
480
490
500
510
520
6
IMON MIRROR
PNP SATURATING
EARLY VOLTAGE
EFFECTS
Figure 3a. IOUT:IIMON Ratio vs VOUT
Figure3. (b) IOUT:IIMON Ratio vs VIMON
In addition, if VIN – VIMON < 1V, the IMON mirror PNP
saturates at high loads, causing the IOUT-to-IMON ratio
to increase quickly. The IMON mirror ratio is affected by
power dissipation in the LT3055; it increases at a rate of
approximately 0.5 percent per watt.
Open-Circuit Detection (IMIN Pin)
The IMIN pin is the collector of a PNP which mirrors
the LT3055 output PNP at a ratio of 1:2000 (see Block
Diagram). The IMIN fault comparator asserts the FAULT1
pin if the IMIN pin voltage is below 0.6V. This low output
current fault threshold voltage (IOPEN) is set by attaching
a resistor from IMIN to GND:
RIMIN =2000 • 0.6V
I
OPEN
LT3055 Series
16
Rev. B
For more information www.analog.com
OPERATION
Table1. FAULT Pins Truth Table
STATUS FAULT1 FAULT2
Open Circuit Low High
Current Limit High Low
Thermal Shutdown Low Low
Depending on the IMIN capacitance, BYP capacitance,
and OUT capacitance, the FAULT pins may assert during
start-up. Consideration should be given to masking the
fault signals during start-up. The FAULT pin circuitry is
inactive (not asserted) during shutdown and when the
OUT pin is pulled above IN pin.
PWRGD Pin Operation
The PWRGD pin is an open-drain high voltage NMOS
digital output. The PWRGD pin deasserts and becomes
high impedance if the output rises above 90% of its
nominal value. If the output falls below 89% of its nominal
value for more than 25μs, the PWRGD pin asserts low.
The PWRGD comparator has 1% hysteresis and 25μs
of deglitching. The PWRGD comparator has a dedicated
reference that does not soft-start when a capacitor is
added to the REF/BYP pin.
The use of a feed-forward capacitor, CFF, as shown in Fig-
ure5, can result in the ADJ pin being pulled artificially high
during start- up transients, which causes the PWRGD flag
to assert early. To avoid this problem, ensure that the REF/
BYP capacitor is significantly larger than the feed-forward
capacitor, causing REF/BYP time constant to dominate over
the time constant of the resistor divider network.
Operation in Dropout
There may be some degradation of the current mirror ac-
curacy for output currents less than 50mA when operating
in dropout.
APPLICATIONS INFORMATION
The LT3055 is a micropower, low noise and low dropout volt-
age, 500mA linear regulator with micropower shutdown,
programmable current limit, and diagnostic functions. The
device supplies up to 500mA at a typical dropout voltage
of 350mV and operates over a 1.6V to 45V input range.
A single external capacitor provides low noise reference
performance and output soft-start functionality. For ex-
ample, connecting a 10nF capacitor from the REF/BYP
pin to GND lowers output noise to 25μVRMS over a 10Hz
to 100kHz bandwidth. This capacitor also soft starts the
reference and prevents output voltage overshoot at turn-on.
The LT3055’s quiescent current is merely 65μA but provides
fast transient response with a minimum low ESR 3.3μF
ceramic output capacitor. In shutdown, quiescent current is
less than 1μA and the reference soft-start capacitor is reset.
The LT3055 optimizes stability and transient response
with low ESR, ceramic output capacitors. The regulator
does not require the addition of ESR as is common with
other regulators. The LT3055 typically provides 0.1% line
regulation and 0.1% load regulation. Internal protection
circuitry includes reverse battery protection, reverse output
protection, reverse current protection, current limit with
fold-back and thermal shutdown.
This “bullet-proof” protection set makes it ideal for use
in battery-powered, automotive and industrial systems.
In battery backup applications where the output is held
up by a backup battery and the input is pulled to ground,
the LT3055 acts like it has a diode in series with its output
and prevents reverse current flow.
LT3055 Series
17
Rev. B
For more information www.analog.com
APPLICATIONS INFORMATION
Adjustable Operation
The adjustable LT3055 has an output voltage range of
0.6V to 40V. The output voltage is set by the ratio of
two external resistors, as shown in Figure4. The device
servos the output to maintain the ADJ pin voltage at 0.6V
referenced to ground. The current in R1 is then equal to
0.6V/R1, and the current in R2 is the current in R1 minus
the ADJ pin bias current.
The ADJ pin bias current, 16nA at 25°C, flows from the
ADJ pin through R1 to GND. Calculate the output voltage
using the formula in Figure4. The value of R1 should be
no greater than 62k to provide a minimum 10μA load cur-
rent so that output voltage errors, caused by the ADJ pin
bias current, are minimized. Note that in shutdown, the
output is turned off and the divider current is zero. Curves
of ADJ Pin Voltage vs Temperature and ADJ Pin Bias Cur-
rent vs Temperature appear in the Typical Performance
Characteristics section.
The LT3055 is tested and specified with the ADJ pin tied
to the OUT pin, yielding VOUT = 0.6V. Specifications for
output voltages greater than 0.6V are proportional to the
ratio of the desired output voltage to 0.6V: VOUT/0.6V. For
example, load regulation for an output current change of
1mA to 500mA is 0.5mV (typical) at VOUT = 0.6V. At VOUT
= 12V, load regulation is:
12V
0.6V
• 0.5mV
( )
=10mV
Table2 shows 1% resistor divider values for some common
output voltages with a resistor divider current of 10μA.
Table2. Output Voltage Resistor Divider Values
VOUT (V) R1 (kΩ) R2 (kΩ)
1.2 60.4 60.4
1.5 59 88.7
1.8 59 118
2.5 60.4 191
3 59 237
3.3 61.9 280
5 59 432
Figure4. Adjustable Operation
VIN
V
OUT
IN OUT
+
LT3055
SHDN ADJ
GND
3055 F04
R2
R1
VOUT =0.6V 1+
R2
R1
– IADJ •R2
( )
VADJ =0.6V
IADJ =16nA AT 25°C
OUTPUT RANGE = 0.6V TO 40V
Bypass Capacitance and Output Voltage Noise
The LT3055 regulator provides low output voltage
noise over a 10Hz to 100kHz bandwidth while operat-
ing at full load with the addition of a bypass capacitor
(CREF/BYP) from the REF/BYP pin to GND. A high quality
low leakage capacitor is recommended. This capacitor
bypasses the internal reference of the regulator, provid-
ing a low frequency noise pole for the internal reference.
With the use of 10nF for CREF/BYP, output voltage noise
decreases to as low as 25μVRMS when the output voltage
is set for 0.6V. For higher output voltages (generated by
using a feedback resistor divider), the output voltage noise
gains up proportionately when using CREF/BYP.
To lower the higher output voltage noise, include a feed-
forward capacitor (CFF) from VOUT to the ADJ pin. A high
quality, low leakage capacitor is recommended. This
capacitor bypasses the error amplifier of the regulator,
providing an additional low frequency noise pole. With
the use of 10nF for both CFF and CREF/BYP, output voltage
noise decreases to 25μVRMS when the output voltage is
set to 5V by a 10μA feedback resistor divider. If the cur-
rent in the feedback resistor divider is doubled, CFF must
also be doubled to achieve equivalent noise performance.
Higher values of output voltage noise can occur if care
is not exercised with regard to circuit layout and testing.
Crosstalk from nearby traces induces unwanted noise
onto the LT3055’s output. Power supply ripple rejection
LT3055 Series
18
Rev. B
For more information www.analog.com
must also be considered. The LT3055 regulator does not
have unlimited power supply rejection and passes a small
portion of the input noise through to the output.
Using a feedforward capacitor (CFF) from VOUT to the
ADJ pin has the added benefit of improving transient
response for output voltages greater than 0.6V. With no
feedforward capacitor, the settling time increases as the
output voltage increases above 0.6V. Use the equation in
Figure5 to determine the minimum value of CFF to achieve
a transient response that is similar to the 0.6V output
voltage performance regardless of the chosen output volt-
age (See Figure6 and Transient Response in the Typical
Performance Characteristics section).
During start-up, the internal reference soft-starts when
a bypass capacitor is present. Regulator start-up time is
directly proportional to the size of the bypass capacitor
(See Start-Up Time vs REF/BYP Capacitor in the Typical
Performance Characteristics section). The reference by-
pass capacitor is actively pulled low during shutdown to
reset the internal reference.
Start-up time is also affected by the presence of a feed-
forward capacitor. Start-up time is directly proportional to
the size of the feedforward capacitor and the output volt-
age, and is inversely proportional to the feedback resistor
divider current, slowing to 15ms with a 10nF feedforward
capacitor and a 10μF output capacitor for an output voltage
set to 5V by a 10μA feedback resistor divider.
Output Capacitance and Transient Response
The LT3055 regulator is stable with a wide range of output
capacitors. The ESR of the output capacitor affects stability,
most notably with small capacitors. Use a minimum output
capacitor of 3.3μF with an ESR of 1Ω or less to prevent
oscillations. If a feedforward capacitor is used with output
voltages set for greater than 24V, use a minimum output
capacitor of 10μF. The LT3055 is a micropower device and
output load transient response is a function of output ca-
pacitance. Larger values of output capacitance decrease the
peak deviations and provide improved transient response
for larger load current changes. Bypass capacitors, used to
decouple individual components powered by the LT3055,
increase the effective output capacitor value. For applica-
tions with large load current transients, a low ESR ceramic
capacitor in parallel with a bulk tantalum capacitor often
provides an optimally damped response.
Give extra consideration to the use of ceramic capacitors.
Manufacturers make ceramic capacitors with a variety of
dielectrics, each with different behavior across tempera-
ture and applied voltage. The most common dielectrics
are specified with EIA temperature characteristic codes
of Z5U, Y5V, X5R and X7R. The Z5U and Y5V dielectrics
provide high C-V products in a small package at low cost,
but exhibit strong voltage and temperature coefficients,
as shown in Figure7 and Figure8. When used with a 5V
regulator, a 16V 10μF Y5V capacitor can exhibit an effective
value as low as 1μF to 2μF for the DC bias voltage applied,
and over the operating temperature range. The X5R and
X7R dielectrics yield much more stable characteristics and
are more suitable for use as the output capacitor.
The X7R type works over a wider temperature range and
has better temperature stability, while the X5R is less
expensive and is available in higher values. Care still must
be exercised when using X5R and X7R capacitors; the X5R
APPLICATIONS INFORMATION
3055 F05
IN
SHDN
OUT
ADJ
GND REF/BYP
LT3055
V
IN
V
OUT
CREF/BYP
CFF
R2
R1
COUT
+
CFF ≥
10nF
10µA •IFB _ DIVIDER
( )
IFB _ DIVIDER =VOUT
R1
+
R2
Figure5. Feedforward Capacitor for Fast Transient Response
Figure6. Transient Response vs Feedforward Capacitor
100µs/DIV
VOUT = 5V
COUT = 10µF
IFB-DIVIDER = 10µA
0
1nF
10nF
LOAD CURRENT
500mA/DIV
FEEDFORWARD
CAPACITOR, CFF
100pF
3055 F06
V
OUT
100mV/DIV
LT3055 Series
19
Rev. B
For more information www.analog.com
and X7R codes only specify operating temperature range
and maximum capacitance change over temperature.
Capacitance change due to DC bias with X5R and X7R
capacitors is better than Y5V and Z5U capacitors, but can
still be significant enough to drop capacitor values below
appropriate levels. Capacitor DC bias characteristics tend
to improve as component case size increases, but expected
capacitance at operating voltage should be verified.
Voltage and temperature coefficients are not the only
sources of problems. Some ceramic capacitors have a
piezoelectric response. A piezoelectric device generates
voltage across its terminals due to mechanical stress,
similar to the way a piezoelectric accelerometer or micro-
phone works. For a ceramic capacitor, the stress is induced
by vibrations in the system or thermal transients. The
resulting voltages produced cause appreciable amounts
APPLICATIONS INFORMATION
DC BIAS VOLTAGE (V)
CHANGE IN VALUE (%)
3055 F07
20
0
–20
–40
–60
–80
–100 04810
2 6 12 14
X5R
Y5V
16
BOTH CAPACITORS ARE 16V,
1210 CASE SIZE, 10µF
TEMPERATURE (°C)
–50
40
20
0
–20
–40
–60
–80
–100 25 75
3055 F08
–25 0 50 100
125
Y5V
CHANGE IN VALUE (%)
X5R
BOTH CAPACITORS ARE 16V,
1210 CASE SIZE, 10µF
Figure7. Ceramic Capacitor DC Bias Characteristics
Figure8. Ceramic Capacitor Temperature Characteristics
VOUT
1mV/DIV
10ms/DIV 3055 F09
VOUT = 5V
COUT = 10µF
C
REF/BYP
= 10nF
Figure9. Noise Resulting from Tapping On a Ceramic Capacitor
of noise. A ceramic capacitor produced the trace in
Figure9 in response to light tapping from a pencil. Similar
vibration induced behavior can masquerade as increased
output voltage noise.
Stability and Input Capacitance
Low ESR, ceramic input bypass capacitors are acceptable
for applications without long input leads. However, appli-
cations connecting a power supply to an LT3055 circuit’s
IN and GND pins with long input wires combined with a
low ESR, ceramic input capacitors are prone to voltage
spikes, reliability concerns and application-specific board
oscillations.
The input wire inductance found in many battery-powered
applications, combined with the low ESR ceramic input
capacitor, forms a high QLC resonant tank circuit. In
some instances this resonant frequency beats against the
output current dependent LDO bandwidth and interferes
with proper operation. Simple circuit modifications/solu-
tions are then required. This behavior is not indicative of
LT3055 instability, but is a common ceramic input bypass
capacitor application issue.
The self-inductance, or isolated inductance, of a wire is
directly proportional to its length. Wire diameter is not
a major factor on its self-inductance. For example, the
self-inductance of a 2-AWG isolated wire (diameter =
0.26") is about half the self-inductance of a 30-AWG wire
(diameter = 0.01"). One foot of 30-AWG wire has approxi-
mately 465nH of self-inductance.
LT3055 Series
20
Rev. B
For more information www.analog.com
APPLICATIONS INFORMATION
Two methods can reduce wire self-inductance. One method
divides the current flowing towards the LT3055 between
two parallel conductors. In this case, the farther apart the
wires are from each other, the more the self-inductance is
reduced; up to a 50% reduction when placed a few inches
apart. Splitting the wires connects two equal inductors in
parallel, but placing them in close proximity creates mutual
inductance adding to the self-inductance. The second and
most effective way to reduce overall inductance is to place
both forward and return current conductors (the input and
GND wires) in very close proximity. Two 30-AWG wires
separated by only 0.02”, used as forward- and return-
current conductors, reduce the overall self-inductance
to approximately one-fifth that of a single isolated wire.
If a battery, mounted in close proximity, powers the LT3055,
a 10µF input capacitor suffices for stability. However, if a
distant supply powers the LT3055, use a larger value input
capacitor. Use a rough guideline of 1µF (in addition to the
10µF minimum) per 8 inches of wire length. The minimum
input capacitance needed to stabilize the application also
varies with power supply output impedance variations.
Placing additional capacitance on the LT3055’s output also
helps. However, this requires an order of magnitude more
capacitance in comparison with additional LT3055 input
bypassing. Series resistance between the supply and the
LT3055 input also helps stabilize the application; as little
as 0.1Ω to 0.5Ω suffices. This impedance dampens the
LC tank circuit at the expense of dropout voltage. A better
alternative is to use higher ESR tantalum or electrolytic ca-
pacitors at the LT3055 input in place of ceramic capacitors.
Paralleling Devices
Higher output current is obtained by paralleling multiple
LT3055 together. Tie the individual OUT pins together
and tie the individual IN pins together. An external NPN
or NMOS current mirror is used in combination with the
LT3055 IMON pins to create a simple amplifier. This ampli-
fier injects current into or out of the feedback divider of
the slave LT3055 in order to ensure that the IMON currents
from each LT3055 are equal.
In Figure10, this is implemented using inexpensive 2N3904
NPN devices. Precision 1k resistors provide 1V emitter
degeneration at full load to guarantee good current mirror
matching. The feedback resistors of the slave LT3055 are
split into sections to ensure adequate headroom for the
slave 2N3904. A 1nF capacitor added to the IMON pin of
the slave device frequency compensates the feedback loop.
This circuit architecture is scalable to as many LT3055s
as are needed simply by extending the current mirror and
adding slave LT3055 devices.
+
–
500x
IMON
600mV
REF
ADJ
LT3055 (MASTER)
IN
OUT
440k 10µF
VOUT
5V
1A
1x
+
–
60k
+
–
500x
IMON
600mV
REF
ADJ
LT3055 (SLAVE)
IN
10µF
VIN
5.6V
OUT
300k
1nF
2N3904
1x
+
–
140k
60k 1k 1k
3055 F10
Figure10. Parallel Devices
LT3055 Series
21
Rev. B
For more information www.analog.com
Spreading the devices on the PC board also spreads the
heat. Series input resistors can further spread the heat if
the input-to-output differential is high.
Overload Recovery
Like many IC power regulators, the LT3055 has safe oper-
ating area protection. The safe area protection decreases
current limit as input-to-output voltage increases, and
keeps the power transistor inside a safe operating region
for all values of input-to-output voltage. The LT3055 pro-
vides some output current at all values of input-to-output
voltage up to the device breakdown.
When power is first applied, the input voltage rises and the
output follows the input; allowing the regulator to start-up
into very heavy loads. During start-up, as the input voltage
is rising, the input-to-output voltage differential is small, al-
lowing the regulator to supply large output currents. With a
high input voltage, a problem can occur wherein the removal
of an output short will not allow the output to recover. Other
regulators, such as the LT1083/LT1084/ LT1085 family and
LT1764A also exhibit this phenomenon, so it is not unique
to the LT3055. The problem occurs with a heavy output load
when the input voltage is high and the output voltage is low.
Common situations are immediately after the removal of a
short circuit or if the shutdown pin is pulled high after the
input voltage is already turned on. The load line intersects
the output current curve at two points. If this happens, there
are two stable output operating points for the regulator. With
this double intersection, the input power supply needs to be
cycled down to zero and back up again to recover the output.
Thermal Considerations
The LT3055’s maximum rated junction temperature of
125°C (E-, I-grades) or 150°C (MP-, H-grades) limits its
power handling capability. Two components comprise the
power dissipated by the device:
1. Output current multiplied by the input/output voltage
difference:
IOUT • (VIN – VOUT), and
2. GND pin current multiplied by the input voltage:
IGND • VIN
GND pin current is determined using the GND Pin Current
curves in the Typical Performance Characteristics section.
Power dissipation equals the sum of the two components
listed above.
The LT3055 regulator has internal thermal limiting that
protects the device during overload conditions. For con-
tinuous normal conditions, do not exceed the maximum
junction temperature of 125°C (E-, I-grades) or 150°C
(MP-, H-grades). Carefully consider all sources of thermal
resistance from junction-to-ambient including other heat
sources mounted in proximity to the LT3055.
The undersides of the LT3055 DFN and MSE packages have
exposed metal from the lead frame to the die attachment.
These packages allow heat to directly transfer from the
die junction to the printed circuit board metal to control
maximum operating junction temperature. The dual-in-
line pin arrangement allows metal to extend beyond the
ends of the package on the topside (component side) of a
PCB. Connect this metal to GND on the PCB. The multiple
IN and OUT pins of the LT3055 also assist in spreading
heat to the PCB.
For surface mount devices, heat sinking is accomplished
by using the heat spreading capabilities of the PC board
and its copper traces. Copper board stiffeners and plated
through-holes also can spread the heat generated by
power devices.
Table3 and Table4 list thermal resistance as a function
of copper area in a fixed board size. All measurements
were taken in still air on a 4-layer FR-4 board with 1oz
solid internal planes, and 2oz external trace planes with a
total board thickness of 1.6mm. For further information
on thermal resistance and using thermal information, refer
to JEDEC standard JESD51, notably JESD51-12.
APPLICATIONS INFORMATION
Table3. MSOP Measured Thermal Resistance
COPPER AREA
BOARD AREA
THERMAL RESISTANCE
(JUNCTION-TO-AMBIENT)TOPSIDE BACKSIDE
2500 sq mm 2500 sq mm 2500 sq mm 35°C/W
1000 sq mm 2500 sq mm 2500 sq mm 36°C/W
225 sq mm 2500 sq mm 2500 sq mm 37°C/W
100 sq mm 2500 sq mm 2500 sq mm 39°C/W
LT3055 Series
22
Rev. B
For more information www.analog.com
Calculating Junction Temperature
Example: Given an output voltage of 5V, an input voltage
range of 12V ±5%, a maximum output current range of
75mA and a maximum ambient temperature of 85°C, what
is the maximum junction temperature?
The power dissipated by the device equals:
IOUT(MAX) • (VIN(MAX) – VOUT) + IGND • VIN(MAX)
where:
IOUT(MAX) = 75mA
VIN(MAX) = 12.6V
IGND at (IOUT = 75mA, VIN = 12V) = 3.5mA
So:
P = 75mA • (12.6V – 5V) + 3.5mA • 12.6V = 0.614W
Using a DFN package, the thermal resistance ranges from
36°C/W to 40°C/W depending on the copper area. So the
junction temperature rise above ambient approximately
equals:
0.614W • 40°C/W = 24.6°C
The maximum junction temperature equals the maximum
ambient temperature plus the maximum junction tempera-
ture rise above ambient or:
TJMAX = 85°C + 24.6°C = 110°C
Protection Features
The LT3055 incorporates several protection features that
make it ideal for use in battery-powered circuits. In ad-
dition to the normal protection features associated with
monolithic regulators, such as current limiting and thermal
limiting, the device also protects against reverse input
voltages, reverse output voltages and reverse output-to-
input voltages.
Current limit protection and thermal overload protection
protect the device against current overload conditions at
the output of the device. For normal operation, do not
exceed a junction temperature of 125°C (E-, I-grades) or
150°C (MP-, H-grades).
The LT3055 IN pin withstands reverse voltages of 50V. The
device limits current flow to less than 1μA (typically less
than 25nA) and no negative voltage appears at OUT. The
device protects both itself and the load against batteries
that are plugged in backwards.
The LT3055 incurs no damage if its output is pulled below
ground. If the input is left open circuit or grounded, the
output can be pulled below ground by 50V. No current
flows through the pass transistor from the output. However,
current flows in (but is limited by) the feedback resistor
divider that sets the output voltage. Current flows from
the bottom resistor in the divider and from the ADJ pin’s
internal clamp through the top resistor in the divider to
the external circuitry pulling OUT below ground. If the
input is powered by a voltage source, the output sources
current equal to its current limit capability and the LT3055
protects itself by thermal limiting. In this case, grounding
the SHDN pin turns off the device and stops the output
from sourcing current.
APPLICATIONS INFORMATION
Table4. DFN Measured Thermal Resistance
COPPER AREA
TOPSIDE BOARD AREA
THERMAL RESISTANCE
(JUNCTION-TO-AMBIENT)
2500 sq mm 2500 sq mm 36°C/W
1000 sq mm 2500 sq mm 37°C/W
225 sq mm 2500 sq mm 38°C/W
100 sq mm 2500 sq mm 40°C/W
Figure11. Reverse Output Current
VOUT (V)
0
0
OUTPUT CURRENT (µA)
0.1
0.3
0.4
0.5
1.0
0.7
10 20 25 40
3055 F11
0.2
0.8
0.9
0.6
5 15 30 35
VIN = 0
LT3055 Series
23
Rev. B
For more information www.analog.com
PACKAGE DESCRIPTION
MSOP (MSE16) 0213 REV F
0.53 ±0.152
(.021 ±.006)
SEATING
PLANE
0.18
(.007)
1.10
(.043)
MAX
0.17 –0.27
(.007 – .011)
TYP
0.86
(.034)
REF
0.50
(.0197)
BSC
16
16151413121110
12345678
9
9
18
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
6. EXPOSED PAD DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD SHALL
NOT EXCEED 0.254mm (.010") PER SIDE.
0.254
(.010) 0° – 6° TYP
DETAIL “A”
DETAIL “A”
GAUGE PLANE
5.10
(.201)
MIN
3.20 – 3.45
(.126 – .136)
0.889 ±0.127
(.035 ±.005)
RECOMMENDED SOLDER PAD LAYOUT
0.305 ±0.038
(.0120 ±.0015)
TYP
0.50
(.0197)
BSC
BOTTOM VIEW OF
EXPOSED PAD OPTION
2.845 ±0.102
(.112 ±.004)
2.845 ±0.102
(.112 ±.004)
4.039 ±0.102
(.159 ±.004)
(NOTE 3)
1.651 ±0.102
(.065 ±.004)
1.651 ±0.102
(.065 ±.004)
0.1016 ±0.0508
(.004 ±.002)
3.00 ±0.102
(.118 ±.004)
(NOTE 4)
0.280 ±0.076
(.011 ±.003)
REF
4.90 ±0.152
(.193 ±.006)
DETAIL “B”
DETAIL “B”
CORNER TAIL IS PART OF
THE LEADFRAME FEATURE.
FOR REFERENCE ONLY
NO MEASUREMENT PURPOSE
0.12 REF
0.35
REF
MSE Package
16-Lead Plastic MSOP, Exposed Die Pad
(Reference LTC DWG # 05-08-1667 Rev F)
LT3055 Series
24
Rev. B
For more information www.analog.com
PACKAGE DESCRIPTION
3.00 ±0.10
(2 SIDES)
4.00 ±0.10
(2 SIDES)
NOTE:
1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WGED-3) IN JEDEC
PACKAGE OUTLINE MO-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
0.40 ±0.10
BOTTOM VIEW—EXPOSED PAD
1.70 ±0.10
0.75 ±0.05
R = 0.115
TYP
R = 0.05
TYP
3.15 REF
1.70 ±0.05
18
169
PIN 1
TOP MARK
(SEE NOTE 6)
0.200 REF
0.00 – 0.05
(DE16) DFN 0806 REV Ø
PIN 1 NOTCH
R = 0.20 OR
0.35 × 45°
CHAMFER
3.15 REF
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
2.20 ±0.05
0.70 ±0.05
3.60 ±0.05
PACKAGE
OUTLINE
0.25 ±0.05
3.30 ±0.05
3.30 ±0.10
0.45 BSC
0.23 ±0.05
0.45 BSC
DE Package
16-Lead Plastic DFN (4mm × 3mm)
(Reference LTC DWG # 05-08-1732 Rev Ø)
LT3055 Series
25
Rev. B
For more information www.analog.com
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 6/14 Modified Minimum VIN to 1.8V
Added 3.3V and 5V options, related specs, Typical Performance Characteristics and Pin Functions
Added specification for absolute maximum SENSE pin voltage
Modified Pinouts to accommodate new fixed voltage options
Modified Note 7
Modified PWRGD applications section
1
Throughout
2
2
5
16
B 10/18 Changed Typical Minimum Input Voltage from 1.8V to 1.6V
Added Note 17 to Electrical Characteristics regarding Minimum Input Voltage
Added new Typical Performance Curve TEMP Pin Minimum Input Voltage
1, 4, 16, 26
4, 5
11
LT3055 Series
26
Rev. B
For more information www.analog.com
ANALOG DEVICES, INC. 2013-2018
10/18
www.analog.com
RELATED PARTS
TYPICAL APPLICATION
PART NUMBER DESCRIPTION COMMENTS
LT1761 100mA, Low Noise LDO 300mV Dropout Voltage, Low Noise: 20μVRMS, VIN: 1.8V to 20V, ThinSOT™ Package
LT1762 150mA, Low Noise LDO 300mV Dropout Voltage, Low Noise: 20μVRMS, VIN: 1.8V to 20V, MS8 Package
LT1763 500mA, Low Noise LDO 300mV Dropout Voltage, Low Noise: 20μVRMS, VIN: 1.8V to 20V, SO-8 Package
LT1962 300mA, Low Noise LDO 270mV Dropout Voltage, Low Noise: 20μVRMS, VIN: 1.8V to 20V, MS8 Package
LT1964 200mA, Low Noise, Negative LDO 340mV Dropout Voltage, Low Noise: 30μVRMS, VIN: –1.8V to –20V, ThinSOT Package
LT1965 1.1A, Low Noise, Low Dropout Linear
Regulator
290mV Dropout Voltage, Low Noise: 40μVRMS, VIN: 1.8V to 20V, VOUT: 1.2V to 19.5V,
Stable with Ceramic Capacitors, TO-220, DDPak, MSOP and 3mm × 3mm DFN
Packages
LT3008 20mA, 45V, 3µA IQ Micropower LDO 300mV Dropout Voltage, Low IQ = 3μA, VIN: 2.0V to 45V, VOUT: 0.6V to 39.5V,
ThinSOT and 2mm × 2mm DFN-6 Packages
LT3009 20mA, 3µA IQ Micropower LDO 280mV Dropout Voltage, Low IQ = 3μA, VIN: 1.6V to 20V, 2mm × 2mm DFN-6 and
SC-70 Packages
LT3010 50mA, High Voltage, Micropower LDO VIN: 3V to 80V, VOUT: 1.275V to 60V, VDO = 0.3V, IQ = 30μA, ISD < 1μA,
Low Noise: <100μVRMSP-P, Stable with 1μF Output Capacitor, Exposed MS8 Package
LT3011 50mA, High Voltage, Micropower LDO with
PWRGD
VIN: 3V to 80V, VOUT: 1.275V to 60V, VDO = 0.3V, IQ = 46μA, ISD < 1μA,
Low Noise: <100μVRMS, PowerGood, Stable with 1μF Output Capacitor,
3mm × 3mm DFN-10 and Exposed MS12E Packages
LT3012 250mA, 4V to 80V, Low Dropout Micropower
Linear Regulator
VIN: 4V to 80V, VOUT: 1.24V to 60V, VDO = 0.4V, IQ = 40μA, ISD < 1μA, TSSOP-16E and
4mm × 3mm DFN-12 Packages
LT3013 250mA, 4V to 80V, Low Dropout Micropower
Linear Regulator with PWRGD
VIN: 4V to 80V, VOUT: 1.24V to 60V, VDO = 0.4V, IQ = 65μA, ISD < 1μA, PowerGood
Feature, TSSOP-16E and 4mm × 3mm DFN-12 Packages
LT3014/LT3014HV 20mA, 3V to 80V, Low Dropout Micropower
Linear Regulator
VIN: 3V to 80V (100V for 2ms, LT3014HV Version), VOUT: 1.22V to 60V, VDO = 0.35V,
IQ = 7μA, ISD < 1μA, ThinSOT and 3mm × 3mm DFN-8 Packages
LT3080/LT3080-1 1.1A, Parallelable, Low Noise, Low Dropout
Linear Regulator
300mV Dropout Voltage (2-Supply 0peration), Low Noise: 40μVRMS, VIN: 1.2V to
36V, VOUT: 0V to 35.7V, Current-Based Reference with 1-Resistor VOUT Set, Directly
Parallelable (No Op Amp Required), Stable with Ceramic Capacitors, TO-220,
SOT-223, MSOP and 3mm × 3mm DFN Packages, LT3080-1 Version Has Integrated
Internal Ballast Resistor
LT3050 100mA LDO with Diagnostics and Precision
Current Limit
340mV Dropout Voltage, Low Noise: 20μVRMS, VIN: 1.6V to 45V, DFN and MSOP
Packages
LT3060 100mA, Low Noise LDO with Soft-Start 300mV Dropout Voltage, Low Noise: 20μVRMS, VIN: 1.6V to 45V, DFN Package
1x
IMON
600mV
REF
ADJ
LT3055
IN
10µF
VIN
7V
OUT
RCABLE • 500
RCABLE/2
100nF
2N3904
500x
+
–
RCABLE/2
440k –RCABLE • 500
60k
10nF
10µF 10µF
+
–
5V, COMPENSATED
FOR DROP ALONG
RCABLE/2 RESISTORS
1k 1k
3055 TA02FF
+
–
Cable Drop Compensation