©2001 Integrated Device Technology, Inc.
DECEMBER 2001
DSC 2941/7
1
IDT70V05S/L
HIGH-SPEED 3.3V
8K x 8 DUAL-PORT
STATIC RAM
Features
◆◆
◆◆
◆True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
◆◆
◆◆
◆High-speed access
– Commercial: 15/20/25/35/55ns (max.)
– Industrial: 20ns (max.)
◆◆
◆◆
◆Low-power operation
– IDT70V05S
Active: 400mW (typ.)
Standby: 3.3mW (typ.)
– IDT70V05L
Active: 380mW (typ.)
Standby: 660
µ
W (typ.)
◆◆
◆◆
◆IDT70V05 easily expands data bus width to 16 bits or more
using the Master/Slave select when cascading more than
one device
◆◆
◆◆
◆M/S = VIH for BUSY output flag on Master
M/S = VIL for BUSY input on Slave
◆◆
◆◆
◆Interrupt Flag
◆◆
◆◆
◆On-chip port arbitration logic
◆◆
◆◆
◆Full on-chip hardware support of semaphore signaling
between ports
◆◆
◆◆
◆Fully asynchronous operation from either port
◆◆
◆◆
◆TTL-compatible, single 3.3V (±0.3V) power supply
◆◆
◆◆
◆Available in 68-pin PGA and PLCC, and a 64-pin TQFP
◆◆
◆◆
◆Industrial temperature range (-40°C to +85°C) is available
for selected speeds
Functional Block Diagram
NOTES:
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.
2. BUSY outputs and INT outputs are non-tri-stated push-pull.
I/O
Control
Address
Decoder
MEMORY
ARRAY
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
Address
Decoder
I/O
Control
R/W
L
CE
L
OE
L
BUSY
L
A
12L
A
0L
2942 drw 01
I/O
0L
-I/O
7L
CE
L
OE
L
R/W
L
SEM
L
INT
L
M/S
BUSY
R
I/O
0R
-I/O
7R
A
12R
A
0R
SEM
R
INT
R
CE
R
OE
R
(2)
(1,2) (1,2)
(2)
R/W
R
CE
R
OE
R
13
13
R/W
R
,
6.42
IDT70V05S/L
High-Speed 3.3V 8K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
2
Description
The IDT70V05 is a high-speed 8K x 8 Dual-Port Static RAM. The
IDT70V05 is designed to be used as a stand-alone 64K-bit Dual-Port
SRAM or as a combination MASTER/SLAVE Dual-Port SRAM for 16-bit-
or-more word systems. Using the IDT MASTER/SLAVE Dual-Port SRAM
approach in 16-bit or wider memory system applications results in full-
speed, error-free operation without the need for additional discrete logic.
This device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access for
reads or writes to any location in memory. An automatic power down
feature controlled by CE permits the on-chip circuitry of each port to enter
a very low standby power mode.
Fabricated using IDT’s CMOS high-performance technology, these
devices typically operate on only 400mW of power.
The IDT70V05 is packaged in a ceramic 68-pin PGA and PLCC
and a 64-pin thin quad flatpack (TQFP).
Pin Configurations(1,2,3)
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. J68-1 package body is approximately .95 in x .95 in x .17 in.
PN64 package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate oriention of the actual part-marking
2941 drw 02
12
13
14
15
16
17
18
INDEX
19
20
21
22
987 6543 2168676665
27 28 29 30 31 32 33 34 35 36 37 38 39
V
DD
V
DD
I/O
1R
I/O
2R
I/O
3R
I/O
4R
INT
L
V
SS
A
4L
A
3L
A
2L
A
1L
A
0L
A
3R
A
0R
A
1R
A
2R
I/O
2L
A
5L
R/W
L
11
10
M/S
23
24
25
26
40 41 42 43
58
57
56
55
54
53
52
51
50
49
48
59
60
47
46
45
44
64 63 62 61
I/O
3L
V
SS
I/O
0R
V
DD
A
4R
BUSY
L
V
SS
BUSY
R
INT
R
A
12R
I/O
7R
N/C
V
SS
OE
R
R/W
R
SEM
R
CE
R
OE
L
SEM
L
CE
L
N/C
I/O
0L
I/O
1L
IDT70V05J
J68-1
(4)
68-Pin PLCC
Top View
(5)
I/O
4L
I/O
5L
I/O
6L
I/O
7L
I/O
5R
I/O
6R
N/C
A
12L
A
11R
N/C
A
10R
A
9R
A
8R
A
7R
A
6R
A
5R
A
11L
A
10L
A
9L
A
8L
A
7L
A
6L
N/C
N/C
,
12/03/01
INDEX
70V05PF
PN-64
(4)
64-Pin TQFP
Top View
(5)
8
9
10
11
12
13
14
15
16
1
2
3
4
5
6
7
46
45
44
43
42
41
40
39
38
37
36
35
34
47
48
33
17
18
19
20
32
31
30
29
28
27
26
25
24
23
22
21
49
50
51
52
63
62
61
60
59
58
57
56
55
54
53
64
I/O
2L
V
DD
V
SS
V
SS
A
4R
BUSY
L
BUSY
R
INT
R
INT
L
V
SS
M/S
OE
L
A
5L
I/O
1L
R/W
L
CE
L
SEM
L
V
DD
N/C
N/C
OE
R
CE
R
R/W
R
SEM
R
A
12R
GND
I/O
3L
I/O
4L
I/O
5L
I/O
6L
I/O
7L
I/O
0R
I/O
1R
I/O
2R
V
DD
I/O
3R
I/O
4R
I/O
5R
I/O
6R
I/O
7R
A
11R
A
10R
A
9R
A
8R
A
7R
A
6R
A
5R
A
3R
A
2R
A
1R
A
0R
A
0L
A
1L
A
2L
A
3L
A
4L
A
6L
A
7L
A
8L
A
9L
A
10L
A
11L
A
12L
I/O
0L
2941 drw 03
,
12/03/01
6.42
IDT70V05S/L
High-Speed 3.3V 8K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
3
Pin Names
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. Package body is approximately 1.18 in x 1.18 in x .16 in.
4. This package code is used to reference the package diagram.
5. This text does not indicate oriention of the actual part-marking.
Pin Configurations(1,2,3) (con't.)
2941 drw 04
51 50 48 46 44 42 40 38 36
53
55
57
59
61
63
65
67
68
66
1357911 13 15
20
22
24
26
28
30
32
35
IDT70V05G
G68-1
(4)
68-Pin PGA
Top View
(5)
ABCDEFGH JKL
47 45 43 41 34
21
23
25
27
29
31
33
246810121416
18 19
17
56
58
60
62
64
11
10
09
08
07
06
05
04
03
02
01
52
54
49 39 37
A
5L
INT
L
N/C
SEM
L
CE
L
V
DD
OE
L
R/W
L
I/O
0L
N/C
V
SS
V
SS
I/O
0R
V
DD
N/C
OE
R
R/W
R
SEM
R
CE
R
V
SS
BUSY
R
BUSY
L
M/SINT
R
N/C
V
SS
A
1R
N/C
N/C
INDEX
A
4L
A
2L
A
0L
A
3R
A
2R
A
4R
A
5R
A
7R
A
6R
A
9R
A
8R
A
11R
A
10R
A
12R
A
0R
A
7L
A
6L
A
3L
A
1L
A
9L
A
8L
A
11L
A
10L
A
12L
V
DD
I/O
2R
I/O
3R
I/O
5R
I/O
6R
I/O
1R
I/O
4R
I/O
7R
I/O
1L
I/O
2L
I/O
4L
I/O
7L
I/O
3L
I/O
5L
I/O
6L
,
12
/
03
/
01
Left Port Right Port Names
CE
L
CE
R
Chip E nab le
R/W
L
R/W
R
Re ad/Write Enab le
OE
L
OE
R
Outp ut Enab le
A
0L
- A
12L
A
0R
- A
12R
Address
I/O
0L
- I/ O
7L
I/O
0R
- I/ O
7R
Data In p ut/ Outp ut
SEM
L
SEM
R
Semaphore Enable
INT
L
INT
R
In te rrup t F lag
BUSY
L
BUSY
R
Busy Flag
M/SMaster or Slave Select
V
DD
P o we r (3.3v )
V
SS
Gro und (0v)
2941 t b l 01
6.42
IDT70V05S/L
High-Speed 3.3V 8K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
4
Truth Table I: Non-Contention Read/Write Control
Truth Table II: Semaphore Read/Write Control(1)
NOTE:
1. A0L — A12L≠ A0R — A12R
NOTE:
1. There are eight semaphore flags written to via I/O0 and read from I/O0 -I/O 7. These eight semaphores are addressed by A0-A2.
Inputs
(1)
Outputs
Mode
CE R/WOE SEM I/O
0-7
H X X H Hig h-Z Des el ec te d: Powe r-Down
LLXHDATA
IN
Write to Me mory
LHLHDATA
OUT
Read Me mory
X X H X Hi g h-Z Outp u ts Di sa bl e d
2941 tbl 02
Inputs
(1)
Outputs
Mode
CE R/WOE SEM I/O
0-7
HHLLDATA
OUT
Read Data in Semaphore Flag
H↑XLDATA
IN
Writ
e
I/O
0
into Semaphore Flag
LXXL
____
No t A ll o we d
2941 tbl 03
6.42
IDT70V05S/L
High-Speed 3.3V 8K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
5
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 3.3V ± 0.3V)
Recommended DC Operating
Conditions
Maximum Operating Temperature
and Supply Voltage(1)
Absolute Maximum Ratings(1)
Capacitance (TA = +25°C, f = 1.0MHz)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed VDD + 0.3V.
NOTE:
1. This is the parameter TA. This is the "instant on" case temperature.
NOTES:
1. VIL> -1.5V for pulse width less than 10ns.
2. VTERM must not exceed VDD +0.3V.
Symbol Rating Commercial
& Indu stri al Unit
V
TERM(2)
Te rminal Vo ltage
with Re s p e c t
to GND
-0.5 to +4.6 V
T
BIAS
Temperature
Unde r Bi as -55 to +125
o
C
T
STG
Storage
Temperature -65 to +150
o
C
I
OUT
DC Outp ut
Current 50 mA
2941 tbl 04
Grade Am bi ent Temperature GND V
DD
Commercial 0
O
C to +70
O
C0V3.3V
+
0.3V
Industrial -40
O
C to +85
O
C0V3.3V
+
0.3V
2941 tbl 05
Symbol Parameter Min. Typ. Max. Unit
VDD Sup ply Vo ltag e 3.0 3.3 3.6 V
VSS Ground 0 0 0 V
V
IH
Input High Voltage 2.0
____
VDD+0.3
(2)
V
V
IL
Input Lo w Vo ltag e -0.5
(1)
____
0.8 V
2941 tbl 06
Symbol Parameter
(1)
Conditions Max. Unit
C
IN
Input Capacitance V
IN
= 3dV 9 pF
C
OUT
Outp ut Cap aci tanc e V
OUT
= 3dV 10 pF
2941 tbl 07
Symbol Parameter Test Condi tions
70V05S 70V05L
UnitMin. Max. Min. Max.
|I
LI
| Inp ut Leak ag e Current
(1)
V
DD
= 3.6V, V
IN
= 0V to V
DD
___
10
___
5µA
|I
LO
| Outp ut Le ak age Curre nt V
OUT
= 0V to V
DD
___
10
___
5µA
V
OL
Output Low Vo ltage I
OL
= +4mA
___
0.4
___
0.4 V
V
OH
Output High Voltage I
OH
= -4mA 2.4
___
2.4
___
V
2941 tbl 08
NOTES:
1. This parameter is determined by device characterization but is not production
tested.
2. 3dV references the interpolated capacitznce when the input and output signals
switch from 0V to 3V or from 3V to 0V.
NOTE:
1. At VDD < 2.0V input leakages are undefined.
6.42
IDT70V05S/L
High-Speed 3.3V 8K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
6
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1) (VDD = 3.3V ± 0.3V)
NOTES:
1. “X” in part number indicates power rating (S or L)
2. VDD = 3.3V, TA = +25°C, and are not production tested. IDD DC = 115mA (Typ.)
3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions” of input levels of
GND to 3V.
4. f = 0 means no address or control lines change.
70V05X15
Com'l Only 70V05X20
Com'l
& I nd
70V05X25
Com'l Only
Symbol Parameter Test Condition Version Typ.
(2)
Max. Typ.
(2)
Max. Typ.
(2)
Max. Unit
I
DD
Dy na m i c O p erat i ng
Current
(Both Po rts Active)
CE = V
IL
, Outputs Disabled
SEM = V
IH
f = f
MAX
(3)
COM'L S
L150
140 215
185 140
130 200
175 130
125 190
165 mA
IND S
L
____
____
____
____
140
130 225
195
____
____
____
____
mA
I
SB1
Stand by Current
(Bo th Po rts - TTL
Lev el Inputs)
CE
R
= CE
L
= V
IH
SEM
R
= SEM
L
= V
IH
f = f
MAX
(3)
COM'L S
L25
20 35
30 20
15 30
25 16
13 30
25 mA
IND S
L
____
____
____
____
20
15 45
40
____
____
____
____
mA
I
SB2
Stand by Current
(One Po rt - TTL
Lev el Inputs)
CE
L
or CE
R
= V
IH
A c tiv e P o rt O utp uts D i sa b l e d ,
f=f
MAX
(3)
COM'L S
L85
80 120
110 80
75 110
100 75
72 110
95 mA
IND S
L
____
____
____
____
80
75 130
115
____
____
____
____
mA
I
SB3
Full Standby Current
(Bo th Po rts -
CMOS Le ve l Inp uts )
Both Po rts CE
L
and
CE
R
> V
DD
- 0. 2V,
V
IN
> V
DD
- 0 .2V o r
V
IN
< 0.2V, f = 0
(4)
SEM
R
= SEM
L
> V
DD
- 0. 2V
COM'L S
L1.0
0.2 5
2.5 1.0
0.2 5
2.5 1.0
0.2 5
2.5 mA
IND S
L
____
____
____
____
1.0
0.2 15
5
____
____
____
____
mA
I
SB4
Full Standby Current
(One Po rt -
CMOS Le ve l Inp uts )
One Port CE
L
or
CE
R
> V
DD
- 0. 2V
SEM
R
= SEM
L
> V
DD
- 0. 2V
V
IN
> V
DD
- 0.2V o r V
IN
< 0. 2V
A c tiv e P o rt O utp uts D i sa b l e d ,
f = f
MAX
(3)
COM'L S
L85
80 125
105 80
75 115
100 75
70 105
90 mA
IND S
L
____
____
____
____
80
75 130
115
____
____
____
____
mA
2 941 tbl 09a
70V05X35
Com'l Only 70V05X55
Com'l Only
Symbol Parameter Test Condition Version Typ.
(2)
Max. Typ.
(2)
Max. Unit
I
DD
Dynamic Operating
Current
(Both Ports Active )
CE = V
IL
, Outputs Disabled
SEM = V
IH
f = f
MAX
(3)
COM'L S
L120
115 180
155 120
115 180
155 mA
IND S
L120
115 200
170 120
115 200
170 mA
I
SB1
Standb y Current
(Both Ports - TTL
Lev el Inp uts)
CE
R
= CE
L
= V
IH
SEM
R
= SEM
L
= V
IH
f = f
MAX
(3)
COM'L S
L13
11 25
20 13
11 25
20 mA
IND S
L13
11 40
35 13
11 40
35 mA
I
SB2
Standb y Current
(One P o rt - TTL
Lev el Inp uts)
CE
L
or CE
R
= V
IH
Active Port Outputs Disabled,
f=f
MAX
(3)
COM'L S
L70
65 100
90 70
65 100
90 mA
IND S
L70
65 120
105 70
65 120
105 mA
I
SB3
Full Standby Current
(Both Ports -
CMOS Le ve l Inp uts)
Bo th Ports CE
L
and
CE
R
> V
DD
- 0. 2V,
V
IN
> V
DD
- 0. 2V or
V
IN
< 0.2V, f = 0
(4)
SEM
R
= SEM
L
> V
DD
- 0. 2V
COM'L S
L1.0
0.2 5
2.5 1.0
0.2 5
2.5 mA
IND S
L1.0
0.2 15
51.0
0.2 15
5mA
I
SB4
Full Standby Current
(One P o rt -
CMOS Le ve l Inp uts)
One Port CE
L
or
CE
R
> V
DD
- 0. 2V
SEM
R
= SEM
L
> V
DD
- 0. 2V
V
IN
> V
DD
- 0.2V o r V
IN
< 0.2V
Active Port Outputs Disabled,
f = f
MAX
(3)
COM'L S
L65
60 100
85 65
60 100
85 mA
IND S
L65
60 115
100 65
60 115
100 mA
2941 tbl 09b
6.42
IDT70V05S/L
High-Speed 3.3V 8K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
7
AC Test Conditions
Timing of Power-Up Power-Down
Figure 1. AC Output Test Load Figure 2. Output Test Load
*Including scope and jig.
(For tLZ, tHZ, tWZ, tOW)
CE
2941 drw 06
t
PU
I
CC
I
SB
t
PD
50% 50%
,
Inp ut Puls e Le v e ls
Inp ut Ris e /Fal l Time s
Inp ut Ti min g Re fere nce Le v e ls
Outp ut Re fe re nc e Le ve l s
Outp ut Load
GND to 3 . 0V
3ns Max .
1.5V
1.5V
Fi g ure s 1 and 2
2941 tbl 10
2941 drw 05
590Ω
30pF
435Ω
3.3V
DATA
OUT
BUSY
INT
590Ω
5pF*
435Ω
3.3V
DATA
OUT
6.42
IDT70V05S/L
High-Speed 3.3V 8K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
8
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is determined by device characterization but is not production tested.
3. To access SRAM, CE = VIL, SEM = VIH.
4. 'X' in part number indicates power rating (S or L).
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(4)
70V05X15
Co m' l On l y 70V05X20
Com'l
& In d
70V05X25
Com'l Only
UnitSymbol Parameter Min.Max.Min.Max.Min.Max.
READ CYCLE
t
RC
Re ad Cyc l e Tim e 15
____
20
____
25
____
ns
t
AA
Address Access Time
____
15
____
20
____
25 ns
t
ACE
Chip Enab le Acce ss Time
(3)
____
15
____
20
____
25 ns
t
AOE
Outp ut Enab le A cce s s Time
(3)
____
10
____
12
____
13 ns
t
OH
Outp ut Hold from Address Change 3
____
3
____
3
____
ns
t
LZ
Outp ut Lo w-Z Tim e
(1,2)
3
____
3
____
3
____
ns
t
HZ
Outp ut Hi g h-Z Ti me
(1,2)
____
10
____
12
____
15 ns
t
PU
Chip Enable to Po we r Up Time
(1,2)
0
____
0
____
0
____
ns
t
PD
Chi p Disab le to P o wer Down Time
(1,2)
____
15
____
20
____
25 ns
t
SOP
Semaphore Flag Update Pulse (OE or SEM)10
____
10
____
10
____
ns
t
SAA
Semaphore Address Access
(3)
____
15
____
20
____
25 ns
29 41 tb l 11 a
70V05X35
Com'l Only 70V05X55
Co m' l Onl y
UnitSymbol Parameter Min. Max. Min. Max.
READ CYCLE
t
RC
Re ad Cyc l e Tim e 35
____
55
____
ns
t
AA
Add re ss Access Time
____
35
____
55 ns
t
ACE
Chip Enab le Acce ss Time
(3)
____
35
____
55 ns
t
AOE
Outp ut Enab le A cce s s Time
(3)
____
20
____
30 ns
t
OH
Outp ut Hold from Address Change 3
____
3
____
ns
t
LZ
Outp ut Lo w-Z Tim e
(1,2)
3
____
3
____
ns
t
HZ
Outp ut Hi g h-Z Ti me
(1,2)
____
15
____
25 ns
t
PU
Chip Enable to Po we r Up Time
(1,2)
0
____
0
____
ns
t
PD
Chi p Disable to P owe r Down Time
(1,2)
____
35
____
50 ns
t
SOP
Semaphore Flag Update Pulse (OE or SEM)15
____
15
____
ns
t
SAA
Semaphore Address Access
(3)
____
35
____
55 ns
2 941 tbl 11b
6.42
IDT70V05S/L
High-Speed 3.3V 8K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
9
Waveform of Read Cycles(5)
NOTES:
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is de-asserted first CE or OE.
3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has no
relation to valid output data.
4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD.
5. SEM = V IH.
t
RC
R/W
CE
ADDR
t
AA
OE
2941 drw 07
(4)
t
ACE (4)
t
AOE(4)
(1)
t
LZ
t
OH
(2)
t
HZ
(3,4)
t
BDD
DATA
OUT
BUSY
OUT
VALID DATA
(4)
6.42
IDT70V05S/L
High-Speed 3.3V 8K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
10
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is determined by device characterization but is not production tested.
3. To access SRAM, CE = VIL, SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time.
4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage and
temperature, the actual tDH will always be smaller than the actual tOW.
5. “X” in part number indicates power rating (S or L).
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage(5)
Symbol Parameter
70V05X15
Com'l Only 70V05X20
Com'l
& I nd 70V05X25
Com'l Only
UnitMin. Max. Min. Max. Min. Max.
WRI T E CYCLE
t
WC
Write Cycle Time 15
____
20
____
25
____
ns
t
EW
Chip Enab le to End-of-Write
(3)
12
____
15
____
20
____
ns
t
AW
Address Valid to End-of-Write 12
____
15
____
20
____
ns
t
AS
Address Set-up Time
(3)
0
____
0
____
0
____
ns
t
WP
Write Pulse Width 12
____
15
____
20
____
ns
t
WR
Write Reco v ery Time 0
____
0
____
0
____
ns
t
DW
Da ta Val id to E nd-o f-Wri te 10
____
15
____
15
____
ns
t
HZ
Output High-Z Time
(1,2)
____
10
____
12
____
15 ns
t
DH
Data H o ld Ti me
(4)
0
____
0
____
0
____
ns
t
WZ
Wri te E nab l e to Outp ut in Hig h-Z
(1,2)
____
10
____
12
____
15 ns
t
OW
Ou tp ut A c tiv e fro m End-o f-Wri te
(1,2,4)
0
____
0
____
0
____
ns
t
SWRD
SEM Flag Write to Read Tim e 5
____
5
____
5
____
ns
t
SPS
SEM F lag Co nte ntio n Wind o w 5
____
5
____
5
____
ns
2 941 tb l 12 a
Symbol Parameter
70V05X35
Com'l Only 70V05X55
Com'l Only
UnitMin. Max. Min. Max.
WR ITE C Y CLE
t
WC
Wri te Cy c le Time 35
____
55
____
ns
t
EW
Chip Enab le to End-of-Write
(3)
30
____
45
____
ns
t
AW
Address Valid to End-of-Write 30
____
45
____
ns
t
AS
Address Set-up Time
(3)
0
____
0
____
ns
t
WP
Write Pulse Width 25
____
40
____
ns
t
WR
Wri te Re c o v e ry Time 0
____
0
____
ns
t
DW
Data Vali d to E nd-o f-Wri te 15
____
30
____
ns
t
HZ
Outp ut Hi gh-Z Ti me
(1,2)
____
15
____
25 ns
t
DH
Data Ho ld Tim e
(4)
0
____
0
____
ns
t
WZ
Wri te E nab le to Outp ut i n Hi g h-Z
(1,2)
____
15
____
25 ns
t
OW
Outp ut A c tiv e fro m End-o f-W rite
(1,2,4)
0
____
0
____
ns
t
SWRD
SEM Flag Write to Re ad Time 5
____
5
____
ns
t
SPS
SEM Flag Conte ntion Window 5
____
5
____
ns
2941 tbl 12 b
6.42
IDT70V05S/L
High-Speed 3.3V 8K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
11
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,3,5,8)
NOTES:
1. R/W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a LOW CE and a LOW R/W for memory array writing cycle.
3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last, CE, or R/W.
7. Timing depends on which enable signal is de-asserted first, CE, or R/W.
8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed on the
bus for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP.
9. To access RAM, CE = VIL and SEM = VIN. To access Semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition.
Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1,3,5,8)
2941 drw 09
t
WC
t
AS
t
WR
t
DW
t
DH
ADDRESS
DATA
IN
CE
or
SEM
R/W
t
AW
t
EW
(3)(2)(6)
(9)
R/W
t
WC
t
HZ
t
AW
t
WR
t
AS
t
WP
DATA
OUT
(2)
t
WZ
t
DW
t
DH
t
OW
OE
ADDRESS
DATA
IN
CE
(6)
(4) (4)
(3)
2941 drw 08
(7)
(7)
or
SEM
(9)
6.42
IDT70V05S/L
High-Speed 3.3V 8K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
12
Timing Waveform of Semaphore Read after Write Timing, Either Side(1)
NOTE:
1. CE = VIH for the duration of the above timing (both write and read cycle).
2. “DATAOUT VALID” represents all I/O's (I/O0-I/O7) equal to the semaphore value.
Timing Waveform of Semaphore Write Contention(1,3,4)
SEM
"A"
2941 drw 11
t
SPS
MATCH
R/W
"A"
MATCH
A
0"A"
-A
2"A"
SIDE "A"
(2)
SEM
"B"
R/W
"B"
A
0"B"
-A
2"B"
SIDE "B"
(2)
NOTES:
1. DOR = DOL = VIL, CER = CEL = VIH, Semaphore Flag is released from both sides (reads as ones from both sides) at cycle start.
2. “A” may be either left or right port. “B” is the opposite port from “A”.
3. This parameter is measured from R/W“A” or SEM“A” going HIGH to R/W“B” or SEM“B” going HIGH.
4. If tSPS is not satisfied, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag.
SEM
2941 drw 10
t
AW
t
EW
t
SOP
DATA
0
VALID ADDRESS
t
SAA
R/W
t
WR
t
OH
t
t
ACE
VALID ADDRESS
DATA
IN
VALID DATA
OUT
t
DW
t
WP
t
DH
t
AS
t
SWRD
t
AOE
t
SOP
Read Cycle
Write Cycle
A
0
-A
2
OE
VALID
(2)
6.42
IDT70V05S/L
High-Speed 3.3V 8K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
13
NOTES:
1. Port-to-port delay through SRAM cells from writing port to reading port, refer to “Timing Waveform of Read With BUSY (M/S = VIH)” or “Timing Waveform of Write With Port-
To-Port Delay (M/S = VIL)”.
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited during contention.
5. To ensure that a write cycle is completed after contention.
6. 'X' is part number indicates power rating (S or L).
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(6)
70V05X15
Com'l Ony 70V05X20
Com'l
& I nd
70V05X25
Com'l Only
Symbol Parameter Min.Max.Min.Max.Min.Max.Unit
BUSY TIMING (M/S = V
IH
)
t
BAA
BUSY Acces s Time from Ad dres s Match
____
15
____
20
____
20 ns
t
BDA
BUSY Disable Time fro m Address Not Matched
____
15
____
20
____
20 ns
t
BAC
BUSY Ac ces s Time fro m Chip Enable LOW
____
15
____
20
____
20 ns
t
BDC
BUSY Disable Time from Chip Enable HIGH
____
15
____
17
____
17 ns
t
APS
A rb i trati o n P ri o rity S e t-up Ti me
(2)
5
____
5
____
5
____
ns
t
BDD
BUSY Disable to Valid Data
(3)
____
18
____
30
____
30 ns
t
WH
Write Hold After BUSY
(5)
12
____
15
____
17
____
ns
BUSY TIMING (M/S = V
IL
)
t
WB
BUSY In p ut to W rite
(4)
0
____
0
____
0
____
ns
t
WH
Write Hold After BUSY
(5)
12
____
15
____
17
____
ns
P ORT -TO- PORT DEL AY T IMI NG
t
WDD
Write Pulse to Data De lay
(1)
____
30
____
45
____
50 ns
t
DDD
Write Data Valid to Re ad Data De lay
(1)
____
25
____
35
____
35 ns
2 941 tb l 13 a
70V05X35
Com'l Only 70V05X55
Com'l Only
Symbol Parameter Min. Max. Min. Max. Unit
BUSY TIMING (M/S = V
IH
)
t
BAA
BUSY Acces s Time fro m Addre ss Match
____
20
____
45 ns
t
BDA
BUSY Dis ab le Tim e fro m A d d re s s No t M atc h e d
____
20
____
40 ns
t
BAC
BUSY Ac ces s Time fro m Chip Enab le LOW
____
20
____
40 ns
t
BDC
BUSY Disable Time fro m Chip Enable HIGH
____
20
____
35 ns
t
APS
Arbitratio n Priority Set-up Time
(2)
5
____
5
____
ns
t
BDD
BUSY Di s ab le to Val id Data
(3)
____
35
____
40 ns
t
WH
Write Hold A fte r BUSY
(5)
25
____
25
____
ns
BUSY TIMING (M/S = V
IL
)
t
WB
BUSY Inp ut to Write
(4)
0
____
0
____
ns
t
WH
Write Hold A fte r BUSY
(5)
25
____
25
____
ns
PORT-TO-PORT DELAY TI MING
t
WDD
Write Pulse to Data Delay
(1)
____
60
____
80 ns
t
DDD
Write Data Valid to Re ad Data Delay
(1)
____
45
____
65 ns
2941 t bl 1 3 b
6.42
IDT70V05S/L
High-Speed 3.3V 8K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
14
2941 drw 12
t
DW
t
APS
ADDR
"A"
t
WC
DATA
OUT "B"
MATCH
t
WP
R/W
"A"
DATA
IN "A"
ADDR
"B"
t
DH
VALID
(1)
MATCH
BUSY
"B"
t
BDA
VALID
t
BDD
t
DDD
(3)
t
WDD
t
BAA
Timing Waveform of Write with Port-to-Port Read with BUSY(2,4,5)
(M/S=VIH)
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (SLAVE).
2. CEL = CER = VIL.
3. OE = VIL for the reading port.
4. If M/S = VIL (SLAVE) then BUSY is input. For this example, BUSY“A” = V IH and BUSY“B” input is shown above.
5. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the port opposite from Port “A”.
6.42
IDT70V05S/L
High-Speed 3.3V 8K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
15
Timing Waveform of Write with BUSY
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.
Waveform of BUSY Arbitration Cycle Controlled by Address Match
Timing(1) (M/S = VIH)
Waveform of BUSY Arbitration Controlled by CE Timing(1) (M/S = VIH)
NOTES:
1. tWH must be met for both BUSY input (slave) and output (master).
2. BUSY is asserted on port “B” Blocking R/W“B”, until BUSY“B” goes HIGH.
3. tWB is only for the slave version.
2941 drw 13
R/W
"A"
BUSY
"B"
t
WP
t
WB
R/W
"B"
t
WH
(1)
(2)
(3)
,
2941 drw 14
ADDR
"A"
and
"B"
ADDRESSES MATCH
CE
"A"
CE
"B"
BUSY
"B"
t
APS
t
BAC
t
BDC
(2)
2941 drw 15
ADDR
"A"
ADDRESS "N"
ADDR
"B"
BUSY
"B"
t
APS
t
BAA
t
BDA
(2)
MATCHING ADDRESS "N"
6.42
IDT70V05S/L
High-Speed 3.3V 8K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
16
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(1)
NOTES:
1. 'X' in part number indicates power rating (S or L).
70V05X15
Co m' l O nl y 70V05X20
Com'l
& In d
70V05X25
Com'l Only
Symbol Parameter Min.Max.Min.Max.Min.Max.Unit
INTERRUPT TIMI NG
t
AS
Address Set-up Time 0
____
0
____
0
____
ns
t
WR
Write Reco very Time 0
____
0
____
0
____
ns
t
INS
In te rru p t S e t Ti me
____
15
____
20
____
20 ns
t
INR
Inte rrup t Re se t Time
____
15
____
20
____
20 ns
2 941 tbl 14 a
70V05X35
Com'l Only 70V05X55
Com'l Only
Symbol Parameter Min. Max. Min. Max. Unit
INTERRUPT TIMING
t
AS
Address Set-up Time 0
____
0
____
ns
t
WR
Write Recovery Time 0
____
0
____
ns
t
INS
Interru p t S e t Ti me
____
25
____
40 ns
t
INR
Inte rrup t Re se t Time
____
25
____
40 ns
2941 tbl 14b
6.42
IDT70V05S/L
High-Speed 3.3V 8K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
17
2941 drw 17
ADDR
"B"
INTERRUPT CLEAR ADDRESS
CE
"B"
OE
"B"
t
AS
t
RC
(3)
t
INR
(3)
INT
"B"
(2)
Waveform of Interrupt Timing(1)
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
2. See Interrupt Truth Table III.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
2941 drw 16
ADDR
"A"
INTERRUPT SET ADDRESS
CE
"A"
R/W
"A"
t
AS
t
WC
t
WR
(3) (4)
t
INS
(3)
INT
"B"
(2)
6.42
IDT70V05S/L
High-Speed 3.3V 8K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
18
Truth Table IV — Address BUSY
Arbitration
NOTES:
1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSYX outputs on the IDT70V05 are push
pull, not open drain outputs. On slaves the BUSYX input internally inhibits writes.
2. VIL if the inputs to the opposite port were stable prior to the address and enable inputs of this port. VIH if the inputs to the opposite port became stable after the address and
enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs cannot be low simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving low regardless of actual logic level on the pin. Writes to the right port are internally ignored when
BUSYR outputs are driving low regardless of actual logic level on the pin.
Truth Table V — Example of Semaphore Procurement Sequence(1,2,3)
NOTES:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70V05.
2. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O7). These eight semaphores are addressed by A0-A2.
3. CE = VIH, SEM = VIL to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table.
Truth Table III — Interrupt Flag(1)
NOTES:
1. Assumes BUSYL = BUSYR = VIH.
2. If BUSYL = VIL, then no change.
3. If BUSYR = VIL, then no change.
Left Port Right Port
FunctionR/W
L
CE
L
OE
L
A
12L
-A
0L
INT
L
R/W
R
CE
R
OE
R
A
12R
-A
0R
INT
R
LLX1FFFXXXX X L
(2)
Set Right INT
R
Flag
XXXXXXLL1FFF H
(3)
Re se t Rig ht INT
R
Flag
XXX X L
(3)
LLX1FFEXSet Left INT
L
Flag
XLL1FFE H
(2)
X X X X X Reset Left INT
L
Flag
2941tbl 15
Inputs Outputs
Function
CE
L
CE
R
A
12L
-A
0L
A
12R
-A
0R
BUSY
L
(1)
BUSY
R
(1)
XXNO MATCHHHNormal
HXMATCHHHNormal
XHMATCHHHNormal
L L MATCH (2) (2) Write Inhib it
(3)
29 41 tbl 16
Functions D
0
- D
7
Left D
0
- D
7
Right Status
No Action 1 1 Semaphore free
Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token
Rig ht P ort Wri te s "0" to Se mapho re 0 1 No chang e . Right s ide has no write acc es s to s emap ho re
Left Port Writes "1" to Semaphore 1 0 Right port obtains semaphore token
Left Po rt Writes "0" to Se map ho re 1 0 No c hange . Le ft p ort has no write ac ce ss to se map ho re
Right Port Writes "1" to Semaphore 0 1 Left port obtains semaphore token
Left Port Writes "1" to Semaphore 1 1 Semaphore free
Right Port Writes "0" to Semaphore 1 0 Right port has semaphore token
Right Port Writes "1" to Semaphore 1 1 Semaphore free
Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token
Left Port Writes "1" to Semaphore 1 1 Semaphore free
2941 tbl 17
6.42
IDT70V05S/L
High-Speed 3.3V 8K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
19
Functional Description
The IDT70V05 provides two ports with separate control, address
and I/O pins that permit independent access for reads or writes to any
location in memory. The IDT70V05 has an automatic power down
feature controlled by CE. The CE controls on-chip power down circuitry
that permits the respective port to go into a standby mode when not
selected (CE HIGH). When a port is enabled, access to the entire
memory array is permitted.
Interrupts
If the user chooses the interrupt function, a memory location (mail
box or message center) is assigned to each port. The left port interrupt
flag (INTL) is set when the right port writes to memory location 1FFE
(HEX). The left port clears the interrupt by reading address location
1FFE. Likewise, the right port interrupt flag (INTR) is set when the left
port writes to memory location 1FFF (HEX) and to clear the interrupt
flag (INTR), the right port must read the memory location 1FFF. The
message (8 bits) at 1FFE or 1FFF is user-defined. If the interrupt
function is not used, address locations 1FFE and 1FFF are not used
as mail boxes, but as part of the random access memory. Refer to
Truth Table III for the interrupt operation.
Busy Logic
Busy Logic provides a hardware indication that both ports of the
SRAM have accessed the same location at the same time. It also
allows one of the two accesses to proceed and signals the other side
that the SRAM is “busy”. The BUSY pin can then be used to stall the
access until the operation on the other side is completed. If a write
operation has been attempted from the side that receives a BUSY
indication, the write signal is gated internally to prevent the write from
proceeding.
The use of BUSY logic is not required or desirable for all applica-
tions. In some cases it may be useful to logically OR the BUSY outputs
together and use any BUSY indication as an interrupt source to flag the
event of an illegal or illogical operation. If the write inhibit function of
BUSY logic is not desirable, the BUSY logic can be disabled by placing
the part in slave mode with the M/S pin. Once in slave mode the BUSY
pin operates solely as a write inhibit input pin. Normal operation can be
programmed by tying the BUSY pins HIGH. If desired, unintended
write operations can be prevented to a port by tying the BUSY pin for
that port LOW.
The BUSY outputs on the IDT 70V05 SRAM in master mode, are
push-pull type outputs and do not require pull up resistors to
operate. If these SRAMs are being expanded in depth, then the
BUSY indication for the resulting array requires the use of an external
AND gate.
Width Expansion with Busy Logic
Master/Slave Arrays
When expanding an IDT70V05 SRAM array in width while using
BUSY logic, one master part is used to decide which side of the RAM
array will receive a BUSY indication, and to output that indication. Any
number of slaves to be addressed in the same address range as the
master, use the BUSY signal as a write inhibit signal. Thus on the
IDT70V05 SRAM the BUSY pin is an output if the part is used as a
master (M/S pin = VIH), and the BUSY pin is an input if the part used
as a slave (M/S pin = VIL) as shown in Figure 3.
If two or more master parts were used when expanding in width, a
split decision could result with one master indicating BUSY on one side
of the array and another master indicating BUSY on one other side of
the array. This would inhibit the write operations from one port for part
of a word and inhibit the write operations from the other port for the
other part of the word.
The BUSY arbitration, on a master, is based on the chip enable and
address signals only. It ignores whether an access is a read or write.
In a master/slave array, both address and chip enable must be valid
long enough for a BUSY flag to be output from the master before the
actual write pulse can be initiated with the R/W signal. Failure to
observe this timing can result in a glitched internal write inhibit signal
and corrupted data in the slave.
Semaphores
The IDT70V05 is a fast Dual-Port 8K x 8 CMOS Static RAM with
an additional 8 address locations dedicated to binary semaphore flags.
These flags allow either processor on the left or right side of the Dual-
Port SRAM to claim a privilege over the other processor for functions
defined by the system designer’s software. As an example, the
semaphore can be used by one processor to inhibit the other from
accessing a portion of the Dual-Port SRAM or any other shared
resource.
The Dual-Port SRAM features a fast access time, and both ports are
Figure 3. Busy and chip enable routing for both width and depth expansion with IDT70V05 SRAMs.
2941 drw 18
MASTER
Dual Port
SRAM
BUSY (L) BUSY (R)
CE
MASTER
Dual Port
SRAM
BUSY (L) BUSY (R)
CE
SLAVE
Dual Port
SRAM
BUSY (L) BUSY (R)
CE
SLAVE
Dual Port
SRAM
BUSY (L) BUSY (R)
CE
BUSY (L)
BUSY (R)
DECODER
,
6.42
IDT70V05S/L
High-Speed 3.3V 8K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
20
completely independent of each other. This means that the activity on the
left port in no way slows the access time of the right port. Both ports are
identical in function to standard CMOS Static RAM and can be read from,
or accessed, at the same time with the only possible conflict arising from
the simultaneous writing of, or a simultaneous READ/WRITE of, a non-
semaphore location. Semaphores are protected against such ambiguous
situations and may be used by the system program to avoid any conflicts
in the non-semaphore portion of the Dual-Port SRAM. These devices
have an automatic power-down feature controlled by CE, the Dual-Port
SRAM enable, and SEM, the semaphore enable. The CE and SEM pins
control on-chip power down circuitry that permits the respective port to go
into standby mode when not selected. This is the condition which is shown
in Truth Table II where CE and SEM are both HIGH.
Systems which can best use the IDT70V05 contain multiple processors
or controllers and are typically very high-speed systems which are
software controlled or software intensive. These systems can benefit from
a performance increase offered by the IDT70V05's hardware sema-
phores, which provide a lockout mechanism without requiring complex
programming.
Software handshaking between processors offers the maximum in
system flexibility by permitting shared resources to be allocated in
varying configurations. The IDT70V05 does not use its semaphore
flags to control any resources through hardware, thus allowing the
system designer total flexibility in system architecture.
An advantage of using semaphores rather than the more common
methods of hardware arbitration is that wait states are never incurred
in either processor. This can prove to be a major advantage in very
high-speed systems.
How the Semaphore Flags Work
The semaphore logic is a set of eight latches which are indepen-
dent of the Dual-Port SRAM. These latches can be used to pass a flag,
or token, from one port to the other to indicate that a shared resource
is in use. The semaphores provide a hardware assist for a use
assignment method called “Token Passing Allocation.” In this method,
the state of a semaphore latch is used as a token indicating that shared
resource is in use. If the left processor wants to use this resource, it
requests the token by setting the latch. This processor then verifies its
success in setting the latch by reading it. If it was successful, it
proceeds to assume control over the shared resource. If it was not
successful in setting the latch, it determines that the right side
processor has set the latch first, has the token and is using the shared
resource. The left processor can then either repeatedly request that
semaphore’s status or remove its request for that semaphore to
perform another task and occasionally attempt again to gain control of
the token via the set and test sequence. Once the right side has
relinquished the token, the left side should succeed in gaining control.
The semaphore flags are active low. A token is requested by writing
a zero into a semaphore latch and is released when the same side
writes a one to that latch.
The eight semaphore flags reside within the IDT70V05 in a
separate memory space from the Dual-Port SRAM. This address
space is accessed by placing a LOW input on the SEM pin (which acts
as a chip select for the semaphore flags) and using the other control
pins (Address, OE, and R/W) as they would be used in accessing a
standard Static RAM. Each of the flags has a unique address which can
be accessed by either side through address pins A0 – A2. When accessing
the semaphores, none of the other address pins has any effect.
When writing to a semaphore, only data pin D0 is used. If a LOW level
is written into an unused semaphore location, that flag will be set to a zero
on that side and a one on the other side (see Truth Table V). That
semaphore can now only be modified by the side showing the zero. When
a one is written into the same location from the same side, the flag will be
set to a one for both sides (unless a semaphore request from the other side
is pending) and then can be written to by both sides. The fact that the side
which is able to write a zero into a semaphore subsequently locks out writes
from the other side is what makes semaphore flags useful in interprocessor
communications. (A thorough discussion on the use of this feature follows
shortly.) A zero written into the same location from the other side will be
stored in the semaphore request latch for that side until the semaphore is
freed by the first side.
When a semaphore flag is read, its value is spread into all data bits so
that a flag that is a one reads as a one in all data bits and a flag containing
a zero reads as all zeros. The read value is latched into one side’s output
register when that side's semaphore select (SEM) and output enable (OE)
signals go active. This serves to disallow the semaphore from changing
state in the middle of a read cycle due to a write cycle from the other side.
Because of this latch, a repeated read of a semaphore in a test loop must
cause either signal (SEM or OE) to go inactive or the output will never
change.
A sequence WRITE/READ must be used by the semaphore in
order to guarantee that no system level contention will occur. A
processor requests access to shared resources by attempting to write
a zero into a semaphore location. If the semaphore is already in use,
the semaphore request latch will contain a zero, yet the semaphore
flag will appear as one, a fact which the processor will verify by the
subsequent read (see Truth Table V). As an example, assume a
processor writes a zero to the left port at a free semaphore location. On
a subsequent read, the processor will verify that it has written success-
fully to that location and will assume control over the resource in
question. Meanwhile, if a processor on the right side attempts to write
a zero to the same semaphore flag it will fail, as will be verified by the
fact that a one will be read from that semaphore on the right side during
subsequent read. Had a sequence of READ/WRITE been used
instead, system contention problems could have occurred during the
gap between the read and write cycles.
It is important to note that a failed semaphore request must be
followed by either repeated reads or by writing a one into the same
location. The reason for this is easily understood by looking at the
simple logic diagram of the semaphore flag in Figure 4. Two sema-
phore request latches feed into a semaphore flag. Whichever latch is
first to present a zero to the semaphore flag will force its side of the
semaphore flag LOW and the other side HIGH. This condition will
continue until a one is written to the same semaphore request latch.
Should the other side’s semaphore request latch have been written to
a zero in the meantime, the semaphore flag will flip over to the other
side as soon as a one is written into the first side’s request latch. The
second side’s flag will now stay LOW until its semaphore request latch
is written to a one. From this it is easy to understand that, if a
semaphore is requested and the processor which requested it no longer
needs the resource, the entire system can hang up until a one is written
into that semaphore request latch.
6.42
IDT70V05S/L
High-Speed 3.3V 8K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
21
D
0
2941 drw 19
DQ
WRITE
D
0D
Q
WRITE
SEMAPHORE
REQUEST FLIP FLOP SEMAPHORE
REQUEST FLIP FLOP
LPORT RPORT
SEMAPHORE
READ SEMAPHORE
READ
,
The critical case of semaphore timing is when both sides request a
single token by attempting to write a zero into it at the same time. The
semaphore logic is specially designed to resolve this problem. If
simultaneous requests are made, the logic guarantees that only one
side receives the token. If one side is earlier than the other in making
the request, the first side to make the request will receive the token. If
both requests arrive at the same time, the assignment will be arbitrarily
made to one port or the other.
One caution that should be noted when using semaphores is that
semaphores alone do not guarantee that access to a resource is
secure. As with any powerful programming technique, if semaphores
are misused or misinterpreted, a software error can easily happen.
Initialization of the semaphores is not automatic and must be
handled via the initialization program at power-up. Since any sema-
phore request flag which contains a zero must be reset to a one, all
semaphores on both sides should have a one written into them at
initialization from both sides to assure that they will be free when
needed.
Using Semaphores—Some Examples
Perhaps the simplest application of semaphores is their applica-
tion as resource markers for the IDT70V05’s Dual-Port SRAM. Say the
8K x 8 SRAM was to be divided into two 4K x 8 blocks which were to be
dedicated at any one time to servicing either the left or right port.
Semaphore 0 could be used to indicate the side which would control
the lower section of memory, and Semaphore 1 could be defined as the
indicator for the upper section of memory.
To take a resource, in this example the lower 4K of Dual-Port
SRAM, the processor on the left port could write and then read a
zero in to Semaphore 0. If this task were successfully completed
(a zero was read back rather than a one), the left processor would
assume control of the lower 4K. Meanwhile the right processor was
attempting to gain control of the resource after the left processor, it
would read back a one in response to the zero it had attempted to
write into Semaphore 0. At this point, the software could choose to try
and gain control of the second 4K section by writing, then reading a zero
into Semaphore 1. If it succeeded in gaining control, it would lock out
the left side.
Once the left side was finished with its task, it would write a one to
Semaphore 0 and may then try to gain access to Semaphore 1. If
Semaphore 1 was still occupied by the right side, the left side could undo
its semaphore request and perform other tasks until it was able to write, then
read a zero into Semaphore 1. If the right processor performs a similar task
with Semaphore 0, this protocol would allow the two processors to swap
4K blocks of Dual-Port SRAM with each other.
The blocks do not have to be any particular size and can even be
variable, depending upon the complexity of the software using the
semaphore flags. All eight semaphores could be used to divide the
Dual-Port SRAM or other shared resources into eight parts. Semaphores
can even be assigned different meanings on different sides rather than
being given a common meaning as was shown in the example above.
Semaphores are a useful form of arbitration in systems like disk
interfaces where the CPU must be locked out of a section of memory
during a transfer and the I/O device cannot tolerate any wait states.
With the use of semaphores, once the two devices has determined
which memory area was “off-limits” to the CPU, both the CPU and the
I/O devices could access their assigned portions of memory continu-
ously without any wait states.
Semaphores are also useful in applications where no memory
“WAIT” state is available on one or both sides. Once a semaphore
handshake has been performed, both processors can access their
assigned SRAM segments at full speed.
Another application is in the area of complex data structures. In this
case, block arbitration is very important. For this application one
processor may be responsible for building and updating a data
structure. The other processor then reads and interprets that data
structure. If the interpreting processor reads an incomplete data
structure, a major error condition may exist. Therefore, some sort of
arbitration must be used between the two different processors. The
building processor arbitrates for the block, locks it and then is able to
go in and update the data structure. When the update is completed, the
data structure block is released. This allows the interpreting processor
to come back and read the complete data structure, thereby guaran-
teeing a consistent data structure.
Figure 4. IDT70V05 Semaphore Logic
6.42
IDT70V05S/L
High-Speed 3.3V 8K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
22
Ordering Information
2941 drw 20
A
Power
999
Speed
A
Package
A
Process/
Temperature
Range
Blank
ICommercial (0°Cto+70°C)
Industrial (-40°Cto+85°C)
PF
G
J
64-pin TQFP (PN64-1)
68-pin PGA (G68-1)
68-pin PLCC (J68-1)
15
20
25
35
55
S
LStandard Power
Low Power
XXXXX
Device
Type
64K(8Kx8)3.3VDual-PortRAM
70V05
IDT
Speed in nanoseconds
Commercial Only
Commercial & Industrial
Commercial Only
Commercial Only
Commercial Only
,
Datasheet Document History
3/11/99: Initiated datasheet document history
Converted to new format
Cosmetic and typographical corrections
Page 2 and 3 Added additional notes to pin configurations
6/9/99: Changed drawing format
11/10/99: Replaced IDT logo
3/10/00: Added 15 & 20ns speed grades
Upgraded DC parameters
Added Industrial Temperature information
Changed ±200mV to 0mV in notes
5/26/00: Page 5 Increased storage temperature parameter
Clarified TA parameter
Page 6 DC Electrical parameters2–changed wording from open to disabled
12/04/01: Page 2 & 3 Added date revision to pin configurations
Page 2, 3, 5 & 6 Changed naming conventions from VCC to VDD and from GND to VSS
Page 6, 8, 10, 13 & 16 Removed industrial temp for 25ns, 35ns and 55ns from DC & AC Electrical Characteristics
Page 22 Removed industrial temp from 25ns, 35ns and 55ns from ordering information
Page 1 & 22 Replaced TM logo with ® logo
CORPORATE HEADQUARTERS for SALES: for Tech Support:
6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 408-284-2794
San Jose, CA 95138 fax: 408-284-2775 DualPortHelp@idt.com
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
NOTE:
1. Contact your local sales office for Industrial temp range in other speeds, packages and powers.
